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4b45efe8 AS |
1 | /* |
2 | * Intel Sunrisepoint LPSS core support. | |
3 | * | |
4 | * Copyright (C) 2015, Intel Corporation | |
5 | * | |
6 | * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> | |
7 | * Mika Westerberg <mika.westerberg@linux.intel.com> | |
8 | * Heikki Krogerus <heikki.krogerus@linux.intel.com> | |
9 | * Jarkko Nikula <jarkko.nikula@linux.intel.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/clkdev.h> | |
18 | #include <linux/clk-provider.h> | |
19 | #include <linux/debugfs.h> | |
20 | #include <linux/idr.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mfd/core.h> | |
25 | #include <linux/pm_qos.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/seq_file.h> | |
9cf5c095 | 28 | #include <linux/io-64-nonatomic-lo-hi.h> |
689d4453 | 29 | |
4b45efe8 AS |
30 | #include "intel-lpss.h" |
31 | ||
32 | #define LPSS_DEV_OFFSET 0x000 | |
33 | #define LPSS_DEV_SIZE 0x200 | |
34 | #define LPSS_PRIV_OFFSET 0x200 | |
35 | #define LPSS_PRIV_SIZE 0x100 | |
36 | #define LPSS_IDMA64_OFFSET 0x800 | |
37 | #define LPSS_IDMA64_SIZE 0x800 | |
38 | ||
39 | /* Offsets from lpss->priv */ | |
40 | #define LPSS_PRIV_RESETS 0x04 | |
41 | #define LPSS_PRIV_RESETS_FUNC BIT(2) | |
42 | #define LPSS_PRIV_RESETS_IDMA 0x3 | |
43 | ||
44 | #define LPSS_PRIV_ACTIVELTR 0x10 | |
45 | #define LPSS_PRIV_IDLELTR 0x14 | |
46 | ||
47 | #define LPSS_PRIV_LTR_REQ BIT(15) | |
48 | #define LPSS_PRIV_LTR_SCALE_MASK 0xc00 | |
49 | #define LPSS_PRIV_LTR_SCALE_1US 0x800 | |
50 | #define LPSS_PRIV_LTR_SCALE_32US 0xc00 | |
51 | #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff | |
52 | ||
53 | #define LPSS_PRIV_SSP_REG 0x20 | |
54 | #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0) | |
55 | ||
689d4453 | 56 | #define LPSS_PRIV_REMAP_ADDR 0x40 |
4b45efe8 AS |
57 | |
58 | #define LPSS_PRIV_CAPS 0xfc | |
59 | #define LPSS_PRIV_CAPS_NO_IDMA BIT(8) | |
60 | #define LPSS_PRIV_CAPS_TYPE_SHIFT 4 | |
61 | #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT) | |
62 | ||
63 | /* This matches the type field in CAPS register */ | |
64 | enum intel_lpss_dev_type { | |
65 | LPSS_DEV_I2C = 0, | |
66 | LPSS_DEV_UART, | |
67 | LPSS_DEV_SPI, | |
68 | }; | |
69 | ||
70 | struct intel_lpss { | |
71 | const struct intel_lpss_platform_info *info; | |
72 | enum intel_lpss_dev_type type; | |
73 | struct clk *clk; | |
74 | struct clk_lookup *clock; | |
75 | const struct mfd_cell *cell; | |
76 | struct device *dev; | |
77 | void __iomem *priv; | |
78 | int devid; | |
79 | u32 caps; | |
80 | u32 active_ltr; | |
81 | u32 idle_ltr; | |
82 | struct dentry *debugfs; | |
83 | }; | |
84 | ||
85 | static const struct resource intel_lpss_dev_resources[] = { | |
86 | DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"), | |
87 | DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"), | |
88 | DEFINE_RES_IRQ(0), | |
89 | }; | |
90 | ||
91 | static const struct resource intel_lpss_idma64_resources[] = { | |
92 | DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE), | |
93 | DEFINE_RES_IRQ(0), | |
94 | }; | |
95 | ||
96 | #define LPSS_IDMA64_DRIVER_NAME "idma64" | |
97 | ||
98 | /* | |
99 | * Cells needs to be ordered so that the iDMA is created first. This is | |
100 | * because we need to be sure the DMA is available when the host controller | |
101 | * driver is probed. | |
102 | */ | |
103 | static const struct mfd_cell intel_lpss_idma64_cell = { | |
104 | .name = LPSS_IDMA64_DRIVER_NAME, | |
105 | .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources), | |
106 | .resources = intel_lpss_idma64_resources, | |
107 | }; | |
108 | ||
109 | static const struct mfd_cell intel_lpss_i2c_cell = { | |
110 | .name = "i2c_designware", | |
111 | .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), | |
112 | .resources = intel_lpss_dev_resources, | |
113 | }; | |
114 | ||
115 | static const struct mfd_cell intel_lpss_uart_cell = { | |
116 | .name = "dw-apb-uart", | |
117 | .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), | |
118 | .resources = intel_lpss_dev_resources, | |
119 | }; | |
120 | ||
121 | static const struct mfd_cell intel_lpss_spi_cell = { | |
122 | .name = "pxa2xx-spi", | |
123 | .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), | |
124 | .resources = intel_lpss_dev_resources, | |
125 | }; | |
126 | ||
127 | static DEFINE_IDA(intel_lpss_devid_ida); | |
128 | static struct dentry *intel_lpss_debugfs; | |
129 | ||
130 | static int intel_lpss_request_dma_module(const char *name) | |
131 | { | |
132 | static bool intel_lpss_dma_requested; | |
133 | ||
134 | if (intel_lpss_dma_requested) | |
135 | return 0; | |
136 | ||
137 | intel_lpss_dma_requested = true; | |
138 | return request_module("%s", name); | |
139 | } | |
140 | ||
141 | static void intel_lpss_cache_ltr(struct intel_lpss *lpss) | |
142 | { | |
143 | lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR); | |
144 | lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR); | |
145 | } | |
146 | ||
147 | static int intel_lpss_debugfs_add(struct intel_lpss *lpss) | |
148 | { | |
149 | struct dentry *dir; | |
150 | ||
151 | dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs); | |
152 | if (IS_ERR(dir)) | |
153 | return PTR_ERR(dir); | |
154 | ||
155 | /* Cache the values into lpss structure */ | |
156 | intel_lpss_cache_ltr(lpss); | |
157 | ||
158 | debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps); | |
159 | debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr); | |
160 | debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr); | |
161 | ||
162 | lpss->debugfs = dir; | |
163 | return 0; | |
164 | } | |
165 | ||
166 | static void intel_lpss_debugfs_remove(struct intel_lpss *lpss) | |
167 | { | |
168 | debugfs_remove_recursive(lpss->debugfs); | |
169 | } | |
170 | ||
171 | static void intel_lpss_ltr_set(struct device *dev, s32 val) | |
172 | { | |
173 | struct intel_lpss *lpss = dev_get_drvdata(dev); | |
174 | u32 ltr; | |
175 | ||
176 | /* | |
177 | * Program latency tolerance (LTR) accordingly what has been asked | |
178 | * by the PM QoS layer or disable it in case we were passed | |
179 | * negative value or PM_QOS_LATENCY_ANY. | |
180 | */ | |
181 | ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR); | |
182 | ||
183 | if (val == PM_QOS_LATENCY_ANY || val < 0) { | |
184 | ltr &= ~LPSS_PRIV_LTR_REQ; | |
185 | } else { | |
186 | ltr |= LPSS_PRIV_LTR_REQ; | |
187 | ltr &= ~LPSS_PRIV_LTR_SCALE_MASK; | |
188 | ltr &= ~LPSS_PRIV_LTR_VALUE_MASK; | |
189 | ||
190 | if (val > LPSS_PRIV_LTR_VALUE_MASK) | |
191 | ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5; | |
192 | else | |
193 | ltr |= LPSS_PRIV_LTR_SCALE_1US | val; | |
194 | } | |
195 | ||
196 | if (ltr == lpss->active_ltr) | |
197 | return; | |
198 | ||
199 | writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR); | |
200 | writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR); | |
201 | ||
202 | /* Cache the values into lpss structure */ | |
203 | intel_lpss_cache_ltr(lpss); | |
204 | } | |
205 | ||
206 | static void intel_lpss_ltr_expose(struct intel_lpss *lpss) | |
207 | { | |
208 | lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set; | |
209 | dev_pm_qos_expose_latency_tolerance(lpss->dev); | |
210 | } | |
211 | ||
212 | static void intel_lpss_ltr_hide(struct intel_lpss *lpss) | |
213 | { | |
214 | dev_pm_qos_hide_latency_tolerance(lpss->dev); | |
215 | lpss->dev->power.set_latency_tolerance = NULL; | |
216 | } | |
217 | ||
218 | static int intel_lpss_assign_devs(struct intel_lpss *lpss) | |
219 | { | |
220 | unsigned int type; | |
221 | ||
222 | type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK; | |
223 | type >>= LPSS_PRIV_CAPS_TYPE_SHIFT; | |
224 | ||
225 | switch (type) { | |
226 | case LPSS_DEV_I2C: | |
227 | lpss->cell = &intel_lpss_i2c_cell; | |
228 | break; | |
229 | case LPSS_DEV_UART: | |
230 | lpss->cell = &intel_lpss_uart_cell; | |
231 | break; | |
232 | case LPSS_DEV_SPI: | |
233 | lpss->cell = &intel_lpss_spi_cell; | |
234 | break; | |
235 | default: | |
236 | return -ENODEV; | |
237 | } | |
238 | ||
239 | lpss->type = type; | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | static bool intel_lpss_has_idma(const struct intel_lpss *lpss) | |
245 | { | |
246 | return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0; | |
247 | } | |
248 | ||
249 | static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss) | |
250 | { | |
251 | resource_size_t addr = lpss->info->mem->start; | |
252 | ||
689d4453 | 253 | lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR); |
4b45efe8 AS |
254 | } |
255 | ||
256 | static void intel_lpss_deassert_reset(const struct intel_lpss *lpss) | |
257 | { | |
258 | u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA; | |
259 | ||
260 | /* Bring out the device from reset */ | |
261 | writel(value, lpss->priv + LPSS_PRIV_RESETS); | |
262 | } | |
263 | ||
264 | static void intel_lpss_init_dev(const struct intel_lpss *lpss) | |
265 | { | |
266 | u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN; | |
267 | ||
268 | intel_lpss_deassert_reset(lpss); | |
269 | ||
270 | if (!intel_lpss_has_idma(lpss)) | |
271 | return; | |
272 | ||
273 | intel_lpss_set_remap_addr(lpss); | |
274 | ||
275 | /* Make sure that SPI multiblock DMA transfers are re-enabled */ | |
276 | if (lpss->type == LPSS_DEV_SPI) | |
277 | writel(value, lpss->priv + LPSS_PRIV_SSP_REG); | |
278 | } | |
279 | ||
280 | static void intel_lpss_unregister_clock_tree(struct clk *clk) | |
281 | { | |
282 | struct clk *parent; | |
283 | ||
284 | while (clk) { | |
285 | parent = clk_get_parent(clk); | |
286 | clk_unregister(clk); | |
287 | clk = parent; | |
288 | } | |
289 | } | |
290 | ||
291 | static int intel_lpss_register_clock_divider(struct intel_lpss *lpss, | |
292 | const char *devname, | |
293 | struct clk **clk) | |
294 | { | |
295 | char name[32]; | |
296 | struct clk *tmp = *clk; | |
297 | ||
298 | snprintf(name, sizeof(name), "%s-enable", devname); | |
299 | tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0, | |
300 | lpss->priv, 0, 0, NULL); | |
301 | if (IS_ERR(tmp)) | |
302 | return PTR_ERR(tmp); | |
303 | ||
304 | snprintf(name, sizeof(name), "%s-div", devname); | |
305 | tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp), | |
306 | 0, lpss->priv, 1, 15, 16, 15, 0, | |
307 | NULL); | |
308 | if (IS_ERR(tmp)) | |
309 | return PTR_ERR(tmp); | |
310 | *clk = tmp; | |
311 | ||
312 | snprintf(name, sizeof(name), "%s-update", devname); | |
313 | tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), | |
314 | CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL); | |
315 | if (IS_ERR(tmp)) | |
316 | return PTR_ERR(tmp); | |
317 | *clk = tmp; | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | static int intel_lpss_register_clock(struct intel_lpss *lpss) | |
323 | { | |
324 | const struct mfd_cell *cell = lpss->cell; | |
325 | struct clk *clk; | |
326 | char devname[24]; | |
327 | int ret; | |
328 | ||
329 | if (!lpss->info->clk_rate) | |
330 | return 0; | |
331 | ||
332 | /* Root clock */ | |
333 | clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, | |
334 | CLK_IS_ROOT, lpss->info->clk_rate); | |
335 | if (IS_ERR(clk)) | |
336 | return PTR_ERR(clk); | |
337 | ||
338 | snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid); | |
339 | ||
340 | /* | |
341 | * Support for clock divider only if it has some preset value. | |
342 | * Otherwise we assume that the divider is not used. | |
343 | */ | |
344 | if (lpss->type != LPSS_DEV_I2C) { | |
345 | ret = intel_lpss_register_clock_divider(lpss, devname, &clk); | |
346 | if (ret) | |
347 | goto err_clk_register; | |
348 | } | |
349 | ||
350 | ret = -ENOMEM; | |
351 | ||
352 | /* Clock for the host controller */ | |
353 | lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname); | |
354 | if (!lpss->clock) | |
355 | goto err_clk_register; | |
356 | ||
357 | lpss->clk = clk; | |
358 | ||
359 | return 0; | |
360 | ||
361 | err_clk_register: | |
362 | intel_lpss_unregister_clock_tree(clk); | |
363 | ||
364 | return ret; | |
365 | } | |
366 | ||
367 | static void intel_lpss_unregister_clock(struct intel_lpss *lpss) | |
368 | { | |
369 | if (IS_ERR_OR_NULL(lpss->clk)) | |
370 | return; | |
371 | ||
372 | clkdev_drop(lpss->clock); | |
373 | intel_lpss_unregister_clock_tree(lpss->clk); | |
374 | } | |
375 | ||
376 | int intel_lpss_probe(struct device *dev, | |
377 | const struct intel_lpss_platform_info *info) | |
378 | { | |
379 | struct intel_lpss *lpss; | |
380 | int ret; | |
381 | ||
382 | if (!info || !info->mem || info->irq <= 0) | |
383 | return -EINVAL; | |
384 | ||
385 | lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL); | |
386 | if (!lpss) | |
387 | return -ENOMEM; | |
388 | ||
389 | lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET, | |
390 | LPSS_PRIV_SIZE); | |
391 | if (!lpss->priv) | |
392 | return -ENOMEM; | |
393 | ||
394 | lpss->info = info; | |
395 | lpss->dev = dev; | |
396 | lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS); | |
397 | ||
398 | dev_set_drvdata(dev, lpss); | |
399 | ||
400 | ret = intel_lpss_assign_devs(lpss); | |
401 | if (ret) | |
402 | return ret; | |
403 | ||
404 | intel_lpss_init_dev(lpss); | |
405 | ||
406 | lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL); | |
407 | if (lpss->devid < 0) | |
408 | return lpss->devid; | |
409 | ||
410 | ret = intel_lpss_register_clock(lpss); | |
411 | if (ret) | |
412 | goto err_clk_register; | |
413 | ||
414 | intel_lpss_ltr_expose(lpss); | |
415 | ||
416 | ret = intel_lpss_debugfs_add(lpss); | |
417 | if (ret) | |
418 | dev_warn(dev, "Failed to create debugfs entries\n"); | |
419 | ||
420 | if (intel_lpss_has_idma(lpss)) { | |
421 | /* | |
422 | * Ensure the DMA driver is loaded before the host | |
423 | * controller device appears, so that the host controller | |
424 | * driver can request its DMA channels as early as | |
425 | * possible. | |
426 | * | |
427 | * If the DMA module is not there that's OK as well. | |
428 | */ | |
429 | intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME); | |
430 | ||
431 | ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell, | |
432 | 1, info->mem, info->irq, NULL); | |
433 | if (ret) | |
434 | dev_warn(dev, "Failed to add %s, fallback to PIO\n", | |
435 | LPSS_IDMA64_DRIVER_NAME); | |
436 | } | |
437 | ||
438 | ret = mfd_add_devices(dev, lpss->devid, lpss->cell, | |
439 | 1, info->mem, info->irq, NULL); | |
440 | if (ret) | |
441 | goto err_remove_ltr; | |
442 | ||
443 | return 0; | |
444 | ||
445 | err_remove_ltr: | |
446 | intel_lpss_debugfs_remove(lpss); | |
447 | intel_lpss_ltr_hide(lpss); | |
448 | ||
449 | err_clk_register: | |
450 | ida_simple_remove(&intel_lpss_devid_ida, lpss->devid); | |
451 | ||
452 | return ret; | |
453 | } | |
454 | EXPORT_SYMBOL_GPL(intel_lpss_probe); | |
455 | ||
456 | void intel_lpss_remove(struct device *dev) | |
457 | { | |
458 | struct intel_lpss *lpss = dev_get_drvdata(dev); | |
459 | ||
460 | mfd_remove_devices(dev); | |
461 | intel_lpss_debugfs_remove(lpss); | |
462 | intel_lpss_ltr_hide(lpss); | |
463 | intel_lpss_unregister_clock(lpss); | |
464 | ida_simple_remove(&intel_lpss_devid_ida, lpss->devid); | |
465 | } | |
466 | EXPORT_SYMBOL_GPL(intel_lpss_remove); | |
467 | ||
468 | static int resume_lpss_device(struct device *dev, void *data) | |
469 | { | |
470 | pm_runtime_resume(dev); | |
471 | return 0; | |
472 | } | |
473 | ||
474 | int intel_lpss_prepare(struct device *dev) | |
475 | { | |
476 | /* | |
477 | * Resume both child devices before entering system sleep. This | |
478 | * ensures that they are in proper state before they get suspended. | |
479 | */ | |
480 | device_for_each_child_reverse(dev, NULL, resume_lpss_device); | |
481 | return 0; | |
482 | } | |
483 | EXPORT_SYMBOL_GPL(intel_lpss_prepare); | |
484 | ||
485 | int intel_lpss_suspend(struct device *dev) | |
486 | { | |
487 | return 0; | |
488 | } | |
489 | EXPORT_SYMBOL_GPL(intel_lpss_suspend); | |
490 | ||
491 | int intel_lpss_resume(struct device *dev) | |
492 | { | |
493 | struct intel_lpss *lpss = dev_get_drvdata(dev); | |
494 | ||
495 | intel_lpss_init_dev(lpss); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | EXPORT_SYMBOL_GPL(intel_lpss_resume); | |
500 | ||
501 | static int __init intel_lpss_init(void) | |
502 | { | |
503 | intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL); | |
504 | return 0; | |
505 | } | |
506 | module_init(intel_lpss_init); | |
507 | ||
508 | static void __exit intel_lpss_exit(void) | |
509 | { | |
510 | debugfs_remove(intel_lpss_debugfs); | |
511 | } | |
512 | module_exit(intel_lpss_exit); | |
513 | ||
514 | MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); | |
515 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
516 | MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>"); | |
517 | MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>"); | |
518 | MODULE_DESCRIPTION("Intel LPSS core driver"); | |
519 | MODULE_LICENSE("GPL v2"); |