[deliverable/linux.git] / drivers / mfd / max8998-irq.c

/*
 * Interrupt controller support for MAX8998
 *
 * Copyright (C) 2010 Samsung Electronics Co.Ltd
 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mfd/max8998-private.h>

struct max8998_irq_data {
	int reg;
	int mask;
};

static struct max8998_irq_data max8998_irqs[] = {
	[MAX8998_IRQ_DCINF] = {
		.reg = 1,
		.mask = MAX8998_IRQ_DCINF_MASK,
	},
	[MAX8998_IRQ_DCINR] = {
		.reg = 1,
		.mask = MAX8998_IRQ_DCINR_MASK,
	},
	[MAX8998_IRQ_JIGF] = {
		.reg = 1,
		.mask = MAX8998_IRQ_JIGF_MASK,
	},
	[MAX8998_IRQ_JIGR] = {
		.reg = 1,
		.mask = MAX8998_IRQ_JIGR_MASK,
	},
	[MAX8998_IRQ_PWRONF] = {
		.reg = 1,
		.mask = MAX8998_IRQ_PWRONF_MASK,
	},
	[MAX8998_IRQ_PWRONR] = {
		.reg = 1,
		.mask = MAX8998_IRQ_PWRONR_MASK,
	},
	[MAX8998_IRQ_WTSREVNT] = {
		.reg = 2,
		.mask = MAX8998_IRQ_WTSREVNT_MASK,
	},
	[MAX8998_IRQ_SMPLEVNT] = {
		.reg = 2,
		.mask = MAX8998_IRQ_SMPLEVNT_MASK,
	},
	[MAX8998_IRQ_ALARM1] = {
		.reg = 2,
		.mask = MAX8998_IRQ_ALARM1_MASK,
	},
	[MAX8998_IRQ_ALARM0] = {
		.reg = 2,
		.mask = MAX8998_IRQ_ALARM0_MASK,
	},
	[MAX8998_IRQ_ONKEY1S] = {
		.reg = 3,
		.mask = MAX8998_IRQ_ONKEY1S_MASK,
	},
	[MAX8998_IRQ_TOPOFFR] = {
		.reg = 3,
		.mask = MAX8998_IRQ_TOPOFFR_MASK,
	},
	[MAX8998_IRQ_DCINOVPR] = {
		.reg = 3,
		.mask = MAX8998_IRQ_DCINOVPR_MASK,
	},
	[MAX8998_IRQ_CHGRSTF] = {
		.reg = 3,
		.mask = MAX8998_IRQ_CHGRSTF_MASK,
	},
	[MAX8998_IRQ_DONER] = {
		.reg = 3,
		.mask = MAX8998_IRQ_DONER_MASK,
	},
	[MAX8998_IRQ_CHGFAULT] = {
		.reg = 3,
		.mask = MAX8998_IRQ_CHGFAULT_MASK,
	},
	[MAX8998_IRQ_LOBAT1] = {
		.reg = 4,
		.mask = MAX8998_IRQ_LOBAT1_MASK,
	},
	[MAX8998_IRQ_LOBAT2] = {
		.reg = 4,
		.mask = MAX8998_IRQ_LOBAT2_MASK,
	},
};

static inline struct max8998_irq_data *
irq_to_max8998_irq(struct max8998_dev *max8998, int irq)
{
	struct irq_data *data = irq_get_irq_data(irq);
	return &max8998_irqs[data->hwirq];
}

static void max8998_irq_lock(struct irq_data *data)
{
	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);

	mutex_lock(&max8998->irqlock);
}

static void max8998_irq_sync_unlock(struct irq_data *data)
{
	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
	int i;

	for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
		/*
		 * If there's been a change in the mask write it back
		 * to the hardware.
		 */
		if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
			max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
			max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
					max8998->irq_masks_cur[i]);
		}
	}

	mutex_unlock(&max8998->irqlock);
}

static void max8998_irq_unmask(struct irq_data *data)
{
	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
							       data->irq);

	max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
}

static void max8998_irq_mask(struct irq_data *data)
{
	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
							       data->irq);

	max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
}

static struct irq_chip max8998_irq_chip = {
	.name = "max8998",
	.irq_bus_lock = max8998_irq_lock,
	.irq_bus_sync_unlock = max8998_irq_sync_unlock,
	.irq_mask = max8998_irq_mask,
	.irq_unmask = max8998_irq_unmask,
};

static irqreturn_t max8998_irq_thread(int irq, void *data)
{
	struct max8998_dev *max8998 = data;
	u8 irq_reg[MAX8998_NUM_IRQ_REGS];
	int ret;
	int i;

	ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
			MAX8998_NUM_IRQ_REGS, irq_reg);
	if (ret < 0) {
		dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
				ret);
		return IRQ_NONE;
	}

	/* Apply masking */
	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
		irq_reg[i] &= ~max8998->irq_masks_cur[i];

	/* Report */
	for (i = 0; i < MAX8998_IRQ_NR; i++) {
		if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
			irq = irq_find_mapping(max8998->irq_domain, i);
			if (WARN_ON(!irq)) {
				disable_irq_nosync(max8998->irq);
				return IRQ_NONE;
			}
			handle_nested_irq(irq);
		}
	}

	return IRQ_HANDLED;
}

int max8998_irq_resume(struct max8998_dev *max8998)
{
	if (max8998->irq && max8998->irq_domain)
		max8998_irq_thread(max8998->irq, max8998);
	return 0;
}

static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
					irq_hw_number_t hw)
{
	struct max8997_dev *max8998 = d->host_data;

	irq_set_chip_data(irq, max8998);
	irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
	irq_set_nested_thread(irq, 1);
#ifdef CONFIG_ARM
	set_irq_flags(irq, IRQF_VALID);
#else
	irq_set_noprobe(irq);
#endif
	return 0;
}

static struct irq_domain_ops max8998_irq_domain_ops = {
	.map = max8998_irq_domain_map,
};

int max8998_irq_init(struct max8998_dev *max8998)
{
	int i;
	int ret;
	struct irq_domain *domain;

	if (!max8998->irq) {
		dev_warn(max8998->dev,
			 "No interrupt specified, no interrupts\n");
		return 0;
	}

	mutex_init(&max8998->irqlock);

	/* Mask the individual interrupt sources */
	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
		max8998->irq_masks_cur[i] = 0xff;
		max8998->irq_masks_cache[i] = 0xff;
		max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
	}

	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);

	domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
			max8998->irq_base, &max8998_irq_domain_ops, max8998);
	if (!domain) {
		dev_err(max8998->dev, "could not create irq domain\n");
		return -ENODEV;
	}
	max8998->irq_domain = domain;

	ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
				   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				   "max8998-irq", max8998);
	if (ret) {
		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
			max8998->irq, ret);
		return ret;
	}

	if (!max8998->ono)
		return 0;

	ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
				   IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
				   IRQF_ONESHOT, "max8998-ono", max8998);
	if (ret)
		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
			max8998->ono, ret);

	return 0;
}

void max8998_irq_exit(struct max8998_dev *max8998)
{
	if (max8998->ono)
		free_irq(max8998->ono, max8998);

	if (max8998->irq)
		free_irq(max8998->irq, max8998);
}
Commit	Line	Data
2c7e6f57 JS	1	/*
	2	* Interrupt controller support for MAX8998
	3	*
	4	* Copyright (C) 2010 Samsung Electronics Co.Ltd
	5	* Author: Joonyoung Shim <jy0922.shim@samsung.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/irq.h>
443c6ae2	17	#include <linux/irqdomain.h>
2c7e6f57 JS	18	#include <linux/mfd/max8998-private.h>
	19
	20	struct max8998_irq_data {
	21	int reg;
	22	int mask;
	23	};
	24
	25	static struct max8998_irq_data max8998_irqs[] = {
	26	[MAX8998_IRQ_DCINF] = {
	27	.reg = 1,
	28	.mask = MAX8998_IRQ_DCINF_MASK,
	29	},
	30	[MAX8998_IRQ_DCINR] = {
	31	.reg = 1,
	32	.mask = MAX8998_IRQ_DCINR_MASK,
	33	},
	34	[MAX8998_IRQ_JIGF] = {
	35	.reg = 1,
	36	.mask = MAX8998_IRQ_JIGF_MASK,
	37	},
	38	[MAX8998_IRQ_JIGR] = {
	39	.reg = 1,
	40	.mask = MAX8998_IRQ_JIGR_MASK,
	41	},
	42	[MAX8998_IRQ_PWRONF] = {
	43	.reg = 1,
	44	.mask = MAX8998_IRQ_PWRONF_MASK,
	45	},
	46	[MAX8998_IRQ_PWRONR] = {
	47	.reg = 1,
	48	.mask = MAX8998_IRQ_PWRONR_MASK,
	49	},
	50	[MAX8998_IRQ_WTSREVNT] = {
	51	.reg = 2,
	52	.mask = MAX8998_IRQ_WTSREVNT_MASK,
	53	},
	54	[MAX8998_IRQ_SMPLEVNT] = {
	55	.reg = 2,
	56	.mask = MAX8998_IRQ_SMPLEVNT_MASK,
	57	},
	58	[MAX8998_IRQ_ALARM1] = {
	59	.reg = 2,
	60	.mask = MAX8998_IRQ_ALARM1_MASK,
	61	},
	62	[MAX8998_IRQ_ALARM0] = {
	63	.reg = 2,
	64	.mask = MAX8998_IRQ_ALARM0_MASK,
	65	},
	66	[MAX8998_IRQ_ONKEY1S] = {
	67	.reg = 3,
	68	.mask = MAX8998_IRQ_ONKEY1S_MASK,
	69	},
	70	[MAX8998_IRQ_TOPOFFR] = {
	71	.reg = 3,
	72	.mask = MAX8998_IRQ_TOPOFFR_MASK,
	73	},
	74	[MAX8998_IRQ_DCINOVPR] = {
	75	.reg = 3,
	76	.mask = MAX8998_IRQ_DCINOVPR_MASK,
	77	},
	78	[MAX8998_IRQ_CHGRSTF] = {
	79	.reg = 3,
	80	.mask = MAX8998_IRQ_CHGRSTF_MASK,
	81	},
82	[MAX8998_IRQ_DONER] = {
83	.reg = 3,
84	.mask = MAX8998_IRQ_DONER_MASK,
85	},
86	[MAX8998_IRQ_CHGFAULT] = {
87	.reg = 3,
88	.mask = MAX8998_IRQ_CHGFAULT_MASK,
89	},
90	[MAX8998_IRQ_LOBAT1] = {
91	.reg = 4,
92	.mask = MAX8998_IRQ_LOBAT1_MASK,
93	},
94	[MAX8998_IRQ_LOBAT2] = {
95	.reg = 4,
96	.mask = MAX8998_IRQ_LOBAT2_MASK,
97	},
98	};
99
100	static inline struct max8998_irq_data *
101	irq_to_max8998_irq(struct max8998_dev *max8998, int irq)
102	{
443c6ae2 TF	103	struct irq_data *data = irq_get_irq_data(irq);
443c6ae2 TF	104	return &max8998_irqs[data->hwirq];
2c7e6f57 JS	105	}
2c7e6f57 JS	106
2898577e	107	static void max8998_irq_lock(struct irq_data *data)
2c7e6f57	108	{
2898577e	109	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
2c7e6f57 JS	110
	111	mutex_lock(&max8998->irqlock);
	112	}
	113
2898577e	114	static void max8998_irq_sync_unlock(struct irq_data *data)
2c7e6f57	115	{
2898577e	116	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
2c7e6f57 JS	117	int i;
	118
	119	for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
	120	/*
	121	* If there's been a change in the mask write it back
	122	* to the hardware.
	123	*/
	124	if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
	125	max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
	126	max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
	127	max8998->irq_masks_cur[i]);
	128	}
	129	}
	130
	131	mutex_unlock(&max8998->irqlock);
	132	}
	133
2898577e	134	static void max8998_irq_unmask(struct irq_data *data)
2c7e6f57	135	{
2898577e MB	136	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
	137	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
	138	data->irq);
2c7e6f57 JS	139
	140	max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
	141	}
	142
2898577e	143	static void max8998_irq_mask(struct irq_data *data)
2c7e6f57	144	{
2898577e MB	145	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
	146	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
	147	data->irq);
2c7e6f57 JS	148
	149	max8998->irq_masks_cur[irq_data->reg - 1] \|= irq_data->mask;
	150	}
	151
	152	static struct irq_chip max8998_irq_chip = {
	153	.name = "max8998",
2898577e MB	154	.irq_bus_lock = max8998_irq_lock,
	155	.irq_bus_sync_unlock = max8998_irq_sync_unlock,
	156	.irq_mask = max8998_irq_mask,
	157	.irq_unmask = max8998_irq_unmask,
2c7e6f57 JS	158	};
	159
	160	static irqreturn_t max8998_irq_thread(int irq, void *data)
	161	{
	162	struct max8998_dev *max8998 = data;
	163	u8 irq_reg[MAX8998_NUM_IRQ_REGS];
	164	int ret;
	165	int i;
	166
	167	ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
	168	MAX8998_NUM_IRQ_REGS, irq_reg);
	169	if (ret < 0) {
	170	dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
	171	ret);
	172	return IRQ_NONE;
	173	}
	174
	175	/* Apply masking */
	176	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
	177	irq_reg[i] &= ~max8998->irq_masks_cur[i];
	178
	179	/* Report */
	180	for (i = 0; i < MAX8998_IRQ_NR; i++) {
443c6ae2 TF	181	if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
	182	irq = irq_find_mapping(max8998->irq_domain, i);
	183	if (WARN_ON(!irq)) {
	184	disable_irq_nosync(max8998->irq);
	185	return IRQ_NONE;
	186	}
	187	handle_nested_irq(irq);
	188	}
2c7e6f57 JS	189	}
	190
	191	return IRQ_HANDLED;
	192	}
	193
cdd137c9 MH	194	int max8998_irq_resume(struct max8998_dev *max8998)
cdd137c9 MH	195	{
443c6ae2 TF	196	if (max8998->irq && max8998->irq_domain)
	197	max8998_irq_thread(max8998->irq, max8998);
	198	return 0;
	199	}
	200
	201	static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
	202	irq_hw_number_t hw)
	203	{
	204	struct max8997_dev *max8998 = d->host_data;
	205
	206	irq_set_chip_data(irq, max8998);
	207	irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
	208	irq_set_nested_thread(irq, 1);
	209	#ifdef CONFIG_ARM
	210	set_irq_flags(irq, IRQF_VALID);
	211	#else
	212	irq_set_noprobe(irq);
	213	#endif
cdd137c9 MH	214	return 0;
	215	}
	216
443c6ae2 TF	217	static struct irq_domain_ops max8998_irq_domain_ops = {
	218	.map = max8998_irq_domain_map,
	219	};
	220
2c7e6f57 JS	221	int max8998_irq_init(struct max8998_dev *max8998)
	222	{
	223	int i;
2c7e6f57	224	int ret;
443c6ae2	225	struct irq_domain *domain;
2c7e6f57 JS	226
	227	if (!max8998->irq) {
	228	dev_warn(max8998->dev,
	229	"No interrupt specified, no interrupts\n");
2c7e6f57 JS	230	return 0;
	231	}
	232
	233	mutex_init(&max8998->irqlock);
	234
	235	/* Mask the individual interrupt sources */
	236	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
	237	max8998->irq_masks_cur[i] = 0xff;
	238	max8998->irq_masks_cache[i] = 0xff;
	239	max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
	240	}
	241
	242	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
	243	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
	244
443c6ae2 TF	245	domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
	246	max8998->irq_base, &max8998_irq_domain_ops, max8998);
	247	if (!domain) {
	248	dev_err(max8998->dev, "could not create irq domain\n");
	249	return -ENODEV;
2c7e6f57	250	}
443c6ae2	251	max8998->irq_domain = domain;
2c7e6f57 JS	252
	253	ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
	254	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	255	"max8998-irq", max8998);
	256	if (ret) {
	257	dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
	258	max8998->irq, ret);
	259	return ret;
	260	}
	261
	262	if (!max8998->ono)
	263	return 0;
	264
	265	ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
	266	IRQF_TRIGGER_FALLING \| IRQF_TRIGGER_RISING \|
	267	IRQF_ONESHOT, "max8998-ono", max8998);
	268	if (ret)
	269	dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
	270	max8998->ono, ret);
	271
	272	return 0;
	273	}
	274
	275	void max8998_irq_exit(struct max8998_dev *max8998)
	276	{
1558b51e AL	277	if (max8998->ono)
	278	free_irq(max8998->ono, max8998);
	279
2c7e6f57 JS	280	if (max8998->irq)
	281	free_irq(max8998->irq, max8998);
	282	}