[deliverable/linux.git] / drivers / mfd / mt6397-core.c

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Flora Fu, MediaTek
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6397/registers.h>
#include <linux/mfd/mt6323/registers.h>

#define MT6397_RTC_BASE		0xe000
#define MT6397_RTC_SIZE		0x3e

#define MT6323_CID_CODE		0x23
#define MT6391_CID_CODE		0x91
#define MT6397_CID_CODE		0x97

static const struct resource mt6397_rtc_resources[] = {
	{
		.start = MT6397_RTC_BASE,
		.end   = MT6397_RTC_BASE + MT6397_RTC_SIZE,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MT6397_IRQ_RTC,
		.end   = MT6397_IRQ_RTC,
		.flags = IORESOURCE_IRQ,
	},
};

static const struct mfd_cell mt6323_devs[] = {
	{
		.name = "mt6323-regulator",
		.of_compatible = "mediatek,mt6323-regulator"
	},
};

static const struct mfd_cell mt6397_devs[] = {
	{
		.name = "mt6397-rtc",
		.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
		.resources = mt6397_rtc_resources,
		.of_compatible = "mediatek,mt6397-rtc",
	}, {
		.name = "mt6397-regulator",
		.of_compatible = "mediatek,mt6397-regulator",
	}, {
		.name = "mt6397-codec",
		.of_compatible = "mediatek,mt6397-codec",
	}, {
		.name = "mt6397-clk",
		.of_compatible = "mediatek,mt6397-clk",
	}, {
		.name = "mt6397-pinctrl",
		.of_compatible = "mediatek,mt6397-pinctrl",
	},
};

static void mt6397_irq_lock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	mutex_lock(&mt6397->irqlock);
}

static void mt6397_irq_sync_unlock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	regmap_write(mt6397->regmap, mt6397->int_con[0],
		     mt6397->irq_masks_cur[0]);
	regmap_write(mt6397->regmap, mt6397->int_con[1],
		     mt6397->irq_masks_cur[1]);

	mutex_unlock(&mt6397->irqlock);
}

static void mt6397_irq_disable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
}

static void mt6397_irq_enable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] |= BIT(shift);
}

#ifdef CONFIG_PM_SLEEP
static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	int shift = irq_data->hwirq & 0xf;
	int reg = irq_data->hwirq >> 4;

	if (on)
		mt6397->wake_mask[reg] |= BIT(shift);
	else
		mt6397->wake_mask[reg] &= ~BIT(shift);

	return 0;
}
#else
#define mt6397_irq_set_wake NULL
#endif

static struct irq_chip mt6397_irq_chip = {
	.name = "mt6397-irq",
	.irq_bus_lock = mt6397_irq_lock,
	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	.irq_enable = mt6397_irq_enable,
	.irq_disable = mt6397_irq_disable,
	.irq_set_wake = mt6397_irq_set_wake,
};

static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
		int irqbase)
{
	unsigned int status;
	int i, irq, ret;

	ret = regmap_read(mt6397->regmap, reg, &status);
	if (ret) {
		dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
		return;
	}

	for (i = 0; i < 16; i++) {
		if (status & BIT(i)) {
			irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
			if (irq)
				handle_nested_irq(irq);
		}
	}

	regmap_write(mt6397->regmap, reg, status);
}

static irqreturn_t mt6397_irq_thread(int irq, void *data)
{
	struct mt6397_chip *mt6397 = data;

	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);

	return IRQ_HANDLED;
}

static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
					irq_hw_number_t hw)
{
	struct mt6397_chip *mt6397 = d->host_data;

	irq_set_chip_data(irq, mt6397);
	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	irq_set_nested_thread(irq, 1);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mt6397_irq_domain_ops = {
	.map = mt6397_irq_domain_map,
};

static int mt6397_irq_init(struct mt6397_chip *mt6397)
{
	int ret;

	mutex_init(&mt6397->irqlock);

	/* Mask all interrupt sources */
	regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
	regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);

	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
		MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
	if (!mt6397->irq_domain) {
		dev_err(mt6397->dev, "could not create irq domain\n");
		return -ENOMEM;
	}

	ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
		mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
	if (ret) {
		dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
			mt6397->irq, ret);
		return ret;
	}

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mt6397_irq_suspend(struct device *dev)
{
	struct mt6397_chip *chip = dev_get_drvdata(dev);

	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);

	enable_irq_wake(chip->irq);

	return 0;
}

static int mt6397_irq_resume(struct device *dev)
{
	struct mt6397_chip *chip = dev_get_drvdata(dev);

	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);

	disable_irq_wake(chip->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
			mt6397_irq_resume);

static int mt6397_probe(struct platform_device *pdev)
{
	int ret;
	unsigned int id;
	struct mt6397_chip *pmic;

	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	if (!pmic)
		return -ENOMEM;

	pmic->dev = &pdev->dev;

	/*
	 * mt6397 MFD is child device of soc pmic wrapper.
	 * Regmap is set from its parent.
	 */
	pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	if (!pmic->regmap)
		return -ENODEV;

	platform_set_drvdata(pdev, pmic);

	ret = regmap_read(pmic->regmap, MT6397_CID, &id);
	if (ret) {
		dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
		goto fail_irq;
	}

	switch (id & 0xff) {
	case MT6323_CID_CODE:
		pmic->int_con[0] = MT6323_INT_CON0;
		pmic->int_con[1] = MT6323_INT_CON1;
		pmic->int_status[0] = MT6323_INT_STATUS0;
		pmic->int_status[1] = MT6323_INT_STATUS1;
		ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
				ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
		break;

	case MT6397_CID_CODE:
	case MT6391_CID_CODE:
		pmic->int_con[0] = MT6397_INT_CON0;
		pmic->int_con[1] = MT6397_INT_CON1;
		pmic->int_status[0] = MT6397_INT_STATUS0;
		pmic->int_status[1] = MT6397_INT_STATUS1;
		ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
				ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
		break;

	default:
		dev_err(&pdev->dev, "unsupported chip: %d\n", id);
		ret = -ENODEV;
		break;
	}

	pmic->irq = platform_get_irq(pdev, 0);
	if (pmic->irq > 0) {
		ret = mt6397_irq_init(pmic);
		if (ret)
			return ret;
	}

fail_irq:
	if (ret) {
		irq_domain_remove(pmic->irq_domain);
		dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
	}

	return ret;
}

static int mt6397_remove(struct platform_device *pdev)
{
	mfd_remove_devices(&pdev->dev);

	return 0;
}

static const struct of_device_id mt6397_of_match[] = {
	{ .compatible = "mediatek,mt6397" },
	{ .compatible = "mediatek,mt6323" },
	{ }
};
MODULE_DEVICE_TABLE(of, mt6397_of_match);

static const struct platform_device_id mt6397_id[] = {
	{ "mt6397", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, mt6397_id);

static struct platform_driver mt6397_driver = {
	.probe = mt6397_probe,
	.remove = mt6397_remove,
	.driver = {
		.name = "mt6397",
		.of_match_table = of_match_ptr(mt6397_of_match),
		.pm = &mt6397_pm_ops,
	},
	.id_table = mt6397_id,
};

module_platform_driver(mt6397_driver);

MODULE_AUTHOR("Flora Fu, MediaTek");
MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
MODULE_LICENSE("GPL");
Commit	Line	Data
6df8dd5c FF	1	/*
	2	* Copyright (c) 2014 MediaTek Inc.
	3	* Author: Flora Fu, MediaTek
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/interrupt.h>
	16	#include <linux/module.h>
	17	#include <linux/of_device.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/regmap.h>
	20	#include <linux/mfd/core.h>
	21	#include <linux/mfd/mt6397/core.h>
44760cf3	22	#include <linux/mfd/mt6323/core.h>
6df8dd5c	23	#include <linux/mfd/mt6397/registers.h>
44760cf3	24	#include <linux/mfd/mt6323/registers.h>
6df8dd5c	25
a5d7ea09 EH	26	#define MT6397_RTC_BASE 0xe000
	27	#define MT6397_RTC_SIZE 0x3e
	28
44760cf3	29	#define MT6323_CID_CODE 0x23
1d2c25ed JC	30	#define MT6391_CID_CODE 0x91
	31	#define MT6397_CID_CODE 0x97
	32
a5d7ea09 EH	33	static const struct resource mt6397_rtc_resources[] = {
	34	{
	35	.start = MT6397_RTC_BASE,
	36	.end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
	37	.flags = IORESOURCE_MEM,
	38	},
	39	{
	40	.start = MT6397_IRQ_RTC,
	41	.end = MT6397_IRQ_RTC,
	42	.flags = IORESOURCE_IRQ,
	43	},
	44	};
	45
44760cf3 JC	46	static const struct mfd_cell mt6323_devs[] = {
	47	{
	48	.name = "mt6323-regulator",
	49	.of_compatible = "mediatek,mt6323-regulator"
	50	},
	51	};
	52
6df8dd5c FF	53	static const struct mfd_cell mt6397_devs[] = {
	54	{
	55	.name = "mt6397-rtc",
a5d7ea09 EH	56	.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
a5d7ea09 EH	57	.resources = mt6397_rtc_resources,
6df8dd5c FF	58	.of_compatible = "mediatek,mt6397-rtc",
	59	}, {
	60	.name = "mt6397-regulator",
	61	.of_compatible = "mediatek,mt6397-regulator",
	62	}, {
	63	.name = "mt6397-codec",
	64	.of_compatible = "mediatek,mt6397-codec",
	65	}, {
	66	.name = "mt6397-clk",
	67	.of_compatible = "mediatek,mt6397-clk",
cf55078b HY	68	}, {
	69	.name = "mt6397-pinctrl",
	70	.of_compatible = "mediatek,mt6397-pinctrl",
6df8dd5c FF	71	},
	72	};
	73
	74	static void mt6397_irq_lock(struct irq_data *data)
	75	{
1e84aa44	76	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	77
	78	mutex_lock(&mt6397->irqlock);
	79	}
	80
	81	static void mt6397_irq_sync_unlock(struct irq_data *data)
	82	{
1e84aa44	83	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c	84
feec4799 JC	85	regmap_write(mt6397->regmap, mt6397->int_con[0],
	86	mt6397->irq_masks_cur[0]);
	87	regmap_write(mt6397->regmap, mt6397->int_con[1],
	88	mt6397->irq_masks_cur[1]);
6df8dd5c FF	89
	90	mutex_unlock(&mt6397->irqlock);
	91	}
	92
	93	static void mt6397_irq_disable(struct irq_data *data)
	94	{
1e84aa44	95	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	96	int shift = data->hwirq & 0xf;
	97	int reg = data->hwirq >> 4;
	98
	99	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
	100	}
	101
	102	static void mt6397_irq_enable(struct irq_data *data)
	103	{
1e84aa44	104	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	105	int shift = data->hwirq & 0xf;
	106	int reg = data->hwirq >> 4;
	107
	108	mt6397->irq_masks_cur[reg] \|= BIT(shift);
	109	}
	110
f3151ab4 HC	111	#ifdef CONFIG_PM_SLEEP
	112	static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
	113	{
	114	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	115	int shift = irq_data->hwirq & 0xf;
	116	int reg = irq_data->hwirq >> 4;
	117
	118	if (on)
	119	mt6397->wake_mask[reg] \|= BIT(shift);
	120	else
	121	mt6397->wake_mask[reg] &= ~BIT(shift);
	122
	123	return 0;
	124	}
	125	#else
	126	#define mt6397_irq_set_wake NULL
	127	#endif
	128
6df8dd5c FF	129	static struct irq_chip mt6397_irq_chip = {
	130	.name = "mt6397-irq",
	131	.irq_bus_lock = mt6397_irq_lock,
	132	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	133	.irq_enable = mt6397_irq_enable,
	134	.irq_disable = mt6397_irq_disable,
f3151ab4	135	.irq_set_wake = mt6397_irq_set_wake,
6df8dd5c FF	136	};
	137
	138	static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
	139	int irqbase)
	140	{
	141	unsigned int status;
	142	int i, irq, ret;
	143
	144	ret = regmap_read(mt6397->regmap, reg, &status);
	145	if (ret) {
	146	dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
	147	return;
	148	}
	149
	150	for (i = 0; i < 16; i++) {
	151	if (status & BIT(i)) {
	152	irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
	153	if (irq)
	154	handle_nested_irq(irq);
	155	}
	156	}
	157
	158	regmap_write(mt6397->regmap, reg, status);
	159	}
	160
	161	static irqreturn_t mt6397_irq_thread(int irq, void *data)
	162	{
	163	struct mt6397_chip *mt6397 = data;
	164
feec4799 JC	165	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
feec4799 JC	166	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
6df8dd5c FF	167
	168	return IRQ_HANDLED;
	169	}
	170
	171	static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
	172	irq_hw_number_t hw)
	173	{
	174	struct mt6397_chip *mt6397 = d->host_data;
	175
	176	irq_set_chip_data(irq, mt6397);
	177	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	178	irq_set_nested_thread(irq, 1);
6df8dd5c	179	irq_set_noprobe(irq);
6df8dd5c FF	180
	181	return 0;
	182	}
	183
7ce7b26f	184	static const struct irq_domain_ops mt6397_irq_domain_ops = {
6df8dd5c FF	185	.map = mt6397_irq_domain_map,
	186	};
	187
	188	static int mt6397_irq_init(struct mt6397_chip *mt6397)
	189	{
	190	int ret;
	191
	192	mutex_init(&mt6397->irqlock);
	193
	194	/* Mask all interrupt sources */
feec4799 JC	195	regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
feec4799 JC	196	regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
6df8dd5c FF	197
	198	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
	199	MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
	200	if (!mt6397->irq_domain) {
	201	dev_err(mt6397->dev, "could not create irq domain\n");
	202	return -ENOMEM;
	203	}
	204
	205	ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
	206	mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
	207	if (ret) {
	208	dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
	209	mt6397->irq, ret);
	210	return ret;
	211	}
	212
	213	return 0;
	214	}
	215
f3151ab4 HC	216	#ifdef CONFIG_PM_SLEEP
	217	static int mt6397_irq_suspend(struct device *dev)
	218	{
	219	struct mt6397_chip *chip = dev_get_drvdata(dev);
	220
feec4799 JC	221	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
feec4799 JC	222	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
f3151ab4 HC	223
	224	enable_irq_wake(chip->irq);
	225
	226	return 0;
	227	}
	228
	229	static int mt6397_irq_resume(struct device *dev)
	230	{
	231	struct mt6397_chip *chip = dev_get_drvdata(dev);
	232
feec4799 JC	233	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
feec4799 JC	234	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
f3151ab4 HC	235
	236	disable_irq_wake(chip->irq);
	237
	238	return 0;
	239	}
	240	#endif
	241
	242	static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
	243	mt6397_irq_resume);
	244
6df8dd5c FF	245	static int mt6397_probe(struct platform_device *pdev)
	246	{
	247	int ret;
1d2c25ed JC	248	unsigned int id;
1d2c25ed JC	249	struct mt6397_chip *pmic;
6df8dd5c	250
1d2c25ed JC	251	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1d2c25ed JC	252	if (!pmic)
6df8dd5c FF	253	return -ENOMEM;
6df8dd5c FF	254
1d2c25ed	255	pmic->dev = &pdev->dev;
feec4799	256
6df8dd5c FF	257	/*
	258	* mt6397 MFD is child device of soc pmic wrapper.
	259	* Regmap is set from its parent.
	260	*/
1d2c25ed JC	261	pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
1d2c25ed JC	262	if (!pmic->regmap)
6df8dd5c FF	263	return -ENODEV;
6df8dd5c FF	264
1d2c25ed JC	265	platform_set_drvdata(pdev, pmic);
	266
	267	ret = regmap_read(pmic->regmap, MT6397_CID, &id);
	268	if (ret) {
	269	dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
	270	goto fail_irq;
	271	}
	272
	273	switch (id & 0xff) {
44760cf3 JC	274	case MT6323_CID_CODE:
	275	pmic->int_con[0] = MT6323_INT_CON0;
	276	pmic->int_con[1] = MT6323_INT_CON1;
	277	pmic->int_status[0] = MT6323_INT_STATUS0;
	278	pmic->int_status[1] = MT6323_INT_STATUS1;
	279	ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
	280	ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
	281	break;
	282
1d2c25ed JC	283	case MT6397_CID_CODE:
	284	case MT6391_CID_CODE:
	285	pmic->int_con[0] = MT6397_INT_CON0;
	286	pmic->int_con[1] = MT6397_INT_CON1;
	287	pmic->int_status[0] = MT6397_INT_STATUS0;
	288	pmic->int_status[1] = MT6397_INT_STATUS1;
	289	ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
	290	ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
	291	break;
	292
	293	default:
	294	dev_err(&pdev->dev, "unsupported chip: %d\n", id);
	295	ret = -ENODEV;
	296	break;
	297	}
6df8dd5c	298
1d2c25ed JC	299	pmic->irq = platform_get_irq(pdev, 0);
	300	if (pmic->irq > 0) {
	301	ret = mt6397_irq_init(pmic);
6df8dd5c FF	302	if (ret)
	303	return ret;
	304	}
	305
1d2c25ed JC	306	fail_irq:
	307	if (ret) {
	308	irq_domain_remove(pmic->irq_domain);
6df8dd5c	309	dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
1d2c25ed	310	}
6df8dd5c FF	311
	312	return ret;
	313	}
	314
	315	static int mt6397_remove(struct platform_device *pdev)
	316	{
	317	mfd_remove_devices(&pdev->dev);
	318
	319	return 0;
	320	}
	321
	322	static const struct of_device_id mt6397_of_match[] = {
	323	{ .compatible = "mediatek,mt6397" },
44760cf3	324	{ .compatible = "mediatek,mt6323" },
6df8dd5c FF	325	{ }
	326	};
	327	MODULE_DEVICE_TABLE(of, mt6397_of_match);
	328
e1d9a109 JMC	329	static const struct platform_device_id mt6397_id[] = {
	330	{ "mt6397", 0 },
	331	{ },
	332	};
	333	MODULE_DEVICE_TABLE(platform, mt6397_id);
	334
6df8dd5c FF	335	static struct platform_driver mt6397_driver = {
	336	.probe = mt6397_probe,
	337	.remove = mt6397_remove,
	338	.driver = {
	339	.name = "mt6397",
	340	.of_match_table = of_match_ptr(mt6397_of_match),
f3151ab4	341	.pm = &mt6397_pm_ops,
6df8dd5c	342	},
e1d9a109	343	.id_table = mt6397_id,
6df8dd5c FF	344	};
	345
	346	module_platform_driver(mt6397_driver);
	347
	348	MODULE_AUTHOR("Flora Fu, MediaTek");
	349	MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
	350	MODULE_LICENSE("GPL");