[deliverable/linux.git] / drivers / mfd / pm8921-core.c

/*
 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/ssbi.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
#include <linux/mfd/core.h>

#define	SSBI_REG_ADDR_IRQ_BASE		0x1BB

#define	SSBI_REG_ADDR_IRQ_ROOT		(SSBI_REG_ADDR_IRQ_BASE + 0)
#define	SSBI_REG_ADDR_IRQ_M_STATUS1	(SSBI_REG_ADDR_IRQ_BASE + 1)
#define	SSBI_REG_ADDR_IRQ_M_STATUS2	(SSBI_REG_ADDR_IRQ_BASE + 2)
#define	SSBI_REG_ADDR_IRQ_M_STATUS3	(SSBI_REG_ADDR_IRQ_BASE + 3)
#define	SSBI_REG_ADDR_IRQ_M_STATUS4	(SSBI_REG_ADDR_IRQ_BASE + 4)
#define	SSBI_REG_ADDR_IRQ_BLK_SEL	(SSBI_REG_ADDR_IRQ_BASE + 5)
#define	SSBI_REG_ADDR_IRQ_IT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 6)
#define	SSBI_REG_ADDR_IRQ_CONFIG	(SSBI_REG_ADDR_IRQ_BASE + 7)
#define	SSBI_REG_ADDR_IRQ_RT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 8)

#define	PM_IRQF_LVL_SEL			0x01	/* level select */
#define	PM_IRQF_MASK_FE			0x02	/* mask falling edge */
#define	PM_IRQF_MASK_RE			0x04	/* mask rising edge */
#define	PM_IRQF_CLR			0x08	/* clear interrupt */
#define	PM_IRQF_BITS_MASK		0x70
#define	PM_IRQF_BITS_SHIFT		4
#define	PM_IRQF_WRITE			0x80

#define	PM_IRQF_MASK_ALL		(PM_IRQF_MASK_FE | \
					PM_IRQF_MASK_RE)

#define REG_HWREV		0x002  /* PMIC4 revision */
#define REG_HWREV_2		0x0E8  /* PMIC4 revision 2 */

#define PM8921_NR_IRQS		256

struct pm_irq_chip {
	struct regmap		*regmap;
	spinlock_t		pm_irq_lock;
	struct irq_domain	*irqdomain;
	unsigned int		num_irqs;
	unsigned int		num_blocks;
	unsigned int		num_masters;
	u8			config[0];
};

static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
				 unsigned int *ip)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
	if (rc)
		pr_err("Failed Reading Status rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int
pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	cp |= PM_IRQF_WRITE;
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
	if (rc)
		pr_err("Failed Configuring IRQ rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
{
	int pmirq, irq, i, ret = 0;
	unsigned int bits;

	ret = pm8xxx_read_block_irq(chip, block, &bits);
	if (ret) {
		pr_err("Failed reading %d block ret=%d", block, ret);
		return ret;
	}
	if (!bits) {
		pr_err("block bit set in master but no irqs: %d", block);
		return 0;
	}

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & (1 << i)) {
			pmirq = block * 8 + i;
			irq = irq_find_mapping(chip->irqdomain, pmirq);
			generic_handle_irq(irq);
		}
	}
	return 0;
}

static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
{
	unsigned int blockbits;
	int block_number, i, ret = 0;

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
			  &blockbits);
	if (ret) {
		pr_err("Failed to read master %d ret=%d\n", master, ret);
		return ret;
	}
	if (!blockbits) {
		pr_err("master bit set in root but no blocks: %d", master);
		return 0;
	}

	for (i = 0; i < 8; i++)
		if (blockbits & (1 << i)) {
			block_number = master * 8 + i;	/* block # */
			ret |= pm8xxx_irq_block_handler(chip, block_number);
		}
	return ret;
}

static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	unsigned int root;
	int	i, ret, masters = 0;

	chained_irq_enter(irq_chip, desc);

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
	if (ret) {
		pr_err("Can't read root status ret=%d\n", ret);
		return;
	}

	/* on pm8xxx series masters start from bit 1 of the root */
	masters = root >> 1;

	/* Read allowed masters for blocks. */
	for (i = 0; i < chip->num_masters; i++)
		if (masters & (1 << i))
			pm8xxx_irq_master_handler(chip, i);

	chained_irq_exit(irq_chip, desc);
}

static void pm8xxx_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
	pm8xxx_config_irq(chip, block, config);
}

static void pm8xxx_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq];
	pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit;
	u8 block, config;

	block = pmirq / 8;
	irq_bit  = pmirq % 8;

	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
							| PM_IRQF_MASK_ALL;
	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
		if (flow_type & IRQF_TRIGGER_RISING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		if (flow_type & IRQF_TRIGGER_FALLING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	} else {
		chip->config[pmirq] |= PM_IRQF_LVL_SEL;

		if (flow_type & IRQF_TRIGGER_HIGH)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		else
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	}

	config = chip->config[pmirq] | PM_IRQF_CLR;
	return pm8xxx_config_irq(chip, block, config);
}

static struct irq_chip pm8xxx_irq_chip = {
	.name		= "pm8xxx",
	.irq_mask_ack	= pm8xxx_irq_mask_ack,
	.irq_unmask	= pm8xxx_irq_unmask,
	.irq_set_type	= pm8xxx_irq_set_type,
	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};

static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
				   irq_hw_number_t hwirq)
{
	struct pm_irq_chip *chip = d->host_data;

	irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
	irq_set_chip_data(irq, chip);
#ifdef CONFIG_ARM
	set_irq_flags(irq, IRQF_VALID);
#else
	irq_set_noprobe(irq);
#endif
	return 0;
}

static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
	.xlate = irq_domain_xlate_twocell,
	.map = pm8xxx_irq_domain_map,
};

static const struct regmap_config ssbi_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.max_register = 0x3ff,
	.fast_io = true,
	.reg_read = ssbi_reg_read,
	.reg_write = ssbi_reg_write
};

static const struct of_device_id pm8921_id_table[] = {
	{ .compatible = "qcom,pm8058", },
	{ .compatible = "qcom,pm8921", },
	{ }
};
MODULE_DEVICE_TABLE(of, pm8921_id_table);

static int pm8921_probe(struct platform_device *pdev)
{
	struct regmap *regmap;
	int irq, rc;
	unsigned int val;
	u32 rev;
	struct pm_irq_chip *chip;
	unsigned int nirqs = PM8921_NR_IRQS;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
				  &ssbi_regmap_config);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	/* Read PMIC chip revision */
	rc = regmap_read(regmap, REG_HWREV, &val);
	if (rc) {
		pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
		return rc;
	}
	pr_info("PMIC revision 1: %02X\n", val);
	rev = val;

	/* Read PMIC chip revision 2 */
	rc = regmap_read(regmap, REG_HWREV_2, &val);
	if (rc) {
		pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
			REG_HWREV_2, rc);
		return rc;
	}
	pr_info("PMIC revision 2: %02X\n", val);
	rev |= val << BITS_PER_BYTE;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
					sizeof(chip->config[0]) * nirqs,
					GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	platform_set_drvdata(pdev, chip);
	chip->regmap = regmap;
	chip->num_irqs = nirqs;
	chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
	spin_lock_init(&chip->pm_irq_lock);

	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
						&pm8xxx_irq_domain_ops,
						chip);
	if (!chip->irqdomain)
		return -ENODEV;

	irq_set_handler_data(irq, chip);
	irq_set_chained_handler(irq, pm8xxx_irq_handler);
	irq_set_irq_wake(irq, 1);

	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	if (rc) {
		irq_set_chained_handler(irq, NULL);
		irq_set_handler_data(irq, NULL);
		irq_domain_remove(chip->irqdomain);
	}

	return rc;
}

static int pm8921_remove_child(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pm8921_remove(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct pm_irq_chip *chip = platform_get_drvdata(pdev);

	device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
	irq_set_chained_handler(irq, NULL);
	irq_set_handler_data(irq, NULL);
	irq_domain_remove(chip->irqdomain);

	return 0;
}

static struct platform_driver pm8921_driver = {
	.probe		= pm8921_probe,
	.remove		= pm8921_remove,
	.driver		= {
		.name	= "pm8921-core",
		.owner	= THIS_MODULE,
		.of_match_table = pm8921_id_table,
	},
};

static int __init pm8921_init(void)
{
	return platform_driver_register(&pm8921_driver);
}
subsys_initcall(pm8921_init);

static void __exit pm8921_exit(void)
{
	platform_driver_unregister(&pm8921_driver);
}
module_exit(pm8921_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("PMIC 8921 core driver");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:pm8921-core");
Commit	Line	Data
cbdb53e1 AD	1	/*
	2	* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#define pr_fmt(fmt) "%s: " fmt, __func__
	15
	16	#include <linux/kernel.h>
bc866fc7	17	#include <linux/interrupt.h>
cced3548	18	#include <linux/irqchip/chained_irq.h>
bc866fc7	19	#include <linux/irq.h>
dc1a95cc	20	#include <linux/irqdomain.h>
ef310f4b	21	#include <linux/module.h>
cbdb53e1 AD	22	#include <linux/platform_device.h>
cbdb53e1 AD	23	#include <linux/slab.h>
c013f0a5	24	#include <linux/err.h>
ce44bf5b	25	#include <linux/ssbi.h>
e7b81fca	26	#include <linux/regmap.h>
dc1a95cc	27	#include <linux/of_platform.h>
cbdb53e1	28	#include <linux/mfd/core.h>
bc866fc7 SB	29
	30	#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
	31
	32	#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
	33	#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
	34	#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
	35	#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
	36	#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
	37	#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
	38	#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
	39	#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
	40	#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
	41
	42	#define PM_IRQF_LVL_SEL 0x01 /* level select */
	43	#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
	44	#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
	45	#define PM_IRQF_CLR 0x08 /* clear interrupt */
	46	#define PM_IRQF_BITS_MASK 0x70
	47	#define PM_IRQF_BITS_SHIFT 4
	48	#define PM_IRQF_WRITE 0x80
	49
	50	#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE \| \
	51	PM_IRQF_MASK_RE)
cbdb53e1 AD	52
	53	#define REG_HWREV 0x002 /* PMIC4 revision */
	54	#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
	55
dc1a95cc SB	56	#define PM8921_NR_IRQS 256
dc1a95cc SB	57
bc866fc7	58	struct pm_irq_chip {
e7b81fca	59	struct regmap *regmap;
bc866fc7	60	spinlock_t pm_irq_lock;
dc1a95cc	61	struct irq_domain *irqdomain;
bc866fc7 SB	62	unsigned int num_irqs;
	63	unsigned int num_blocks;
	64	unsigned int num_masters;
	65	u8 config[0];
	66	};
	67
e7b81fca SB	68	static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
e7b81fca SB	69	unsigned int *ip)
bc866fc7 SB	70	{
	71	int rc;
	72
	73	spin_lock(&chip->pm_irq_lock);
e7b81fca	74	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	75	if (rc) {
	76	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	77	goto bail;
	78	}
	79
e7b81fca	80	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
bc866fc7 SB	81	if (rc)
	82	pr_err("Failed Reading Status rc=%d\n", rc);
	83	bail:
	84	spin_unlock(&chip->pm_irq_lock);
	85	return rc;
	86	}
	87
e7b81fca SB	88	static int
e7b81fca SB	89	pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
bc866fc7 SB	90	{
	91	int rc;
	92
	93	spin_lock(&chip->pm_irq_lock);
e7b81fca	94	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	95	if (rc) {
	96	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	97	goto bail;
	98	}
	99
	100	cp \|= PM_IRQF_WRITE;
e7b81fca	101	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
bc866fc7 SB	102	if (rc)
	103	pr_err("Failed Configuring IRQ rc=%d\n", rc);
	104	bail:
	105	spin_unlock(&chip->pm_irq_lock);
	106	return rc;
	107	}
	108
	109	static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
	110	{
	111	int pmirq, irq, i, ret = 0;
e7b81fca	112	unsigned int bits;
bc866fc7 SB	113
	114	ret = pm8xxx_read_block_irq(chip, block, &bits);
	115	if (ret) {
	116	pr_err("Failed reading %d block ret=%d", block, ret);
	117	return ret;
	118	}
	119	if (!bits) {
	120	pr_err("block bit set in master but no irqs: %d", block);
	121	return 0;
	122	}
	123
	124	/* Check IRQ bits */
	125	for (i = 0; i < 8; i++) {
	126	if (bits & (1 << i)) {
	127	pmirq = block * 8 + i;
dc1a95cc	128	irq = irq_find_mapping(chip->irqdomain, pmirq);
bc866fc7 SB	129	generic_handle_irq(irq);
	130	}
	131	}
	132	return 0;
	133	}
	134
	135	static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
	136	{
e7b81fca	137	unsigned int blockbits;
bc866fc7 SB	138	int block_number, i, ret = 0;
bc866fc7 SB	139
e7b81fca SB	140	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
e7b81fca SB	141	&blockbits);
bc866fc7 SB	142	if (ret) {
	143	pr_err("Failed to read master %d ret=%d\n", master, ret);
	144	return ret;
	145	}
	146	if (!blockbits) {
	147	pr_err("master bit set in root but no blocks: %d", master);
	148	return 0;
	149	}
	150
	151	for (i = 0; i < 8; i++)
	152	if (blockbits & (1 << i)) {
	153	block_number = master * 8 + i; /* block # */
	154	ret \|= pm8xxx_irq_block_handler(chip, block_number);
	155	}
	156	return ret;
	157	}
	158
	159	static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
	160	{
	161	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	162	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
e7b81fca	163	unsigned int root;
bc866fc7 SB	164	int i, ret, masters = 0;
bc866fc7 SB	165
cced3548 SB	166	chained_irq_enter(irq_chip, desc);
cced3548 SB	167
e7b81fca	168	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
bc866fc7 SB	169	if (ret) {
	170	pr_err("Can't read root status ret=%d\n", ret);
	171	return;
	172	}
	173
	174	/* on pm8xxx series masters start from bit 1 of the root */
	175	masters = root >> 1;
	176
	177	/* Read allowed masters for blocks. */
	178	for (i = 0; i < chip->num_masters; i++)
	179	if (masters & (1 << i))
	180	pm8xxx_irq_master_handler(chip, i);
	181
cced3548	182	chained_irq_exit(irq_chip, desc);
bc866fc7 SB	183	}
	184
	185	static void pm8xxx_irq_mask_ack(struct irq_data *d)
	186	{
	187	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	188	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	189	u8 block, config;
	190
	191	block = pmirq / 8;
bc866fc7 SB	192
	193	config = chip->config[pmirq] \| PM_IRQF_MASK_ALL \| PM_IRQF_CLR;
	194	pm8xxx_config_irq(chip, block, config);
	195	}
	196
	197	static void pm8xxx_irq_unmask(struct irq_data *d)
	198	{
	199	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	200	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	201	u8 block, config;
	202
	203	block = pmirq / 8;
bc866fc7 SB	204
	205	config = chip->config[pmirq];
	206	pm8xxx_config_irq(chip, block, config);
	207	}
	208
	209	static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
	210	{
	211	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc SB	212	unsigned int pmirq = irqd_to_hwirq(d);
dc1a95cc SB	213	int irq_bit;
bc866fc7 SB	214	u8 block, config;
	215
	216	block = pmirq / 8;
bc866fc7 SB	217	irq_bit = pmirq % 8;
	218
	219	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
	220	\| PM_IRQF_MASK_ALL;
	221	if (flow_type & (IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING)) {
	222	if (flow_type & IRQF_TRIGGER_RISING)
	223	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	224	if (flow_type & IRQF_TRIGGER_FALLING)
	225	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	226	} else {
	227	chip->config[pmirq] \|= PM_IRQF_LVL_SEL;
	228
	229	if (flow_type & IRQF_TRIGGER_HIGH)
	230	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	231	else
	232	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	233	}
	234
	235	config = chip->config[pmirq] \| PM_IRQF_CLR;
	236	return pm8xxx_config_irq(chip, block, config);
	237	}
	238
bc866fc7 SB	239	static struct irq_chip pm8xxx_irq_chip = {
	240	.name = "pm8xxx",
	241	.irq_mask_ack = pm8xxx_irq_mask_ack,
	242	.irq_unmask = pm8xxx_irq_unmask,
	243	.irq_set_type = pm8xxx_irq_set_type,
d2d24ad1	244	.flags = IRQCHIP_MASK_ON_SUSPEND \| IRQCHIP_SKIP_SET_WAKE,
bc866fc7 SB	245	};
bc866fc7 SB	246
dc1a95cc SB	247	static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
	248	irq_hw_number_t hwirq)
	249	{
	250	struct pm_irq_chip *chip = d->host_data;
bc866fc7	251
dc1a95cc SB	252	irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
dc1a95cc SB	253	irq_set_chip_data(irq, chip);
bc866fc7	254	#ifdef CONFIG_ARM
dc1a95cc	255	set_irq_flags(irq, IRQF_VALID);
bc866fc7	256	#else
dc1a95cc	257	irq_set_noprobe(irq);
bc866fc7	258	#endif
bc866fc7 SB	259	return 0;
	260	}
	261
dc1a95cc SB	262	static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
	263	.xlate = irq_domain_xlate_twocell,
	264	.map = pm8xxx_irq_domain_map,
	265	};
	266
e7b81fca SB	267	static const struct regmap_config ssbi_regmap_config = {
	268	.reg_bits = 16,
	269	.val_bits = 8,
	270	.max_register = 0x3ff,
	271	.fast_io = true,
	272	.reg_read = ssbi_reg_read,
	273	.reg_write = ssbi_reg_write
	274	};
	275
c5865a53 SB	276	static const struct of_device_id pm8921_id_table[] = {
	277	{ .compatible = "qcom,pm8058", },
	278	{ .compatible = "qcom,pm8921", },
	279	{ }
	280	};
	281	MODULE_DEVICE_TABLE(of, pm8921_id_table);
	282
f791be49	283	static int pm8921_probe(struct platform_device *pdev)
cbdb53e1	284	{
e7b81fca	285	struct regmap *regmap;
202f7680	286	int irq, rc;
e7b81fca	287	unsigned int val;
c013f0a5	288	u32 rev;
dc1a95cc SB	289	struct pm_irq_chip *chip;
dc1a95cc SB	290	unsigned int nirqs = PM8921_NR_IRQS;
cbdb53e1	291
dc1a95cc SB	292	irq = platform_get_irq(pdev, 0);
	293	if (irq < 0)
	294	return irq;
cbdb53e1	295
e7b81fca SB	296	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
	297	&ssbi_regmap_config);
	298	if (IS_ERR(regmap))
	299	return PTR_ERR(regmap);
	300
cbdb53e1	301	/* Read PMIC chip revision */
e7b81fca	302	rc = regmap_read(regmap, REG_HWREV, &val);
cbdb53e1 AD	303	if (rc) {
cbdb53e1 AD	304	pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
b2cdcfac	305	return rc;
cbdb53e1 AD	306	}
cbdb53e1 AD	307	pr_info("PMIC revision 1: %02X\n", val);
c013f0a5	308	rev = val;
cbdb53e1 AD	309
cbdb53e1 AD	310	/* Read PMIC chip revision 2 */
e7b81fca	311	rc = regmap_read(regmap, REG_HWREV_2, &val);
cbdb53e1 AD	312	if (rc) {
	313	pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
	314	REG_HWREV_2, rc);
b2cdcfac	315	return rc;
cbdb53e1 AD	316	}
cbdb53e1 AD	317	pr_info("PMIC revision 2: %02X\n", val);
c013f0a5	318	rev \|= val << BITS_PER_BYTE;
cbdb53e1	319
dc1a95cc SB	320	chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
	321	sizeof(chip->config[0]) * nirqs,
	322	GFP_KERNEL);
	323	if (!chip)
	324	return -ENOMEM;
	325
3e87933a	326	platform_set_drvdata(pdev, chip);
e7b81fca	327	chip->regmap = regmap;
dc1a95cc SB	328	chip->num_irqs = nirqs;
	329	chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
	330	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
	331	spin_lock_init(&chip->pm_irq_lock);
	332
	333	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
	334	&pm8xxx_irq_domain_ops,
	335	chip);
	336	if (!chip->irqdomain)
	337	return -ENODEV;
	338
	339	irq_set_handler_data(irq, chip);
	340	irq_set_chained_handler(irq, pm8xxx_irq_handler);
	341	irq_set_irq_wake(irq, 1);
	342
	343	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
c013f0a5	344	if (rc) {
dc1a95cc SB	345	irq_set_chained_handler(irq, NULL);
	346	irq_set_handler_data(irq, NULL);
	347	irq_domain_remove(chip->irqdomain);
c013f0a5 AD	348	}
c013f0a5 AD	349
dc1a95cc SB	350	return rc;
dc1a95cc SB	351	}
c013f0a5	352
dc1a95cc SB	353	static int pm8921_remove_child(struct device dev, void unused)
	354	{
	355	platform_device_unregister(to_platform_device(dev));
cbdb53e1	356	return 0;
cbdb53e1 AD	357	}
cbdb53e1 AD	358
4740f73f	359	static int pm8921_remove(struct platform_device *pdev)
cbdb53e1	360	{
dc1a95cc	361	int irq = platform_get_irq(pdev, 0);
3e87933a	362	struct pm_irq_chip *chip = platform_get_drvdata(pdev);
dc1a95cc SB	363
	364	device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
	365	irq_set_chained_handler(irq, NULL);
	366	irq_set_handler_data(irq, NULL);
	367	irq_domain_remove(chip->irqdomain);
cbdb53e1 AD	368
	369	return 0;
	370	}
	371
	372	static struct platform_driver pm8921_driver = {
	373	.probe = pm8921_probe,
84449216	374	.remove = pm8921_remove,
cbdb53e1 AD	375	.driver = {
	376	.name = "pm8921-core",
	377	.owner = THIS_MODULE,
c5865a53	378	.of_match_table = pm8921_id_table,
cbdb53e1 AD	379	},
	380	};
	381
	382	static int __init pm8921_init(void)
	383	{
	384	return platform_driver_register(&pm8921_driver);
	385	}
	386	subsys_initcall(pm8921_init);
	387
	388	static void __exit pm8921_exit(void)
	389	{
	390	platform_driver_unregister(&pm8921_driver);
	391	}
	392	module_exit(pm8921_exit);
	393
	394	MODULE_LICENSE("GPL v2");
	395	MODULE_DESCRIPTION("PMIC 8921 core driver");
	396	MODULE_VERSION("1.0");
	397	MODULE_ALIAS("platform:pm8921-core");