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mfd: rtsx: Implement driving adjustment to device-dependent callbacks
[deliverable/linux.git] / drivers / mfd / rtsx_pcr.c
CommitLineData
ada8a8a1
WW		 1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/pci.h>
24#include <linux/module.h>
aec17ea1 25#include <linux/slab.h>
ada8a8a1
WW		 26#include <linux/dma-mapping.h>
27#include <linux/highmem.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/idr.h>
31#include <linux/platform_device.h>
32#include <linux/mfd/core.h>
33#include <linux/mfd/rtsx_pci.h>
34#include <asm/unaligned.h>
35
36#include "rtsx_pcr.h"
37
38static bool msi_en = true;
39module_param(msi_en, bool, S_IRUGO | S_IWUSR);
40MODULE_PARM_DESC(msi_en, "Enable MSI");
41
42static DEFINE_IDR(rtsx_pci_idr);
43static DEFINE_SPINLOCK(rtsx_pci_lock);
44
45static struct mfd_cell rtsx_pcr_cells[] = {
46 [RTSX_SD_CARD] = {
47 .name = DRV_NAME_RTSX_PCI_SDMMC,
48 },
49 [RTSX_MS_CARD] = {
50 .name = DRV_NAME_RTSX_PCI_MS,
51 },
52};
53
54static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
58 { 0, }
59};
60
61MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
62
63void rtsx_pci_start_run(struct rtsx_pcr *pcr)
64{
65 /* If pci device removed, don't queue idle work any more */
66 if (pcr->remove_pci)
67 return;
68
69 if (pcr->state != PDEV_STAT_RUN) {
70 pcr->state = PDEV_STAT_RUN;
71 if (pcr->ops->enable_auto_blink)
72 pcr->ops->enable_auto_blink(pcr);
73 }
74
75 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
76}
77EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
78
79int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
80{
81 int i;
82 u32 val = HAIMR_WRITE_START;
83
84 val |= (u32)(addr & 0x3FFF) << 16;
85 val |= (u32)mask << 8;
86 val |= (u32)data;
87
88 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
89
90 for (i = 0; i < MAX_RW_REG_CNT; i++) {
91 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
92 if ((val & HAIMR_TRANS_END) == 0) {
93 if (data != (u8)val)
94 return -EIO;
95 return 0;
96 }
97 }
98
99 return -ETIMEDOUT;
100}
101EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
102
103int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
104{
105 u32 val = HAIMR_READ_START;
106 int i;
107
108 val |= (u32)(addr & 0x3FFF) << 16;
109 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
110
111 for (i = 0; i < MAX_RW_REG_CNT; i++) {
112 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
113 if ((val & HAIMR_TRANS_END) == 0)
114 break;
115 }
116
117 if (i >= MAX_RW_REG_CNT)
118 return -ETIMEDOUT;
119
120 if (data)
121 *data = (u8)(val & 0xFF);
122
123 return 0;
124}
125EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
126
127int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
128{
129 int err, i, finished = 0;
130 u8 tmp;
131
132 rtsx_pci_init_cmd(pcr);
133
134 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
135 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
136 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
137 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
138
139 err = rtsx_pci_send_cmd(pcr, 100);
140 if (err < 0)
141 return err;
142
143 for (i = 0; i < 100000; i++) {
144 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
145 if (err < 0)
146 return err;
147
148 if (!(tmp & 0x80)) {
149 finished = 1;
150 break;
151 }
152 }
153
154 if (!finished)
155 return -ETIMEDOUT;
156
157 return 0;
158}
159EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
160
161int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
162{
163 int err, i, finished = 0;
164 u16 data;
165 u8 *ptr, tmp;
166
167 rtsx_pci_init_cmd(pcr);
168
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
170 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
171
172 err = rtsx_pci_send_cmd(pcr, 100);
173 if (err < 0)
174 return err;
175
176 for (i = 0; i < 100000; i++) {
177 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
178 if (err < 0)
179 return err;
180
181 if (!(tmp & 0x80)) {
182 finished = 1;
183 break;
184 }
185 }
186
187 if (!finished)
188 return -ETIMEDOUT;
189
190 rtsx_pci_init_cmd(pcr);
191
192 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
193 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
194
195 err = rtsx_pci_send_cmd(pcr, 100);
196 if (err < 0)
197 return err;
198
199 ptr = rtsx_pci_get_cmd_data(pcr);
200 data = ((u16)ptr[1] << 8) | ptr[0];
201
202 if (val)
203 *val = data;
204
205 return 0;
206}
207EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
208
209void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
210{
211 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
212 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
213
214 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
215 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
216}
217EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
218
219void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
220 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
221{
222 unsigned long flags;
223 u32 val = 0;
224 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
225
226 val |= (u32)(cmd_type & 0x03) << 30;
227 val |= (u32)(reg_addr & 0x3FFF) << 16;
228 val |= (u32)mask << 8;
229 val |= (u32)data;
230
231 spin_lock_irqsave(&pcr->lock, flags);
232 ptr += pcr->ci;
233 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
234 put_unaligned_le32(val, ptr);
235 ptr++;
236 pcr->ci++;
237 }
238 spin_unlock_irqrestore(&pcr->lock, flags);
239}
240EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
241
242void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
243{
244 u32 val = 1 << 31;
245
246 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
247
248 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
249 /* Hardware Auto Response */
250 val |= 0x40000000;
251 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
252}
253EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
254
255int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
256{
257 struct completion trans_done;
258 u32 val = 1 << 31;
259 long timeleft;
260 unsigned long flags;
261 int err = 0;
262
263 spin_lock_irqsave(&pcr->lock, flags);
264
265 /* set up data structures for the wakeup system */
266 pcr->done = &trans_done;
267 pcr->trans_result = TRANS_NOT_READY;
268 init_completion(&trans_done);
269
270 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
271
272 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
273 /* Hardware Auto Response */
274 val |= 0x40000000;
275 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
276
277 spin_unlock_irqrestore(&pcr->lock, flags);
278
279 /* Wait for TRANS_OK_INT */
280 timeleft = wait_for_completion_interruptible_timeout(
281 &trans_done, msecs_to_jiffies(timeout));
282 if (timeleft <= 0) {
283 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
284 __func__, __LINE__);
285 err = -ETIMEDOUT;
286 goto finish_send_cmd;
287 }
288
289 spin_lock_irqsave(&pcr->lock, flags);
290 if (pcr->trans_result == TRANS_RESULT_FAIL)
291 err = -EINVAL;
292 else if (pcr->trans_result == TRANS_RESULT_OK)
293 err = 0;
294 else if (pcr->trans_result == TRANS_NO_DEVICE)
295 err = -ENODEV;
296 spin_unlock_irqrestore(&pcr->lock, flags);
297
298finish_send_cmd:
299 spin_lock_irqsave(&pcr->lock, flags);
300 pcr->done = NULL;
301 spin_unlock_irqrestore(&pcr->lock, flags);
302
303 if ((err < 0) && (err != -ENODEV))
304 rtsx_pci_stop_cmd(pcr);
305
306 if (pcr->finish_me)
307 complete(pcr->finish_me);
308
309 return err;
310}
311EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
312
313static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
314 dma_addr_t addr, unsigned int len, int end)
315{
316 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
317 u64 val;
318 u8 option = SG_VALID | SG_TRANS_DATA;
319
320 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
321 (unsigned int)addr, len);
322
323 if (end)
324 option |= SG_END;
325 val = ((u64)addr << 32) | ((u64)len << 12) | option;
326
327 put_unaligned_le64(val, ptr);
ada8a8a1
WW		 328 pcr->sgi++;
329}
330
331int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
332 int num_sg, bool read, int timeout)
333{
334 struct completion trans_done;
335 u8 dir;
336 int err = 0, i, count;
337 long timeleft;
338 unsigned long flags;
339 struct scatterlist *sg;
340 enum dma_data_direction dma_dir;
341 u32 val;
342 dma_addr_t addr;
343 unsigned int len;
344
345 dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
346
347 /* don't transfer data during abort processing */
348 if (pcr->remove_pci)
349 return -EINVAL;
350
351 if ((sglist == NULL) || (num_sg <= 0))
352 return -EINVAL;
353
354 if (read) {
355 dir = DEVICE_TO_HOST;
356 dma_dir = DMA_FROM_DEVICE;
357 } else {
358 dir = HOST_TO_DEVICE;
359 dma_dir = DMA_TO_DEVICE;
360 }
361
362 count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
363 if (count < 1) {
364 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
365 return -EINVAL;
366 }
367 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
368
369 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
370 pcr->sgi = 0;
371 for_each_sg(sglist, sg, count, i) {
372 addr = sg_dma_address(sg);
373 len = sg_dma_len(sg);
374 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
375 }
376
377 spin_lock_irqsave(&pcr->lock, flags);
378
379 pcr->done = &trans_done;
380 pcr->trans_result = TRANS_NOT_READY;
381 init_completion(&trans_done);
382 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
383 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
384
385 spin_unlock_irqrestore(&pcr->lock, flags);
386
387 timeleft = wait_for_completion_interruptible_timeout(
388 &trans_done, msecs_to_jiffies(timeout));
389 if (timeleft <= 0) {
390 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
391 __func__, __LINE__);
392 err = -ETIMEDOUT;
393 goto out;
394 }
395
396 spin_lock_irqsave(&pcr->lock, flags);
397
398 if (pcr->trans_result == TRANS_RESULT_FAIL)
399 err = -EINVAL;
400 else if (pcr->trans_result == TRANS_NO_DEVICE)
401 err = -ENODEV;
402
403 spin_unlock_irqrestore(&pcr->lock, flags);
404
405out:
406 spin_lock_irqsave(&pcr->lock, flags);
407 pcr->done = NULL;
408 spin_unlock_irqrestore(&pcr->lock, flags);
409
410 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
411
412 if ((err < 0) && (err != -ENODEV))
413 rtsx_pci_stop_cmd(pcr);
414
415 if (pcr->finish_me)
416 complete(pcr->finish_me);
417
418 return err;
419}
420EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
421
422int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
423{
424 int err;
425 int i, j;
426 u16 reg;
427 u8 *ptr;
428
429 if (buf_len > 512)
430 buf_len = 512;
431
432 ptr = buf;
433 reg = PPBUF_BASE2;
434 for (i = 0; i < buf_len / 256; i++) {
435 rtsx_pci_init_cmd(pcr);
436
437 for (j = 0; j < 256; j++)
438 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
439
440 err = rtsx_pci_send_cmd(pcr, 250);
441 if (err < 0)
442 return err;
443
444 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
445 ptr += 256;
446 }
447
448 if (buf_len % 256) {
449 rtsx_pci_init_cmd(pcr);
450
451 for (j = 0; j < buf_len % 256; j++)
452 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
453
454 err = rtsx_pci_send_cmd(pcr, 250);
455 if (err < 0)
456 return err;
457 }
458
459 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
460
461 return 0;
462}
463EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
464
465int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
466{
467 int err;
468 int i, j;
469 u16 reg;
470 u8 *ptr;
471
472 if (buf_len > 512)
473 buf_len = 512;
474
475 ptr = buf;
476 reg = PPBUF_BASE2;
477 for (i = 0; i < buf_len / 256; i++) {
478 rtsx_pci_init_cmd(pcr);
479
480 for (j = 0; j < 256; j++) {
481 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
482 reg++, 0xFF, *ptr);
483 ptr++;
484 }
485
486 err = rtsx_pci_send_cmd(pcr, 250);
487 if (err < 0)
488 return err;
489 }
490
491 if (buf_len % 256) {
492 rtsx_pci_init_cmd(pcr);
493
494 for (j = 0; j < buf_len % 256; j++) {
495 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
496 reg++, 0xFF, *ptr);
497 ptr++;
498 }
499
500 err = rtsx_pci_send_cmd(pcr, 250);
501 if (err < 0)
502 return err;
503 }
504
505 return 0;
506}
507EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
508
509static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
510{
511 int err;
512
513 rtsx_pci_init_cmd(pcr);
514
515 while (*tbl & 0xFFFF0000) {
516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
517 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
518 tbl++;
519 }
520
521 err = rtsx_pci_send_cmd(pcr, 100);
522 if (err < 0)
523 return err;
524
525 return 0;
526}
527
528int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
529{
530 const u32 *tbl;
531
532 if (card == RTSX_SD_CARD)
533 tbl = pcr->sd_pull_ctl_enable_tbl;
534 else if (card == RTSX_MS_CARD)
535 tbl = pcr->ms_pull_ctl_enable_tbl;
536 else
537 return -EINVAL;
538
539 return rtsx_pci_set_pull_ctl(pcr, tbl);
540}
541EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
542
543int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
544{
545 const u32 *tbl;
546
547 if (card == RTSX_SD_CARD)
548 tbl = pcr->sd_pull_ctl_disable_tbl;
549 else if (card == RTSX_MS_CARD)
550 tbl = pcr->ms_pull_ctl_disable_tbl;
551 else
552 return -EINVAL;
553
554
555 return rtsx_pci_set_pull_ctl(pcr, tbl);
556}
557EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
558
559static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
560{
561 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
562
563 if (pcr->num_slots > 1)
564 pcr->bier |= MS_INT_EN;
565
566 /* Enable Bus Interrupt */
567 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
568
569 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
570}
571
572static inline u8 double_ssc_depth(u8 depth)
573{
574 return ((depth > 1) ? (depth - 1) : depth);
575}
576
577static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
578{
579 if (div > CLK_DIV_1) {
580 if (ssc_depth > (div - 1))
581 ssc_depth -= (div - 1);
582 else
583 ssc_depth = SSC_DEPTH_4M;
584 }
585
586 return ssc_depth;
587}
588
589int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
590 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
591{
592 int err, clk;
eebbe254 593 u8 n, clk_divider, mcu_cnt, div;
ada8a8a1
WW		 594 u8 depth[] = {
595 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
596 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
597 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
598 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
599 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
600 };
601
602 if (initial_mode) {
603 /* We use 250k(around) here, in initial stage */
604 clk_divider = SD_CLK_DIVIDE_128;
605 card_clock = 30000000;
606 } else {
607 clk_divider = SD_CLK_DIVIDE_0;
608 }
609 err = rtsx_pci_write_register(pcr, SD_CFG1,
610 SD_CLK_DIVIDE_MASK, clk_divider);
611 if (err < 0)
612 return err;
613
614 card_clock /= 1000000;
615 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
616
ada8a8a1
WW		 617 clk = card_clock;
618 if (!initial_mode && double_clk)
619 clk = card_clock * 2;
620 dev_dbg(&(pcr->pci->dev),
621 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
622 clk, pcr->cur_clock);
623
624 if (clk == pcr->cur_clock)
625 return 0;
626
ab4e8f8b 627 if (pcr->ops->conv_clk_and_div_n)
678cacdf 628 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
ab4e8f8b 629 else
678cacdf 630 n = (u8)(clk - 2);
eebbe254 631 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
ada8a8a1
WW		 632 return -EINVAL;
633
634 mcu_cnt = (u8)(125/clk + 3);
635 if (mcu_cnt > 15)
636 mcu_cnt = 15;
637
eebbe254 638 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
ada8a8a1 639 div = CLK_DIV_1;
eebbe254 640 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
ab4e8f8b 641 if (pcr->ops->conv_clk_and_div_n) {
678cacdf 642 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
ab4e8f8b 643 DIV_N_TO_CLK) * 2;
678cacdf 644 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
ab4e8f8b
WW		 645 CLK_TO_DIV_N);
646 } else {
678cacdf 647 n = (n + 2) * 2 - 2;
ab4e8f8b 648 }
ada8a8a1
WW		 649 div++;
650 }
678cacdf 651 dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
ada8a8a1
WW		 652
653 ssc_depth = depth[ssc_depth];
654 if (double_clk)
655 ssc_depth = double_ssc_depth(ssc_depth);
656
657 ssc_depth = revise_ssc_depth(ssc_depth, div);
658 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
659
660 rtsx_pci_init_cmd(pcr);
661 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
662 CLK_LOW_FREQ, CLK_LOW_FREQ);
663 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
664 0xFF, (div << 4) | mcu_cnt);
665 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
666 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
667 SSC_DEPTH_MASK, ssc_depth);
678cacdf 668 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
ada8a8a1
WW		 669 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
670 if (vpclk) {
671 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
672 PHASE_NOT_RESET, 0);
673 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
674 PHASE_NOT_RESET, PHASE_NOT_RESET);
675 }
676
677 err = rtsx_pci_send_cmd(pcr, 2000);
678 if (err < 0)
679 return err;
680
681 /* Wait SSC clock stable */
682 udelay(10);
683 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
684 if (err < 0)
685 return err;
686
687 pcr->cur_clock = clk;
688 return 0;
689}
690EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
691
692int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
693{
694 if (pcr->ops->card_power_on)
695 return pcr->ops->card_power_on(pcr, card);
696
697 return 0;
698}
699EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
700
701int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
702{
703 if (pcr->ops->card_power_off)
704 return pcr->ops->card_power_off(pcr, card);
705
706 return 0;
707}
708EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
709
d817ac4e
WW		 710int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
711{
712 if (pcr->ops->switch_output_voltage)
713 return pcr->ops->switch_output_voltage(pcr, voltage);
714
715 return 0;
716}
717EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
718
ada8a8a1
WW		 719unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
720{
721 unsigned int val;
722
723 val = rtsx_pci_readl(pcr, RTSX_BIPR);
724 if (pcr->ops->cd_deglitch)
725 val = pcr->ops->cd_deglitch(pcr);
726
727 return val;
728}
729EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
730
731void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
732{
733 struct completion finish;
734
735 pcr->finish_me = &finish;
736 init_completion(&finish);
737
738 if (pcr->done)
739 complete(pcr->done);
740
741 if (!pcr->remove_pci)
742 rtsx_pci_stop_cmd(pcr);
743
744 wait_for_completion_interruptible_timeout(&finish,
745 msecs_to_jiffies(2));
746 pcr->finish_me = NULL;
747}
748EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
749
750static void rtsx_pci_card_detect(struct work_struct *work)
751{
752 struct delayed_work *dwork;
753 struct rtsx_pcr *pcr;
754 unsigned long flags;
504decc0 755 unsigned int card_detect = 0, card_inserted, card_removed;
ada8a8a1
WW		 756 u32 irq_status;
757
758 dwork = to_delayed_work(work);
759 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
760
761 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
762
504decc0 763 mutex_lock(&pcr->pcr_mutex);
ada8a8a1
WW		 764 spin_lock_irqsave(&pcr->lock, flags);
765
766 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
767 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
768
504decc0
WW		 769 irq_status &= CARD_EXIST;
770 card_inserted = pcr->card_inserted & irq_status;
771 card_removed = pcr->card_removed;
772 pcr->card_inserted = 0;
773 pcr->card_removed = 0;
774
775 spin_unlock_irqrestore(&pcr->lock, flags);
776
777 if (card_inserted || card_removed) {
ada8a8a1
WW		 778 dev_dbg(&(pcr->pci->dev),
779 "card_inserted: 0x%x, card_removed: 0x%x\n",
504decc0 780 card_inserted, card_removed);
ada8a8a1
WW		 781
782 if (pcr->ops->cd_deglitch)
504decc0 783 card_inserted = pcr->ops->cd_deglitch(pcr);
ada8a8a1 784
504decc0 785 card_detect = card_inserted | card_removed;
ada8a8a1
WW		 786 }
787
504decc0 788 mutex_unlock(&pcr->pcr_mutex);
ada8a8a1 789
2d1484f5 790 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
ada8a8a1
WW		 791 pcr->slots[RTSX_SD_CARD].card_event(
792 pcr->slots[RTSX_SD_CARD].p_dev);
2d1484f5 793 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
ada8a8a1
WW		 794 pcr->slots[RTSX_MS_CARD].card_event(
795 pcr->slots[RTSX_MS_CARD].p_dev);
796}
797
798static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
799{
800 struct rtsx_pcr *pcr = dev_id;
801 u32 int_reg;
802
803 if (!pcr)
804 return IRQ_NONE;
805
806 spin_lock(&pcr->lock);
807
808 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
809 /* Clear interrupt flag */
810 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
811 if ((int_reg & pcr->bier) == 0) {
812 spin_unlock(&pcr->lock);
813 return IRQ_NONE;
814 }
815 if (int_reg == 0xFFFFFFFF) {
816 spin_unlock(&pcr->lock);
817 return IRQ_HANDLED;
818 }
819
820 int_reg &= (pcr->bier | 0x7FFFFF);
821
822 if (int_reg & SD_INT) {
823 if (int_reg & SD_EXIST) {
824 pcr->card_inserted |= SD_EXIST;
825 } else {
826 pcr->card_removed |= SD_EXIST;
827 pcr->card_inserted &= ~SD_EXIST;
828 }
829 }
830
831 if (int_reg & MS_INT) {
832 if (int_reg & MS_EXIST) {
833 pcr->card_inserted |= MS_EXIST;
834 } else {
835 pcr->card_removed |= MS_EXIST;
836 pcr->card_inserted &= ~MS_EXIST;
837 }
838 }
839
ada8a8a1
WW		 840 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
841 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
842 pcr->trans_result = TRANS_RESULT_FAIL;
843 if (pcr->done)
844 complete(pcr->done);
845 } else if (int_reg & TRANS_OK_INT) {
846 pcr->trans_result = TRANS_RESULT_OK;
847 if (pcr->done)
848 complete(pcr->done);
849 }
850 }
851
504decc0
WW		 852 if (pcr->card_inserted || pcr->card_removed)
853 schedule_delayed_work(&pcr->carddet_work,
854 msecs_to_jiffies(200));
855
ada8a8a1
WW		 856 spin_unlock(&pcr->lock);
857 return IRQ_HANDLED;
858}
859
860static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
861{
862 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
863 __func__, pcr->msi_en, pcr->pci->irq);
864
865 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
866 pcr->msi_en ? 0 : IRQF_SHARED,
867 DRV_NAME_RTSX_PCI, pcr)) {
868 dev_err(&(pcr->pci->dev),
869 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
870 pcr->pci->irq);
871 return -1;
872 }
873
874 pcr->irq = pcr->pci->irq;
875 pci_intx(pcr->pci, !pcr->msi_en);
876
877 return 0;
878}
879
880static void rtsx_pci_idle_work(struct work_struct *work)
881{
882 struct delayed_work *dwork = to_delayed_work(work);
883 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
884
885 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
886
887 mutex_lock(&pcr->pcr_mutex);
888
889 pcr->state = PDEV_STAT_IDLE;
890
891 if (pcr->ops->disable_auto_blink)
892 pcr->ops->disable_auto_blink(pcr);
893 if (pcr->ops->turn_off_led)
894 pcr->ops->turn_off_led(pcr);
895
896 mutex_unlock(&pcr->pcr_mutex);
897}
898
899static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
900{
901 int err;
902
903 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
904
905 rtsx_pci_enable_bus_int(pcr);
906
907 /* Power on SSC */
908 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
909 if (err < 0)
910 return err;
911
912 /* Wait SSC power stable */
913 udelay(200);
914
915 if (pcr->ops->optimize_phy) {
916 err = pcr->ops->optimize_phy(pcr);
917 if (err < 0)
918 return err;
919 }
920
921 rtsx_pci_init_cmd(pcr);
922
923 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
924 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
925
926 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
927 /* Disable card clock */
928 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
929 /* Reset ASPM state to default value */
930 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
931 /* Reset delink mode */
932 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
933 /* Card driving select */
934 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
935 0x07, DRIVER_TYPE_D);
936 /* Enable SSC Clock */
937 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
938 0xFF, SSC_8X_EN | SSC_SEL_4M);
939 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
940 /* Disable cd_pwr_save */
941 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
942 /* Clear Link Ready Interrupt */
943 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
944 LINK_RDY_INT, LINK_RDY_INT);
945 /* Enlarge the estimation window of PERST# glitch
946 * to reduce the chance of invalid card interrupt
947 */
948 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
949 /* Update RC oscillator to 400k
950 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
951 * 1: 2M 0: 400k
952 */
953 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
954 /* Set interrupt write clear
955 * bit 1: U_elbi_if_rd_clr_en
956 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
957 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
958 */
959 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
960 /* Force CLKREQ# PIN to drive 0 to request clock */
961 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
962
963 err = rtsx_pci_send_cmd(pcr, 100);
964 if (err < 0)
965 return err;
966
967 /* Enable clk_request_n to enable clock power management */
968 rtsx_pci_write_config_byte(pcr, 0x81, 1);
969 /* Enter L1 when host tx idle */
970 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
971
972 if (pcr->ops->extra_init_hw) {
973 err = pcr->ops->extra_init_hw(pcr);
974 if (err < 0)
975 return err;
976 }
977
978 return 0;
979}
980
981static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
982{
983 int err;
984
985 spin_lock_init(&pcr->lock);
986 mutex_init(&pcr->pcr_mutex);
987
988 switch (PCI_PID(pcr)) {
989 default:
990 case 0x5209:
991 rts5209_init_params(pcr);
992 break;
993
994 case 0x5229:
995 rts5229_init_params(pcr);
996 break;
997
998 case 0x5289:
999 rtl8411_init_params(pcr);
1000 break;
1001 }
1002
1003 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1004 PCI_PID(pcr), pcr->ic_version);
1005
1006 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1007 GFP_KERNEL);
1008 if (!pcr->slots)
1009 return -ENOMEM;
1010
1011 pcr->state = PDEV_STAT_IDLE;
1012 err = rtsx_pci_init_hw(pcr);
1013 if (err < 0) {
1014 kfree(pcr->slots);
1015 return err;
1016 }
1017
1018 return 0;
1019}
1020
612b95cd
GKH		 1021static int rtsx_pci_probe(struct pci_dev *pcidev,
1022 const struct pci_device_id *id)
ada8a8a1
WW		 1023{
1024 struct rtsx_pcr *pcr;
1025 struct pcr_handle *handle;
1026 u32 base, len;
1027 int ret, i;
1028
1029 dev_dbg(&(pcidev->dev),
1030 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1031 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1032 (int)pcidev->revision);
1033
f84ef042
WW		 1034 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1035 if (ret < 0)
1036 return ret;
1037
ada8a8a1
WW		 1038 ret = pci_enable_device(pcidev);
1039 if (ret)
1040 return ret;
1041
1042 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1043 if (ret)
1044 goto disable;
1045
1046 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1047 if (!pcr) {
1048 ret = -ENOMEM;
1049 goto release_pci;
1050 }
1051
1052 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1053 if (!handle) {
1054 ret = -ENOMEM;
1055 goto free_pcr;
1056 }
1057 handle->pcr = pcr;
1058
1059 if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
1060 ret = -ENOMEM;
1061 goto free_handle;
1062 }
1063
1064 spin_lock(&rtsx_pci_lock);
1065 ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
1066 spin_unlock(&rtsx_pci_lock);
1067 if (ret)
1068 goto free_handle;
1069
1070 pcr->pci = pcidev;
1071 dev_set_drvdata(&pcidev->dev, handle);
1072
1073 len = pci_resource_len(pcidev, 0);
1074 base = pci_resource_start(pcidev, 0);
1075 pcr->remap_addr = ioremap_nocache(base, len);
1076 if (!pcr->remap_addr) {
1077 ret = -ENOMEM;
1078 goto free_host;
1079 }
1080
1081 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1082 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1083 GFP_KERNEL);
1084 if (pcr->rtsx_resv_buf == NULL) {
1085 ret = -ENXIO;
1086 goto unmap;
1087 }
1088 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1089 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1090 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1091 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1092
1093 pcr->card_inserted = 0;
1094 pcr->card_removed = 0;
1095 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1096 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1097
1098 pcr->msi_en = msi_en;
1099 if (pcr->msi_en) {
1100 ret = pci_enable_msi(pcidev);
1101 if (ret < 0)
1102 pcr->msi_en = false;
1103 }
1104
1105 ret = rtsx_pci_acquire_irq(pcr);
1106 if (ret < 0)
1107 goto free_dma;
1108
1109 pci_set_master(pcidev);
1110 synchronize_irq(pcr->irq);
1111
1112 ret = rtsx_pci_init_chip(pcr);
1113 if (ret < 0)
1114 goto disable_irq;
1115
1116 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1117 rtsx_pcr_cells[i].platform_data = handle;
1118 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1119 }
1120 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1121 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1122 if (ret < 0)
1123 goto disable_irq;
1124
1125 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1126
1127 return 0;
1128
1129disable_irq:
1130 free_irq(pcr->irq, (void *)pcr);
1131free_dma:
1132 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1133 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1134unmap:
1135 iounmap(pcr->remap_addr);
1136free_host:
1137 dev_set_drvdata(&pcidev->dev, NULL);
1138free_handle:
1139 kfree(handle);
1140free_pcr:
1141 kfree(pcr);
1142release_pci:
1143 pci_release_regions(pcidev);
1144disable:
1145 pci_disable_device(pcidev);
1146
1147 return ret;
1148}
1149
612b95cd 1150static void rtsx_pci_remove(struct pci_dev *pcidev)
ada8a8a1
WW		 1151{
1152 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1153 struct rtsx_pcr *pcr = handle->pcr;
1154
1155 pcr->remove_pci = true;
1156
1157 cancel_delayed_work(&pcr->carddet_work);
1158 cancel_delayed_work(&pcr->idle_work);
1159
1160 mfd_remove_devices(&pcidev->dev);
1161
1162 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1163 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1164 free_irq(pcr->irq, (void *)pcr);
1165 if (pcr->msi_en)
1166 pci_disable_msi(pcr->pci);
1167 iounmap(pcr->remap_addr);
1168
1169 dev_set_drvdata(&pcidev->dev, NULL);
1170 pci_release_regions(pcidev);
1171 pci_disable_device(pcidev);
1172
1173 spin_lock(&rtsx_pci_lock);
1174 idr_remove(&rtsx_pci_idr, pcr->id);
1175 spin_unlock(&rtsx_pci_lock);
1176
1177 kfree(pcr->slots);
1178 kfree(pcr);
1179 kfree(handle);
1180
1181 dev_dbg(&(pcidev->dev),
1182 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1183 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1184}
1185
1186#ifdef CONFIG_PM
1187
1188static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1189{
1190 struct pcr_handle *handle;
1191 struct rtsx_pcr *pcr;
1192 int ret = 0;
1193
1194 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1195
1196 handle = pci_get_drvdata(pcidev);
1197 pcr = handle->pcr;
1198
1199 cancel_delayed_work(&pcr->carddet_work);
1200 cancel_delayed_work(&pcr->idle_work);
1201
1202 mutex_lock(&pcr->pcr_mutex);
1203
1204 if (pcr->ops->turn_off_led)
1205 pcr->ops->turn_off_led(pcr);
1206
1207 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1208 pcr->bier = 0;
1209
1210 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1211 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1212
1213 pci_save_state(pcidev);
1214 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1215 pci_disable_device(pcidev);
1216 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1217
1218 mutex_unlock(&pcr->pcr_mutex);
1219 return ret;
1220}
1221
1222static int rtsx_pci_resume(struct pci_dev *pcidev)
1223{
1224 struct pcr_handle *handle;
1225 struct rtsx_pcr *pcr;
1226 int ret = 0;
1227
1228 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1229
1230 handle = pci_get_drvdata(pcidev);
1231 pcr = handle->pcr;
1232
1233 mutex_lock(&pcr->pcr_mutex);
1234
1235 pci_set_power_state(pcidev, PCI_D0);
1236 pci_restore_state(pcidev);
1237 ret = pci_enable_device(pcidev);
1238 if (ret)
1239 goto out;
1240 pci_set_master(pcidev);
1241
1242 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1243 if (ret)
1244 goto out;
1245
1246 ret = rtsx_pci_init_hw(pcr);
1247 if (ret)
1248 goto out;
1249
1250 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1251
1252out:
1253 mutex_unlock(&pcr->pcr_mutex);
1254 return ret;
1255}
1256
1257#else /* CONFIG_PM */
1258
1259#define rtsx_pci_suspend NULL
1260#define rtsx_pci_resume NULL
1261
1262#endif /* CONFIG_PM */
1263
1264static struct pci_driver rtsx_pci_driver = {
1265 .name = DRV_NAME_RTSX_PCI,
1266 .id_table = rtsx_pci_ids,
1267 .probe = rtsx_pci_probe,
612b95cd 1268 .remove = rtsx_pci_remove,
ada8a8a1
WW		 1269 .suspend = rtsx_pci_suspend,
1270 .resume = rtsx_pci_resume,
1271};
1272module_pci_driver(rtsx_pci_driver);
1273
1274MODULE_LICENSE("GPL");
1275MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1276MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Linux kernel - Deliverables
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