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mfd: Explicitely include slab.h to rtsx
[deliverable/linux.git] / drivers / mfd / rtsx_pcr.c
CommitLineData
ada8a8a1
WW		 1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/pci.h>
24#include <linux/module.h>
aec17ea1 25#include <linux/slab.h>
ada8a8a1
WW		 26#include <linux/dma-mapping.h>
27#include <linux/highmem.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/idr.h>
31#include <linux/platform_device.h>
32#include <linux/mfd/core.h>
33#include <linux/mfd/rtsx_pci.h>
34#include <asm/unaligned.h>
35
36#include "rtsx_pcr.h"
37
38static bool msi_en = true;
39module_param(msi_en, bool, S_IRUGO | S_IWUSR);
40MODULE_PARM_DESC(msi_en, "Enable MSI");
41
42static DEFINE_IDR(rtsx_pci_idr);
43static DEFINE_SPINLOCK(rtsx_pci_lock);
44
45static struct mfd_cell rtsx_pcr_cells[] = {
46 [RTSX_SD_CARD] = {
47 .name = DRV_NAME_RTSX_PCI_SDMMC,
48 },
49 [RTSX_MS_CARD] = {
50 .name = DRV_NAME_RTSX_PCI_MS,
51 },
52};
53
54static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
58 { 0, }
59};
60
61MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
62
63void rtsx_pci_start_run(struct rtsx_pcr *pcr)
64{
65 /* If pci device removed, don't queue idle work any more */
66 if (pcr->remove_pci)
67 return;
68
69 if (pcr->state != PDEV_STAT_RUN) {
70 pcr->state = PDEV_STAT_RUN;
71 if (pcr->ops->enable_auto_blink)
72 pcr->ops->enable_auto_blink(pcr);
73 }
74
75 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
76}
77EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
78
79int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
80{
81 int i;
82 u32 val = HAIMR_WRITE_START;
83
84 val |= (u32)(addr & 0x3FFF) << 16;
85 val |= (u32)mask << 8;
86 val |= (u32)data;
87
88 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
89
90 for (i = 0; i < MAX_RW_REG_CNT; i++) {
91 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
92 if ((val & HAIMR_TRANS_END) == 0) {
93 if (data != (u8)val)
94 return -EIO;
95 return 0;
96 }
97 }
98
99 return -ETIMEDOUT;
100}
101EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
102
103int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
104{
105 u32 val = HAIMR_READ_START;
106 int i;
107
108 val |= (u32)(addr & 0x3FFF) << 16;
109 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
110
111 for (i = 0; i < MAX_RW_REG_CNT; i++) {
112 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
113 if ((val & HAIMR_TRANS_END) == 0)
114 break;
115 }
116
117 if (i >= MAX_RW_REG_CNT)
118 return -ETIMEDOUT;
119
120 if (data)
121 *data = (u8)(val & 0xFF);
122
123 return 0;
124}
125EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
126
127int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
128{
129 int err, i, finished = 0;
130 u8 tmp;
131
132 rtsx_pci_init_cmd(pcr);
133
134 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
135 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
136 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
137 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
138
139 err = rtsx_pci_send_cmd(pcr, 100);
140 if (err < 0)
141 return err;
142
143 for (i = 0; i < 100000; i++) {
144 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
145 if (err < 0)
146 return err;
147
148 if (!(tmp & 0x80)) {
149 finished = 1;
150 break;
151 }
152 }
153
154 if (!finished)
155 return -ETIMEDOUT;
156
157 return 0;
158}
159EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
160
161int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
162{
163 int err, i, finished = 0;
164 u16 data;
165 u8 *ptr, tmp;
166
167 rtsx_pci_init_cmd(pcr);
168
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
170 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
171
172 err = rtsx_pci_send_cmd(pcr, 100);
173 if (err < 0)
174 return err;
175
176 for (i = 0; i < 100000; i++) {
177 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
178 if (err < 0)
179 return err;
180
181 if (!(tmp & 0x80)) {
182 finished = 1;
183 break;
184 }
185 }
186
187 if (!finished)
188 return -ETIMEDOUT;
189
190 rtsx_pci_init_cmd(pcr);
191
192 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
193 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
194
195 err = rtsx_pci_send_cmd(pcr, 100);
196 if (err < 0)
197 return err;
198
199 ptr = rtsx_pci_get_cmd_data(pcr);
200 data = ((u16)ptr[1] << 8) | ptr[0];
201
202 if (val)
203 *val = data;
204
205 return 0;
206}
207EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
208
209void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
210{
211 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
212 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
213
214 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
215 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
216}
217EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
218
219void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
220 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
221{
222 unsigned long flags;
223 u32 val = 0;
224 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
225
226 val |= (u32)(cmd_type & 0x03) << 30;
227 val |= (u32)(reg_addr & 0x3FFF) << 16;
228 val |= (u32)mask << 8;
229 val |= (u32)data;
230
231 spin_lock_irqsave(&pcr->lock, flags);
232 ptr += pcr->ci;
233 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
234 put_unaligned_le32(val, ptr);
235 ptr++;
236 pcr->ci++;
237 }
238 spin_unlock_irqrestore(&pcr->lock, flags);
239}
240EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
241
242void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
243{
244 u32 val = 1 << 31;
245
246 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
247
248 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
249 /* Hardware Auto Response */
250 val |= 0x40000000;
251 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
252}
253EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
254
255int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
256{
257 struct completion trans_done;
258 u32 val = 1 << 31;
259 long timeleft;
260 unsigned long flags;
261 int err = 0;
262
263 spin_lock_irqsave(&pcr->lock, flags);
264
265 /* set up data structures for the wakeup system */
266 pcr->done = &trans_done;
267 pcr->trans_result = TRANS_NOT_READY;
268 init_completion(&trans_done);
269
270 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
271
272 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
273 /* Hardware Auto Response */
274 val |= 0x40000000;
275 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
276
277 spin_unlock_irqrestore(&pcr->lock, flags);
278
279 /* Wait for TRANS_OK_INT */
280 timeleft = wait_for_completion_interruptible_timeout(
281 &trans_done, msecs_to_jiffies(timeout));
282 if (timeleft <= 0) {
283 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
284 __func__, __LINE__);
285 err = -ETIMEDOUT;
286 goto finish_send_cmd;
287 }
288
289 spin_lock_irqsave(&pcr->lock, flags);
290 if (pcr->trans_result == TRANS_RESULT_FAIL)
291 err = -EINVAL;
292 else if (pcr->trans_result == TRANS_RESULT_OK)
293 err = 0;
294 else if (pcr->trans_result == TRANS_NO_DEVICE)
295 err = -ENODEV;
296 spin_unlock_irqrestore(&pcr->lock, flags);
297
298finish_send_cmd:
299 spin_lock_irqsave(&pcr->lock, flags);
300 pcr->done = NULL;
301 spin_unlock_irqrestore(&pcr->lock, flags);
302
303 if ((err < 0) && (err != -ENODEV))
304 rtsx_pci_stop_cmd(pcr);
305
306 if (pcr->finish_me)
307 complete(pcr->finish_me);
308
309 return err;
310}
311EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
312
313static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
314 dma_addr_t addr, unsigned int len, int end)
315{
316 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
317 u64 val;
318 u8 option = SG_VALID | SG_TRANS_DATA;
319
320 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
321 (unsigned int)addr, len);
322
323 if (end)
324 option |= SG_END;
325 val = ((u64)addr << 32) | ((u64)len << 12) | option;
326
327 put_unaligned_le64(val, ptr);
328 ptr++;
329 pcr->sgi++;
330}
331
332int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
333 int num_sg, bool read, int timeout)
334{
335 struct completion trans_done;
336 u8 dir;
337 int err = 0, i, count;
338 long timeleft;
339 unsigned long flags;
340 struct scatterlist *sg;
341 enum dma_data_direction dma_dir;
342 u32 val;
343 dma_addr_t addr;
344 unsigned int len;
345
346 dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
347
348 /* don't transfer data during abort processing */
349 if (pcr->remove_pci)
350 return -EINVAL;
351
352 if ((sglist == NULL) || (num_sg <= 0))
353 return -EINVAL;
354
355 if (read) {
356 dir = DEVICE_TO_HOST;
357 dma_dir = DMA_FROM_DEVICE;
358 } else {
359 dir = HOST_TO_DEVICE;
360 dma_dir = DMA_TO_DEVICE;
361 }
362
363 count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
364 if (count < 1) {
365 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
366 return -EINVAL;
367 }
368 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
369
370 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
371 pcr->sgi = 0;
372 for_each_sg(sglist, sg, count, i) {
373 addr = sg_dma_address(sg);
374 len = sg_dma_len(sg);
375 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
376 }
377
378 spin_lock_irqsave(&pcr->lock, flags);
379
380 pcr->done = &trans_done;
381 pcr->trans_result = TRANS_NOT_READY;
382 init_completion(&trans_done);
383 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
384 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
385
386 spin_unlock_irqrestore(&pcr->lock, flags);
387
388 timeleft = wait_for_completion_interruptible_timeout(
389 &trans_done, msecs_to_jiffies(timeout));
390 if (timeleft <= 0) {
391 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
392 __func__, __LINE__);
393 err = -ETIMEDOUT;
394 goto out;
395 }
396
397 spin_lock_irqsave(&pcr->lock, flags);
398
399 if (pcr->trans_result == TRANS_RESULT_FAIL)
400 err = -EINVAL;
401 else if (pcr->trans_result == TRANS_NO_DEVICE)
402 err = -ENODEV;
403
404 spin_unlock_irqrestore(&pcr->lock, flags);
405
406out:
407 spin_lock_irqsave(&pcr->lock, flags);
408 pcr->done = NULL;
409 spin_unlock_irqrestore(&pcr->lock, flags);
410
411 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
412
413 if ((err < 0) && (err != -ENODEV))
414 rtsx_pci_stop_cmd(pcr);
415
416 if (pcr->finish_me)
417 complete(pcr->finish_me);
418
419 return err;
420}
421EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
422
423int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
424{
425 int err;
426 int i, j;
427 u16 reg;
428 u8 *ptr;
429
430 if (buf_len > 512)
431 buf_len = 512;
432
433 ptr = buf;
434 reg = PPBUF_BASE2;
435 for (i = 0; i < buf_len / 256; i++) {
436 rtsx_pci_init_cmd(pcr);
437
438 for (j = 0; j < 256; j++)
439 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
440
441 err = rtsx_pci_send_cmd(pcr, 250);
442 if (err < 0)
443 return err;
444
445 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
446 ptr += 256;
447 }
448
449 if (buf_len % 256) {
450 rtsx_pci_init_cmd(pcr);
451
452 for (j = 0; j < buf_len % 256; j++)
453 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
454
455 err = rtsx_pci_send_cmd(pcr, 250);
456 if (err < 0)
457 return err;
458 }
459
460 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
461
462 return 0;
463}
464EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
465
466int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
467{
468 int err;
469 int i, j;
470 u16 reg;
471 u8 *ptr;
472
473 if (buf_len > 512)
474 buf_len = 512;
475
476 ptr = buf;
477 reg = PPBUF_BASE2;
478 for (i = 0; i < buf_len / 256; i++) {
479 rtsx_pci_init_cmd(pcr);
480
481 for (j = 0; j < 256; j++) {
482 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
483 reg++, 0xFF, *ptr);
484 ptr++;
485 }
486
487 err = rtsx_pci_send_cmd(pcr, 250);
488 if (err < 0)
489 return err;
490 }
491
492 if (buf_len % 256) {
493 rtsx_pci_init_cmd(pcr);
494
495 for (j = 0; j < buf_len % 256; j++) {
496 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
497 reg++, 0xFF, *ptr);
498 ptr++;
499 }
500
501 err = rtsx_pci_send_cmd(pcr, 250);
502 if (err < 0)
503 return err;
504 }
505
506 return 0;
507}
508EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
509
510static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
511{
512 int err;
513
514 rtsx_pci_init_cmd(pcr);
515
516 while (*tbl & 0xFFFF0000) {
517 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
518 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
519 tbl++;
520 }
521
522 err = rtsx_pci_send_cmd(pcr, 100);
523 if (err < 0)
524 return err;
525
526 return 0;
527}
528
529int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
530{
531 const u32 *tbl;
532
533 if (card == RTSX_SD_CARD)
534 tbl = pcr->sd_pull_ctl_enable_tbl;
535 else if (card == RTSX_MS_CARD)
536 tbl = pcr->ms_pull_ctl_enable_tbl;
537 else
538 return -EINVAL;
539
540 return rtsx_pci_set_pull_ctl(pcr, tbl);
541}
542EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
543
544int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
545{
546 const u32 *tbl;
547
548 if (card == RTSX_SD_CARD)
549 tbl = pcr->sd_pull_ctl_disable_tbl;
550 else if (card == RTSX_MS_CARD)
551 tbl = pcr->ms_pull_ctl_disable_tbl;
552 else
553 return -EINVAL;
554
555
556 return rtsx_pci_set_pull_ctl(pcr, tbl);
557}
558EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
559
560static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
561{
562 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
563
564 if (pcr->num_slots > 1)
565 pcr->bier |= MS_INT_EN;
566
567 /* Enable Bus Interrupt */
568 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
569
570 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
571}
572
573static inline u8 double_ssc_depth(u8 depth)
574{
575 return ((depth > 1) ? (depth - 1) : depth);
576}
577
578static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
579{
580 if (div > CLK_DIV_1) {
581 if (ssc_depth > (div - 1))
582 ssc_depth -= (div - 1);
583 else
584 ssc_depth = SSC_DEPTH_4M;
585 }
586
587 return ssc_depth;
588}
589
590int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
591 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
592{
593 int err, clk;
594 u8 N, min_N, max_N, clk_divider;
595 u8 mcu_cnt, div, max_div;
596 u8 depth[] = {
597 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
598 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
599 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
600 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
601 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
602 };
603
604 if (initial_mode) {
605 /* We use 250k(around) here, in initial stage */
606 clk_divider = SD_CLK_DIVIDE_128;
607 card_clock = 30000000;
608 } else {
609 clk_divider = SD_CLK_DIVIDE_0;
610 }
611 err = rtsx_pci_write_register(pcr, SD_CFG1,
612 SD_CLK_DIVIDE_MASK, clk_divider);
613 if (err < 0)
614 return err;
615
616 card_clock /= 1000000;
617 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
618
619 min_N = 80;
620 max_N = 208;
621 max_div = CLK_DIV_8;
622
623 clk = card_clock;
624 if (!initial_mode && double_clk)
625 clk = card_clock * 2;
626 dev_dbg(&(pcr->pci->dev),
627 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
628 clk, pcr->cur_clock);
629
630 if (clk == pcr->cur_clock)
631 return 0;
632
633 N = (u8)(clk - 2);
634 if ((clk <= 2) || (N > max_N))
635 return -EINVAL;
636
637 mcu_cnt = (u8)(125/clk + 3);
638 if (mcu_cnt > 15)
639 mcu_cnt = 15;
640
641 /* Make sure that the SSC clock div_n is equal or greater than min_N */
642 div = CLK_DIV_1;
643 while ((N < min_N) && (div < max_div)) {
644 N = (N + 2) * 2 - 2;
645 div++;
646 }
647 dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div);
648
649 ssc_depth = depth[ssc_depth];
650 if (double_clk)
651 ssc_depth = double_ssc_depth(ssc_depth);
652
653 ssc_depth = revise_ssc_depth(ssc_depth, div);
654 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
655
656 rtsx_pci_init_cmd(pcr);
657 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
658 CLK_LOW_FREQ, CLK_LOW_FREQ);
659 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
660 0xFF, (div << 4) | mcu_cnt);
661 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
662 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
663 SSC_DEPTH_MASK, ssc_depth);
664 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
665 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
666 if (vpclk) {
667 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
668 PHASE_NOT_RESET, 0);
669 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
670 PHASE_NOT_RESET, PHASE_NOT_RESET);
671 }
672
673 err = rtsx_pci_send_cmd(pcr, 2000);
674 if (err < 0)
675 return err;
676
677 /* Wait SSC clock stable */
678 udelay(10);
679 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
680 if (err < 0)
681 return err;
682
683 pcr->cur_clock = clk;
684 return 0;
685}
686EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
687
688int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
689{
690 if (pcr->ops->card_power_on)
691 return pcr->ops->card_power_on(pcr, card);
692
693 return 0;
694}
695EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
696
697int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
698{
699 if (pcr->ops->card_power_off)
700 return pcr->ops->card_power_off(pcr, card);
701
702 return 0;
703}
704EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
705
706unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
707{
708 unsigned int val;
709
710 val = rtsx_pci_readl(pcr, RTSX_BIPR);
711 if (pcr->ops->cd_deglitch)
712 val = pcr->ops->cd_deglitch(pcr);
713
714 return val;
715}
716EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
717
718void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
719{
720 struct completion finish;
721
722 pcr->finish_me = &finish;
723 init_completion(&finish);
724
725 if (pcr->done)
726 complete(pcr->done);
727
728 if (!pcr->remove_pci)
729 rtsx_pci_stop_cmd(pcr);
730
731 wait_for_completion_interruptible_timeout(&finish,
732 msecs_to_jiffies(2));
733 pcr->finish_me = NULL;
734}
735EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
736
737static void rtsx_pci_card_detect(struct work_struct *work)
738{
739 struct delayed_work *dwork;
740 struct rtsx_pcr *pcr;
741 unsigned long flags;
742 unsigned int card_detect = 0;
743 u32 irq_status;
744
745 dwork = to_delayed_work(work);
746 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
747
748 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
749
750 spin_lock_irqsave(&pcr->lock, flags);
751
752 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
753 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
754
755 if (pcr->card_inserted || pcr->card_removed) {
756 dev_dbg(&(pcr->pci->dev),
757 "card_inserted: 0x%x, card_removed: 0x%x\n",
758 pcr->card_inserted, pcr->card_removed);
759
760 if (pcr->ops->cd_deglitch)
761 pcr->card_inserted = pcr->ops->cd_deglitch(pcr);
762
763 card_detect = pcr->card_inserted | pcr->card_removed;
764 pcr->card_inserted = 0;
765 pcr->card_removed = 0;
766 }
767
768 spin_unlock_irqrestore(&pcr->lock, flags);
769
770 if (card_detect & SD_EXIST)
771 pcr->slots[RTSX_SD_CARD].card_event(
772 pcr->slots[RTSX_SD_CARD].p_dev);
773 if (card_detect & MS_EXIST)
774 pcr->slots[RTSX_MS_CARD].card_event(
775 pcr->slots[RTSX_MS_CARD].p_dev);
776}
777
778static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
779{
780 struct rtsx_pcr *pcr = dev_id;
781 u32 int_reg;
782
783 if (!pcr)
784 return IRQ_NONE;
785
786 spin_lock(&pcr->lock);
787
788 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
789 /* Clear interrupt flag */
790 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
791 if ((int_reg & pcr->bier) == 0) {
792 spin_unlock(&pcr->lock);
793 return IRQ_NONE;
794 }
795 if (int_reg == 0xFFFFFFFF) {
796 spin_unlock(&pcr->lock);
797 return IRQ_HANDLED;
798 }
799
800 int_reg &= (pcr->bier | 0x7FFFFF);
801
802 if (int_reg & SD_INT) {
803 if (int_reg & SD_EXIST) {
804 pcr->card_inserted |= SD_EXIST;
805 } else {
806 pcr->card_removed |= SD_EXIST;
807 pcr->card_inserted &= ~SD_EXIST;
808 }
809 }
810
811 if (int_reg & MS_INT) {
812 if (int_reg & MS_EXIST) {
813 pcr->card_inserted |= MS_EXIST;
814 } else {
815 pcr->card_removed |= MS_EXIST;
816 pcr->card_inserted &= ~MS_EXIST;
817 }
818 }
819
820 if (pcr->card_inserted || pcr->card_removed)
821 schedule_delayed_work(&pcr->carddet_work,
822 msecs_to_jiffies(200));
823
824 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
825 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
826 pcr->trans_result = TRANS_RESULT_FAIL;
827 if (pcr->done)
828 complete(pcr->done);
829 } else if (int_reg & TRANS_OK_INT) {
830 pcr->trans_result = TRANS_RESULT_OK;
831 if (pcr->done)
832 complete(pcr->done);
833 }
834 }
835
836 spin_unlock(&pcr->lock);
837 return IRQ_HANDLED;
838}
839
840static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
841{
842 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
843 __func__, pcr->msi_en, pcr->pci->irq);
844
845 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
846 pcr->msi_en ? 0 : IRQF_SHARED,
847 DRV_NAME_RTSX_PCI, pcr)) {
848 dev_err(&(pcr->pci->dev),
849 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
850 pcr->pci->irq);
851 return -1;
852 }
853
854 pcr->irq = pcr->pci->irq;
855 pci_intx(pcr->pci, !pcr->msi_en);
856
857 return 0;
858}
859
860static void rtsx_pci_idle_work(struct work_struct *work)
861{
862 struct delayed_work *dwork = to_delayed_work(work);
863 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
864
865 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
866
867 mutex_lock(&pcr->pcr_mutex);
868
869 pcr->state = PDEV_STAT_IDLE;
870
871 if (pcr->ops->disable_auto_blink)
872 pcr->ops->disable_auto_blink(pcr);
873 if (pcr->ops->turn_off_led)
874 pcr->ops->turn_off_led(pcr);
875
876 mutex_unlock(&pcr->pcr_mutex);
877}
878
879static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
880{
881 int err;
882
883 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
884
885 rtsx_pci_enable_bus_int(pcr);
886
887 /* Power on SSC */
888 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
889 if (err < 0)
890 return err;
891
892 /* Wait SSC power stable */
893 udelay(200);
894
895 if (pcr->ops->optimize_phy) {
896 err = pcr->ops->optimize_phy(pcr);
897 if (err < 0)
898 return err;
899 }
900
901 rtsx_pci_init_cmd(pcr);
902
903 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
904 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
905
906 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
907 /* Disable card clock */
908 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
909 /* Reset ASPM state to default value */
910 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
911 /* Reset delink mode */
912 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
913 /* Card driving select */
914 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
915 0x07, DRIVER_TYPE_D);
916 /* Enable SSC Clock */
917 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
918 0xFF, SSC_8X_EN | SSC_SEL_4M);
919 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
920 /* Disable cd_pwr_save */
921 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
922 /* Clear Link Ready Interrupt */
923 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
924 LINK_RDY_INT, LINK_RDY_INT);
925 /* Enlarge the estimation window of PERST# glitch
926 * to reduce the chance of invalid card interrupt
927 */
928 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
929 /* Update RC oscillator to 400k
930 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
931 * 1: 2M 0: 400k
932 */
933 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
934 /* Set interrupt write clear
935 * bit 1: U_elbi_if_rd_clr_en
936 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
937 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
938 */
939 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
940 /* Force CLKREQ# PIN to drive 0 to request clock */
941 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
942
943 err = rtsx_pci_send_cmd(pcr, 100);
944 if (err < 0)
945 return err;
946
947 /* Enable clk_request_n to enable clock power management */
948 rtsx_pci_write_config_byte(pcr, 0x81, 1);
949 /* Enter L1 when host tx idle */
950 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
951
952 if (pcr->ops->extra_init_hw) {
953 err = pcr->ops->extra_init_hw(pcr);
954 if (err < 0)
955 return err;
956 }
957
958 return 0;
959}
960
961static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
962{
963 int err;
964
965 spin_lock_init(&pcr->lock);
966 mutex_init(&pcr->pcr_mutex);
967
968 switch (PCI_PID(pcr)) {
969 default:
970 case 0x5209:
971 rts5209_init_params(pcr);
972 break;
973
974 case 0x5229:
975 rts5229_init_params(pcr);
976 break;
977
978 case 0x5289:
979 rtl8411_init_params(pcr);
980 break;
981 }
982
983 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
984 PCI_PID(pcr), pcr->ic_version);
985
986 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
987 GFP_KERNEL);
988 if (!pcr->slots)
989 return -ENOMEM;
990
991 pcr->state = PDEV_STAT_IDLE;
992 err = rtsx_pci_init_hw(pcr);
993 if (err < 0) {
994 kfree(pcr->slots);
995 return err;
996 }
997
998 return 0;
999}
1000
1001static int __devinit rtsx_pci_probe(struct pci_dev *pcidev,
1002 const struct pci_device_id *id)
1003{
1004 struct rtsx_pcr *pcr;
1005 struct pcr_handle *handle;
1006 u32 base, len;
1007 int ret, i;
1008
1009 dev_dbg(&(pcidev->dev),
1010 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1011 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1012 (int)pcidev->revision);
1013
1014 ret = pci_enable_device(pcidev);
1015 if (ret)
1016 return ret;
1017
1018 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1019 if (ret)
1020 goto disable;
1021
1022 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1023 if (!pcr) {
1024 ret = -ENOMEM;
1025 goto release_pci;
1026 }
1027
1028 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1029 if (!handle) {
1030 ret = -ENOMEM;
1031 goto free_pcr;
1032 }
1033 handle->pcr = pcr;
1034
1035 if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
1036 ret = -ENOMEM;
1037 goto free_handle;
1038 }
1039
1040 spin_lock(&rtsx_pci_lock);
1041 ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
1042 spin_unlock(&rtsx_pci_lock);
1043 if (ret)
1044 goto free_handle;
1045
1046 pcr->pci = pcidev;
1047 dev_set_drvdata(&pcidev->dev, handle);
1048
1049 len = pci_resource_len(pcidev, 0);
1050 base = pci_resource_start(pcidev, 0);
1051 pcr->remap_addr = ioremap_nocache(base, len);
1052 if (!pcr->remap_addr) {
1053 ret = -ENOMEM;
1054 goto free_host;
1055 }
1056
1057 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1058 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1059 GFP_KERNEL);
1060 if (pcr->rtsx_resv_buf == NULL) {
1061 ret = -ENXIO;
1062 goto unmap;
1063 }
1064 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1065 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1066 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1067 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1068
1069 pcr->card_inserted = 0;
1070 pcr->card_removed = 0;
1071 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1072 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1073
1074 pcr->msi_en = msi_en;
1075 if (pcr->msi_en) {
1076 ret = pci_enable_msi(pcidev);
1077 if (ret < 0)
1078 pcr->msi_en = false;
1079 }
1080
1081 ret = rtsx_pci_acquire_irq(pcr);
1082 if (ret < 0)
1083 goto free_dma;
1084
1085 pci_set_master(pcidev);
1086 synchronize_irq(pcr->irq);
1087
1088 ret = rtsx_pci_init_chip(pcr);
1089 if (ret < 0)
1090 goto disable_irq;
1091
1092 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1093 rtsx_pcr_cells[i].platform_data = handle;
1094 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1095 }
1096 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1097 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1098 if (ret < 0)
1099 goto disable_irq;
1100
1101 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1102
1103 return 0;
1104
1105disable_irq:
1106 free_irq(pcr->irq, (void *)pcr);
1107free_dma:
1108 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1109 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1110unmap:
1111 iounmap(pcr->remap_addr);
1112free_host:
1113 dev_set_drvdata(&pcidev->dev, NULL);
1114free_handle:
1115 kfree(handle);
1116free_pcr:
1117 kfree(pcr);
1118release_pci:
1119 pci_release_regions(pcidev);
1120disable:
1121 pci_disable_device(pcidev);
1122
1123 return ret;
1124}
1125
1126static void __devexit rtsx_pci_remove(struct pci_dev *pcidev)
1127{
1128 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1129 struct rtsx_pcr *pcr = handle->pcr;
1130
1131 pcr->remove_pci = true;
1132
1133 cancel_delayed_work(&pcr->carddet_work);
1134 cancel_delayed_work(&pcr->idle_work);
1135
1136 mfd_remove_devices(&pcidev->dev);
1137
1138 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1139 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1140 free_irq(pcr->irq, (void *)pcr);
1141 if (pcr->msi_en)
1142 pci_disable_msi(pcr->pci);
1143 iounmap(pcr->remap_addr);
1144
1145 dev_set_drvdata(&pcidev->dev, NULL);
1146 pci_release_regions(pcidev);
1147 pci_disable_device(pcidev);
1148
1149 spin_lock(&rtsx_pci_lock);
1150 idr_remove(&rtsx_pci_idr, pcr->id);
1151 spin_unlock(&rtsx_pci_lock);
1152
1153 kfree(pcr->slots);
1154 kfree(pcr);
1155 kfree(handle);
1156
1157 dev_dbg(&(pcidev->dev),
1158 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1159 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1160}
1161
1162#ifdef CONFIG_PM
1163
1164static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1165{
1166 struct pcr_handle *handle;
1167 struct rtsx_pcr *pcr;
1168 int ret = 0;
1169
1170 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1171
1172 handle = pci_get_drvdata(pcidev);
1173 pcr = handle->pcr;
1174
1175 cancel_delayed_work(&pcr->carddet_work);
1176 cancel_delayed_work(&pcr->idle_work);
1177
1178 mutex_lock(&pcr->pcr_mutex);
1179
1180 if (pcr->ops->turn_off_led)
1181 pcr->ops->turn_off_led(pcr);
1182
1183 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1184 pcr->bier = 0;
1185
1186 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1187 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1188
1189 pci_save_state(pcidev);
1190 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1191 pci_disable_device(pcidev);
1192 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1193
1194 mutex_unlock(&pcr->pcr_mutex);
1195 return ret;
1196}
1197
1198static int rtsx_pci_resume(struct pci_dev *pcidev)
1199{
1200 struct pcr_handle *handle;
1201 struct rtsx_pcr *pcr;
1202 int ret = 0;
1203
1204 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1205
1206 handle = pci_get_drvdata(pcidev);
1207 pcr = handle->pcr;
1208
1209 mutex_lock(&pcr->pcr_mutex);
1210
1211 pci_set_power_state(pcidev, PCI_D0);
1212 pci_restore_state(pcidev);
1213 ret = pci_enable_device(pcidev);
1214 if (ret)
1215 goto out;
1216 pci_set_master(pcidev);
1217
1218 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1219 if (ret)
1220 goto out;
1221
1222 ret = rtsx_pci_init_hw(pcr);
1223 if (ret)
1224 goto out;
1225
1226 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1227
1228out:
1229 mutex_unlock(&pcr->pcr_mutex);
1230 return ret;
1231}
1232
1233#else /* CONFIG_PM */
1234
1235#define rtsx_pci_suspend NULL
1236#define rtsx_pci_resume NULL
1237
1238#endif /* CONFIG_PM */
1239
1240static struct pci_driver rtsx_pci_driver = {
1241 .name = DRV_NAME_RTSX_PCI,
1242 .id_table = rtsx_pci_ids,
1243 .probe = rtsx_pci_probe,
1244 .remove = __devexit_p(rtsx_pci_remove),
1245 .suspend = rtsx_pci_suspend,
1246 .resume = rtsx_pci_resume,
1247};
1248module_pci_driver(rtsx_pci_driver);
1249
1250MODULE_LICENSE("GPL");
1251MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1252MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Linux kernel - Deliverables
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