Commit | Line | Data |
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5ac2ffa7 | 1 | /* |
63063bfb | 2 | * sec-irq.c |
5ac2ffa7 SK |
3 | * |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/irq.h> | |
6445b84a SK |
17 | #include <linux/regmap.h> |
18 | ||
54227bcf SK |
19 | #include <linux/mfd/samsung/core.h> |
20 | #include <linux/mfd/samsung/irq.h> | |
6445b84a | 21 | #include <linux/mfd/samsung/s2mps11.h> |
54227bcf SK |
22 | #include <linux/mfd/samsung/s5m8763.h> |
23 | #include <linux/mfd/samsung/s5m8767.h> | |
5ac2ffa7 | 24 | |
6445b84a SK |
25 | static struct regmap_irq s2mps11_irqs[] = { |
26 | [S2MPS11_IRQ_PWRONF] = { | |
27 | .reg_offset = 1, | |
28 | .mask = S2MPS11_IRQ_PWRONF_MASK, | |
29 | }, | |
30 | [S2MPS11_IRQ_PWRONR] = { | |
31 | .reg_offset = 1, | |
32 | .mask = S2MPS11_IRQ_PWRONR_MASK, | |
33 | }, | |
34 | [S2MPS11_IRQ_JIGONBF] = { | |
35 | .reg_offset = 1, | |
36 | .mask = S2MPS11_IRQ_JIGONBF_MASK, | |
37 | }, | |
38 | [S2MPS11_IRQ_JIGONBR] = { | |
39 | .reg_offset = 1, | |
40 | .mask = S2MPS11_IRQ_JIGONBR_MASK, | |
41 | }, | |
42 | [S2MPS11_IRQ_ACOKBF] = { | |
43 | .reg_offset = 1, | |
44 | .mask = S2MPS11_IRQ_ACOKBF_MASK, | |
45 | }, | |
46 | [S2MPS11_IRQ_ACOKBR] = { | |
47 | .reg_offset = 1, | |
48 | .mask = S2MPS11_IRQ_ACOKBR_MASK, | |
49 | }, | |
50 | [S2MPS11_IRQ_PWRON1S] = { | |
51 | .reg_offset = 1, | |
52 | .mask = S2MPS11_IRQ_PWRON1S_MASK, | |
53 | }, | |
54 | [S2MPS11_IRQ_MRB] = { | |
55 | .reg_offset = 1, | |
56 | .mask = S2MPS11_IRQ_MRB_MASK, | |
57 | }, | |
58 | [S2MPS11_IRQ_RTC60S] = { | |
59 | .reg_offset = 2, | |
60 | .mask = S2MPS11_IRQ_RTC60S_MASK, | |
61 | }, | |
62 | [S2MPS11_IRQ_RTCA1] = { | |
63 | .reg_offset = 2, | |
64 | .mask = S2MPS11_IRQ_RTCA1_MASK, | |
65 | }, | |
66 | [S2MPS11_IRQ_RTCA2] = { | |
67 | .reg_offset = 2, | |
68 | .mask = S2MPS11_IRQ_RTCA2_MASK, | |
69 | }, | |
70 | [S2MPS11_IRQ_SMPL] = { | |
71 | .reg_offset = 2, | |
72 | .mask = S2MPS11_IRQ_SMPL_MASK, | |
73 | }, | |
74 | [S2MPS11_IRQ_RTC1S] = { | |
75 | .reg_offset = 2, | |
76 | .mask = S2MPS11_IRQ_RTC1S_MASK, | |
77 | }, | |
78 | [S2MPS11_IRQ_WTSR] = { | |
79 | .reg_offset = 2, | |
80 | .mask = S2MPS11_IRQ_WTSR_MASK, | |
81 | }, | |
82 | [S2MPS11_IRQ_INT120C] = { | |
83 | .reg_offset = 3, | |
84 | .mask = S2MPS11_IRQ_INT120C_MASK, | |
85 | }, | |
86 | [S2MPS11_IRQ_INT140C] = { | |
87 | .reg_offset = 3, | |
88 | .mask = S2MPS11_IRQ_INT140C_MASK, | |
89 | }, | |
5ac2ffa7 SK |
90 | }; |
91 | ||
6445b84a SK |
92 | |
93 | static struct regmap_irq s5m8767_irqs[] = { | |
5ac2ffa7 | 94 | [S5M8767_IRQ_PWRR] = { |
6445b84a | 95 | .reg_offset = 1, |
5ac2ffa7 SK |
96 | .mask = S5M8767_IRQ_PWRR_MASK, |
97 | }, | |
98 | [S5M8767_IRQ_PWRF] = { | |
6445b84a | 99 | .reg_offset = 1, |
5ac2ffa7 SK |
100 | .mask = S5M8767_IRQ_PWRF_MASK, |
101 | }, | |
102 | [S5M8767_IRQ_PWR1S] = { | |
6445b84a | 103 | .reg_offset = 1, |
5ac2ffa7 SK |
104 | .mask = S5M8767_IRQ_PWR1S_MASK, |
105 | }, | |
106 | [S5M8767_IRQ_JIGR] = { | |
6445b84a | 107 | .reg_offset = 1, |
5ac2ffa7 SK |
108 | .mask = S5M8767_IRQ_JIGR_MASK, |
109 | }, | |
110 | [S5M8767_IRQ_JIGF] = { | |
6445b84a | 111 | .reg_offset = 1, |
5ac2ffa7 SK |
112 | .mask = S5M8767_IRQ_JIGF_MASK, |
113 | }, | |
114 | [S5M8767_IRQ_LOWBAT2] = { | |
6445b84a | 115 | .reg_offset = 1, |
5ac2ffa7 SK |
116 | .mask = S5M8767_IRQ_LOWBAT2_MASK, |
117 | }, | |
118 | [S5M8767_IRQ_LOWBAT1] = { | |
6445b84a | 119 | .reg_offset = 1, |
5ac2ffa7 SK |
120 | .mask = S5M8767_IRQ_LOWBAT1_MASK, |
121 | }, | |
122 | [S5M8767_IRQ_MRB] = { | |
6445b84a | 123 | .reg_offset = 2, |
5ac2ffa7 SK |
124 | .mask = S5M8767_IRQ_MRB_MASK, |
125 | }, | |
126 | [S5M8767_IRQ_DVSOK2] = { | |
6445b84a | 127 | .reg_offset = 2, |
5ac2ffa7 SK |
128 | .mask = S5M8767_IRQ_DVSOK2_MASK, |
129 | }, | |
130 | [S5M8767_IRQ_DVSOK3] = { | |
6445b84a | 131 | .reg_offset = 2, |
5ac2ffa7 SK |
132 | .mask = S5M8767_IRQ_DVSOK3_MASK, |
133 | }, | |
134 | [S5M8767_IRQ_DVSOK4] = { | |
6445b84a | 135 | .reg_offset = 2, |
5ac2ffa7 SK |
136 | .mask = S5M8767_IRQ_DVSOK4_MASK, |
137 | }, | |
138 | [S5M8767_IRQ_RTC60S] = { | |
6445b84a | 139 | .reg_offset = 3, |
5ac2ffa7 SK |
140 | .mask = S5M8767_IRQ_RTC60S_MASK, |
141 | }, | |
142 | [S5M8767_IRQ_RTCA1] = { | |
6445b84a | 143 | .reg_offset = 3, |
5ac2ffa7 SK |
144 | .mask = S5M8767_IRQ_RTCA1_MASK, |
145 | }, | |
146 | [S5M8767_IRQ_RTCA2] = { | |
6445b84a | 147 | .reg_offset = 3, |
5ac2ffa7 SK |
148 | .mask = S5M8767_IRQ_RTCA2_MASK, |
149 | }, | |
150 | [S5M8767_IRQ_SMPL] = { | |
6445b84a | 151 | .reg_offset = 3, |
5ac2ffa7 SK |
152 | .mask = S5M8767_IRQ_SMPL_MASK, |
153 | }, | |
154 | [S5M8767_IRQ_RTC1S] = { | |
6445b84a | 155 | .reg_offset = 3, |
5ac2ffa7 SK |
156 | .mask = S5M8767_IRQ_RTC1S_MASK, |
157 | }, | |
158 | [S5M8767_IRQ_WTSR] = { | |
6445b84a | 159 | .reg_offset = 3, |
5ac2ffa7 SK |
160 | .mask = S5M8767_IRQ_WTSR_MASK, |
161 | }, | |
162 | }; | |
163 | ||
6445b84a | 164 | static struct regmap_irq s5m8763_irqs[] = { |
5ac2ffa7 | 165 | [S5M8763_IRQ_DCINF] = { |
6445b84a | 166 | .reg_offset = 1, |
5ac2ffa7 SK |
167 | .mask = S5M8763_IRQ_DCINF_MASK, |
168 | }, | |
169 | [S5M8763_IRQ_DCINR] = { | |
6445b84a | 170 | .reg_offset = 1, |
5ac2ffa7 SK |
171 | .mask = S5M8763_IRQ_DCINR_MASK, |
172 | }, | |
173 | [S5M8763_IRQ_JIGF] = { | |
6445b84a | 174 | .reg_offset = 1, |
5ac2ffa7 SK |
175 | .mask = S5M8763_IRQ_JIGF_MASK, |
176 | }, | |
177 | [S5M8763_IRQ_JIGR] = { | |
6445b84a | 178 | .reg_offset = 1, |
5ac2ffa7 SK |
179 | .mask = S5M8763_IRQ_JIGR_MASK, |
180 | }, | |
181 | [S5M8763_IRQ_PWRONF] = { | |
6445b84a | 182 | .reg_offset = 1, |
5ac2ffa7 SK |
183 | .mask = S5M8763_IRQ_PWRONF_MASK, |
184 | }, | |
185 | [S5M8763_IRQ_PWRONR] = { | |
6445b84a | 186 | .reg_offset = 1, |
5ac2ffa7 SK |
187 | .mask = S5M8763_IRQ_PWRONR_MASK, |
188 | }, | |
189 | [S5M8763_IRQ_WTSREVNT] = { | |
6445b84a | 190 | .reg_offset = 2, |
5ac2ffa7 SK |
191 | .mask = S5M8763_IRQ_WTSREVNT_MASK, |
192 | }, | |
193 | [S5M8763_IRQ_SMPLEVNT] = { | |
6445b84a | 194 | .reg_offset = 2, |
5ac2ffa7 SK |
195 | .mask = S5M8763_IRQ_SMPLEVNT_MASK, |
196 | }, | |
197 | [S5M8763_IRQ_ALARM1] = { | |
6445b84a | 198 | .reg_offset = 2, |
5ac2ffa7 SK |
199 | .mask = S5M8763_IRQ_ALARM1_MASK, |
200 | }, | |
201 | [S5M8763_IRQ_ALARM0] = { | |
6445b84a | 202 | .reg_offset = 2, |
5ac2ffa7 SK |
203 | .mask = S5M8763_IRQ_ALARM0_MASK, |
204 | }, | |
205 | [S5M8763_IRQ_ONKEY1S] = { | |
6445b84a | 206 | .reg_offset = 3, |
5ac2ffa7 SK |
207 | .mask = S5M8763_IRQ_ONKEY1S_MASK, |
208 | }, | |
209 | [S5M8763_IRQ_TOPOFFR] = { | |
6445b84a | 210 | .reg_offset = 3, |
5ac2ffa7 SK |
211 | .mask = S5M8763_IRQ_TOPOFFR_MASK, |
212 | }, | |
213 | [S5M8763_IRQ_DCINOVPR] = { | |
6445b84a | 214 | .reg_offset = 3, |
5ac2ffa7 SK |
215 | .mask = S5M8763_IRQ_DCINOVPR_MASK, |
216 | }, | |
217 | [S5M8763_IRQ_CHGRSTF] = { | |
6445b84a | 218 | .reg_offset = 3, |
5ac2ffa7 SK |
219 | .mask = S5M8763_IRQ_CHGRSTF_MASK, |
220 | }, | |
221 | [S5M8763_IRQ_DONER] = { | |
6445b84a | 222 | .reg_offset = 3, |
5ac2ffa7 SK |
223 | .mask = S5M8763_IRQ_DONER_MASK, |
224 | }, | |
225 | [S5M8763_IRQ_CHGFAULT] = { | |
6445b84a | 226 | .reg_offset = 3, |
5ac2ffa7 SK |
227 | .mask = S5M8763_IRQ_CHGFAULT_MASK, |
228 | }, | |
229 | [S5M8763_IRQ_LOBAT1] = { | |
6445b84a | 230 | .reg_offset = 4, |
5ac2ffa7 SK |
231 | .mask = S5M8763_IRQ_LOBAT1_MASK, |
232 | }, | |
233 | [S5M8763_IRQ_LOBAT2] = { | |
6445b84a | 234 | .reg_offset = 4, |
5ac2ffa7 SK |
235 | .mask = S5M8763_IRQ_LOBAT2_MASK, |
236 | }, | |
237 | }; | |
238 | ||
6445b84a SK |
239 | static struct regmap_irq_chip s2mps11_irq_chip = { |
240 | .name = "s2mps11", | |
241 | .irqs = s2mps11_irqs, | |
242 | .num_irqs = ARRAY_SIZE(s2mps11_irqs), | |
243 | .num_regs = 3, | |
244 | .status_base = S2MPS11_REG_INT1, | |
245 | .mask_base = S2MPS11_REG_INT1M, | |
246 | .ack_base = S2MPS11_REG_INT1, | |
247 | }; | |
5ac2ffa7 | 248 | |
6445b84a | 249 | static struct regmap_irq_chip s5m8767_irq_chip = { |
5ac2ffa7 | 250 | .name = "s5m8767", |
6445b84a SK |
251 | .irqs = s5m8767_irqs, |
252 | .num_irqs = ARRAY_SIZE(s5m8767_irqs), | |
253 | .num_regs = 3, | |
254 | .status_base = S5M8767_REG_INT1, | |
255 | .mask_base = S5M8767_REG_INT1M, | |
256 | .ack_base = S5M8767_REG_INT1, | |
5ac2ffa7 SK |
257 | }; |
258 | ||
6445b84a | 259 | static struct regmap_irq_chip s5m8763_irq_chip = { |
5ac2ffa7 | 260 | .name = "s5m8763", |
6445b84a SK |
261 | .irqs = s5m8763_irqs, |
262 | .num_irqs = ARRAY_SIZE(s5m8763_irqs), | |
263 | .num_regs = 4, | |
264 | .status_base = S5M8763_REG_IRQ1, | |
265 | .mask_base = S5M8763_REG_IRQM1, | |
266 | .ack_base = S5M8763_REG_IRQ1, | |
5ac2ffa7 SK |
267 | }; |
268 | ||
63063bfb | 269 | int sec_irq_init(struct sec_pmic_dev *sec_pmic) |
5ac2ffa7 | 270 | { |
5ac2ffa7 | 271 | int ret = 0; |
63063bfb | 272 | int type = sec_pmic->device_type; |
5ac2ffa7 | 273 | |
63063bfb SK |
274 | if (!sec_pmic->irq) { |
275 | dev_warn(sec_pmic->dev, | |
5ac2ffa7 | 276 | "No interrupt specified, no interrupts\n"); |
63063bfb | 277 | sec_pmic->irq_base = 0; |
5ac2ffa7 SK |
278 | return 0; |
279 | } | |
280 | ||
5ac2ffa7 SK |
281 | switch (type) { |
282 | case S5M8763X: | |
6445b84a SK |
283 | ret = regmap_add_irq_chip(sec_pmic->regmap, sec_pmic->irq, |
284 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
285 | sec_pmic->irq_base, &s5m8763_irq_chip, | |
286 | &sec_pmic->irq_data); | |
5ac2ffa7 SK |
287 | break; |
288 | case S5M8767X: | |
6445b84a SK |
289 | ret = regmap_add_irq_chip(sec_pmic->regmap, sec_pmic->irq, |
290 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
291 | sec_pmic->irq_base, &s5m8767_irq_chip, | |
292 | &sec_pmic->irq_data); | |
5ac2ffa7 | 293 | break; |
6445b84a SK |
294 | case S2MPS11X: |
295 | ret = regmap_add_irq_chip(sec_pmic->regmap, sec_pmic->irq, | |
296 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
297 | sec_pmic->irq_base, &s2mps11_irq_chip, | |
298 | &sec_pmic->irq_data); | |
5ac2ffa7 SK |
299 | break; |
300 | default: | |
6445b84a SK |
301 | dev_err(sec_pmic->dev, "Unknown device type %d\n", |
302 | sec_pmic->device_type); | |
303 | return -EINVAL; | |
5ac2ffa7 SK |
304 | } |
305 | ||
6445b84a SK |
306 | if (ret != 0) { |
307 | dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret); | |
c7a1fcf3 JC |
308 | return ret; |
309 | } | |
5ac2ffa7 SK |
310 | |
311 | return 0; | |
312 | } | |
313 | ||
63063bfb | 314 | void sec_irq_exit(struct sec_pmic_dev *sec_pmic) |
5ac2ffa7 | 315 | { |
6445b84a | 316 | regmap_del_irq_chip(sec_pmic->irq, sec_pmic->irq_data); |
5ac2ffa7 | 317 | } |