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mfd: stmpe: Use generic bit mask name
[deliverable/linux.git] / drivers / mfd / stmpe.c
CommitLineData
27e34995 1/*
1a6e4b74
VK		 2 * ST Microelectronics MFD: stmpe's driver
3 *
27e34995
RV		 4 * Copyright (C) ST-Ericsson SA 2010
5 *
6 * License Terms: GNU General Public License, version 2
7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
8 */
9
ac713cc9 10#include <linux/err.h>
73de16db 11#include <linux/gpio.h>
dba61c8f 12#include <linux/export.h>
27e34995 13#include <linux/kernel.h>
27e34995
RV		 14#include <linux/interrupt.h>
15#include <linux/irq.h>
76f93992 16#include <linux/irqdomain.h>
20d5c7de 17#include <linux/of.h>
ac713cc9 18#include <linux/of_gpio.h>
1a6e4b74 19#include <linux/pm.h>
27e34995 20#include <linux/slab.h>
27e34995 21#include <linux/mfd/core.h>
230f13a5 22#include <linux/delay.h>
9c9e3214 23#include <linux/regulator/consumer.h>
27e34995
RV		 24#include "stmpe.h"
25
fc1882dc
LW		 26/**
27 * struct stmpe_platform_data - STMPE platform data
28 * @id: device id to distinguish between multiple STMPEs on the same board
29 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
30 * @irq_trigger: IRQ trigger to use for the interrupt to the host
31 * @autosleep: bool to enable/disable stmpe autosleep
32 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
33 * @irq_over_gpio: true if gpio is used to get irq
34 * @irq_gpio: gpio number over which irq will be requested (significant only if
35 * irq_over_gpio is true)
36 */
37struct stmpe_platform_data {
38 int id;
39 unsigned int blocks;
40 unsigned int irq_trigger;
41 bool autosleep;
42 bool irq_over_gpio;
43 int irq_gpio;
44 int autosleep_timeout;
45};
46
27e34995
RV		 47static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
48{
49 return stmpe->variant->enable(stmpe, blocks, true);
50}
51
52static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
53{
54 return stmpe->variant->enable(stmpe, blocks, false);
55}
56
57static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
58{
59 int ret;
60
1a6e4b74 61 ret = stmpe->ci->read_byte(stmpe, reg);
27e34995 62 if (ret < 0)
1a6e4b74 63 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
27e34995
RV		 64
65 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
66
67 return ret;
68}
69
70static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
71{
72 int ret;
73
74 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
75
1a6e4b74 76 ret = stmpe->ci->write_byte(stmpe, reg, val);
27e34995 77 if (ret < 0)
1a6e4b74 78 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
27e34995
RV		 79
80 return ret;
81}
82
83static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
84{
85 int ret;
86
87 ret = __stmpe_reg_read(stmpe, reg);
88 if (ret < 0)
89 return ret;
90
91 ret &= ~mask;
92 ret |= val;
93
94 return __stmpe_reg_write(stmpe, reg, ret);
95}
96
97static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
98 u8 *values)
99{
100 int ret;
101
1a6e4b74 102 ret = stmpe->ci->read_block(stmpe, reg, length, values);
27e34995 103 if (ret < 0)
1a6e4b74 104 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
27e34995
RV		 105
106 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
107 stmpe_dump_bytes("stmpe rd: ", values, length);
108
109 return ret;
110}
111
112static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
113 const u8 *values)
114{
115 int ret;
116
117 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
118 stmpe_dump_bytes("stmpe wr: ", values, length);
119
1a6e4b74 120 ret = stmpe->ci->write_block(stmpe, reg, length, values);
27e34995 121 if (ret < 0)
1a6e4b74 122 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
27e34995
RV		 123
124 return ret;
125}
126
127/**
128 * stmpe_enable - enable blocks on an STMPE device
129 * @stmpe: Device to work on
130 * @blocks: Mask of blocks (enum stmpe_block values) to enable
131 */
132int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
133{
134 int ret;
135
136 mutex_lock(&stmpe->lock);
137 ret = __stmpe_enable(stmpe, blocks);
138 mutex_unlock(&stmpe->lock);
139
140 return ret;
141}
142EXPORT_SYMBOL_GPL(stmpe_enable);
143
144/**
145 * stmpe_disable - disable blocks on an STMPE device
146 * @stmpe: Device to work on
147 * @blocks: Mask of blocks (enum stmpe_block values) to enable
148 */
149int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
150{
151 int ret;
152
153 mutex_lock(&stmpe->lock);
154 ret = __stmpe_disable(stmpe, blocks);
155 mutex_unlock(&stmpe->lock);
156
157 return ret;
158}
159EXPORT_SYMBOL_GPL(stmpe_disable);
160
161/**
162 * stmpe_reg_read() - read a single STMPE register
163 * @stmpe: Device to read from
164 * @reg: Register to read
165 */
166int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
167{
168 int ret;
169
170 mutex_lock(&stmpe->lock);
171 ret = __stmpe_reg_read(stmpe, reg);
172 mutex_unlock(&stmpe->lock);
173
174 return ret;
175}
176EXPORT_SYMBOL_GPL(stmpe_reg_read);
177
178/**
179 * stmpe_reg_write() - write a single STMPE register
180 * @stmpe: Device to write to
181 * @reg: Register to write
182 * @val: Value to write
183 */
184int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
185{
186 int ret;
187
188 mutex_lock(&stmpe->lock);
189 ret = __stmpe_reg_write(stmpe, reg, val);
190 mutex_unlock(&stmpe->lock);
191
192 return ret;
193}
194EXPORT_SYMBOL_GPL(stmpe_reg_write);
195
196/**
197 * stmpe_set_bits() - set the value of a bitfield in a STMPE register
198 * @stmpe: Device to write to
199 * @reg: Register to write
200 * @mask: Mask of bits to set
201 * @val: Value to set
202 */
203int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
204{
205 int ret;
206
207 mutex_lock(&stmpe->lock);
208 ret = __stmpe_set_bits(stmpe, reg, mask, val);
209 mutex_unlock(&stmpe->lock);
210
211 return ret;
212}
213EXPORT_SYMBOL_GPL(stmpe_set_bits);
214
215/**
216 * stmpe_block_read() - read multiple STMPE registers
217 * @stmpe: Device to read from
218 * @reg: First register
219 * @length: Number of registers
220 * @values: Buffer to write to
221 */
222int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
223{
224 int ret;
225
226 mutex_lock(&stmpe->lock);
227 ret = __stmpe_block_read(stmpe, reg, length, values);
228 mutex_unlock(&stmpe->lock);
229
230 return ret;
231}
232EXPORT_SYMBOL_GPL(stmpe_block_read);
233
234/**
235 * stmpe_block_write() - write multiple STMPE registers
236 * @stmpe: Device to write to
237 * @reg: First register
238 * @length: Number of registers
239 * @values: Values to write
240 */
241int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
242 const u8 *values)
243{
244 int ret;
245
246 mutex_lock(&stmpe->lock);
247 ret = __stmpe_block_write(stmpe, reg, length, values);
248 mutex_unlock(&stmpe->lock);
249
250 return ret;
251}
252EXPORT_SYMBOL_GPL(stmpe_block_write);
253
254/**
4dcaa6b6 255 * stmpe_set_altfunc()- set the alternate function for STMPE pins
27e34995
RV		 256 * @stmpe: Device to configure
257 * @pins: Bitmask of pins to affect
258 * @block: block to enable alternate functions for
259 *
260 * @pins is assumed to have a bit set for each of the bits whose alternate
261 * function is to be changed, numbered according to the GPIOXY numbers.
262 *
263 * If the GPIO module is not enabled, this function automatically enables it in
264 * order to perform the change.
265 */
266int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
267{
268 struct stmpe_variant_info *variant = stmpe->variant;
269 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
270 int af_bits = variant->af_bits;
271 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
27e34995 272 int mask = (1 << af_bits) - 1;
7929fa77 273 u8 regs[8];
7f7f4ea1
VK		 274 int af, afperreg, ret;
275
276 if (!variant->get_altfunc)
277 return 0;
27e34995 278
7f7f4ea1 279 afperreg = 8 / af_bits;
27e34995
RV		 280 mutex_lock(&stmpe->lock);
281
282 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
283 if (ret < 0)
284 goto out;
285
286 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
287 if (ret < 0)
288 goto out;
289
290 af = variant->get_altfunc(stmpe, block);
291
292 while (pins) {
293 int pin = __ffs(pins);
294 int regoffset = numregs - (pin / afperreg) - 1;
295 int pos = (pin % afperreg) * (8 / afperreg);
296
297 regs[regoffset] &= ~(mask << pos);
298 regs[regoffset] |= af << pos;
299
300 pins &= ~(1 << pin);
301 }
302
303 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
304
305out:
306 mutex_unlock(&stmpe->lock);
307 return ret;
308}
309EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
310
311/*
312 * GPIO (all variants)
313 */
314
315static struct resource stmpe_gpio_resources[] = {
316 /* Start and end filled dynamically */
317 {
318 .flags = IORESOURCE_IRQ,
319 },
320};
321
6bbb3c4c 322static const struct mfd_cell stmpe_gpio_cell = {
27e34995 323 .name = "stmpe-gpio",
86605cfe 324 .of_compatible = "st,stmpe-gpio",
27e34995
RV		 325 .resources = stmpe_gpio_resources,
326 .num_resources = ARRAY_SIZE(stmpe_gpio_resources),
327};
328
6bbb3c4c 329static const struct mfd_cell stmpe_gpio_cell_noirq = {
e31f9b82 330 .name = "stmpe-gpio",
86605cfe 331 .of_compatible = "st,stmpe-gpio",
e31f9b82
CB		 332 /* gpio cell resources consist of an irq only so no resources here */
333};
334
27e34995
RV		 335/*
336 * Keypad (1601, 2401, 2403)
337 */
338
339static struct resource stmpe_keypad_resources[] = {
340 {
341 .name = "KEYPAD",
27e34995
RV		 342 .flags = IORESOURCE_IRQ,
343 },
344 {
345 .name = "KEYPAD_OVER",
27e34995
RV		 346 .flags = IORESOURCE_IRQ,
347 },
348};
349
6bbb3c4c 350static const struct mfd_cell stmpe_keypad_cell = {
27e34995 351 .name = "stmpe-keypad",
6ea32387 352 .of_compatible = "st,stmpe-keypad",
27e34995
RV		 353 .resources = stmpe_keypad_resources,
354 .num_resources = ARRAY_SIZE(stmpe_keypad_resources),
355};
356
b273c5e0
LW		 357/*
358 * PWM (1601, 2401, 2403)
359 */
360static struct resource stmpe_pwm_resources[] = {
361 {
362 .name = "PWM0",
363 .flags = IORESOURCE_IRQ,
364 },
365 {
366 .name = "PWM1",
367 .flags = IORESOURCE_IRQ,
368 },
369 {
370 .name = "PWM2",
371 .flags = IORESOURCE_IRQ,
372 },
373};
374
375static const struct mfd_cell stmpe_pwm_cell = {
376 .name = "stmpe-pwm",
377 .of_compatible = "st,stmpe-pwm",
378 .resources = stmpe_pwm_resources,
379 .num_resources = ARRAY_SIZE(stmpe_pwm_resources),
380};
381
7f7f4ea1
VK		 382/*
383 * STMPE801
384 */
385static const u8 stmpe801_regs[] = {
386 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID,
387 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL,
388 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA,
389 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN,
390 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN,
391 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR,
392 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
393 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
394
395};
396
397static struct stmpe_variant_block stmpe801_blocks[] = {
398 {
399 .cell = &stmpe_gpio_cell,
400 .irq = 0,
401 .block = STMPE_BLOCK_GPIO,
402 },
403};
404
e31f9b82
CB		 405static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
406 {
407 .cell = &stmpe_gpio_cell_noirq,
408 .block = STMPE_BLOCK_GPIO,
409 },
410};
411
7f7f4ea1
VK		 412static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
413 bool enable)
414{
415 if (blocks & STMPE_BLOCK_GPIO)
416 return 0;
417 else
418 return -EINVAL;
419}
420
421static struct stmpe_variant_info stmpe801 = {
422 .name = "stmpe801",
423 .id_val = STMPE801_ID,
424 .id_mask = 0xffff,
425 .num_gpios = 8,
426 .regs = stmpe801_regs,
427 .blocks = stmpe801_blocks,
428 .num_blocks = ARRAY_SIZE(stmpe801_blocks),
429 .num_irqs = STMPE801_NR_INTERNAL_IRQS,
430 .enable = stmpe801_enable,
431};
432
e31f9b82
CB		 433static struct stmpe_variant_info stmpe801_noirq = {
434 .name = "stmpe801",
435 .id_val = STMPE801_ID,
436 .id_mask = 0xffff,
437 .num_gpios = 8,
438 .regs = stmpe801_regs,
439 .blocks = stmpe801_blocks_noirq,
440 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq),
441 .enable = stmpe801_enable,
442};
443
27e34995 444/*
1cda2394 445 * Touchscreen (STMPE811 or STMPE610)
27e34995
RV		 446 */
447
448static struct resource stmpe_ts_resources[] = {
449 {
450 .name = "TOUCH_DET",
27e34995
RV		 451 .flags = IORESOURCE_IRQ,
452 },
453 {
454 .name = "FIFO_TH",
27e34995
RV		 455 .flags = IORESOURCE_IRQ,
456 },
457};
458
6bbb3c4c 459static const struct mfd_cell stmpe_ts_cell = {
27e34995 460 .name = "stmpe-ts",
037db524 461 .of_compatible = "st,stmpe-ts",
27e34995
RV		 462 .resources = stmpe_ts_resources,
463 .num_resources = ARRAY_SIZE(stmpe_ts_resources),
464};
465
466/*
1cda2394 467 * STMPE811 or STMPE610
27e34995
RV		 468 */
469
470static const u8 stmpe811_regs[] = {
471 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
0f4be8cf
PC		 472 [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL,
473 [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2,
27e34995
RV		 474 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
475 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
476 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
477 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA,
478 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN,
479 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN,
480 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR,
481 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE,
482 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE,
483 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
484 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
485 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
486 [STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED,
487};
488
489static struct stmpe_variant_block stmpe811_blocks[] = {
490 {
491 .cell = &stmpe_gpio_cell,
492 .irq = STMPE811_IRQ_GPIOC,
493 .block = STMPE_BLOCK_GPIO,
494 },
495 {
496 .cell = &stmpe_ts_cell,
497 .irq = STMPE811_IRQ_TOUCH_DET,
498 .block = STMPE_BLOCK_TOUCHSCREEN,
499 },
500};
501
502static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
503 bool enable)
504{
505 unsigned int mask = 0;
506
507 if (blocks & STMPE_BLOCK_GPIO)
508 mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
509
510 if (blocks & STMPE_BLOCK_ADC)
511 mask |= STMPE811_SYS_CTRL2_ADC_OFF;
512
513 if (blocks & STMPE_BLOCK_TOUCHSCREEN)
514 mask |= STMPE811_SYS_CTRL2_TSC_OFF;
515
0f4be8cf 516 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
27e34995
RV		 517 enable ? 0 : mask);
518}
519
520static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
521{
522 /* 0 for touchscreen, 1 for GPIO */
523 return block != STMPE_BLOCK_TOUCHSCREEN;
524}
525
526static struct stmpe_variant_info stmpe811 = {
527 .name = "stmpe811",
528 .id_val = 0x0811,
529 .id_mask = 0xffff,
530 .num_gpios = 8,
531 .af_bits = 1,
532 .regs = stmpe811_regs,
533 .blocks = stmpe811_blocks,
534 .num_blocks = ARRAY_SIZE(stmpe811_blocks),
535 .num_irqs = STMPE811_NR_INTERNAL_IRQS,
536 .enable = stmpe811_enable,
537 .get_altfunc = stmpe811_get_altfunc,
538};
539
1cda2394
VK		 540/* Similar to 811, except number of gpios */
541static struct stmpe_variant_info stmpe610 = {
542 .name = "stmpe610",
543 .id_val = 0x0811,
544 .id_mask = 0xffff,
545 .num_gpios = 6,
546 .af_bits = 1,
547 .regs = stmpe811_regs,
548 .blocks = stmpe811_blocks,
549 .num_blocks = ARRAY_SIZE(stmpe811_blocks),
550 .num_irqs = STMPE811_NR_INTERNAL_IRQS,
551 .enable = stmpe811_enable,
552 .get_altfunc = stmpe811_get_altfunc,
553};
554
27e34995
RV		 555/*
556 * STMPE1601
557 */
558
559static const u8 stmpe1601_regs[] = {
560 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
0f4be8cf
PC		 561 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
562 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
27e34995
RV		 563 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
564 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
565 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
566 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
567 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
568 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
569 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
570 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
571 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
80e1dd82 572 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB,
27e34995
RV		 573 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
574 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
575 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
576 [STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB,
577};
578
579static struct stmpe_variant_block stmpe1601_blocks[] = {
580 {
581 .cell = &stmpe_gpio_cell,
5204e51d 582 .irq = STMPE1601_IRQ_GPIOC,
27e34995
RV		 583 .block = STMPE_BLOCK_GPIO,
584 },
585 {
586 .cell = &stmpe_keypad_cell,
5204e51d 587 .irq = STMPE1601_IRQ_KEYPAD,
27e34995
RV		 588 .block = STMPE_BLOCK_KEYPAD,
589 },
b273c5e0
LW		 590 {
591 .cell = &stmpe_pwm_cell,
592 .irq = STMPE1601_IRQ_PWM0,
593 .block = STMPE_BLOCK_PWM,
594 },
27e34995
RV		 595};
596
5981f4e6
SI		 597/* supported autosleep timeout delay (in msecs) */
598static const int stmpe_autosleep_delay[] = {
599 4, 16, 32, 64, 128, 256, 512, 1024,
600};
601
602static int stmpe_round_timeout(int timeout)
603{
604 int i;
605
606 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
607 if (stmpe_autosleep_delay[i] >= timeout)
608 return i;
609 }
610
611 /*
612 * requests for delays longer than supported should not return the
613 * longest supported delay
614 */
615 return -EINVAL;
616}
617
618static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
619{
620 int ret;
621
622 if (!stmpe->variant->enable_autosleep)
623 return -ENOSYS;
624
625 mutex_lock(&stmpe->lock);
626 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
627 mutex_unlock(&stmpe->lock);
628
629 return ret;
630}
631
632/*
633 * Both stmpe 1601/2403 support same layout for autosleep
634 */
635static int stmpe1601_autosleep(struct stmpe *stmpe,
636 int autosleep_timeout)
637{
638 int ret, timeout;
639
640 /* choose the best available timeout */
641 timeout = stmpe_round_timeout(autosleep_timeout);
642 if (timeout < 0) {
643 dev_err(stmpe->dev, "invalid timeout\n");
644 return timeout;
645 }
646
0f4be8cf 647 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
5981f4e6
SI		 648 STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
649 timeout);
650 if (ret < 0)
651 return ret;
652
0f4be8cf 653 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
5981f4e6
SI		 654 STPME1601_AUTOSLEEP_ENABLE,
655 STPME1601_AUTOSLEEP_ENABLE);
656}
657
27e34995
RV		 658static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
659 bool enable)
660{
661 unsigned int mask = 0;
662
663 if (blocks & STMPE_BLOCK_GPIO)
664 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
b69d2ad6
LW		 665 else
666 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
27e34995
RV		 667
668 if (blocks & STMPE_BLOCK_KEYPAD)
669 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
b69d2ad6
LW		 670 else
671 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
672
673 if (blocks & STMPE_BLOCK_PWM)
674 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
675 else
676 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
27e34995 677
0f4be8cf 678 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
27e34995
RV		 679 enable ? mask : 0);
680}
681
682static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
683{
684 switch (block) {
685 case STMPE_BLOCK_PWM:
686 return 2;
687
688 case STMPE_BLOCK_KEYPAD:
689 return 1;
690
691 case STMPE_BLOCK_GPIO:
692 default:
693 return 0;
694 }
695}
696
697static struct stmpe_variant_info stmpe1601 = {
698 .name = "stmpe1601",
699 .id_val = 0x0210,
700 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */
701 .num_gpios = 16,
702 .af_bits = 2,
703 .regs = stmpe1601_regs,
704 .blocks = stmpe1601_blocks,
705 .num_blocks = ARRAY_SIZE(stmpe1601_blocks),
706 .num_irqs = STMPE1601_NR_INTERNAL_IRQS,
707 .enable = stmpe1601_enable,
708 .get_altfunc = stmpe1601_get_altfunc,
5981f4e6 709 .enable_autosleep = stmpe1601_autosleep,
27e34995
RV		 710};
711
230f13a5
JNG		 712/*
713 * STMPE1801
714 */
715static const u8 stmpe1801_regs[] = {
716 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
0f4be8cf 717 [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL,
230f13a5
JNG		 718 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
719 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
720 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
721 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
722 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
723 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
724 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
725 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
726 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
80e1dd82 727 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW,
230f13a5
JNG		 728 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
729 [STMPE_IDX_ISGPIOR_LSB] = STMPE1801_REG_INT_STA_GPIO_LOW,
730};
731
732static struct stmpe_variant_block stmpe1801_blocks[] = {
733 {
734 .cell = &stmpe_gpio_cell,
735 .irq = STMPE1801_IRQ_GPIOC,
736 .block = STMPE_BLOCK_GPIO,
737 },
738 {
739 .cell = &stmpe_keypad_cell,
740 .irq = STMPE1801_IRQ_KEYPAD,
741 .block = STMPE_BLOCK_KEYPAD,
742 },
743};
744
745static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
746 bool enable)
747{
748 unsigned int mask = 0;
749 if (blocks & STMPE_BLOCK_GPIO)
750 mask |= STMPE1801_MSK_INT_EN_GPIO;
751
752 if (blocks & STMPE_BLOCK_KEYPAD)
753 mask |= STMPE1801_MSK_INT_EN_KPC;
754
755 return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
756 enable ? mask : 0);
757}
758
c4dd1ba3 759static int stmpe_reset(struct stmpe *stmpe)
230f13a5 760{
c4dd1ba3 761 u16 id_val = stmpe->variant->id_val;
230f13a5
JNG		 762 unsigned long timeout;
763 int ret = 0;
c4dd1ba3
PC		 764 u8 reset_bit;
765
766 if (id_val == STMPE811_ID)
767 /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
768 reset_bit = STMPE811_SYS_CTRL_RESET;
769 else
770 /* all other STMPE variant use bit 7 of SYS_CTRL register */
771 reset_bit = STMPE_SYS_CTRL_RESET;
230f13a5 772
0f4be8cf 773 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
c4dd1ba3 774 reset_bit, reset_bit);
230f13a5
JNG		 775 if (ret < 0)
776 return ret;
777
778 timeout = jiffies + msecs_to_jiffies(100);
779 while (time_before(jiffies, timeout)) {
0f4be8cf 780 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
230f13a5
JNG		 781 if (ret < 0)
782 return ret;
c4dd1ba3 783 if (!(ret & reset_bit))
230f13a5
JNG		 784 return 0;
785 usleep_range(100, 200);
52397fe1 786 }
230f13a5
JNG		 787 return -EIO;
788}
789
790static struct stmpe_variant_info stmpe1801 = {
791 .name = "stmpe1801",
792 .id_val = STMPE1801_ID,
793 .id_mask = 0xfff0,
794 .num_gpios = 18,
795 .af_bits = 0,
796 .regs = stmpe1801_regs,
797 .blocks = stmpe1801_blocks,
798 .num_blocks = ARRAY_SIZE(stmpe1801_blocks),
799 .num_irqs = STMPE1801_NR_INTERNAL_IRQS,
800 .enable = stmpe1801_enable,
801 /* stmpe1801 do not have any gpio alternate function */
802 .get_altfunc = NULL,
803};
804
27e34995
RV		 805/*
806 * STMPE24XX
807 */
808
809static const u8 stmpe24xx_regs[] = {
810 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
0f4be8cf
PC		 811 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
812 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
27e34995
RV		 813 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
814 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
815 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
816 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
817 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
818 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
819 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
820 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
821 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
80e1dd82
LW		 822 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB,
823 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB,
27e34995
RV		 824 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
825 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
826 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
827 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
828};
829
830static struct stmpe_variant_block stmpe24xx_blocks[] = {
831 {
832 .cell = &stmpe_gpio_cell,
833 .irq = STMPE24XX_IRQ_GPIOC,
834 .block = STMPE_BLOCK_GPIO,
835 },
836 {
837 .cell = &stmpe_keypad_cell,
838 .irq = STMPE24XX_IRQ_KEYPAD,
839 .block = STMPE_BLOCK_KEYPAD,
840 },
b273c5e0
LW		 841 {
842 .cell = &stmpe_pwm_cell,
843 .irq = STMPE24XX_IRQ_PWM0,
844 .block = STMPE_BLOCK_PWM,
845 },
27e34995
RV		 846};
847
848static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
849 bool enable)
850{
851 unsigned int mask = 0;
852
853 if (blocks & STMPE_BLOCK_GPIO)
854 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
855
856 if (blocks & STMPE_BLOCK_KEYPAD)
857 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
858
0f4be8cf 859 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
27e34995
RV		 860 enable ? mask : 0);
861}
862
863static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
864{
865 switch (block) {
866 case STMPE_BLOCK_ROTATOR:
867 return 2;
868
869 case STMPE_BLOCK_KEYPAD:
f6d10341 870 case STMPE_BLOCK_PWM:
27e34995
RV		 871 return 1;
872
873 case STMPE_BLOCK_GPIO:
874 default:
875 return 0;
876 }
877}
878
879static struct stmpe_variant_info stmpe2401 = {
880 .name = "stmpe2401",
881 .id_val = 0x0101,
882 .id_mask = 0xffff,
883 .num_gpios = 24,
884 .af_bits = 2,
885 .regs = stmpe24xx_regs,
886 .blocks = stmpe24xx_blocks,
887 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
888 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
889 .enable = stmpe24xx_enable,
890 .get_altfunc = stmpe24xx_get_altfunc,
891};
892
893static struct stmpe_variant_info stmpe2403 = {
894 .name = "stmpe2403",
895 .id_val = 0x0120,
896 .id_mask = 0xffff,
897 .num_gpios = 24,
898 .af_bits = 2,
899 .regs = stmpe24xx_regs,
900 .blocks = stmpe24xx_blocks,
901 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
902 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
903 .enable = stmpe24xx_enable,
904 .get_altfunc = stmpe24xx_get_altfunc,
5981f4e6 905 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */
27e34995
RV		 906};
907
e31f9b82 908static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
1cda2394 909 [STMPE610] = &stmpe610,
7f7f4ea1 910 [STMPE801] = &stmpe801,
27e34995
RV		 911 [STMPE811] = &stmpe811,
912 [STMPE1601] = &stmpe1601,
230f13a5 913 [STMPE1801] = &stmpe1801,
27e34995
RV		 914 [STMPE2401] = &stmpe2401,
915 [STMPE2403] = &stmpe2403,
916};
917
e31f9b82
CB		 918/*
919 * These devices can be connected in a 'no-irq' configuration - the irq pin
920 * is not used and the device cannot interrupt the CPU. Here we only list
921 * devices which support this configuration - the driver will fail probing
922 * for any devices not listed here which are configured in this way.
923 */
924static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
925 [STMPE801] = &stmpe801_noirq,
926};
927
27e34995
RV		 928static irqreturn_t stmpe_irq(int irq, void *data)
929{
930 struct stmpe *stmpe = data;
931 struct stmpe_variant_info *variant = stmpe->variant;
932 int num = DIV_ROUND_UP(variant->num_irqs, 8);
230f13a5 933 u8 israddr;
7929fa77 934 u8 isr[3];
27e34995
RV		 935 int ret;
936 int i;
937
7f7f4ea1 938 if (variant->id_val == STMPE801_ID) {
76f93992
LJ		 939 int base = irq_create_mapping(stmpe->domain, 0);
940
941 handle_nested_irq(base);
7f7f4ea1
VK		 942 return IRQ_HANDLED;
943 }
944
230f13a5
JNG		 945 if (variant->id_val == STMPE1801_ID)
946 israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
947 else
948 israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
949
27e34995
RV		 950 ret = stmpe_block_read(stmpe, israddr, num, isr);
951 if (ret < 0)
952 return IRQ_NONE;
953
954 for (i = 0; i < num; i++) {
955 int bank = num - i - 1;
956 u8 status = isr[i];
957 u8 clear;
958
959 status &= stmpe->ier[bank];
960 if (!status)
961 continue;
962
963 clear = status;
964 while (status) {
965 int bit = __ffs(status);
966 int line = bank * 8 + bit;
76f93992 967 int nestedirq = irq_create_mapping(stmpe->domain, line);
27e34995 968
76f93992 969 handle_nested_irq(nestedirq);
27e34995
RV		 970 status &= ~(1 << bit);
971 }
972
973 stmpe_reg_write(stmpe, israddr + i, clear);
974 }
975
976 return IRQ_HANDLED;
977}
978
43b8c084 979static void stmpe_irq_lock(struct irq_data *data)
27e34995 980{
43b8c084 981 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
27e34995
RV		 982
983 mutex_lock(&stmpe->irq_lock);
984}
985
43b8c084 986static void stmpe_irq_sync_unlock(struct irq_data *data)
27e34995 987{
43b8c084 988 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
27e34995
RV		 989 struct stmpe_variant_info *variant = stmpe->variant;
990 int num = DIV_ROUND_UP(variant->num_irqs, 8);
991 int i;
992
993 for (i = 0; i < num; i++) {
994 u8 new = stmpe->ier[i];
995 u8 old = stmpe->oldier[i];
996
997 if (new == old)
998 continue;
999
1000 stmpe->oldier[i] = new;
1001 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new);
1002 }
1003
1004 mutex_unlock(&stmpe->irq_lock);
1005}
1006
43b8c084 1007static void stmpe_irq_mask(struct irq_data *data)
27e34995 1008{
43b8c084 1009 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
76f93992 1010 int offset = data->hwirq;
27e34995
RV		 1011 int regoffset = offset / 8;
1012 int mask = 1 << (offset % 8);
1013
1014 stmpe->ier[regoffset] &= ~mask;
1015}
1016
43b8c084 1017static void stmpe_irq_unmask(struct irq_data *data)
27e34995 1018{
43b8c084 1019 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
76f93992 1020 int offset = data->hwirq;
27e34995
RV		 1021 int regoffset = offset / 8;
1022 int mask = 1 << (offset % 8);
1023
1024 stmpe->ier[regoffset] |= mask;
1025}
1026
1027static struct irq_chip stmpe_irq_chip = {
1028 .name = "stmpe",
43b8c084
MB		 1029 .irq_bus_lock = stmpe_irq_lock,
1030 .irq_bus_sync_unlock = stmpe_irq_sync_unlock,
1031 .irq_mask = stmpe_irq_mask,
1032 .irq_unmask = stmpe_irq_unmask,
27e34995
RV		 1033};
1034
76f93992
LJ		 1035static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
1036 irq_hw_number_t hwirq)
27e34995 1037{
76f93992 1038 struct stmpe *stmpe = d->host_data;
7f7f4ea1 1039 struct irq_chip *chip = NULL;
27e34995 1040
7f7f4ea1
VK		 1041 if (stmpe->variant->id_val != STMPE801_ID)
1042 chip = &stmpe_irq_chip;
1043
76f93992
LJ		 1044 irq_set_chip_data(virq, stmpe);
1045 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
1046 irq_set_nested_thread(virq, 1);
76f93992 1047 irq_set_noprobe(virq);
27e34995
RV		 1048
1049 return 0;
1050}
1051
76f93992 1052static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
27e34995 1053{
76f93992
LJ		 1054 irq_set_chip_and_handler(virq, NULL, NULL);
1055 irq_set_chip_data(virq, NULL);
1056}
1057
7ce7b26f 1058static const struct irq_domain_ops stmpe_irq_ops = {
76f93992
LJ		 1059 .map = stmpe_irq_map,
1060 .unmap = stmpe_irq_unmap,
1061 .xlate = irq_domain_xlate_twocell,
1062};
1063
612b95cd 1064static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
76f93992 1065{
b20a4371 1066 int base = 0;
76f93992
LJ		 1067 int num_irqs = stmpe->variant->num_irqs;
1068
b20a4371
LJ		 1069 stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
1070 &stmpe_irq_ops, stmpe);
76f93992
LJ		 1071 if (!stmpe->domain) {
1072 dev_err(stmpe->dev, "Failed to create irqdomain\n");
1073 return -ENOSYS;
27e34995 1074 }
76f93992
LJ		 1075
1076 return 0;
27e34995
RV		 1077}
1078
612b95cd 1079static int stmpe_chip_init(struct stmpe *stmpe)
27e34995
RV		 1080{
1081 unsigned int irq_trigger = stmpe->pdata->irq_trigger;
5981f4e6 1082 int autosleep_timeout = stmpe->pdata->autosleep_timeout;
27e34995 1083 struct stmpe_variant_info *variant = stmpe->variant;
e31f9b82 1084 u8 icr = 0;
27e34995
RV		 1085 unsigned int id;
1086 u8 data[2];
1087 int ret;
1088
1089 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
1090 ARRAY_SIZE(data), data);
1091 if (ret < 0)
1092 return ret;
1093
1094 id = (data[0] << 8) | data[1];
1095 if ((id & variant->id_mask) != variant->id_val) {
1096 dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
1097 return -EINVAL;
1098 }
1099
1100 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
1101
1102 /* Disable all modules -- subdrivers should enable what they need. */
1103 ret = stmpe_disable(stmpe, ~0);
1104 if (ret)
1105 return ret;
1106
c4dd1ba3
PC		 1107 ret = stmpe_reset(stmpe);
1108 if (ret < 0)
1109 return ret;
230f13a5 1110
e31f9b82 1111 if (stmpe->irq >= 0) {
7f7f4ea1 1112 if (id == STMPE801_ID)
c16bee78 1113 icr = STMPE_SYS_CTRL_INT_EN;
7f7f4ea1 1114 else
e31f9b82 1115 icr = STMPE_ICR_LSB_GIM;
27e34995 1116
e31f9b82
CB		 1117 /* STMPE801 doesn't support Edge interrupts */
1118 if (id != STMPE801_ID) {
1119 if (irq_trigger == IRQF_TRIGGER_FALLING ||
1120 irq_trigger == IRQF_TRIGGER_RISING)
1121 icr |= STMPE_ICR_LSB_EDGE;
1122 }
1123
1124 if (irq_trigger == IRQF_TRIGGER_RISING ||
1125 irq_trigger == IRQF_TRIGGER_HIGH) {
1126 if (id == STMPE801_ID)
c16bee78 1127 icr |= STMPE_SYS_CTRL_INT_HI;
e31f9b82
CB		 1128 else
1129 icr |= STMPE_ICR_LSB_HIGH;
1130 }
7f7f4ea1 1131 }
27e34995 1132
5981f4e6
SI		 1133 if (stmpe->pdata->autosleep) {
1134 ret = stmpe_autosleep(stmpe, autosleep_timeout);
1135 if (ret)
1136 return ret;
1137 }
1138
27e34995
RV		 1139 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
1140}
1141
6bbb3c4c 1142static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
27e34995
RV		 1143{
1144 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
9e9dc7d9 1145 NULL, 0, stmpe->domain);
27e34995
RV		 1146}
1147
612b95cd 1148static int stmpe_devices_init(struct stmpe *stmpe)
27e34995
RV		 1149{
1150 struct stmpe_variant_info *variant = stmpe->variant;
1151 unsigned int platform_blocks = stmpe->pdata->blocks;
1152 int ret = -EINVAL;
7da0cbfc 1153 int i, j;
27e34995
RV		 1154
1155 for (i = 0; i < variant->num_blocks; i++) {
1156 struct stmpe_variant_block *block = &variant->blocks[i];
1157
1158 if (!(platform_blocks & block->block))
1159 continue;
1160
7da0cbfc
LJ		 1161 for (j = 0; j < block->cell->num_resources; j++) {
1162 struct resource *res =
1163 (struct resource *) &block->cell->resources[j];
1164
1165 /* Dynamically fill in a variant's IRQ. */
1166 if (res->flags & IORESOURCE_IRQ)
1167 res->start = res->end = block->irq + j;
1168 }
1169
27e34995 1170 platform_blocks &= ~block->block;
7da0cbfc 1171 ret = stmpe_add_device(stmpe, block->cell);
27e34995
RV		 1172 if (ret)
1173 return ret;
1174 }
1175
1176 if (platform_blocks)
1177 dev_warn(stmpe->dev,
1178 "platform wants blocks (%#x) not present on variant",
1179 platform_blocks);
1180
1181 return ret;
1182}
1183
a9c4055d
MB		 1184static void stmpe_of_probe(struct stmpe_platform_data *pdata,
1185 struct device_node *np)
909582ca
LJ		 1186{
1187 struct device_node *child;
1188
408a3fa8
GF		 1189 pdata->id = of_alias_get_id(np, "stmpe-i2c");
1190 if (pdata->id < 0)
1191 pdata->id = -1;
1192
851ec596
SC		 1193 pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0,
1194 &pdata->irq_trigger);
1195 if (gpio_is_valid(pdata->irq_gpio))
1196 pdata->irq_over_gpio = 1;
1197 else
1198 pdata->irq_trigger = IRQF_TRIGGER_NONE;
ac713cc9 1199
909582ca
LJ		 1200 of_property_read_u32(np, "st,autosleep-timeout",
1201 &pdata->autosleep_timeout);
1202
1203 pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
1204
1205 for_each_child_of_node(np, child) {
1206 if (!strcmp(child->name, "stmpe_gpio")) {
1207 pdata->blocks |= STMPE_BLOCK_GPIO;
ac713cc9 1208 } else if (!strcmp(child->name, "stmpe_keypad")) {
909582ca 1209 pdata->blocks |= STMPE_BLOCK_KEYPAD;
ac713cc9 1210 } else if (!strcmp(child->name, "stmpe_touchscreen")) {
909582ca 1211 pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
ac713cc9 1212 } else if (!strcmp(child->name, "stmpe_adc")) {
909582ca 1213 pdata->blocks |= STMPE_BLOCK_ADC;
ac713cc9
VKS		 1214 } else if (!strcmp(child->name, "stmpe_pwm")) {
1215 pdata->blocks |= STMPE_BLOCK_PWM;
1216 } else if (!strcmp(child->name, "stmpe_rotator")) {
1217 pdata->blocks |= STMPE_BLOCK_ROTATOR;
909582ca
LJ		 1218 }
1219 }
1220}
1221
1a6e4b74 1222/* Called from client specific probe routines */
c00572bc 1223int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
208c4343 1224{
fc1882dc 1225 struct stmpe_platform_data *pdata;
909582ca 1226 struct device_node *np = ci->dev->of_node;
27e34995
RV		 1227 struct stmpe *stmpe;
1228 int ret;
1229
fc1882dc
LW		 1230 pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
1231 if (!pdata)
1232 return -ENOMEM;
cb5faba9 1233
fc1882dc 1234 stmpe_of_probe(pdata, np);
a200e320 1235
fc1882dc
LW		 1236 if (of_find_property(np, "interrupts", NULL) == NULL)
1237 ci->irq = -1;
27e34995 1238
cb5faba9 1239 stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL);
27e34995
RV		 1240 if (!stmpe)
1241 return -ENOMEM;
1242
1243 mutex_init(&stmpe->irq_lock);
1244 mutex_init(&stmpe->lock);
1245
1a6e4b74
VK		 1246 stmpe->dev = ci->dev;
1247 stmpe->client = ci->client;
27e34995 1248 stmpe->pdata = pdata;
1a6e4b74
VK		 1249 stmpe->ci = ci;
1250 stmpe->partnum = partnum;
1251 stmpe->variant = stmpe_variant_info[partnum];
27e34995
RV		 1252 stmpe->regs = stmpe->variant->regs;
1253 stmpe->num_gpios = stmpe->variant->num_gpios;
9c9e3214
LW		 1254 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
1255 if (!IS_ERR(stmpe->vcc)) {
1256 ret = regulator_enable(stmpe->vcc);
1257 if (ret)
1258 dev_warn(ci->dev, "failed to enable VCC supply\n");
1259 }
1260 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
1261 if (!IS_ERR(stmpe->vio)) {
1262 ret = regulator_enable(stmpe->vio);
1263 if (ret)
1264 dev_warn(ci->dev, "failed to enable VIO supply\n");
1265 }
1a6e4b74 1266 dev_set_drvdata(stmpe->dev, stmpe);
27e34995 1267
1a6e4b74
VK		 1268 if (ci->init)
1269 ci->init(stmpe);
27e34995 1270
73de16db 1271 if (pdata->irq_over_gpio) {
cb5faba9
VK		 1272 ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio,
1273 GPIOF_DIR_IN, "stmpe");
73de16db
VK		 1274 if (ret) {
1275 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n",
1276 ret);
cb5faba9 1277 return ret;
73de16db
VK		 1278 }
1279
1280 stmpe->irq = gpio_to_irq(pdata->irq_gpio);
1281 } else {
1a6e4b74 1282 stmpe->irq = ci->irq;
73de16db
VK		 1283 }
1284
e31f9b82
CB		 1285 if (stmpe->irq < 0) {
1286 /* use alternate variant info for no-irq mode, if supported */
1287 dev_info(stmpe->dev,
1288 "%s configured in no-irq mode by platform data\n",
1289 stmpe->variant->name);
1290 if (!stmpe_noirq_variant_info[stmpe->partnum]) {
1291 dev_err(stmpe->dev,
1292 "%s does not support no-irq mode!\n",
1293 stmpe->variant->name);
cb5faba9 1294 return -ENODEV;
e31f9b82
CB		 1295 }
1296 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
ac713cc9 1297 } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) {
1a5595cb 1298 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq);
e31f9b82
CB		 1299 }
1300
27e34995
RV		 1301 ret = stmpe_chip_init(stmpe);
1302 if (ret)
cb5faba9 1303 return ret;
27e34995 1304
e31f9b82 1305 if (stmpe->irq >= 0) {
909582ca 1306 ret = stmpe_irq_init(stmpe, np);
e31f9b82 1307 if (ret)
cb5faba9 1308 return ret;
27e34995 1309
cb5faba9
VK		 1310 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL,
1311 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT,
e31f9b82
CB		 1312 "stmpe", stmpe);
1313 if (ret) {
1314 dev_err(stmpe->dev, "failed to request IRQ: %d\n",
1315 ret);
cb5faba9 1316 return ret;
e31f9b82 1317 }
27e34995
RV		 1318 }
1319
1320 ret = stmpe_devices_init(stmpe);
cb5faba9
VK		 1321 if (!ret)
1322 return 0;
27e34995 1323
cb5faba9 1324 dev_err(stmpe->dev, "failed to add children\n");
27e34995 1325 mfd_remove_devices(stmpe->dev);
cb5faba9 1326
27e34995
RV		 1327 return ret;
1328}
1329
1a6e4b74 1330int stmpe_remove(struct stmpe *stmpe)
27e34995 1331{
9c9e3214
LW		 1332 if (!IS_ERR(stmpe->vio))
1333 regulator_disable(stmpe->vio);
1334 if (!IS_ERR(stmpe->vcc))
1335 regulator_disable(stmpe->vcc);
1336
27e34995
RV		 1337 mfd_remove_devices(stmpe->dev);
1338
27e34995
RV		 1339 return 0;
1340}
1341
208c4343 1342#ifdef CONFIG_PM
1a6e4b74
VK		 1343static int stmpe_suspend(struct device *dev)
1344{
1345 struct stmpe *stmpe = dev_get_drvdata(dev);
208c4343 1346
e31f9b82 1347 if (stmpe->irq >= 0 && device_may_wakeup(dev))
1a6e4b74 1348 enable_irq_wake(stmpe->irq);
27e34995 1349
1a6e4b74 1350 return 0;
27e34995 1351}
27e34995 1352
1a6e4b74 1353static int stmpe_resume(struct device *dev)
27e34995 1354{
1a6e4b74
VK		 1355 struct stmpe *stmpe = dev_get_drvdata(dev);
1356
e31f9b82 1357 if (stmpe->irq >= 0 && device_may_wakeup(dev))
1a6e4b74
VK		 1358 disable_irq_wake(stmpe->irq);
1359
1360 return 0;
27e34995 1361}
27e34995 1362
1a6e4b74
VK		 1363const struct dev_pm_ops stmpe_dev_pm_ops = {
1364 .suspend = stmpe_suspend,
1365 .resume = stmpe_resume,
1366};
1367#endif
Linux kernel - Deliverables
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