projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 27e34995 RV |
1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | * | |
| 4 | * License Terms: GNU General Public License, version 2 | |
| 5 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
| 6 | */ | |
| 7 | ||
| 8 | #ifndef __STMPE_H | |
| 9 | #define __STMPE_H | |
| 10 | ||
| 11 | #ifdef STMPE_DUMP_BYTES | |
| 12 | static inline void stmpe_dump_bytes(const char *str, const void *buf, | |
| 13 | size_t len) | |
| 14 | { | |
| 15 | print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len); | |
| 16 | } | |
| 17 | #else | |
| 18 | static inline void stmpe_dump_bytes(const char *str, const void *buf, | |
| 19 | size_t len) | |
| 20 | { | |
| 21 | } | |
| 22 | #endif | |
| 23 | ||
| 24 | /** | |
| 25 | * struct stmpe_variant_block - information about block | |
| 26 | * @cell: base mfd cell | |
| 27 | * @irq: interrupt number to be added to each IORESOURCE_IRQ | |
| 28 | * in the cell | |
| 29 | * @block: block id; used for identification with platform data and for | |
| 30 | * enable and altfunc callbacks | |
| 31 | */ | |
| 32 | struct stmpe_variant_block { | |
| 33 | struct mfd_cell *cell; | |
| 34 | int irq; | |
| 35 | enum stmpe_block block; | |
| 36 | }; | |
| 37 | ||
| 38 | /** | |
| 39 | * struct stmpe_variant_info - variant-specific information | |
| 40 | * @name: part name | |
| 41 | * @id_val: content of CHIPID register | |
| 42 | * @id_mask: bits valid in CHIPID register for comparison with id_val | |
| 43 | * @num_gpios: number of GPIOS | |
| 44 | * @af_bits: number of bits used to specify the alternate function | |
| 45 | * @blocks: list of blocks present on this device | |
| 46 | * @num_blocks: number of blocks present on this device | |
| 47 | * @num_irqs: number of internal IRQs available on this device | |
| 48 | * @enable: callback to enable the specified blocks. | |
| 49 | * Called with the I/O lock held. | |
| 50 | * @get_altfunc: callback to get the alternate function number for the | |
| 51 | * specific block | |
| 52 | */ | |
| 53 | struct stmpe_variant_info { | |
| 54 | const char *name; | |
| 55 | u16 id_val; | |
| 56 | u16 id_mask; | |
| 57 | int num_gpios; | |
| 58 | int af_bits; | |
| 59 | const u8 *regs; | |
| 60 | struct stmpe_variant_block *blocks; | |
| 61 | int num_blocks; | |
| 62 | int num_irqs; | |
| 63 | int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable); | |
| 64 | int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block); | |
| 65 | }; | |
| 66 | ||
| 67 | #define STMPE_ICR_LSB_HIGH (1 << 2) | |
| 68 | #define STMPE_ICR_LSB_EDGE (1 << 1) | |
| 69 | #define STMPE_ICR_LSB_GIM (1 << 0) | |
| 70 | ||
| 71 | /* | |
| 72 | * STMPE811 | |
| 73 | */ | |
| 74 | ||
| 75 | #define STMPE811_IRQ_TOUCH_DET 0 | |
| 76 | #define STMPE811_IRQ_FIFO_TH 1 | |
| 77 | #define STMPE811_IRQ_FIFO_OFLOW 2 | |
| 78 | #define STMPE811_IRQ_FIFO_FULL 3 | |
| 79 | #define STMPE811_IRQ_FIFO_EMPTY 4 | |
| 80 | #define STMPE811_IRQ_TEMP_SENS 5 | |
| 81 | #define STMPE811_IRQ_ADC 6 | |
| 82 | #define STMPE811_IRQ_GPIOC 7 | |
| 83 | #define STMPE811_NR_INTERNAL_IRQS 8 | |
| 84 | ||
| 85 | #define STMPE811_REG_CHIP_ID 0x00 | |
| 86 | #define STMPE811_REG_SYS_CTRL2 0x04 | |
| 87 | #define STMPE811_REG_INT_CTRL 0x09 | |
| 88 | #define STMPE811_REG_INT_EN 0x0A | |
| 89 | #define STMPE811_REG_INT_STA 0x0B | |
| 90 | #define STMPE811_REG_GPIO_INT_EN 0x0C | |
| 91 | #define STMPE811_REG_GPIO_INT_STA 0x0D | |
| 92 | #define STMPE811_REG_GPIO_SET_PIN 0x10 | |
| 93 | #define STMPE811_REG_GPIO_CLR_PIN 0x11 | |
| 94 | #define STMPE811_REG_GPIO_MP_STA 0x12 | |
| 95 | #define STMPE811_REG_GPIO_DIR 0x13 | |
| 96 | #define STMPE811_REG_GPIO_ED 0x14 | |
| 97 | #define STMPE811_REG_GPIO_RE 0x15 | |
| 98 | #define STMPE811_REG_GPIO_FE 0x16 | |
| 99 | #define STMPE811_REG_GPIO_AF 0x17 | |
| 100 | ||
| 101 | #define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0) | |
| 102 | #define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1) | |
| 103 | #define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2) | |
| 104 | #define STMPE811_SYS_CTRL2_TS_OFF (1 << 3) | |
| 105 | ||
| 106 | /* | |
| 107 | * STMPE1601 | |
| 108 | */ | |
| 109 | ||
| 110 | #define STMPE1601_IRQ_GPIOC 8 | |
| 111 | #define STMPE1601_IRQ_PWM3 7 | |
| 112 | #define STMPE1601_IRQ_PWM2 6 | |
| 113 | #define STMPE1601_IRQ_PWM1 5 | |
| 114 | #define STMPE1601_IRQ_PWM0 4 | |
| 115 | #define STMPE1601_IRQ_KEYPAD_OVER 2 | |
| 116 | #define STMPE1601_IRQ_KEYPAD 1 | |
| 117 | #define STMPE1601_IRQ_WAKEUP 0 | |
| 118 | #define STMPE1601_NR_INTERNAL_IRQS 9 | |
| 119 | ||
| 120 | #define STMPE1601_REG_SYS_CTRL 0x02 | |
| 121 | #define STMPE1601_REG_ICR_LSB 0x11 | |
| 122 | #define STMPE1601_REG_IER_LSB 0x13 | |
| 123 | #define STMPE1601_REG_ISR_MSB 0x14 | |
| 124 | #define STMPE1601_REG_CHIP_ID 0x80 | |
| 125 | #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17 | |
| 126 | #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18 | |
| 127 | #define STMPE1601_REG_GPIO_MP_LSB 0x87 | |
| 128 | #define STMPE1601_REG_GPIO_SET_LSB 0x83 | |
| 129 | #define STMPE1601_REG_GPIO_CLR_LSB 0x85 | |
| 130 | #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89 | |
| 131 | #define STMPE1601_REG_GPIO_ED_MSB 0x8A | |
| 132 | #define STMPE1601_REG_GPIO_RE_LSB 0x8D | |
| 133 | #define STMPE1601_REG_GPIO_FE_LSB 0x8F | |
| 134 | #define STMPE1601_REG_GPIO_AF_U_MSB 0x92 | |
| 135 | ||
| 136 | #define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3) | |
| 137 | #define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1) | |
| 138 | #define STMPE1601_SYSCON_ENABLE_SPWM (1 << 0) | |
| 139 | ||
| 140 | /* | |
| 141 | * STMPE24xx | |
| 142 | */ | |
| 143 | ||
| 144 | #define STMPE24XX_IRQ_GPIOC 8 | |
| 145 | #define STMPE24XX_IRQ_PWM2 7 | |
| 146 | #define STMPE24XX_IRQ_PWM1 6 | |
| 147 | #define STMPE24XX_IRQ_PWM0 5 | |
| 148 | #define STMPE24XX_IRQ_ROT_OVER 4 | |
| 149 | #define STMPE24XX_IRQ_ROT 3 | |
| 150 | #define STMPE24XX_IRQ_KEYPAD_OVER 2 | |
| 151 | #define STMPE24XX_IRQ_KEYPAD 1 | |
| 152 | #define STMPE24XX_IRQ_WAKEUP 0 | |
| 153 | #define STMPE24XX_NR_INTERNAL_IRQS 9 | |
| 154 | ||
| 155 | #define STMPE24XX_REG_SYS_CTRL 0x02 | |
| 156 | #define STMPE24XX_REG_ICR_LSB 0x11 | |
| 157 | #define STMPE24XX_REG_IER_LSB 0x13 | |
| 158 | #define STMPE24XX_REG_ISR_MSB 0x14 | |
| 159 | #define STMPE24XX_REG_CHIP_ID 0x80 | |
| 160 | #define STMPE24XX_REG_IEGPIOR_LSB 0x18 | |
| 161 | #define STMPE24XX_REG_ISGPIOR_MSB 0x19 | |
| 162 | #define STMPE24XX_REG_GPMR_LSB 0xA5 | |
| 163 | #define STMPE24XX_REG_GPSR_LSB 0x85 | |
| 164 | #define STMPE24XX_REG_GPCR_LSB 0x88 | |
| 165 | #define STMPE24XX_REG_GPDR_LSB 0x8B | |
| 166 | #define STMPE24XX_REG_GPEDR_MSB 0x8C | |
| 167 | #define STMPE24XX_REG_GPRER_LSB 0x91 | |
| 168 | #define STMPE24XX_REG_GPFER_LSB 0x94 | |
| 169 | #define STMPE24XX_REG_GPAFR_U_MSB 0x9B | |
| 170 | ||
| 171 | #define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3) | |
| 172 | #define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2) | |
| 173 | #define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1) | |
| 174 | #define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0) | |
| 175 | ||
| 176 | #endif |