[deliverable/linux.git] / drivers / mfd / ti_am335x_tscadc.c

/*
 * TI Touch Screen / ADC MFD driver
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/sched.h>

#include <linux/mfd/ti_am335x_tscadc.h>

static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
{
	unsigned int val;

	regmap_read(tsadc->regmap_tscadc, reg, &val);
	return val;
}

static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
					unsigned int val)
{
	regmap_write(tsadc->regmap_tscadc, reg, val);
}

static const struct regmap_config tscadc_regmap_config = {
	.name = "ti_tscadc",
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
};

void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tsadc->reg_lock, flags);
	tsadc->reg_se_cache |= val;
	if (tsadc->adc_waiting)
		wake_up(&tsadc->reg_se_wait);
	else if (!tsadc->adc_in_use)
		tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);

	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);

static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
{
	DEFINE_WAIT(wait);
	u32 reg;

	/*
	 * disable TSC steps so it does not run while the ADC is using it. If
	 * write 0 while it is running (it just started or was already running)
	 * then it completes all steps that were enabled and stops then.
	 */
	tscadc_writel(tsadc, REG_SE, 0);
	reg = tscadc_readl(tsadc, REG_ADCFSM);
	if (reg & SEQ_STATUS) {
		tsadc->adc_waiting = true;
		prepare_to_wait(&tsadc->reg_se_wait, &wait,
				TASK_UNINTERRUPTIBLE);
		spin_unlock_irq(&tsadc->reg_lock);

		schedule();

		spin_lock_irq(&tsadc->reg_lock);
		finish_wait(&tsadc->reg_se_wait, &wait);

		reg = tscadc_readl(tsadc, REG_ADCFSM);
		WARN_ON(reg & SEQ_STATUS);
		tsadc->adc_waiting = false;
	}
	tsadc->adc_in_use = true;
}

void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
{
	spin_lock_irq(&tsadc->reg_lock);
	tsadc->reg_se_cache |= val;
	am335x_tscadc_need_adc(tsadc);

	tscadc_writel(tsadc, REG_SE, val);
	spin_unlock_irq(&tsadc->reg_lock);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);

void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc)
{
	unsigned long flags;

	spin_lock_irqsave(&tsadc->reg_lock, flags);
	tsadc->adc_in_use = false;
	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);

void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tsadc->reg_lock, flags);
	tsadc->reg_se_cache &= ~val;
	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);

static void tscadc_idle_config(struct ti_tscadc_dev *config)
{
	unsigned int idleconfig;

	idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
			STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;

	tscadc_writel(config, REG_IDLECONFIG, idleconfig);
}

static	int ti_tscadc_probe(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc;
	struct resource		*res;
	struct clk		*clk;
	struct device_node	*node = pdev->dev.of_node;
	struct mfd_cell		*cell;
	struct property         *prop;
	const __be32            *cur;
	u32			val;
	int			err, ctrl;
	int			clock_rate;
	int			tsc_wires = 0, adc_channels = 0, total_channels;
	int			readouts = 0;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "Could not find valid DT data.\n");
		return -EINVAL;
	}

	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
	of_property_read_u32(node, "ti,wires", &tsc_wires);
	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);

	node = of_get_child_by_name(pdev->dev.of_node, "adc");
	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
		adc_channels++;
		if (val > 7) {
			dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
					val);
			return -EINVAL;
		}
	}
	total_channels = tsc_wires + adc_channels;
	if (total_channels > 8) {
		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
		return -EINVAL;
	}
	if (total_channels == 0) {
		dev_err(&pdev->dev, "Need atleast one channel.\n");
		return -EINVAL;
	}

	if (readouts * 2 + 2 + adc_channels > 16) {
		dev_err(&pdev->dev, "Too many step configurations requested\n");
		return -EINVAL;
	}

	/* Allocate memory for device */
	tscadc = devm_kzalloc(&pdev->dev,
			sizeof(struct ti_tscadc_dev), GFP_KERNEL);
	if (!tscadc) {
		dev_err(&pdev->dev, "failed to allocate memory.\n");
		return -ENOMEM;
	}
	tscadc->dev = &pdev->dev;

	err = platform_get_irq(pdev, 0);
	if (err < 0) {
		dev_err(&pdev->dev, "no irq ID is specified.\n");
		goto ret;
	} else
		tscadc->irq = err;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(tscadc->tscadc_base))
		return PTR_ERR(tscadc->tscadc_base);

	tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
			tscadc->tscadc_base, &tscadc_regmap_config);
	if (IS_ERR(tscadc->regmap_tscadc)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		err = PTR_ERR(tscadc->regmap_tscadc);
		goto ret;
	}

	spin_lock_init(&tscadc->reg_lock);
	init_waitqueue_head(&tscadc->reg_se_wait);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	/*
	 * The TSC_ADC_Subsystem has 2 clock domains
	 * OCP_CLK and ADC_CLK.
	 * The ADC clock is expected to run at target of 3MHz,
	 * and expected to capture 12-bit data at a rate of 200 KSPS.
	 * The TSC_ADC_SS controller design assumes the OCP clock is
	 * at least 6x faster than the ADC clock.
	 */
	clk = clk_get(&pdev->dev, "adc_tsc_fck");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get TSC fck\n");
		err = PTR_ERR(clk);
		goto err_disable_clk;
	}
	clock_rate = clk_get_rate(clk);
	clk_put(clk);
	tscadc->clk_div = clock_rate / ADC_CLK;

	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
	tscadc->clk_div--;
	tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);

	/* Set the control register bits */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	tscadc_writel(tscadc, REG_CTRL, ctrl);

	/* Set register bits for Idle Config Mode */
	if (tsc_wires > 0) {
		tscadc->tsc_wires = tsc_wires;
		if (tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc);
	}

	/* Enable the TSC module enable bit */
	ctrl |= CNTRLREG_TSCSSENB;
	tscadc_writel(tscadc, REG_CTRL, ctrl);

	tscadc->used_cells = 0;
	tscadc->tsc_cell = -1;
	tscadc->adc_cell = -1;

	/* TSC Cell */
	if (tsc_wires > 0) {
		tscadc->tsc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-tsc";
		cell->of_compatible = "ti,am3359-tsc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	/* ADC Cell */
	if (adc_channels > 0) {
		tscadc->adc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-adc";
		cell->of_compatible = "ti,am3359-adc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
			tscadc->used_cells, NULL, 0, NULL);
	if (err < 0)
		goto err_disable_clk;

	device_init_wakeup(&pdev->dev, true);
	platform_set_drvdata(pdev, tscadc);
	return 0;

err_disable_clk:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
ret:
	return err;
}

static int ti_tscadc_remove(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc = platform_get_drvdata(pdev);

	tscadc_writel(tscadc, REG_SE, 0x00);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	mfd_remove_devices(tscadc->dev);

	return 0;
}

#ifdef CONFIG_PM
static int tscadc_suspend(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc_dev = dev_get_drvdata(dev);

	tscadc_writel(tscadc_dev, REG_SE, 0x00);
	pm_runtime_put_sync(dev);

	return 0;
}

static int tscadc_resume(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc_dev = dev_get_drvdata(dev);
	u32 ctrl;

	pm_runtime_get_sync(dev);

	/* context restore */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	tscadc_writel(tscadc_dev, REG_CTRL, ctrl);

	if (tscadc_dev->tsc_cell != -1) {
		if (tscadc_dev->tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc_dev);
	}
	ctrl |= CNTRLREG_TSCSSENB;
	tscadc_writel(tscadc_dev, REG_CTRL, ctrl);

	tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);

	return 0;
}

static const struct dev_pm_ops tscadc_pm_ops = {
	.suspend = tscadc_suspend,
	.resume = tscadc_resume,
};
#define TSCADC_PM_OPS (&tscadc_pm_ops)
#else
#define TSCADC_PM_OPS NULL
#endif

static const struct of_device_id ti_tscadc_dt_ids[] = {
	{ .compatible = "ti,am3359-tscadc", },
	{ }
};
MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);

static struct platform_driver ti_tscadc_driver = {
	.driver = {
		.name   = "ti_am3359-tscadc",
		.owner	= THIS_MODULE,
		.pm	= TSCADC_PM_OPS,
		.of_match_table = ti_tscadc_dt_ids,
	},
	.probe	= ti_tscadc_probe,
	.remove	= ti_tscadc_remove,

};

module_platform_driver(ti_tscadc_driver);

MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
01636eb9 PR	1	/*
	2	* TI Touch Screen / ADC MFD driver
	3	*
	4	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/module.h>
01636eb9 PR	17	#include <linux/slab.h>
	18	#include <linux/err.h>
	19	#include <linux/io.h>
	20	#include <linux/clk.h>
	21	#include <linux/regmap.h>
	22	#include <linux/mfd/core.h>
	23	#include <linux/pm_runtime.h>
a6543a1c PR	24	#include <linux/of.h>
a6543a1c PR	25	#include <linux/of_device.h>
7ca6740c	26	#include <linux/sched.h>
01636eb9 PR	27
	28	#include <linux/mfd/ti_am335x_tscadc.h>
	29
	30	static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
	31	{
	32	unsigned int val;
	33
	34	regmap_read(tsadc->regmap_tscadc, reg, &val);
	35	return val;
	36	}
	37
	38	static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
	39	unsigned int val)
	40	{
	41	regmap_write(tsadc->regmap_tscadc, reg, val);
	42	}
	43
	44	static const struct regmap_config tscadc_regmap_config = {
	45	.name = "ti_tscadc",
	46	.reg_bits = 32,
	47	.reg_stride = 4,
	48	.val_bits = 32,
	49	};
	50
7e170c6e	51	void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
abeccee4	52	{
317b2099 SAS	53	unsigned long flags;
	54
	55	spin_lock_irqsave(&tsadc->reg_lock, flags);
6ac734d2	56	tsadc->reg_se_cache \|= val;
7ca6740c SAS	57	if (tsadc->adc_waiting)
	58	wake_up(&tsadc->reg_se_wait);
	59	else if (!tsadc->adc_in_use)
6a71f38d	60	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
7ca6740c	61
317b2099	62	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
abeccee4	63	}
7e170c6e SAS	64	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
7e170c6e SAS	65
7ca6740c SAS	66	static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
	67	{
	68	DEFINE_WAIT(wait);
	69	u32 reg;
	70
	71	/*
	72	* disable TSC steps so it does not run while the ADC is using it. If
	73	* write 0 while it is running (it just started or was already running)
	74	* then it completes all steps that were enabled and stops then.
	75	*/
	76	tscadc_writel(tsadc, REG_SE, 0);
	77	reg = tscadc_readl(tsadc, REG_ADCFSM);
	78	if (reg & SEQ_STATUS) {
	79	tsadc->adc_waiting = true;
	80	prepare_to_wait(&tsadc->reg_se_wait, &wait,
	81	TASK_UNINTERRUPTIBLE);
	82	spin_unlock_irq(&tsadc->reg_lock);
	83
	84	schedule();
	85
	86	spin_lock_irq(&tsadc->reg_lock);
	87	finish_wait(&tsadc->reg_se_wait, &wait);
	88
	89	reg = tscadc_readl(tsadc, REG_ADCFSM);
	90	WARN_ON(reg & SEQ_STATUS);
	91	tsadc->adc_waiting = false;
	92	}
	93	tsadc->adc_in_use = true;
	94	}
	95
7e170c6e	96	void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
7ca6740c SAS	97	{
7ca6740c SAS	98	spin_lock_irq(&tsadc->reg_lock);
6ac734d2	99	tsadc->reg_se_cache \|= val;
7ca6740c SAS	100	am335x_tscadc_need_adc(tsadc);
	101
	102	tscadc_writel(tsadc, REG_SE, val);
	103	spin_unlock_irq(&tsadc->reg_lock);
	104	}
	105	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
	106
	107	void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc)
7e170c6e SAS	108	{
	109	unsigned long flags;
	110
	111	spin_lock_irqsave(&tsadc->reg_lock, flags);
7ca6740c SAS	112	tsadc->adc_in_use = false;
7ca6740c SAS	113	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
7e170c6e SAS	114	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
7e170c6e SAS	115	}
7ca6740c	116	EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
abeccee4 PR	117
	118	void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
	119	{
317b2099 SAS	120	unsigned long flags;
	121
	122	spin_lock_irqsave(&tsadc->reg_lock, flags);
abeccee4	123	tsadc->reg_se_cache &= ~val;
7ca6740c	124	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
317b2099	125	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
abeccee4 PR	126	}
	127	EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
	128
01636eb9 PR	129	static void tscadc_idle_config(struct ti_tscadc_dev *config)
	130	{
	131	unsigned int idleconfig;
	132
	133	idleconfig = STEPCONFIG_YNN \| STEPCONFIG_INM_ADCREFM \|
	134	STEPCONFIG_INP_ADCREFM \| STEPCONFIG_YPN;
	135
	136	tscadc_writel(config, REG_IDLECONFIG, idleconfig);
	137	}
	138
612b95cd	139	static int ti_tscadc_probe(struct platform_device *pdev)
01636eb9 PR	140	{
	141	struct ti_tscadc_dev *tscadc;
	142	struct resource *res;
	143	struct clk *clk;
a6543a1c	144	struct device_node *node = pdev->dev.of_node;
2b99bafa	145	struct mfd_cell *cell;
18926ede SAS	146	struct property *prop;
	147	const __be32 *cur;
	148	u32 val;
01636eb9	149	int err, ctrl;
e90f8754	150	int clock_rate;
a6543a1c	151	int tsc_wires = 0, adc_channels = 0, total_channels;
18926ede	152	int readouts = 0;
01636eb9	153
9e5775f3 SAS	154	if (!pdev->dev.of_node) {
9e5775f3 SAS	155	dev_err(&pdev->dev, "Could not find valid DT data.\n");
01636eb9 PR	156	return -EINVAL;
	157	}
	158
9e5775f3 SAS	159	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
9e5775f3 SAS	160	of_property_read_u32(node, "ti,wires", &tsc_wires);
18926ede	161	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
a6543a1c	162
9e5775f3	163	node = of_get_child_by_name(pdev->dev.of_node, "adc");
18926ede SAS	164	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
	165	adc_channels++;
	166	if (val > 7) {
	167	dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
	168	val);
	169	return -EINVAL;
	170	}
	171	}
5e53a69b	172	total_channels = tsc_wires + adc_channels;
5e53a69b PR	173	if (total_channels > 8) {
	174	dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
	175	return -EINVAL;
	176	}
24d5c82f PA	177	if (total_channels == 0) {
	178	dev_err(&pdev->dev, "Need atleast one channel.\n");
	179	return -EINVAL;
	180	}
2b99bafa	181
18926ede SAS	182	if (readouts * 2 + 2 + adc_channels > 16) {
	183	dev_err(&pdev->dev, "Too many step configurations requested\n");
	184	return -EINVAL;
	185	}
	186
01636eb9 PR	187	/* Allocate memory for device */
	188	tscadc = devm_kzalloc(&pdev->dev,
	189	sizeof(struct ti_tscadc_dev), GFP_KERNEL);
	190	if (!tscadc) {
	191	dev_err(&pdev->dev, "failed to allocate memory.\n");
	192	return -ENOMEM;
	193	}
	194	tscadc->dev = &pdev->dev;
3c39c9c6 PR	195
	196	err = platform_get_irq(pdev, 0);
	197	if (err < 0) {
	198	dev_err(&pdev->dev, "no irq ID is specified.\n");
	199	goto ret;
	200	} else
	201	tscadc->irq = err;
01636eb9	202
924ff918 JH	203	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	204	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	205	if (IS_ERR(tscadc->tscadc_base))
	206	return PTR_ERR(tscadc->tscadc_base);
01636eb9 PR	207
	208	tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
	209	tscadc->tscadc_base, &tscadc_regmap_config);
	210	if (IS_ERR(tscadc->regmap_tscadc)) {
	211	dev_err(&pdev->dev, "regmap init failed\n");
	212	err = PTR_ERR(tscadc->regmap_tscadc);
3c39c9c6	213	goto ret;
01636eb9 PR	214	}
01636eb9 PR	215
abeccee4	216	spin_lock_init(&tscadc->reg_lock);
7ca6740c SAS	217	init_waitqueue_head(&tscadc->reg_se_wait);
7ca6740c SAS	218
01636eb9 PR	219	pm_runtime_enable(&pdev->dev);
	220	pm_runtime_get_sync(&pdev->dev);
	221
	222	/*
	223	* The TSC_ADC_Subsystem has 2 clock domains
	224	* OCP_CLK and ADC_CLK.
	225	* The ADC clock is expected to run at target of 3MHz,
	226	* and expected to capture 12-bit data at a rate of 200 KSPS.
	227	* The TSC_ADC_SS controller design assumes the OCP clock is
	228	* at least 6x faster than the ADC clock.
	229	*/
	230	clk = clk_get(&pdev->dev, "adc_tsc_fck");
	231	if (IS_ERR(clk)) {
	232	dev_err(&pdev->dev, "failed to get TSC fck\n");
	233	err = PTR_ERR(clk);
	234	goto err_disable_clk;
	235	}
	236	clock_rate = clk_get_rate(clk);
	237	clk_put(clk);
e90f8754	238	tscadc->clk_div = clock_rate / ADC_CLK;
efe3126a	239
01636eb9	240	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
e90f8754 MK	241	tscadc->clk_div--;
e90f8754 MK	242	tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);
01636eb9 PR	243
01636eb9 PR	244	/* Set the control register bits */
f0933a60	245	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
01636eb9 PR	246	tscadc_writel(tscadc, REG_CTRL, ctrl);
	247
	248	/* Set register bits for Idle Config Mode */
f0933a60 JL	249	if (tsc_wires > 0) {
	250	tscadc->tsc_wires = tsc_wires;
	251	if (tsc_wires == 5)
	252	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	253	else
	254	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
b5f8b763	255	tscadc_idle_config(tscadc);
f0933a60	256	}
01636eb9 PR	257
01636eb9 PR	258	/* Enable the TSC module enable bit */
01636eb9 PR	259	ctrl \|= CNTRLREG_TSCSSENB;
	260	tscadc_writel(tscadc, REG_CTRL, ctrl);
	261
24d5c82f PA	262	tscadc->used_cells = 0;
	263	tscadc->tsc_cell = -1;
	264	tscadc->adc_cell = -1;
	265
2b99bafa	266	/* TSC Cell */
24d5c82f PA	267	if (tsc_wires > 0) {
	268	tscadc->tsc_cell = tscadc->used_cells;
	269	cell = &tscadc->cells[tscadc->used_cells++];
5f184e63	270	cell->name = "TI-am335x-tsc";
24d5c82f PA	271	cell->of_compatible = "ti,am3359-tsc";
	272	cell->platform_data = &tscadc;
	273	cell->pdata_size = sizeof(tscadc);
	274	}
2b99bafa	275
5e53a69b	276	/* ADC Cell */
24d5c82f PA	277	if (adc_channels > 0) {
	278	tscadc->adc_cell = tscadc->used_cells;
	279	cell = &tscadc->cells[tscadc->used_cells++];
9f99928f	280	cell->name = "TI-am335x-adc";
24d5c82f PA	281	cell->of_compatible = "ti,am3359-adc";
	282	cell->platform_data = &tscadc;
	283	cell->pdata_size = sizeof(tscadc);
	284	}
5e53a69b	285
01636eb9	286	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
24d5c82f	287	tscadc->used_cells, NULL, 0, NULL);
01636eb9 PR	288	if (err < 0)
	289	goto err_disable_clk;
	290
	291	device_init_wakeup(&pdev->dev, true);
	292	platform_set_drvdata(pdev, tscadc);
01636eb9 PR	293	return 0;
	294
	295	err_disable_clk:
	296	pm_runtime_put_sync(&pdev->dev);
	297	pm_runtime_disable(&pdev->dev);
3c39c9c6	298	ret:
01636eb9 PR	299	return err;
	300	}
	301
612b95cd	302	static int ti_tscadc_remove(struct platform_device *pdev)
01636eb9 PR	303	{
	304	struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
	305
	306	tscadc_writel(tscadc, REG_SE, 0x00);
	307
	308	pm_runtime_put_sync(&pdev->dev);
	309	pm_runtime_disable(&pdev->dev);
	310
	311	mfd_remove_devices(tscadc->dev);
	312
	313	return 0;
	314	}
	315
	316	#ifdef CONFIG_PM
	317	static int tscadc_suspend(struct device *dev)
	318	{
	319	struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
	320
	321	tscadc_writel(tscadc_dev, REG_SE, 0x00);
	322	pm_runtime_put_sync(dev);
	323
	324	return 0;
	325	}
	326
	327	static int tscadc_resume(struct device *dev)
	328	{
	329	struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
f0933a60	330	u32 ctrl;
01636eb9 PR	331
	332	pm_runtime_get_sync(dev);
	333
	334	/* context restore */
b5f8b763	335	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
01636eb9	336	tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
b5f8b763	337
f0933a60 JL	338	if (tscadc_dev->tsc_cell != -1) {
	339	if (tscadc_dev->tsc_wires == 5)
	340	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	341	else
	342	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
b5f8b763	343	tscadc_idle_config(tscadc_dev);
f0933a60 JL	344	}
	345	ctrl \|= CNTRLREG_TSCSSENB;
	346	tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
01636eb9	347
e90f8754 MK	348	tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);
e90f8754 MK	349
01636eb9 PR	350	return 0;
	351	}
	352
	353	static const struct dev_pm_ops tscadc_pm_ops = {
	354	.suspend = tscadc_suspend,
	355	.resume = tscadc_resume,
	356	};
	357	#define TSCADC_PM_OPS (&tscadc_pm_ops)
	358	#else
	359	#define TSCADC_PM_OPS NULL
	360	#endif
	361
a6543a1c PR	362	static const struct of_device_id ti_tscadc_dt_ids[] = {
	363	{ .compatible = "ti,am3359-tscadc", },
	364	{ }
	365	};
	366	MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
	367
01636eb9 PR	368	static struct platform_driver ti_tscadc_driver = {
01636eb9 PR	369	.driver = {
a6543a1c	370	.name = "ti_am3359-tscadc",
01636eb9 PR	371	.owner = THIS_MODULE,
01636eb9 PR	372	.pm = TSCADC_PM_OPS,
131221bc	373	.of_match_table = ti_tscadc_dt_ids,
01636eb9 PR	374	},
01636eb9 PR	375	.probe = ti_tscadc_probe,
612b95cd	376	.remove = ti_tscadc_remove,
01636eb9 PR	377
	378	};
	379
	380	module_platform_driver(ti_tscadc_driver);
	381
	382	MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
	383	MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
	384	MODULE_LICENSE("GPL");