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1 | /* |
2 | * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/mfd/core.h> | |
19 | #include <linux/interrupt.h> | |
20 | ||
21 | #include <linux/mfd/wm831x/core.h> | |
22 | #include <linux/mfd/wm831x/pdata.h> | |
23 | #include <linux/mfd/wm831x/irq.h> | |
24 | ||
25 | #include <linux/delay.h> | |
26 | ||
27 | /* | |
28 | * Since generic IRQs don't currently support interrupt controllers on | |
29 | * interrupt driven buses we don't use genirq but instead provide an | |
30 | * interface that looks very much like the standard ones. This leads | |
31 | * to some bodges, including storing interrupt handler information in | |
32 | * the static irq_data table we use to look up the data for individual | |
33 | * interrupts, but hopefully won't last too long. | |
34 | */ | |
35 | ||
36 | struct wm831x_irq_data { | |
37 | int primary; | |
38 | int reg; | |
39 | int mask; | |
40 | irq_handler_t handler; | |
41 | void *handler_data; | |
42 | }; | |
43 | ||
44 | static struct wm831x_irq_data wm831x_irqs[] = { | |
45 | [WM831X_IRQ_TEMP_THW] = { | |
46 | .primary = WM831X_TEMP_INT, | |
47 | .reg = 1, | |
48 | .mask = WM831X_TEMP_THW_EINT, | |
49 | }, | |
50 | [WM831X_IRQ_GPIO_1] = { | |
51 | .primary = WM831X_GP_INT, | |
52 | .reg = 5, | |
53 | .mask = WM831X_GP1_EINT, | |
54 | }, | |
55 | [WM831X_IRQ_GPIO_2] = { | |
56 | .primary = WM831X_GP_INT, | |
57 | .reg = 5, | |
58 | .mask = WM831X_GP2_EINT, | |
59 | }, | |
60 | [WM831X_IRQ_GPIO_3] = { | |
61 | .primary = WM831X_GP_INT, | |
62 | .reg = 5, | |
63 | .mask = WM831X_GP3_EINT, | |
64 | }, | |
65 | [WM831X_IRQ_GPIO_4] = { | |
66 | .primary = WM831X_GP_INT, | |
67 | .reg = 5, | |
68 | .mask = WM831X_GP4_EINT, | |
69 | }, | |
70 | [WM831X_IRQ_GPIO_5] = { | |
71 | .primary = WM831X_GP_INT, | |
72 | .reg = 5, | |
73 | .mask = WM831X_GP5_EINT, | |
74 | }, | |
75 | [WM831X_IRQ_GPIO_6] = { | |
76 | .primary = WM831X_GP_INT, | |
77 | .reg = 5, | |
78 | .mask = WM831X_GP6_EINT, | |
79 | }, | |
80 | [WM831X_IRQ_GPIO_7] = { | |
81 | .primary = WM831X_GP_INT, | |
82 | .reg = 5, | |
83 | .mask = WM831X_GP7_EINT, | |
84 | }, | |
85 | [WM831X_IRQ_GPIO_8] = { | |
86 | .primary = WM831X_GP_INT, | |
87 | .reg = 5, | |
88 | .mask = WM831X_GP8_EINT, | |
89 | }, | |
90 | [WM831X_IRQ_GPIO_9] = { | |
91 | .primary = WM831X_GP_INT, | |
92 | .reg = 5, | |
93 | .mask = WM831X_GP9_EINT, | |
94 | }, | |
95 | [WM831X_IRQ_GPIO_10] = { | |
96 | .primary = WM831X_GP_INT, | |
97 | .reg = 5, | |
98 | .mask = WM831X_GP10_EINT, | |
99 | }, | |
100 | [WM831X_IRQ_GPIO_11] = { | |
101 | .primary = WM831X_GP_INT, | |
102 | .reg = 5, | |
103 | .mask = WM831X_GP11_EINT, | |
104 | }, | |
105 | [WM831X_IRQ_GPIO_12] = { | |
106 | .primary = WM831X_GP_INT, | |
107 | .reg = 5, | |
108 | .mask = WM831X_GP12_EINT, | |
109 | }, | |
110 | [WM831X_IRQ_GPIO_13] = { | |
111 | .primary = WM831X_GP_INT, | |
112 | .reg = 5, | |
113 | .mask = WM831X_GP13_EINT, | |
114 | }, | |
115 | [WM831X_IRQ_GPIO_14] = { | |
116 | .primary = WM831X_GP_INT, | |
117 | .reg = 5, | |
118 | .mask = WM831X_GP14_EINT, | |
119 | }, | |
120 | [WM831X_IRQ_GPIO_15] = { | |
121 | .primary = WM831X_GP_INT, | |
122 | .reg = 5, | |
123 | .mask = WM831X_GP15_EINT, | |
124 | }, | |
125 | [WM831X_IRQ_GPIO_16] = { | |
126 | .primary = WM831X_GP_INT, | |
127 | .reg = 5, | |
128 | .mask = WM831X_GP16_EINT, | |
129 | }, | |
130 | [WM831X_IRQ_ON] = { | |
131 | .primary = WM831X_ON_PIN_INT, | |
132 | .reg = 1, | |
133 | .mask = WM831X_ON_PIN_EINT, | |
134 | }, | |
135 | [WM831X_IRQ_PPM_SYSLO] = { | |
136 | .primary = WM831X_PPM_INT, | |
137 | .reg = 1, | |
138 | .mask = WM831X_PPM_SYSLO_EINT, | |
139 | }, | |
140 | [WM831X_IRQ_PPM_PWR_SRC] = { | |
141 | .primary = WM831X_PPM_INT, | |
142 | .reg = 1, | |
143 | .mask = WM831X_PPM_PWR_SRC_EINT, | |
144 | }, | |
145 | [WM831X_IRQ_PPM_USB_CURR] = { | |
146 | .primary = WM831X_PPM_INT, | |
147 | .reg = 1, | |
148 | .mask = WM831X_PPM_USB_CURR_EINT, | |
149 | }, | |
150 | [WM831X_IRQ_WDOG_TO] = { | |
151 | .primary = WM831X_WDOG_INT, | |
152 | .reg = 1, | |
153 | .mask = WM831X_WDOG_TO_EINT, | |
154 | }, | |
155 | [WM831X_IRQ_RTC_PER] = { | |
156 | .primary = WM831X_RTC_INT, | |
157 | .reg = 1, | |
158 | .mask = WM831X_RTC_PER_EINT, | |
159 | }, | |
160 | [WM831X_IRQ_RTC_ALM] = { | |
161 | .primary = WM831X_RTC_INT, | |
162 | .reg = 1, | |
163 | .mask = WM831X_RTC_ALM_EINT, | |
164 | }, | |
165 | [WM831X_IRQ_CHG_BATT_HOT] = { | |
166 | .primary = WM831X_CHG_INT, | |
167 | .reg = 2, | |
168 | .mask = WM831X_CHG_BATT_HOT_EINT, | |
169 | }, | |
170 | [WM831X_IRQ_CHG_BATT_COLD] = { | |
171 | .primary = WM831X_CHG_INT, | |
172 | .reg = 2, | |
173 | .mask = WM831X_CHG_BATT_COLD_EINT, | |
174 | }, | |
175 | [WM831X_IRQ_CHG_BATT_FAIL] = { | |
176 | .primary = WM831X_CHG_INT, | |
177 | .reg = 2, | |
178 | .mask = WM831X_CHG_BATT_FAIL_EINT, | |
179 | }, | |
180 | [WM831X_IRQ_CHG_OV] = { | |
181 | .primary = WM831X_CHG_INT, | |
182 | .reg = 2, | |
183 | .mask = WM831X_CHG_OV_EINT, | |
184 | }, | |
185 | [WM831X_IRQ_CHG_END] = { | |
186 | .primary = WM831X_CHG_INT, | |
187 | .reg = 2, | |
188 | .mask = WM831X_CHG_END_EINT, | |
189 | }, | |
190 | [WM831X_IRQ_CHG_TO] = { | |
191 | .primary = WM831X_CHG_INT, | |
192 | .reg = 2, | |
193 | .mask = WM831X_CHG_TO_EINT, | |
194 | }, | |
195 | [WM831X_IRQ_CHG_MODE] = { | |
196 | .primary = WM831X_CHG_INT, | |
197 | .reg = 2, | |
198 | .mask = WM831X_CHG_MODE_EINT, | |
199 | }, | |
200 | [WM831X_IRQ_CHG_START] = { | |
201 | .primary = WM831X_CHG_INT, | |
202 | .reg = 2, | |
203 | .mask = WM831X_CHG_START_EINT, | |
204 | }, | |
205 | [WM831X_IRQ_TCHDATA] = { | |
206 | .primary = WM831X_TCHDATA_INT, | |
207 | .reg = 1, | |
208 | .mask = WM831X_TCHDATA_EINT, | |
209 | }, | |
210 | [WM831X_IRQ_TCHPD] = { | |
211 | .primary = WM831X_TCHPD_INT, | |
212 | .reg = 1, | |
213 | .mask = WM831X_TCHPD_EINT, | |
214 | }, | |
215 | [WM831X_IRQ_AUXADC_DATA] = { | |
216 | .primary = WM831X_AUXADC_INT, | |
217 | .reg = 1, | |
218 | .mask = WM831X_AUXADC_DATA_EINT, | |
219 | }, | |
220 | [WM831X_IRQ_AUXADC_DCOMP1] = { | |
221 | .primary = WM831X_AUXADC_INT, | |
222 | .reg = 1, | |
223 | .mask = WM831X_AUXADC_DCOMP1_EINT, | |
224 | }, | |
225 | [WM831X_IRQ_AUXADC_DCOMP2] = { | |
226 | .primary = WM831X_AUXADC_INT, | |
227 | .reg = 1, | |
228 | .mask = WM831X_AUXADC_DCOMP2_EINT, | |
229 | }, | |
230 | [WM831X_IRQ_AUXADC_DCOMP3] = { | |
231 | .primary = WM831X_AUXADC_INT, | |
232 | .reg = 1, | |
233 | .mask = WM831X_AUXADC_DCOMP3_EINT, | |
234 | }, | |
235 | [WM831X_IRQ_AUXADC_DCOMP4] = { | |
236 | .primary = WM831X_AUXADC_INT, | |
237 | .reg = 1, | |
238 | .mask = WM831X_AUXADC_DCOMP4_EINT, | |
239 | }, | |
240 | [WM831X_IRQ_CS1] = { | |
241 | .primary = WM831X_CS_INT, | |
242 | .reg = 2, | |
243 | .mask = WM831X_CS1_EINT, | |
244 | }, | |
245 | [WM831X_IRQ_CS2] = { | |
246 | .primary = WM831X_CS_INT, | |
247 | .reg = 2, | |
248 | .mask = WM831X_CS2_EINT, | |
249 | }, | |
250 | [WM831X_IRQ_HC_DC1] = { | |
251 | .primary = WM831X_HC_INT, | |
252 | .reg = 4, | |
253 | .mask = WM831X_HC_DC1_EINT, | |
254 | }, | |
255 | [WM831X_IRQ_HC_DC2] = { | |
256 | .primary = WM831X_HC_INT, | |
257 | .reg = 4, | |
258 | .mask = WM831X_HC_DC2_EINT, | |
259 | }, | |
260 | [WM831X_IRQ_UV_LDO1] = { | |
261 | .primary = WM831X_UV_INT, | |
262 | .reg = 3, | |
263 | .mask = WM831X_UV_LDO1_EINT, | |
264 | }, | |
265 | [WM831X_IRQ_UV_LDO2] = { | |
266 | .primary = WM831X_UV_INT, | |
267 | .reg = 3, | |
268 | .mask = WM831X_UV_LDO2_EINT, | |
269 | }, | |
270 | [WM831X_IRQ_UV_LDO3] = { | |
271 | .primary = WM831X_UV_INT, | |
272 | .reg = 3, | |
273 | .mask = WM831X_UV_LDO3_EINT, | |
274 | }, | |
275 | [WM831X_IRQ_UV_LDO4] = { | |
276 | .primary = WM831X_UV_INT, | |
277 | .reg = 3, | |
278 | .mask = WM831X_UV_LDO4_EINT, | |
279 | }, | |
280 | [WM831X_IRQ_UV_LDO5] = { | |
281 | .primary = WM831X_UV_INT, | |
282 | .reg = 3, | |
283 | .mask = WM831X_UV_LDO5_EINT, | |
284 | }, | |
285 | [WM831X_IRQ_UV_LDO6] = { | |
286 | .primary = WM831X_UV_INT, | |
287 | .reg = 3, | |
288 | .mask = WM831X_UV_LDO6_EINT, | |
289 | }, | |
290 | [WM831X_IRQ_UV_LDO7] = { | |
291 | .primary = WM831X_UV_INT, | |
292 | .reg = 3, | |
293 | .mask = WM831X_UV_LDO7_EINT, | |
294 | }, | |
295 | [WM831X_IRQ_UV_LDO8] = { | |
296 | .primary = WM831X_UV_INT, | |
297 | .reg = 3, | |
298 | .mask = WM831X_UV_LDO8_EINT, | |
299 | }, | |
300 | [WM831X_IRQ_UV_LDO9] = { | |
301 | .primary = WM831X_UV_INT, | |
302 | .reg = 3, | |
303 | .mask = WM831X_UV_LDO9_EINT, | |
304 | }, | |
305 | [WM831X_IRQ_UV_LDO10] = { | |
306 | .primary = WM831X_UV_INT, | |
307 | .reg = 3, | |
308 | .mask = WM831X_UV_LDO10_EINT, | |
309 | }, | |
310 | [WM831X_IRQ_UV_DC1] = { | |
311 | .primary = WM831X_UV_INT, | |
312 | .reg = 4, | |
313 | .mask = WM831X_UV_DC1_EINT, | |
314 | }, | |
315 | [WM831X_IRQ_UV_DC2] = { | |
316 | .primary = WM831X_UV_INT, | |
317 | .reg = 4, | |
318 | .mask = WM831X_UV_DC2_EINT, | |
319 | }, | |
320 | [WM831X_IRQ_UV_DC3] = { | |
321 | .primary = WM831X_UV_INT, | |
322 | .reg = 4, | |
323 | .mask = WM831X_UV_DC3_EINT, | |
324 | }, | |
325 | [WM831X_IRQ_UV_DC4] = { | |
326 | .primary = WM831X_UV_INT, | |
327 | .reg = 4, | |
328 | .mask = WM831X_UV_DC4_EINT, | |
329 | }, | |
330 | }; | |
331 | ||
332 | static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data) | |
333 | { | |
334 | return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg; | |
335 | } | |
336 | ||
337 | static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data) | |
338 | { | |
339 | return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg; | |
340 | } | |
341 | ||
342 | static void __wm831x_enable_irq(struct wm831x *wm831x, int irq) | |
343 | { | |
344 | struct wm831x_irq_data *irq_data = &wm831x_irqs[irq]; | |
345 | ||
346 | wm831x->irq_masks[irq_data->reg - 1] &= ~irq_data->mask; | |
347 | wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data), | |
348 | wm831x->irq_masks[irq_data->reg - 1]); | |
349 | } | |
350 | ||
351 | void wm831x_enable_irq(struct wm831x *wm831x, int irq) | |
352 | { | |
353 | mutex_lock(&wm831x->irq_lock); | |
354 | __wm831x_enable_irq(wm831x, irq); | |
355 | mutex_unlock(&wm831x->irq_lock); | |
356 | } | |
357 | EXPORT_SYMBOL_GPL(wm831x_enable_irq); | |
358 | ||
359 | static void __wm831x_disable_irq(struct wm831x *wm831x, int irq) | |
360 | { | |
361 | struct wm831x_irq_data *irq_data = &wm831x_irqs[irq]; | |
362 | ||
363 | wm831x->irq_masks[irq_data->reg - 1] |= irq_data->mask; | |
364 | wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data), | |
365 | wm831x->irq_masks[irq_data->reg - 1]); | |
366 | } | |
367 | ||
368 | void wm831x_disable_irq(struct wm831x *wm831x, int irq) | |
369 | { | |
370 | mutex_lock(&wm831x->irq_lock); | |
371 | __wm831x_disable_irq(wm831x, irq); | |
372 | mutex_unlock(&wm831x->irq_lock); | |
373 | } | |
374 | EXPORT_SYMBOL_GPL(wm831x_disable_irq); | |
375 | ||
376 | int wm831x_request_irq(struct wm831x *wm831x, | |
377 | unsigned int irq, irq_handler_t handler, | |
378 | unsigned long flags, const char *name, | |
379 | void *dev) | |
380 | { | |
381 | int ret = 0; | |
382 | ||
383 | if (irq < 0 || irq >= WM831X_NUM_IRQS) | |
384 | return -EINVAL; | |
385 | ||
386 | mutex_lock(&wm831x->irq_lock); | |
387 | ||
388 | if (wm831x_irqs[irq].handler) { | |
389 | dev_err(wm831x->dev, "Already have handler for IRQ %d\n", irq); | |
390 | ret = -EINVAL; | |
391 | goto out; | |
392 | } | |
393 | ||
394 | wm831x_irqs[irq].handler = handler; | |
395 | wm831x_irqs[irq].handler_data = dev; | |
396 | ||
397 | __wm831x_enable_irq(wm831x, irq); | |
398 | ||
399 | out: | |
400 | mutex_unlock(&wm831x->irq_lock); | |
401 | ||
402 | return ret; | |
403 | } | |
404 | EXPORT_SYMBOL_GPL(wm831x_request_irq); | |
405 | ||
406 | void wm831x_free_irq(struct wm831x *wm831x, unsigned int irq, void *data) | |
407 | { | |
408 | if (irq < 0 || irq >= WM831X_NUM_IRQS) | |
409 | return; | |
410 | ||
411 | mutex_lock(&wm831x->irq_lock); | |
412 | ||
413 | wm831x_irqs[irq].handler = NULL; | |
414 | wm831x_irqs[irq].handler_data = NULL; | |
415 | ||
416 | __wm831x_disable_irq(wm831x, irq); | |
417 | ||
418 | mutex_unlock(&wm831x->irq_lock); | |
419 | } | |
420 | EXPORT_SYMBOL_GPL(wm831x_free_irq); | |
421 | ||
422 | ||
423 | static void wm831x_handle_irq(struct wm831x *wm831x, int irq, int status) | |
424 | { | |
425 | struct wm831x_irq_data *irq_data = &wm831x_irqs[irq]; | |
426 | ||
427 | if (irq_data->handler) { | |
428 | irq_data->handler(irq, irq_data->handler_data); | |
429 | wm831x_reg_write(wm831x, irq_data_to_status_reg(irq_data), | |
430 | irq_data->mask); | |
431 | } else { | |
432 | dev_err(wm831x->dev, "Unhandled IRQ %d, masking\n", irq); | |
433 | __wm831x_disable_irq(wm831x, irq); | |
434 | } | |
435 | } | |
436 | ||
437 | /* Main interrupt handling occurs in a workqueue since we need | |
438 | * interrupts enabled to interact with the chip. */ | |
439 | static void wm831x_irq_worker(struct work_struct *work) | |
440 | { | |
441 | struct wm831x *wm831x = container_of(work, struct wm831x, irq_work); | |
442 | unsigned int i; | |
443 | int primary; | |
444 | int status_regs[5]; | |
445 | int read[5] = { 0 }; | |
446 | int *status; | |
447 | ||
448 | primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS); | |
449 | if (primary < 0) { | |
450 | dev_err(wm831x->dev, "Failed to read system interrupt: %d\n", | |
451 | primary); | |
452 | goto out; | |
453 | } | |
454 | ||
455 | mutex_lock(&wm831x->irq_lock); | |
456 | ||
457 | for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) { | |
458 | int offset = wm831x_irqs[i].reg - 1; | |
459 | ||
460 | if (!(primary & wm831x_irqs[i].primary)) | |
461 | continue; | |
462 | ||
463 | status = &status_regs[offset]; | |
464 | ||
465 | /* Hopefully there should only be one register to read | |
466 | * each time otherwise we ought to do a block read. */ | |
467 | if (!read[offset]) { | |
468 | *status = wm831x_reg_read(wm831x, | |
469 | irq_data_to_status_reg(&wm831x_irqs[i])); | |
470 | if (*status < 0) { | |
471 | dev_err(wm831x->dev, | |
472 | "Failed to read IRQ status: %d\n", | |
473 | *status); | |
474 | goto out_lock; | |
475 | } | |
476 | ||
477 | /* Mask out the disabled IRQs */ | |
478 | *status &= ~wm831x->irq_masks[offset]; | |
479 | read[offset] = 1; | |
480 | } | |
481 | ||
482 | if (*status & wm831x_irqs[i].mask) | |
483 | wm831x_handle_irq(wm831x, i, *status); | |
484 | } | |
485 | ||
486 | out_lock: | |
487 | mutex_unlock(&wm831x->irq_lock); | |
488 | out: | |
489 | enable_irq(wm831x->irq); | |
490 | } | |
491 | ||
492 | ||
493 | static irqreturn_t wm831x_cpu_irq(int irq, void *data) | |
494 | { | |
495 | struct wm831x *wm831x = data; | |
496 | ||
497 | /* Shut the interrupt to the CPU up and schedule the actual | |
498 | * handler; we can't check that the IRQ is asserted. */ | |
499 | disable_irq_nosync(irq); | |
500 | ||
501 | queue_work(wm831x->irq_wq, &wm831x->irq_work); | |
502 | ||
503 | return IRQ_HANDLED; | |
504 | } | |
505 | ||
506 | int wm831x_irq_init(struct wm831x *wm831x, int irq) | |
507 | { | |
508 | int i, ret; | |
509 | ||
510 | if (!irq) { | |
511 | dev_warn(wm831x->dev, | |
512 | "No interrupt specified - functionality limited\n"); | |
513 | return 0; | |
514 | } | |
515 | ||
516 | ||
517 | wm831x->irq_wq = create_singlethread_workqueue("wm831x-irq"); | |
518 | if (!wm831x->irq_wq) { | |
519 | dev_err(wm831x->dev, "Failed to allocate IRQ worker\n"); | |
520 | return -ESRCH; | |
521 | } | |
522 | ||
523 | wm831x->irq = irq; | |
524 | mutex_init(&wm831x->irq_lock); | |
525 | INIT_WORK(&wm831x->irq_work, wm831x_irq_worker); | |
526 | ||
527 | /* Mask the individual interrupt sources */ | |
528 | for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks); i++) { | |
529 | wm831x->irq_masks[i] = 0xffff; | |
530 | wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i, | |
531 | 0xffff); | |
532 | } | |
533 | ||
534 | /* Enable top level interrupts, we mask at secondary level */ | |
535 | wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0); | |
536 | ||
537 | /* We're good to go. We set IRQF_SHARED since there's a | |
538 | * chance the driver will interoperate with another driver but | |
539 | * the need to disable the IRQ while handing via I2C/SPI means | |
540 | * that this may break and performance will be impacted. If | |
541 | * this does happen it's a hardware design issue and the only | |
542 | * other alternative would be polling. | |
543 | */ | |
544 | ret = request_irq(irq, wm831x_cpu_irq, IRQF_TRIGGER_LOW | IRQF_SHARED, | |
545 | "wm831x", wm831x); | |
546 | if (ret != 0) { | |
547 | dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n", | |
548 | irq, ret); | |
549 | return ret; | |
550 | } | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | void wm831x_irq_exit(struct wm831x *wm831x) | |
556 | { | |
557 | if (wm831x->irq) | |
558 | free_irq(wm831x->irq, wm831x); | |
559 | } |