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82dca611 AS |
1 | /* |
2 | * Driver for the CS5535/CS5536 Multi-Function General Purpose Timers (MFGPT) | |
3 | * | |
4 | * Copyright (C) 2006, Advanced Micro Devices, Inc. | |
5 | * Copyright (C) 2007 Andres Salomon <dilinger@debian.org> | |
6 | * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of version 2 of the GNU General Public License | |
10 | * as published by the Free Software Foundation. | |
11 | * | |
12 | * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/cs5535.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
82dca611 AS |
22 | |
23 | #define DRV_NAME "cs5535-mfgpt" | |
24 | #define MFGPT_BAR 2 | |
25 | ||
26 | static int mfgpt_reset_timers; | |
27 | module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644); | |
28 | MODULE_PARM_DESC(mfgptfix, "Reset the MFGPT timers during init; " | |
29 | "required by some broken BIOSes (ie, TinyBIOS < 0.99)."); | |
30 | ||
31 | struct cs5535_mfgpt_timer { | |
32 | struct cs5535_mfgpt_chip *chip; | |
33 | int nr; | |
34 | }; | |
35 | ||
36 | static struct cs5535_mfgpt_chip { | |
37 | DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS); | |
38 | resource_size_t base; | |
39 | ||
40 | struct pci_dev *pdev; | |
41 | spinlock_t lock; | |
42 | int initialized; | |
43 | } cs5535_mfgpt_chip; | |
44 | ||
45 | int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp, | |
46 | int event, int enable) | |
47 | { | |
48 | uint32_t msr, mask, value, dummy; | |
49 | int shift = (cmp == MFGPT_CMP1) ? 0 : 8; | |
50 | ||
51 | if (!timer) { | |
52 | WARN_ON(1); | |
53 | return -EIO; | |
54 | } | |
55 | ||
56 | /* | |
57 | * The register maps for these are described in sections 6.17.1.x of | |
58 | * the AMD Geode CS5536 Companion Device Data Book. | |
59 | */ | |
60 | switch (event) { | |
61 | case MFGPT_EVENT_RESET: | |
62 | /* | |
63 | * XXX: According to the docs, we cannot reset timers above | |
64 | * 6; that is, resets for 7 and 8 will be ignored. Is this | |
65 | * a problem? -dilinger | |
66 | */ | |
67 | msr = MSR_MFGPT_NR; | |
68 | mask = 1 << (timer->nr + 24); | |
69 | break; | |
70 | ||
71 | case MFGPT_EVENT_NMI: | |
72 | msr = MSR_MFGPT_NR; | |
73 | mask = 1 << (timer->nr + shift); | |
74 | break; | |
75 | ||
76 | case MFGPT_EVENT_IRQ: | |
77 | msr = MSR_MFGPT_IRQ; | |
78 | mask = 1 << (timer->nr + shift); | |
79 | break; | |
80 | ||
81 | default: | |
82 | return -EIO; | |
83 | } | |
84 | ||
85 | rdmsr(msr, value, dummy); | |
86 | ||
87 | if (enable) | |
88 | value |= mask; | |
89 | else | |
90 | value &= ~mask; | |
91 | ||
92 | wrmsr(msr, value, dummy); | |
93 | return 0; | |
94 | } | |
95 | EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event); | |
96 | ||
97 | int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq, | |
98 | int enable) | |
99 | { | |
100 | uint32_t zsel, lpc, dummy; | |
101 | int shift; | |
102 | ||
103 | if (!timer) { | |
104 | WARN_ON(1); | |
105 | return -EIO; | |
106 | } | |
107 | ||
108 | /* | |
109 | * Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA | |
110 | * is using the same CMP of the timer's Siamese twin, the IRQ is set to | |
111 | * 2, and we mustn't use nor change it. | |
112 | * XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the | |
113 | * IRQ of the 1st. This can only happen if forcing an IRQ, calling this | |
114 | * with *irq==0 is safe. Currently there _are_ no 2 drivers. | |
115 | */ | |
116 | rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); | |
117 | shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4; | |
118 | if (((zsel >> shift) & 0xF) == 2) | |
119 | return -EIO; | |
120 | ||
121 | /* Choose IRQ: if none supplied, keep IRQ already set or use default */ | |
122 | if (!*irq) | |
123 | *irq = (zsel >> shift) & 0xF; | |
124 | if (!*irq) | |
125 | *irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ; | |
126 | ||
127 | /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */ | |
128 | if (*irq < 1 || *irq == 2 || *irq > 15) | |
129 | return -EIO; | |
130 | rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy); | |
131 | if (lpc & (1 << *irq)) | |
132 | return -EIO; | |
133 | ||
134 | /* All chosen and checked - go for it */ | |
135 | if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable)) | |
136 | return -EIO; | |
137 | if (enable) { | |
138 | zsel = (zsel & ~(0xF << shift)) | (*irq << shift); | |
139 | wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); | |
140 | } | |
141 | ||
142 | return 0; | |
143 | } | |
144 | EXPORT_SYMBOL_GPL(cs5535_mfgpt_set_irq); | |
145 | ||
146 | struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer_nr, int domain) | |
147 | { | |
148 | struct cs5535_mfgpt_chip *mfgpt = &cs5535_mfgpt_chip; | |
149 | struct cs5535_mfgpt_timer *timer = NULL; | |
150 | unsigned long flags; | |
151 | int max; | |
152 | ||
153 | if (!mfgpt->initialized) | |
154 | goto done; | |
155 | ||
156 | /* only allocate timers from the working domain if requested */ | |
157 | if (domain == MFGPT_DOMAIN_WORKING) | |
158 | max = 6; | |
159 | else | |
160 | max = MFGPT_MAX_TIMERS; | |
161 | ||
162 | if (timer_nr >= max) { | |
163 | /* programmer error. silly programmers! */ | |
164 | WARN_ON(1); | |
165 | goto done; | |
166 | } | |
167 | ||
168 | spin_lock_irqsave(&mfgpt->lock, flags); | |
169 | if (timer_nr < 0) { | |
170 | unsigned long t; | |
171 | ||
172 | /* try to find any available timer */ | |
173 | t = find_first_bit(mfgpt->avail, max); | |
174 | /* set timer_nr to -1 if no timers available */ | |
175 | timer_nr = t < max ? (int) t : -1; | |
176 | } else { | |
177 | /* check if the requested timer's available */ | |
178 | if (test_bit(timer_nr, mfgpt->avail)) | |
179 | timer_nr = -1; | |
180 | } | |
181 | ||
182 | if (timer_nr >= 0) | |
183 | /* if timer_nr is not -1, it's an available timer */ | |
184 | __clear_bit(timer_nr, mfgpt->avail); | |
185 | spin_unlock_irqrestore(&mfgpt->lock, flags); | |
186 | ||
187 | if (timer_nr < 0) | |
188 | goto done; | |
189 | ||
190 | timer = kmalloc(sizeof(*timer), GFP_KERNEL); | |
191 | if (!timer) { | |
192 | /* aw hell */ | |
193 | spin_lock_irqsave(&mfgpt->lock, flags); | |
194 | __set_bit(timer_nr, mfgpt->avail); | |
195 | spin_unlock_irqrestore(&mfgpt->lock, flags); | |
196 | goto done; | |
197 | } | |
198 | timer->chip = mfgpt; | |
199 | timer->nr = timer_nr; | |
200 | dev_info(&mfgpt->pdev->dev, "registered timer %d\n", timer_nr); | |
201 | ||
202 | done: | |
203 | return timer; | |
204 | } | |
205 | EXPORT_SYMBOL_GPL(cs5535_mfgpt_alloc_timer); | |
206 | ||
207 | /* | |
208 | * XXX: This frees the timer memory, but never resets the actual hardware | |
209 | * timer. The old geode_mfgpt code did this; it would be good to figure | |
210 | * out a way to actually release the hardware timer. See comments below. | |
211 | */ | |
212 | void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer) | |
213 | { | |
ecd62691 JR |
214 | unsigned long flags; |
215 | uint16_t val; | |
216 | ||
217 | /* timer can be made available again only if never set up */ | |
218 | val = cs5535_mfgpt_read(timer, MFGPT_REG_SETUP); | |
219 | if (!(val & MFGPT_SETUP_SETUP)) { | |
220 | spin_lock_irqsave(&timer->chip->lock, flags); | |
221 | __set_bit(timer->nr, timer->chip->avail); | |
222 | spin_unlock_irqrestore(&timer->chip->lock, flags); | |
223 | } | |
224 | ||
82dca611 AS |
225 | kfree(timer); |
226 | } | |
227 | EXPORT_SYMBOL_GPL(cs5535_mfgpt_free_timer); | |
228 | ||
229 | uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg) | |
230 | { | |
231 | return inw(timer->chip->base + reg + (timer->nr * 8)); | |
232 | } | |
233 | EXPORT_SYMBOL_GPL(cs5535_mfgpt_read); | |
234 | ||
235 | void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg, | |
236 | uint16_t value) | |
237 | { | |
238 | outw(value, timer->chip->base + reg + (timer->nr * 8)); | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(cs5535_mfgpt_write); | |
241 | ||
242 | /* | |
243 | * This is a sledgehammer that resets all MFGPT timers. This is required by | |
244 | * some broken BIOSes which leave the system in an unstable state | |
245 | * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to | |
246 | * whether or not this secret MSR can be used to release individual timers. | |
247 | * Jordan tells me that he and Mitch once played w/ it, but it's unclear | |
248 | * what the results of that were (and they experienced some instability). | |
249 | */ | |
250 | static void __init reset_all_timers(void) | |
251 | { | |
252 | uint32_t val, dummy; | |
253 | ||
254 | /* The following undocumented bit resets the MFGPT timers */ | |
255 | val = 0xFF; dummy = 0; | |
256 | wrmsr(MSR_MFGPT_SETUP, val, dummy); | |
257 | } | |
258 | ||
259 | /* | |
260 | * Check whether any MFGPTs are available for the kernel to use. In most | |
261 | * cases, firmware that uses AMD's VSA code will claim all timers during | |
262 | * bootup; we certainly don't want to take them if they're already in use. | |
263 | * In other cases (such as with VSAless OpenFirmware), the system firmware | |
264 | * leaves timers available for us to use. | |
265 | */ | |
266 | static int __init scan_timers(struct cs5535_mfgpt_chip *mfgpt) | |
267 | { | |
268 | struct cs5535_mfgpt_timer timer = { .chip = mfgpt }; | |
269 | unsigned long flags; | |
270 | int timers = 0; | |
271 | uint16_t val; | |
272 | int i; | |
273 | ||
274 | /* bios workaround */ | |
275 | if (mfgpt_reset_timers) | |
276 | reset_all_timers(); | |
277 | ||
278 | /* just to be safe, protect this section w/ lock */ | |
279 | spin_lock_irqsave(&mfgpt->lock, flags); | |
280 | for (i = 0; i < MFGPT_MAX_TIMERS; i++) { | |
281 | timer.nr = i; | |
282 | val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP); | |
283 | if (!(val & MFGPT_SETUP_SETUP)) { | |
284 | __set_bit(i, mfgpt->avail); | |
285 | timers++; | |
286 | } | |
287 | } | |
288 | spin_unlock_irqrestore(&mfgpt->lock, flags); | |
289 | ||
290 | return timers; | |
291 | } | |
292 | ||
293 | static int __init cs5535_mfgpt_probe(struct pci_dev *pdev, | |
294 | const struct pci_device_id *pci_id) | |
295 | { | |
296 | int err, t; | |
297 | ||
298 | /* There are two ways to get the MFGPT base address; one is by | |
299 | * fetching it from MSR_LBAR_MFGPT, the other is by reading the | |
300 | * PCI BAR info. The latter method is easier (especially across | |
301 | * different architectures), so we'll stick with that for now. If | |
302 | * it turns out to be unreliable in the face of crappy BIOSes, we | |
303 | * can always go back to using MSRs.. */ | |
304 | ||
305 | err = pci_enable_device_io(pdev); | |
306 | if (err) { | |
307 | dev_err(&pdev->dev, "can't enable device IO\n"); | |
308 | goto done; | |
309 | } | |
310 | ||
311 | err = pci_request_region(pdev, MFGPT_BAR, DRV_NAME); | |
312 | if (err) { | |
313 | dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", MFGPT_BAR); | |
314 | goto done; | |
315 | } | |
316 | ||
317 | /* set up the driver-specific struct */ | |
318 | cs5535_mfgpt_chip.base = pci_resource_start(pdev, MFGPT_BAR); | |
319 | cs5535_mfgpt_chip.pdev = pdev; | |
320 | spin_lock_init(&cs5535_mfgpt_chip.lock); | |
321 | ||
322 | dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", MFGPT_BAR, | |
323 | (unsigned long long) cs5535_mfgpt_chip.base); | |
324 | ||
325 | /* detect the available timers */ | |
326 | t = scan_timers(&cs5535_mfgpt_chip); | |
327 | dev_info(&pdev->dev, DRV_NAME ": %d MFGPT timers available\n", t); | |
328 | cs5535_mfgpt_chip.initialized = 1; | |
329 | return 0; | |
330 | ||
331 | done: | |
332 | return err; | |
333 | } | |
334 | ||
335 | static struct pci_device_id cs5535_mfgpt_pci_tbl[] = { | |
336 | { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) }, | |
337 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) }, | |
338 | { 0, }, | |
339 | }; | |
340 | MODULE_DEVICE_TABLE(pci, cs5535_mfgpt_pci_tbl); | |
341 | ||
342 | /* | |
343 | * Just like with the cs5535-gpio driver, we can't use the standard PCI driver | |
344 | * registration stuff. It only allows only one driver to bind to each PCI | |
345 | * device, and we want the GPIO and MFGPT drivers to be able to share a PCI | |
346 | * device. Instead, we manually scan for the PCI device, request a single | |
347 | * region, and keep track of the devices that we're using. | |
348 | */ | |
349 | ||
350 | static int __init cs5535_mfgpt_scan_pci(void) | |
351 | { | |
352 | struct pci_dev *pdev; | |
353 | int err = -ENODEV; | |
354 | int i; | |
355 | ||
356 | for (i = 0; i < ARRAY_SIZE(cs5535_mfgpt_pci_tbl); i++) { | |
357 | pdev = pci_get_device(cs5535_mfgpt_pci_tbl[i].vendor, | |
358 | cs5535_mfgpt_pci_tbl[i].device, NULL); | |
359 | if (pdev) { | |
360 | err = cs5535_mfgpt_probe(pdev, | |
361 | &cs5535_mfgpt_pci_tbl[i]); | |
362 | if (err) | |
363 | pci_dev_put(pdev); | |
364 | ||
365 | /* we only support a single CS5535/6 southbridge */ | |
366 | break; | |
367 | } | |
368 | } | |
369 | ||
370 | return err; | |
371 | } | |
372 | ||
373 | static int __init cs5535_mfgpt_init(void) | |
374 | { | |
375 | return cs5535_mfgpt_scan_pci(); | |
376 | } | |
377 | ||
378 | module_init(cs5535_mfgpt_init); | |
379 | ||
d45840d9 | 380 | MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>"); |
82dca611 AS |
381 | MODULE_DESCRIPTION("CS5535/CS5536 MFGPT timer driver"); |
382 | MODULE_LICENSE("GPL"); |