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cxl: Fix bug where AFU disable operation had no effect
[deliverable/linux.git] / drivers / misc / cxl / cxl.h
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _CXL_H_
11#define _CXL_H_
12
13#include <linux/interrupt.h>
14#include <linux/semaphore.h>
15#include <linux/device.h>
16#include <linux/types.h>
17#include <linux/cdev.h>
18#include <linux/pid.h>
19#include <linux/io.h>
20#include <linux/pci.h>
0520336a 21#include <linux/fs.h>
f204e0b8
IM		 22#include <asm/cputable.h>
23#include <asm/mmu.h>
24#include <asm/reg.h>
ec249dd8 25#include <misc/cxl-base.h>
f204e0b8 26
b810253b 27#include <misc/cxl.h>
f204e0b8
IM		 28#include <uapi/misc/cxl.h>
29
30extern uint cxl_verbose;
31
32#define CXL_TIMEOUT 5
33
34/*
35 * Bump version each time a user API change is made, whether it is
36 * backwards compatible ot not.
37 */
b810253b 38#define CXL_API_VERSION 3
f204e0b8
IM		 39#define CXL_API_VERSION_COMPATIBLE 1
40
41/*
42 * Opaque types to avoid accidentally passing registers for the wrong MMIO
43 *
44 * At the end of the day, I'm not married to using typedef here, but it might
45 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
46 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
47 *
48 * I'm quite happy if these are changed back to #defines before upstreaming, it
49 * should be little more than a regexp search+replace operation in this file.
50 */
51typedef struct {
52 const int x;
53} cxl_p1_reg_t;
54typedef struct {
55 const int x;
56} cxl_p1n_reg_t;
57typedef struct {
58 const int x;
59} cxl_p2n_reg_t;
60#define cxl_reg_off(reg) \
61 (reg.x)
62
63/* Memory maps. Ref CXL Appendix A */
64
65/* PSL Privilege 1 Memory Map */
66/* Configuration and Control area */
67static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
68static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
69static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
70static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
71static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
72/* Downloading */
73static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
74static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
75
76/* PSL Lookaside Buffer Management Area */
77static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
78static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
79static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
80static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
81static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
82static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
83
84/* 0x00C0:7EFF Implementation dependent area */
6d382616 85/* PSL registers */
f204e0b8
IM		 86static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
87static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
390fd592 88static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
f204e0b8
IM		 89static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
90static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
390fd592 91static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
f204e0b8
IM		 92static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
93static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
94static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
95static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
6d382616
FB		 96/* XSL registers (Mellanox CX4) */
97static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100};
98static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
99static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
100static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
f204e0b8
IM		 101/* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
102/* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
103
104/* PSL Slice Privilege 1 Memory Map */
105/* Configuration Area */
106static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
107static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
108static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
109static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
110static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
111static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
112/* Memory Management and Lookaside Buffer Management */
113static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
114static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
115/* Pointer Area */
116static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
117static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
118static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
119/* Control Area */
120static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
121static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
122static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
123static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
124/* 0xC0:FF Implementation Dependent Area */
125static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
126static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
127static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
128static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
129static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
130static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
131
132/* PSL Slice Privilege 2 Memory Map */
133/* Configuration and Control Area */
134static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
135static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
136static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
137static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
138static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
139static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
140static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
141/* Segment Lookaside Buffer Management */
142static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
143static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
144static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
145/* Interrupt Registers */
146static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
147static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
148static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
149static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
150static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
151static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
152/* AFU Registers */
153static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
154static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
155/* Work Element Descriptor */
156static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
157/* 0x0C0:FFF Implementation Dependent Area */
158
159#define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
160#define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
161#define CXL_PSL_SPAP_Size_Shift 4
162#define CXL_PSL_SPAP_V 0x0000000000000001ULL
163
390fd592
PB		 164/****** CXL_PSL_Control ****************************************************/
165#define CXL_PSL_Control_tb 0x0000000000000001ULL
166
f204e0b8
IM		 167/****** CXL_PSL_DLCNTL *****************************************************/
168#define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
169#define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
170#define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
171#define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
172#define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
173#define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
174
175/****** CXL_PSL_SR_An ******************************************************/
176#define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
177#define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
178#define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
179#define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
180#define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
181#define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
182#define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
183#define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
184#define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
185#define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
186#define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
187
f204e0b8
IM		 188/****** CXL_PSL_ID_An ****************************************************/
189#define CXL_PSL_ID_An_F (1ull << (63-31))
190#define CXL_PSL_ID_An_L (1ull << (63-30))
191
192/****** CXL_PSL_SCNTL_An ****************************************************/
193#define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
194/* Programming Modes: */
195#define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
196#define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
197#define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
198#define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
199#define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
200#define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
201/* Purge Status (ro) */
202#define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
203#define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
204#define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
205/* Purge */
206#define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
207/* Suspend Status (ro) */
208#define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
209#define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
210#define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
211/* Suspend Control */
212#define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
213
214/* AFU Slice Enable Status (ro) */
215#define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
216#define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
217#define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
218/* AFU Slice Enable */
219#define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
220/* AFU Slice Reset status (ro) */
221#define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
222#define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
223#define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
224/* AFU Slice Reset */
225#define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
226
227/****** CXL_SSTP0/1_An ******************************************************/
228/* These top bits are for the segment that CONTAINS the segment table */
229#define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
230#define CXL_SSTP0_An_KS (1ull << (63-2))
231#define CXL_SSTP0_An_KP (1ull << (63-3))
232#define CXL_SSTP0_An_N (1ull << (63-4))
233#define CXL_SSTP0_An_L (1ull << (63-5))
234#define CXL_SSTP0_An_C (1ull << (63-6))
235#define CXL_SSTP0_An_TA (1ull << (63-7))
236#define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
237/* And finally, the virtual address & size of the segment table: */
238#define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
239#define CXL_SSTP0_An_SegTableSize_MASK \
240 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
241#define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
242#define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
243#define CXL_SSTP1_An_V (1ull << (63-63))
244
245/****** CXL_PSL_SLBIE_[An] **************************************************/
246/* write: */
247#define CXL_SLBIE_C PPC_BIT(36) /* Class */
248#define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
249#define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
250#define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
251/* read: */
252#define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
253#define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
254
255/****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
256#define CXL_TLB_SLB_P (1ull) /* Pending (read) */
257
258/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
259#define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
260#define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
261#define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
262
263/****** CXL_PSL_AFUSEL ******************************************************/
264#define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
265
266/****** CXL_PSL_DSISR_An ****************************************************/
267#define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
268#define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
269#define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
270#define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
271#define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
272#define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
273#define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
274#define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
2bc79ffc 275#define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
f204e0b8
IM		 276/* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
277#define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
278#define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
279#define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
280#define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
281#define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
282
283/****** CXL_PSL_TFC_An ******************************************************/
284#define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
285#define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
286#define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
287#define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
288
289/* cxl_process_element->software_status */
290#define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
291#define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
292#define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
293#define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
294
d6a6af2c
IM		 295/****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
296 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
297 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
298 * of the hang pulse frequency.
299 */
300#define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
301
f204e0b8
IM		 302/* SPA->sw_command_status */
303#define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
304#define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
305#define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
306#define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
307#define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
308#define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
309#define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
310#define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
311#define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
312#define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
313#define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
314#define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
315#define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
316#define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
317#define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
318#define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
319
320#define CXL_MAX_SLICES 4
321#define MAX_AFU_MMIO_REGS 3
322
f204e0b8
IM		 323#define CXL_MODE_TIME_SLICED 0x4
324#define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
325
594ff7d0
CL		 326#define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
327#define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
328#define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
329
f204e0b8
IM		 330enum cxl_context_status {
331 CLOSED,
332 OPENED,
333 STARTED
334};
335
336enum prefault_modes {
337 CXL_PREFAULT_NONE,
338 CXL_PREFAULT_WED,
339 CXL_PREFAULT_ALL,
340};
341
4752876c
CL		 342enum cxl_attrs {
343 CXL_ADAPTER_ATTRS,
344 CXL_AFU_MASTER_ATTRS,
345 CXL_AFU_ATTRS,
346};
347
f204e0b8
IM		 348struct cxl_sste {
349 __be64 esid_data;
350 __be64 vsid_data;
351};
352
353#define to_cxl_adapter(d) container_of(d, struct cxl, dev)
354#define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
355
cbffa3a5
CL		 356struct cxl_afu_native {
357 void __iomem *p1n_mmio;
358 void __iomem *afu_desc_mmio;
f204e0b8 359 irq_hw_number_t psl_hwirq;
cbffa3a5
CL		 360 unsigned int psl_virq;
361 struct mutex spa_mutex;
362 /*
363 * Only the first part of the SPA is used for the process element
364 * linked list. The only other part that software needs to worry about
365 * is sw_command_status, which we store a separate pointer to.
366 * Everything else in the SPA is only used by hardware
367 */
368 struct cxl_process_element *spa;
369 __be64 *sw_command_status;
370 unsigned int spa_size;
371 int spa_order;
372 int spa_max_procs;
373 u64 pp_offset;
374};
375
376struct cxl_afu_guest {
266eab8f 377 struct cxl_afu *parent;
cbffa3a5
CL		 378 u64 handle;
379 phys_addr_t p2n_phys;
380 u64 p2n_size;
381 int max_ints;
266eab8f
CL		 382 bool handle_err;
383 struct delayed_work work_err;
0d400f77 384 int previous_state;
cbffa3a5
CL		 385};
386
387struct cxl_afu {
388 struct cxl_afu_native *native;
389 struct cxl_afu_guest *guest;
f204e0b8
IM		 390 irq_hw_number_t serr_hwirq;
391 unsigned int serr_virq;
cbffa3a5
CL		 392 char *psl_irq_name;
393 char *err_irq_name;
f204e0b8
IM		 394 void __iomem *p2n_mmio;
395 phys_addr_t psn_phys;
f204e0b8 396 u64 pp_size;
cbffa3a5 397
f204e0b8
IM		 398 struct cxl *adapter;
399 struct device dev;
400 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
401 struct device *chardev_s, *chardev_m, *chardev_d;
402 struct idr contexts_idr;
403 struct dentry *debugfs;
ee41d11d 404 struct mutex contexts_lock;
f204e0b8
IM		 405 spinlock_t afu_cntl_lock;
406
e36f6fe1
VJ		 407 /* AFU error buffer fields and bin attribute for sysfs */
408 u64 eb_len, eb_offset;
409 struct bin_attribute attr_eb;
410
6f7f0b3d
MN		 411 /* pointer to the vphb */
412 struct pci_controller *phb;
413
f204e0b8
IM		 414 int pp_irqs;
415 int irqs_max;
416 int num_procs;
417 int max_procs_virtualised;
418 int slice;
419 int modes_supported;
420 int current_mode;
b087e619
IM		 421 int crs_num;
422 u64 crs_len;
423 u64 crs_offset;
424 struct list_head crs;
f204e0b8
IM		 425 enum prefault_modes prefault_mode;
426 bool psa;
427 bool pp_psa;
428 bool enabled;
429};
430
1b5df59e
VJ		 431/* AFU refcount management */
432static inline struct cxl_afu *cxl_afu_get(struct cxl_afu *afu)
433{
434
435 return (get_device(&afu->dev) == NULL) ? NULL : afu;
436}
437
438static inline void cxl_afu_put(struct cxl_afu *afu)
439{
440 put_device(&afu->dev);
441}
442
80fa93fc
MN		 443
444struct cxl_irq_name {
445 struct list_head list;
446 char *name;
447};
448
14baf4d9
CL		 449struct irq_avail {
450 irq_hw_number_t offset;
451 irq_hw_number_t range;
452 unsigned long *bitmap;
453};
454
f204e0b8
IM		 455/*
456 * This is a cxl context. If the PSL is in dedicated mode, there will be one
457 * of these per AFU. If in AFU directed there can be lots of these.
458 */
459struct cxl_context {
460 struct cxl_afu *afu;
461
462 /* Problem state MMIO */
463 phys_addr_t psn_phys;
464 u64 psn_size;
465
b123429e
IM		 466 /* Used to unmap any mmaps when force detaching */
467 struct address_space *mapping;
468 struct mutex mapping_lock;
d9232a3d
IM		 469 struct page *ff_page;
470 bool mmio_err_ff;
55e07668 471 bool kernelapi;
b123429e 472
f204e0b8
IM		 473 spinlock_t sste_lock; /* Protects segment table entries */
474 struct cxl_sste *sstp;
475 u64 sstp0, sstp1;
476 unsigned int sst_size, sst_lru;
477
478 wait_queue_head_t wq;
7b8ad495
VJ		 479 /* pid of the group leader associated with the pid */
480 struct pid *glpid;
481 /* use mm context associated with this pid for ds faults */
f204e0b8
IM		 482 struct pid *pid;
483 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
484 /* Only used in PR mode */
485 u64 process_token;
486
ad42de85
MN		 487 /* driver private data */
488 void *priv;
489
f204e0b8
IM		 490 unsigned long *irq_bitmap; /* Accessed from IRQ context */
491 struct cxl_irq_ranges irqs;
80fa93fc 492 struct list_head irq_names;
f204e0b8
IM		 493 u64 fault_addr;
494 u64 fault_dsisr;
495 u64 afu_err;
496
497 /*
498 * This status and it's lock pretects start and detach context
499 * from racing. It also prevents detach from racing with
500 * itself
501 */
502 enum cxl_context_status status;
503 struct mutex status_mutex;
504
505
506 /* XXX: Is it possible to need multiple work items at once? */
507 struct work_struct fault_work;
508 u64 dsisr;
509 u64 dar;
510
511 struct cxl_process_element *elem;
512
14baf4d9
CL		 513 /*
514 * pe is the process element handle, assigned by this driver when the
515 * context is initialized.
516 *
517 * external_pe is the PE shown outside of cxl.
518 * On bare-metal, pe=external_pe, because we decide what the handle is.
519 * In a guest, we only find out about the pe used by pHyp when the
520 * context is attached, and that's the value we want to report outside
521 * of cxl.
522 */
523 int pe;
524 int external_pe;
525
f204e0b8
IM		 526 u32 irq_count;
527 bool pe_inserted;
528 bool master;
529 bool kernel;
7a0d85d3 530 bool real_mode;
f204e0b8
IM		 531 bool pending_irq;
532 bool pending_fault;
533 bool pending_afu_err;
8ac75b96 534
b810253b
PB		 535 /* Used by AFU drivers for driver specific event delivery */
536 struct cxl_afu_driver_ops *afu_driver_ops;
537 atomic_t afu_driver_events;
538
8ac75b96 539 struct rcu_head rcu;
f204e0b8
IM		 540};
541
6d382616
FB		 542struct cxl_service_layer_ops {
543 int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
544 int (*afu_regs_init)(struct cxl_afu *afu);
545 int (*register_serr_irq)(struct cxl_afu *afu);
546 void (*release_serr_irq)(struct cxl_afu *afu);
547 void (*debugfs_add_adapter_sl_regs)(struct cxl *adapter, struct dentry *dir);
548 void (*debugfs_add_afu_sl_regs)(struct cxl_afu *afu, struct dentry *dir);
549 void (*psl_irq_dump_registers)(struct cxl_context *ctx);
550 void (*err_irq_dump_registers)(struct cxl *adapter);
551 void (*debugfs_stop_trace)(struct cxl *adapter);
552 void (*write_timebase_ctrl)(struct cxl *adapter);
553 u64 (*timebase_read)(struct cxl *adapter);
b385c9e9 554 int capi_mode;
5e7823c9 555 bool needs_reset_before_disable;
6d382616
FB		 556};
557
cbffa3a5
CL		 558struct cxl_native {
559 u64 afu_desc_off;
560 u64 afu_desc_size;
f204e0b8
IM		 561 void __iomem *p1_mmio;
562 void __iomem *p2_mmio;
563 irq_hw_number_t err_hwirq;
564 unsigned int err_virq;
cbffa3a5 565 u64 ps_off;
6d382616 566 const struct cxl_service_layer_ops *sl_ops;
cbffa3a5
CL		 567};
568
569struct cxl_guest {
570 struct platform_device *pdev;
571 int irq_nranges;
572 struct cdev cdev;
573 irq_hw_number_t irq_base_offset;
574 struct irq_avail *irq_avail;
575 spinlock_t irq_alloc_lock;
576 u64 handle;
577 char *status;
578 u16 vendor;
579 u16 device;
580 u16 subsystem_vendor;
581 u16 subsystem;
582};
583
584struct cxl {
585 struct cxl_native *native;
586 struct cxl_guest *guest;
f204e0b8
IM		 587 spinlock_t afu_list_lock;
588 struct cxl_afu *afu[CXL_MAX_SLICES];
589 struct device dev;
590 struct dentry *trace;
591 struct dentry *psl_err_chk;
592 struct dentry *debugfs;
80fa93fc 593 char *irq_name;
f204e0b8
IM		 594 struct bin_attribute cxl_attr;
595 int adapter_num;
596 int user_irqs;
f204e0b8
IM		 597 u64 ps_size;
598 u16 psl_rev;
599 u16 base_image;
600 u8 vsec_status;
601 u8 caia_major;
602 u8 caia_minor;
603 u8 slices;
604 bool user_image_loaded;
605 bool perst_loads_image;
606 bool perst_select_user;
13e68d8b 607 bool perst_same_image;
e009a7e8 608 bool psl_timebase_synced;
f204e0b8
IM		 609};
610
2b04cf31
FB		 611int cxl_pci_alloc_one_irq(struct cxl *adapter);
612void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
613int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
614void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
615int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
4beb5421 616int cxl_update_image_control(struct cxl *adapter);
2b04cf31
FB		 617int cxl_pci_reset(struct cxl *adapter);
618void cxl_pci_release_afu(struct device *dev);
d601ea91 619ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
f204e0b8
IM		 620
621/* common == phyp + powernv */
622struct cxl_process_element_common {
623 __be32 tid;
624 __be32 pid;
625 __be64 csrp;
626 __be64 aurp0;
627 __be64 aurp1;
628 __be64 sstp0;
629 __be64 sstp1;
630 __be64 amr;
631 u8 reserved3[4];
632 __be64 wed;
633} __packed;
634
635/* just powernv */
636struct cxl_process_element {
637 __be64 sr;
638 __be64 SPOffset;
639 __be64 sdr;
640 __be64 haurp;
641 __be32 ctxtime;
642 __be16 ivte_offsets[4];
643 __be16 ivte_ranges[4];
644 __be32 lpid;
645 struct cxl_process_element_common common;
646 __be32 software_state;
647} __packed;
648
0d400f77 649static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
0b3f9c75
DA		 650{
651 struct pci_dev *pdev;
652
ea2d1f95
FB		 653 if (cpu_has_feature(CPU_FTR_HVMODE)) {
654 pdev = to_pci_dev(cxl->dev.parent);
655 return !pci_channel_offline(pdev);
656 }
657 return true;
0b3f9c75
DA		 658}
659
f204e0b8
IM		 660static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
661{
662 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
cbffa3a5 663 return cxl->native->p1_mmio + cxl_reg_off(reg);
f204e0b8
IM		 664}
665
588b34be
DA		 666static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
667{
0d400f77 668 if (likely(cxl_adapter_link_ok(cxl, NULL)))
0b3f9c75 669 out_be64(_cxl_p1_addr(cxl, reg), val);
588b34be
DA		 670}
671
672static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
673{
0d400f77 674 if (likely(cxl_adapter_link_ok(cxl, NULL)))
0b3f9c75
DA		 675 return in_be64(_cxl_p1_addr(cxl, reg));
676 else
677 return ~0ULL;
588b34be 678}
f204e0b8
IM		 679
680static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
681{
682 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
cbffa3a5 683 return afu->native->p1n_mmio + cxl_reg_off(reg);
f204e0b8
IM		 684}
685
588b34be
DA		 686static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
687{
0d400f77 688 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75 689 out_be64(_cxl_p1n_addr(afu, reg), val);
588b34be
DA		 690}
691
692static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
693{
0d400f77 694 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75
DA		 695 return in_be64(_cxl_p1n_addr(afu, reg));
696 else
697 return ~0ULL;
588b34be 698}
f204e0b8
IM		 699
700static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
701{
702 return afu->p2n_mmio + cxl_reg_off(reg);
703}
704
588b34be
DA		 705static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
706{
0d400f77 707 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75 708 out_be64(_cxl_p2n_addr(afu, reg), val);
588b34be 709}
f204e0b8 710
588b34be
DA		 711static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
712{
0d400f77 713 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75
DA		 714 return in_be64(_cxl_p2n_addr(afu, reg));
715 else
716 return ~0ULL;
588b34be 717}
b087e619 718
2b04cf31 719ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
e36f6fe1
VJ		 720 loff_t off, size_t count);
721
b087e619 722
f204e0b8
IM		 723struct cxl_calls {
724 void (*cxl_slbia)(struct mm_struct *mm);
725 struct module *owner;
726};
727int register_cxl_calls(struct cxl_calls *calls);
728void unregister_cxl_calls(struct cxl_calls *calls);
594ff7d0 729int cxl_update_properties(struct device_node *dn, struct property *new_prop);
f204e0b8 730
f204e0b8
IM		 731void cxl_remove_adapter_nr(struct cxl *adapter);
732
05155772
DA		 733int cxl_alloc_spa(struct cxl_afu *afu);
734void cxl_release_spa(struct cxl_afu *afu);
735
594ff7d0 736dev_t cxl_get_dev(void);
f204e0b8
IM		 737int cxl_file_init(void);
738void cxl_file_exit(void);
739int cxl_register_adapter(struct cxl *adapter);
740int cxl_register_afu(struct cxl_afu *afu);
741int cxl_chardev_d_afu_add(struct cxl_afu *afu);
742int cxl_chardev_m_afu_add(struct cxl_afu *afu);
743int cxl_chardev_s_afu_add(struct cxl_afu *afu);
744void cxl_chardev_afu_remove(struct cxl_afu *afu);
745
746void cxl_context_detach_all(struct cxl_afu *afu);
747void cxl_context_free(struct cxl_context *ctx);
748void cxl_context_detach(struct cxl_context *ctx);
749
750int cxl_sysfs_adapter_add(struct cxl *adapter);
751void cxl_sysfs_adapter_remove(struct cxl *adapter);
752int cxl_sysfs_afu_add(struct cxl_afu *afu);
753void cxl_sysfs_afu_remove(struct cxl_afu *afu);
754int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
755void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
756
86331862
CL		 757struct cxl *cxl_alloc_adapter(void);
758struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
f204e0b8
IM		 759int cxl_afu_select_best_mode(struct cxl_afu *afu);
760
2b04cf31
FB		 761int cxl_native_register_psl_irq(struct cxl_afu *afu);
762void cxl_native_release_psl_irq(struct cxl_afu *afu);
763int cxl_native_register_psl_err_irq(struct cxl *adapter);
764void cxl_native_release_psl_err_irq(struct cxl *adapter);
765int cxl_native_register_serr_irq(struct cxl_afu *afu);
766void cxl_native_release_serr_irq(struct cxl_afu *afu);
f204e0b8 767int afu_register_irqs(struct cxl_context *ctx, u32 count);
6428832a 768void afu_release_irqs(struct cxl_context *ctx, void *cookie);
8dde152e 769void afu_irq_name_free(struct cxl_context *ctx);
f204e0b8
IM		 770
771int cxl_debugfs_init(void);
772void cxl_debugfs_exit(void);
773int cxl_debugfs_adapter_add(struct cxl *adapter);
774void cxl_debugfs_adapter_remove(struct cxl *adapter);
775int cxl_debugfs_afu_add(struct cxl_afu *afu);
776void cxl_debugfs_afu_remove(struct cxl_afu *afu);
777
778void cxl_handle_fault(struct work_struct *work);
779void cxl_prefault(struct cxl_context *ctx, u64 wed);
780
781struct cxl *get_cxl_adapter(int num);
782int cxl_alloc_sst(struct cxl_context *ctx);
444c4ba4 783void cxl_dump_debug_buffer(void *addr, size_t size);
f204e0b8
IM		 784
785void init_cxl_native(void);
786
787struct cxl_context *cxl_context_alloc(void);
b123429e
IM		 788int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
789 struct address_space *mapping);
f204e0b8
IM		 790void cxl_context_free(struct cxl_context *ctx);
791int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1a1a94b8
MN		 792unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
793 irq_handler_t handler, void *cookie, const char *name);
794void cxl_unmap_irq(unsigned int virq, void *cookie);
eda3693c 795int __detach_context(struct cxl_context *ctx);
f204e0b8 796
444c4ba4
CL		 797/*
798 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
799 * in PAPR.
800 * A word about endianness: a pointer to this structure is passed when
801 * calling the hcall. However, it is not a block of memory filled up by
802 * the hypervisor. The return values are found in registers, and copied
803 * one by one when returning from the hcall. See the end of the call to
804 * plpar_hcall9() in hvCall.S
805 * As a consequence:
806 * - we don't need to do any endianness conversion
807 * - the pid and tid are an exception. They are 32-bit values returned in
808 * the same 64-bit register. So we do need to worry about byte ordering.
809 */
f204e0b8
IM		 810struct cxl_irq_info {
811 u64 dsisr;
812 u64 dar;
813 u64 dsr;
444c4ba4 814#ifndef CONFIG_CPU_LITTLE_ENDIAN
f204e0b8
IM		 815 u32 pid;
816 u32 tid;
444c4ba4
CL		 817#else
818 u32 tid;
819 u32 pid;
820#endif
f204e0b8
IM		 821 u64 afu_err;
822 u64 errstat;
444c4ba4
CL		 823 u64 proc_handle;
824 u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
f204e0b8
IM		 825};
826
1a1a94b8 827void cxl_assign_psn_space(struct cxl_context *ctx);
6d625ed9 828irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
86331862
CL		 829int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
830 void *cookie, irq_hw_number_t *dest_hwirq,
831 unsigned int *dest_virq, const char *name);
832
f204e0b8
IM		 833int cxl_check_error(struct cxl_afu *afu);
834int cxl_afu_slbia(struct cxl_afu *afu);
835int cxl_tlb_slb_invalidate(struct cxl *adapter);
836int cxl_afu_disable(struct cxl_afu *afu);
f204e0b8
IM		 837int cxl_psl_purge(struct cxl_afu *afu);
838
6d382616
FB		 839void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir);
840void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter, struct dentry *dir);
841void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir);
842void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx);
843void cxl_native_err_irq_dump_regs(struct cxl *adapter);
f204e0b8 844void cxl_stop_trace(struct cxl *cxl);
6f7f0b3d
MN		 845int cxl_pci_vphb_add(struct cxl_afu *afu);
846void cxl_pci_vphb_remove(struct cxl_afu *afu);
f204e0b8
IM		 847
848extern struct pci_driver cxl_pci_driver;
14baf4d9 849extern struct platform_driver cxl_of_driver;
c358d84b 850int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
f204e0b8 851
0520336a
MN		 852int afu_open(struct inode *inode, struct file *file);
853int afu_release(struct inode *inode, struct file *file);
854long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
855int afu_mmap(struct file *file, struct vm_area_struct *vm);
856unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
857ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
858extern const struct file_operations afu_fops;
859
14baf4d9
CL		 860struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
861void cxl_guest_remove_adapter(struct cxl *adapter);
862int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
863int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
864ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
865ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
866int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
867void cxl_guest_remove_afu(struct cxl_afu *afu);
868int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
869int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
870int cxl_guest_add_chardev(struct cxl *adapter);
871void cxl_guest_remove_chardev(struct cxl *adapter);
872void cxl_guest_reload_module(struct cxl *adapter);
873int cxl_of_probe(struct platform_device *pdev);
874
5be587b1
FB		 875struct cxl_backend_ops {
876 struct module *module;
877 int (*adapter_reset)(struct cxl *adapter);
878 int (*alloc_one_irq)(struct cxl *adapter);
879 void (*release_one_irq)(struct cxl *adapter, int hwirq);
880 int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
881 struct cxl *adapter, unsigned int num);
882 void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
883 struct cxl *adapter);
884 int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
885 unsigned int virq);
886 irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
887 u64 dsisr, u64 errstat);
888 irqreturn_t (*psl_interrupt)(int irq, void *data);
889 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
2bc79ffc 890 void (*irq_wait)(struct cxl_context *ctx);
5be587b1
FB		 891 int (*attach_process)(struct cxl_context *ctx, bool kernel,
892 u64 wed, u64 amr);
893 int (*detach_process)(struct cxl_context *ctx);
292841b0 894 void (*update_ivtes)(struct cxl_context *ctx);
4752876c 895 bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
0d400f77 896 bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
5be587b1
FB		 897 void (*release_afu)(struct device *dev);
898 ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
899 loff_t off, size_t count);
900 int (*afu_check_and_enable)(struct cxl_afu *afu);
901 int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
902 int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
903 int (*afu_reset)(struct cxl_afu *afu);
904 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
905 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
906 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
907 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
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FB		 908 int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
909 int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
910 int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
911 ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
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FB		 912};
913extern const struct cxl_backend_ops cxl_native_ops;
14baf4d9 914extern const struct cxl_backend_ops cxl_guest_ops;
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FB		 915extern const struct cxl_backend_ops *cxl_ops;
916
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VJ		 917/* check if the given pci_dev is on the the cxl vphb bus */
918bool cxl_pci_is_vphb_device(struct pci_dev *dev);
f204e0b8 919#endif
Linux kernel - Deliverables
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