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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/pci_regs.h> | |
11 | #include <linux/pci_ids.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/sort.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/delay.h> | |
20 | #include <asm/opal.h> | |
21 | #include <asm/msi_bitmap.h> | |
f204e0b8 | 22 | #include <asm/pnv-pci.h> |
62fa19d4 | 23 | #include <asm/io.h> |
aa14138a | 24 | #include <asm/reg.h> |
f204e0b8 IM |
25 | |
26 | #include "cxl.h" | |
9e8df8a2 | 27 | #include <misc/cxl.h> |
f204e0b8 IM |
28 | |
29 | ||
30 | #define CXL_PCI_VSEC_ID 0x1280 | |
31 | #define CXL_VSEC_MIN_SIZE 0x80 | |
32 | ||
33 | #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ | |
34 | { \ | |
35 | pci_read_config_word(dev, vsec + 0x6, dest); \ | |
36 | *dest >>= 4; \ | |
37 | } | |
38 | #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ | |
39 | pci_read_config_byte(dev, vsec + 0x8, dest) | |
40 | ||
41 | #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ | |
42 | pci_read_config_byte(dev, vsec + 0x9, dest) | |
43 | #define CXL_STATUS_SECOND_PORT 0x80 | |
44 | #define CXL_STATUS_MSI_X_FULL 0x40 | |
45 | #define CXL_STATUS_MSI_X_SINGLE 0x20 | |
46 | #define CXL_STATUS_FLASH_RW 0x08 | |
47 | #define CXL_STATUS_FLASH_RO 0x04 | |
48 | #define CXL_STATUS_LOADABLE_AFU 0x02 | |
49 | #define CXL_STATUS_LOADABLE_PSL 0x01 | |
50 | /* If we see these features we won't try to use the card */ | |
51 | #define CXL_UNSUPPORTED_FEATURES \ | |
52 | (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) | |
53 | ||
54 | #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ | |
55 | pci_read_config_byte(dev, vsec + 0xa, dest) | |
56 | #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ | |
57 | pci_write_config_byte(dev, vsec + 0xa, val) | |
b0b5e591 AD |
58 | #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \ |
59 | pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val) | |
f204e0b8 IM |
60 | #define CXL_VSEC_PROTOCOL_MASK 0xe0 |
61 | #define CXL_VSEC_PROTOCOL_1024TB 0x80 | |
62 | #define CXL_VSEC_PROTOCOL_512TB 0x40 | |
63 | #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */ | |
64 | #define CXL_VSEC_PROTOCOL_ENABLE 0x01 | |
65 | ||
66 | #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ | |
67 | pci_read_config_word(dev, vsec + 0xc, dest) | |
68 | #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ | |
69 | pci_read_config_byte(dev, vsec + 0xe, dest) | |
70 | #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ | |
71 | pci_read_config_byte(dev, vsec + 0xf, dest) | |
72 | #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ | |
73 | pci_read_config_word(dev, vsec + 0x10, dest) | |
74 | ||
75 | #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ | |
76 | pci_read_config_byte(dev, vsec + 0x13, dest) | |
77 | #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ | |
78 | pci_write_config_byte(dev, vsec + 0x13, val) | |
79 | #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ | |
80 | #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ | |
81 | #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ | |
82 | ||
83 | #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ | |
84 | pci_read_config_dword(dev, vsec + 0x20, dest) | |
85 | #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ | |
86 | pci_read_config_dword(dev, vsec + 0x24, dest) | |
87 | #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ | |
88 | pci_read_config_dword(dev, vsec + 0x28, dest) | |
89 | #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ | |
90 | pci_read_config_dword(dev, vsec + 0x2c, dest) | |
91 | ||
92 | ||
93 | /* This works a little different than the p1/p2 register accesses to make it | |
94 | * easier to pull out individual fields */ | |
cbffa3a5 CL |
95 | #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off) |
96 | #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off) | |
f204e0b8 IM |
97 | #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) |
98 | #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) | |
99 | ||
100 | #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) | |
101 | #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) | |
102 | #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) | |
103 | #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) | |
104 | #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) | |
105 | #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) | |
106 | #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) | |
107 | #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) | |
108 | #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) | |
109 | #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) | |
110 | #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
111 | #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) | |
112 | #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) | |
113 | #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) | |
114 | #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) | |
115 | #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
116 | #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) | |
117 | #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) | |
118 | #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
119 | #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) | |
120 | ||
f47f966f | 121 | static const struct pci_device_id cxl_pci_tbl[] = { |
f204e0b8 IM |
122 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, |
123 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, | |
124 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, | |
68adb7bf | 125 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), }, |
f204e0b8 IM |
126 | { PCI_DEVICE_CLASS(0x120000, ~0), }, |
127 | ||
128 | { } | |
129 | }; | |
130 | MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); | |
131 | ||
132 | ||
133 | /* | |
134 | * Mostly using these wrappers to avoid confusion: | |
135 | * priv 1 is BAR2, while priv 2 is BAR0 | |
136 | */ | |
137 | static inline resource_size_t p1_base(struct pci_dev *dev) | |
138 | { | |
139 | return pci_resource_start(dev, 2); | |
140 | } | |
141 | ||
142 | static inline resource_size_t p1_size(struct pci_dev *dev) | |
143 | { | |
144 | return pci_resource_len(dev, 2); | |
145 | } | |
146 | ||
147 | static inline resource_size_t p2_base(struct pci_dev *dev) | |
148 | { | |
149 | return pci_resource_start(dev, 0); | |
150 | } | |
151 | ||
152 | static inline resource_size_t p2_size(struct pci_dev *dev) | |
153 | { | |
154 | return pci_resource_len(dev, 0); | |
155 | } | |
156 | ||
157 | static int find_cxl_vsec(struct pci_dev *dev) | |
158 | { | |
159 | int vsec = 0; | |
160 | u16 val; | |
161 | ||
162 | while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { | |
163 | pci_read_config_word(dev, vsec + 0x4, &val); | |
164 | if (val == CXL_PCI_VSEC_ID) | |
165 | return vsec; | |
166 | } | |
167 | return 0; | |
168 | ||
169 | } | |
170 | ||
171 | static void dump_cxl_config_space(struct pci_dev *dev) | |
172 | { | |
173 | int vsec; | |
174 | u32 val; | |
175 | ||
176 | dev_info(&dev->dev, "dump_cxl_config_space\n"); | |
177 | ||
178 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); | |
179 | dev_info(&dev->dev, "BAR0: %#.8x\n", val); | |
180 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); | |
181 | dev_info(&dev->dev, "BAR1: %#.8x\n", val); | |
182 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); | |
183 | dev_info(&dev->dev, "BAR2: %#.8x\n", val); | |
184 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); | |
185 | dev_info(&dev->dev, "BAR3: %#.8x\n", val); | |
186 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); | |
187 | dev_info(&dev->dev, "BAR4: %#.8x\n", val); | |
188 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); | |
189 | dev_info(&dev->dev, "BAR5: %#.8x\n", val); | |
190 | ||
191 | dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", | |
192 | p1_base(dev), p1_size(dev)); | |
193 | dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", | |
f2931069 | 194 | p2_base(dev), p2_size(dev)); |
f204e0b8 IM |
195 | dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", |
196 | pci_resource_start(dev, 4), pci_resource_len(dev, 4)); | |
197 | ||
198 | if (!(vsec = find_cxl_vsec(dev))) | |
199 | return; | |
200 | ||
201 | #define show_reg(name, what) \ | |
202 | dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) | |
203 | ||
204 | pci_read_config_dword(dev, vsec + 0x0, &val); | |
205 | show_reg("Cap ID", (val >> 0) & 0xffff); | |
206 | show_reg("Cap Ver", (val >> 16) & 0xf); | |
207 | show_reg("Next Cap Ptr", (val >> 20) & 0xfff); | |
208 | pci_read_config_dword(dev, vsec + 0x4, &val); | |
209 | show_reg("VSEC ID", (val >> 0) & 0xffff); | |
210 | show_reg("VSEC Rev", (val >> 16) & 0xf); | |
211 | show_reg("VSEC Length", (val >> 20) & 0xfff); | |
212 | pci_read_config_dword(dev, vsec + 0x8, &val); | |
213 | show_reg("Num AFUs", (val >> 0) & 0xff); | |
214 | show_reg("Status", (val >> 8) & 0xff); | |
215 | show_reg("Mode Control", (val >> 16) & 0xff); | |
216 | show_reg("Reserved", (val >> 24) & 0xff); | |
217 | pci_read_config_dword(dev, vsec + 0xc, &val); | |
218 | show_reg("PSL Rev", (val >> 0) & 0xffff); | |
219 | show_reg("CAIA Ver", (val >> 16) & 0xffff); | |
220 | pci_read_config_dword(dev, vsec + 0x10, &val); | |
221 | show_reg("Base Image Rev", (val >> 0) & 0xffff); | |
222 | show_reg("Reserved", (val >> 16) & 0x0fff); | |
223 | show_reg("Image Control", (val >> 28) & 0x3); | |
224 | show_reg("Reserved", (val >> 30) & 0x1); | |
225 | show_reg("Image Loaded", (val >> 31) & 0x1); | |
226 | ||
227 | pci_read_config_dword(dev, vsec + 0x14, &val); | |
228 | show_reg("Reserved", val); | |
229 | pci_read_config_dword(dev, vsec + 0x18, &val); | |
230 | show_reg("Reserved", val); | |
231 | pci_read_config_dword(dev, vsec + 0x1c, &val); | |
232 | show_reg("Reserved", val); | |
233 | ||
234 | pci_read_config_dword(dev, vsec + 0x20, &val); | |
235 | show_reg("AFU Descriptor Offset", val); | |
236 | pci_read_config_dword(dev, vsec + 0x24, &val); | |
237 | show_reg("AFU Descriptor Size", val); | |
238 | pci_read_config_dword(dev, vsec + 0x28, &val); | |
239 | show_reg("Problem State Offset", val); | |
240 | pci_read_config_dword(dev, vsec + 0x2c, &val); | |
241 | show_reg("Problem State Size", val); | |
242 | ||
243 | pci_read_config_dword(dev, vsec + 0x30, &val); | |
244 | show_reg("Reserved", val); | |
245 | pci_read_config_dword(dev, vsec + 0x34, &val); | |
246 | show_reg("Reserved", val); | |
247 | pci_read_config_dword(dev, vsec + 0x38, &val); | |
248 | show_reg("Reserved", val); | |
249 | pci_read_config_dword(dev, vsec + 0x3c, &val); | |
250 | show_reg("Reserved", val); | |
251 | ||
252 | pci_read_config_dword(dev, vsec + 0x40, &val); | |
253 | show_reg("PSL Programming Port", val); | |
254 | pci_read_config_dword(dev, vsec + 0x44, &val); | |
255 | show_reg("PSL Programming Control", val); | |
256 | ||
257 | pci_read_config_dword(dev, vsec + 0x48, &val); | |
258 | show_reg("Reserved", val); | |
259 | pci_read_config_dword(dev, vsec + 0x4c, &val); | |
260 | show_reg("Reserved", val); | |
261 | ||
262 | pci_read_config_dword(dev, vsec + 0x50, &val); | |
263 | show_reg("Flash Address Register", val); | |
264 | pci_read_config_dword(dev, vsec + 0x54, &val); | |
265 | show_reg("Flash Size Register", val); | |
266 | pci_read_config_dword(dev, vsec + 0x58, &val); | |
267 | show_reg("Flash Status/Control Register", val); | |
268 | pci_read_config_dword(dev, vsec + 0x58, &val); | |
269 | show_reg("Flash Data Port", val); | |
270 | ||
271 | #undef show_reg | |
272 | } | |
273 | ||
274 | static void dump_afu_descriptor(struct cxl_afu *afu) | |
275 | { | |
bfcdc8ff MN |
276 | u64 val, afu_cr_num, afu_cr_off, afu_cr_len; |
277 | int i; | |
f204e0b8 IM |
278 | |
279 | #define show_reg(name, what) \ | |
280 | dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) | |
281 | ||
282 | val = AFUD_READ_INFO(afu); | |
283 | show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); | |
284 | show_reg("num_of_processes", AFUD_NUM_PROCS(val)); | |
285 | show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); | |
286 | show_reg("req_prog_mode", val & 0xffffULL); | |
bfcdc8ff | 287 | afu_cr_num = AFUD_NUM_CRS(val); |
f204e0b8 IM |
288 | |
289 | val = AFUD_READ(afu, 0x8); | |
290 | show_reg("Reserved", val); | |
291 | val = AFUD_READ(afu, 0x10); | |
292 | show_reg("Reserved", val); | |
293 | val = AFUD_READ(afu, 0x18); | |
294 | show_reg("Reserved", val); | |
295 | ||
296 | val = AFUD_READ_CR(afu); | |
297 | show_reg("Reserved", (val >> (63-7)) & 0xff); | |
298 | show_reg("AFU_CR_len", AFUD_CR_LEN(val)); | |
bfcdc8ff | 299 | afu_cr_len = AFUD_CR_LEN(val) * 256; |
f204e0b8 IM |
300 | |
301 | val = AFUD_READ_CR_OFF(afu); | |
bfcdc8ff | 302 | afu_cr_off = val; |
f204e0b8 IM |
303 | show_reg("AFU_CR_offset", val); |
304 | ||
305 | val = AFUD_READ_PPPSA(afu); | |
306 | show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); | |
307 | show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); | |
308 | ||
309 | val = AFUD_READ_PPPSA_OFF(afu); | |
310 | show_reg("PerProcessPSA_offset", val); | |
311 | ||
312 | val = AFUD_READ_EB(afu); | |
313 | show_reg("Reserved", (val >> (63-7)) & 0xff); | |
314 | show_reg("AFU_EB_len", AFUD_EB_LEN(val)); | |
315 | ||
316 | val = AFUD_READ_EB_OFF(afu); | |
317 | show_reg("AFU_EB_offset", val); | |
318 | ||
bfcdc8ff MN |
319 | for (i = 0; i < afu_cr_num; i++) { |
320 | val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len); | |
321 | show_reg("CR Vendor", val & 0xffff); | |
322 | show_reg("CR Device", (val >> 16) & 0xffff); | |
323 | } | |
f204e0b8 IM |
324 | #undef show_reg |
325 | } | |
326 | ||
aa14138a PB |
327 | #define CAPP_UNIT0_ID 0xBA |
328 | #define CAPP_UNIT1_ID 0XBE | |
329 | ||
330 | static u64 get_capp_unit_id(struct device_node *np) | |
331 | { | |
332 | u32 phb_index; | |
333 | ||
334 | /* | |
335 | * For chips other than POWER8NVL, we only have CAPP 0, | |
336 | * irrespective of which PHB is used. | |
337 | */ | |
338 | if (!pvr_version_is(PVR_POWER8NVL)) | |
339 | return CAPP_UNIT0_ID; | |
340 | ||
341 | /* | |
342 | * For POWER8NVL, assume CAPP 0 is attached to PHB0 and | |
343 | * CAPP 1 is attached to PHB1. | |
344 | */ | |
345 | if (of_property_read_u32(np, "ibm,phb-index", &phb_index)) | |
346 | return 0; | |
347 | ||
348 | if (phb_index == 0) | |
349 | return CAPP_UNIT0_ID; | |
350 | ||
351 | if (phb_index == 1) | |
352 | return CAPP_UNIT1_ID; | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
6d382616 | 357 | static int calc_capp_routing(struct pci_dev *dev, u64 *chipid, u64 *capp_unit_id) |
f204e0b8 IM |
358 | { |
359 | struct device_node *np; | |
360 | const __be32 *prop; | |
f204e0b8 | 361 | |
6f963ec2 | 362 | if (!(np = pnv_pci_get_phb_node(dev))) |
f204e0b8 IM |
363 | return -ENODEV; |
364 | ||
365 | while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) | |
366 | np = of_get_next_parent(np); | |
367 | if (!np) | |
368 | return -ENODEV; | |
6d382616 FB |
369 | *chipid = be32_to_cpup(prop); |
370 | *capp_unit_id = get_capp_unit_id(np); | |
f204e0b8 | 371 | of_node_put(np); |
6d382616 | 372 | if (!*capp_unit_id) { |
aa14138a PB |
373 | pr_err("cxl: invalid capp unit id\n"); |
374 | return -ENODEV; | |
375 | } | |
f204e0b8 | 376 | |
6d382616 FB |
377 | return 0; |
378 | } | |
379 | ||
380 | static int init_implementation_adapter_psl_regs(struct cxl *adapter, struct pci_dev *dev) | |
381 | { | |
c6d2ee09 | 382 | u64 psl_dsnctl, psl_fircntl; |
6d382616 FB |
383 | u64 chipid; |
384 | u64 capp_unit_id; | |
385 | int rc; | |
386 | ||
387 | rc = calc_capp_routing(dev, &chipid, &capp_unit_id); | |
388 | if (rc) | |
389 | return rc; | |
390 | ||
4aec6ec0 FB |
391 | psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */ |
392 | psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */ | |
f204e0b8 | 393 | /* Tell PSL where to route data to */ |
4aec6ec0 | 394 | psl_dsnctl |= (chipid << (63-5)); |
aa14138a PB |
395 | psl_dsnctl |= (capp_unit_id << (63-13)); |
396 | ||
f204e0b8 IM |
397 | cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); |
398 | cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); | |
399 | /* snoop write mask */ | |
400 | cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); | |
c6d2ee09 FB |
401 | /* set fir_cntl to recommended value for production env */ |
402 | psl_fircntl = (0x2ULL << (63-3)); /* ce_report */ | |
403 | psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */ | |
404 | psl_fircntl |= 0x1ULL; /* ce_thresh */ | |
405 | cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl); | |
f204e0b8 IM |
406 | /* for debugging with trace arrays */ |
407 | cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
6d382616 FB |
412 | static int init_implementation_adapter_xsl_regs(struct cxl *adapter, struct pci_dev *dev) |
413 | { | |
414 | u64 xsl_dsnctl; | |
415 | u64 chipid; | |
416 | u64 capp_unit_id; | |
417 | int rc; | |
418 | ||
419 | rc = calc_capp_routing(dev, &chipid, &capp_unit_id); | |
420 | if (rc) | |
421 | return rc; | |
422 | ||
423 | /* Tell XSL where to route data to */ | |
424 | xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5)); | |
425 | xsl_dsnctl |= (capp_unit_id << (63-13)); | |
426 | cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | /* PSL & XSL */ | |
432 | #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3)) | |
390fd592 | 433 | #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6)) |
6d382616 FB |
434 | /* For the PSL this is a multiple for 0 < n <= 7: */ |
435 | #define PSL_2048_250MHZ_CYCLES 1 | |
436 | ||
437 | static void write_timebase_ctrl_psl(struct cxl *adapter) | |
438 | { | |
439 | cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT, | |
440 | TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES)); | |
441 | } | |
442 | ||
443 | /* XSL */ | |
444 | #define TBSYNC_ENA (1ULL << 63) | |
445 | /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */ | |
446 | #define XSL_2000_CLOCKS 1 | |
447 | #define XSL_4000_CLOCKS 2 | |
448 | #define XSL_8000_CLOCKS 3 | |
449 | ||
450 | static void write_timebase_ctrl_xsl(struct cxl *adapter) | |
451 | { | |
452 | cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT, | |
453 | TBSYNC_ENA | | |
454 | TBSYNC_CAL(3) | | |
455 | TBSYNC_CNT(XSL_4000_CLOCKS)); | |
456 | } | |
457 | ||
458 | static u64 timebase_read_psl(struct cxl *adapter) | |
459 | { | |
460 | return cxl_p1_read(adapter, CXL_PSL_Timebase); | |
461 | } | |
462 | ||
463 | static u64 timebase_read_xsl(struct cxl *adapter) | |
464 | { | |
465 | return cxl_p1_read(adapter, CXL_XSL_Timebase); | |
466 | } | |
390fd592 | 467 | |
e009a7e8 | 468 | static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev) |
390fd592 PB |
469 | { |
470 | u64 psl_tb; | |
471 | int delta; | |
472 | unsigned int retry = 0; | |
473 | struct device_node *np; | |
474 | ||
e009a7e8 FB |
475 | adapter->psl_timebase_synced = false; |
476 | ||
390fd592 | 477 | if (!(np = pnv_pci_get_phb_node(dev))) |
e009a7e8 | 478 | return; |
390fd592 PB |
479 | |
480 | /* Do not fail when CAPP timebase sync is not supported by OPAL */ | |
481 | of_node_get(np); | |
482 | if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) { | |
483 | of_node_put(np); | |
e009a7e8 FB |
484 | dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n"); |
485 | return; | |
390fd592 PB |
486 | } |
487 | of_node_put(np); | |
488 | ||
489 | /* | |
490 | * Setup PSL Timebase Control and Status register | |
491 | * with the recommended Timebase Sync Count value | |
492 | */ | |
6d382616 | 493 | adapter->native->sl_ops->write_timebase_ctrl(adapter); |
390fd592 PB |
494 | |
495 | /* Enable PSL Timebase */ | |
496 | cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000); | |
497 | cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb); | |
498 | ||
499 | /* Wait until CORE TB and PSL TB difference <= 16usecs */ | |
500 | do { | |
501 | msleep(1); | |
502 | if (retry++ > 5) { | |
e009a7e8 FB |
503 | dev_info(&dev->dev, "PSL timebase can't synchronize\n"); |
504 | return; | |
390fd592 | 505 | } |
6d382616 | 506 | psl_tb = adapter->native->sl_ops->timebase_read(adapter); |
390fd592 PB |
507 | delta = mftb() - psl_tb; |
508 | if (delta < 0) | |
509 | delta = -delta; | |
923adb16 | 510 | } while (tb_to_ns(delta) > 16000); |
390fd592 | 511 | |
e009a7e8 FB |
512 | adapter->psl_timebase_synced = true; |
513 | return; | |
390fd592 PB |
514 | } |
515 | ||
6d382616 | 516 | static int init_implementation_afu_psl_regs(struct cxl_afu *afu) |
f204e0b8 IM |
517 | { |
518 | /* read/write masks for this slice */ | |
519 | cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); | |
520 | /* APC read/write masks for this slice */ | |
521 | cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); | |
522 | /* for debugging with trace arrays */ | |
523 | cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); | |
d6a6af2c | 524 | cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S); |
f204e0b8 IM |
525 | |
526 | return 0; | |
527 | } | |
528 | ||
2b04cf31 FB |
529 | int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, |
530 | unsigned int virq) | |
f204e0b8 IM |
531 | { |
532 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
533 | ||
534 | return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); | |
535 | } | |
536 | ||
4beb5421 RG |
537 | int cxl_update_image_control(struct cxl *adapter) |
538 | { | |
539 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
540 | int rc; | |
541 | int vsec; | |
542 | u8 image_state; | |
543 | ||
544 | if (!(vsec = find_cxl_vsec(dev))) { | |
545 | dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); | |
546 | return -ENODEV; | |
547 | } | |
548 | ||
549 | if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { | |
550 | dev_err(&dev->dev, "failed to read image state: %i\n", rc); | |
551 | return rc; | |
552 | } | |
553 | ||
554 | if (adapter->perst_loads_image) | |
555 | image_state |= CXL_VSEC_PERST_LOADS_IMAGE; | |
556 | else | |
557 | image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE; | |
558 | ||
559 | if (adapter->perst_select_user) | |
560 | image_state |= CXL_VSEC_PERST_SELECT_USER; | |
561 | else | |
562 | image_state &= ~CXL_VSEC_PERST_SELECT_USER; | |
563 | ||
564 | if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { | |
565 | dev_err(&dev->dev, "failed to update image control: %i\n", rc); | |
566 | return rc; | |
567 | } | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
2b04cf31 | 572 | int cxl_pci_alloc_one_irq(struct cxl *adapter) |
f204e0b8 IM |
573 | { |
574 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
575 | ||
576 | return pnv_cxl_alloc_hwirqs(dev, 1); | |
577 | } | |
578 | ||
2b04cf31 | 579 | void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq) |
f204e0b8 IM |
580 | { |
581 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
582 | ||
583 | return pnv_cxl_release_hwirqs(dev, hwirq, 1); | |
584 | } | |
585 | ||
2b04cf31 FB |
586 | int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, |
587 | struct cxl *adapter, unsigned int num) | |
f204e0b8 IM |
588 | { |
589 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
590 | ||
591 | return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); | |
592 | } | |
593 | ||
2b04cf31 FB |
594 | void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, |
595 | struct cxl *adapter) | |
f204e0b8 IM |
596 | { |
597 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
598 | ||
599 | pnv_cxl_release_hwirq_ranges(irqs, dev); | |
600 | } | |
601 | ||
602 | static int setup_cxl_bars(struct pci_dev *dev) | |
603 | { | |
604 | /* Safety check in case we get backported to < 3.17 without M64 */ | |
605 | if ((p1_base(dev) < 0x100000000ULL) || | |
606 | (p2_base(dev) < 0x100000000ULL)) { | |
607 | dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); | |
608 | return -ENODEV; | |
609 | } | |
610 | ||
611 | /* | |
612 | * BAR 4/5 has a special meaning for CXL and must be programmed with a | |
613 | * special value corresponding to the CXL protocol address range. | |
614 | * For POWER 8 that means bits 48:49 must be set to 10 | |
615 | */ | |
616 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); | |
617 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
b0b5e591 AD |
622 | #ifdef CONFIG_CXL_BIMODAL |
623 | ||
624 | struct cxl_switch_work { | |
625 | struct pci_dev *dev; | |
626 | struct work_struct work; | |
f204e0b8 | 627 | int vsec; |
b0b5e591 AD |
628 | int mode; |
629 | }; | |
630 | ||
631 | static void switch_card_to_cxl(struct work_struct *work) | |
632 | { | |
633 | struct cxl_switch_work *switch_work = | |
634 | container_of(work, struct cxl_switch_work, work); | |
635 | struct pci_dev *dev = switch_work->dev; | |
636 | struct pci_bus *bus = dev->bus; | |
637 | struct pci_controller *hose = pci_bus_to_host(bus); | |
638 | struct pci_dev *bridge; | |
639 | struct pnv_php_slot *php_slot; | |
640 | unsigned int devfn; | |
f204e0b8 IM |
641 | u8 val; |
642 | int rc; | |
643 | ||
b0b5e591 AD |
644 | dev_info(&bus->dev, "cxl: Preparing for mode switch...\n"); |
645 | bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev, | |
646 | bus_list); | |
647 | if (!bridge) { | |
648 | dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n"); | |
649 | goto err_dev_put; | |
650 | } | |
f204e0b8 | 651 | |
b0b5e591 AD |
652 | php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge)); |
653 | if (!php_slot) { | |
654 | dev_err(&bus->dev, "cxl: Failed to find slot hotplug " | |
655 | "information. You may need to upgrade " | |
656 | "skiboot. Aborting.\n"); | |
657 | goto err_dev_put; | |
658 | } | |
659 | ||
660 | rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val); | |
661 | if (rc) { | |
662 | dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc); | |
663 | goto err_dev_put; | |
664 | } | |
665 | devfn = dev->devfn; | |
666 | ||
667 | /* Release the reference obtained in cxl_check_and_switch_mode() */ | |
668 | pci_dev_put(dev); | |
669 | ||
670 | dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n"); | |
671 | pci_lock_rescan_remove(); | |
672 | pci_hp_remove_devices(bridge->subordinate); | |
673 | pci_unlock_rescan_remove(); | |
674 | ||
675 | /* Switch the CXL protocol on the card */ | |
676 | if (switch_work->mode == CXL_BIMODE_CXL) { | |
677 | dev_info(&bus->dev, "cxl: Switching card to CXL mode\n"); | |
678 | val &= ~CXL_VSEC_PROTOCOL_MASK; | |
679 | val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; | |
680 | rc = pnv_cxl_enable_phb_kernel_api(hose, true); | |
681 | if (rc) { | |
682 | dev_err(&bus->dev, "cxl: Failed to enable kernel API" | |
683 | " on real PHB, aborting\n"); | |
684 | goto err_free_work; | |
685 | } | |
686 | } else { | |
687 | dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n"); | |
688 | goto err_free_work; | |
689 | } | |
690 | ||
691 | rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val); | |
692 | if (rc) { | |
693 | dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc); | |
694 | goto err_free_work; | |
695 | } | |
696 | ||
697 | /* | |
698 | * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states | |
699 | * we must wait 100ms after this mode switch before touching PCIe config | |
700 | * space. | |
701 | */ | |
702 | msleep(100); | |
703 | ||
704 | /* | |
705 | * Hot reset to cause the card to come back in cxl mode. A | |
706 | * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support | |
707 | * in skiboot, so we use a hot reset instead. | |
708 | * | |
709 | * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is | |
710 | * guaranteed to sit directly under the root port, and setting the reset | |
711 | * state on a device directly under the root port is equivalent to doing | |
712 | * it on the root port iself. | |
713 | */ | |
714 | dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n"); | |
715 | pci_set_pcie_reset_state(bridge, pcie_hot_reset); | |
716 | pci_set_pcie_reset_state(bridge, pcie_deassert_reset); | |
717 | ||
718 | dev_dbg(&bus->dev, "cxl: Offlining slot\n"); | |
719 | rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE); | |
720 | if (rc) { | |
721 | dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc); | |
722 | goto err_free_work; | |
723 | } | |
724 | ||
725 | dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n"); | |
726 | rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE); | |
727 | if (rc) { | |
728 | dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc); | |
729 | goto err_free_work; | |
730 | } | |
731 | ||
732 | pci_lock_rescan_remove(); | |
733 | pci_hp_add_devices(bridge->subordinate); | |
734 | pci_unlock_rescan_remove(); | |
735 | ||
736 | dev_info(&bus->dev, "cxl: CAPI mode switch completed\n"); | |
737 | kfree(switch_work); | |
738 | return; | |
739 | ||
740 | err_dev_put: | |
741 | /* Release the reference obtained in cxl_check_and_switch_mode() */ | |
742 | pci_dev_put(dev); | |
743 | err_free_work: | |
744 | kfree(switch_work); | |
745 | } | |
746 | ||
747 | int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec) | |
748 | { | |
749 | struct cxl_switch_work *work; | |
750 | u8 val; | |
751 | int rc; | |
752 | ||
753 | if (!cpu_has_feature(CPU_FTR_HVMODE)) | |
f204e0b8 | 754 | return -ENODEV; |
b0b5e591 AD |
755 | |
756 | if (!vsec) { | |
757 | vsec = find_cxl_vsec(dev); | |
758 | if (!vsec) { | |
759 | dev_info(&dev->dev, "CXL VSEC not found\n"); | |
760 | return -ENODEV; | |
761 | } | |
f204e0b8 IM |
762 | } |
763 | ||
b0b5e591 AD |
764 | rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val); |
765 | if (rc) { | |
766 | dev_err(&dev->dev, "Failed to read current mode control: %i", rc); | |
f204e0b8 IM |
767 | return rc; |
768 | } | |
b0b5e591 AD |
769 | |
770 | if (mode == CXL_BIMODE_PCI) { | |
771 | if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) { | |
772 | dev_info(&dev->dev, "Card is already in PCI mode\n"); | |
773 | return 0; | |
774 | } | |
775 | /* | |
776 | * TODO: Before it's safe to switch the card back to PCI mode | |
777 | * we need to disable the CAPP and make sure any cachelines the | |
778 | * card holds have been flushed out. Needs skiboot support. | |
779 | */ | |
780 | dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n"); | |
781 | return -EIO; | |
f204e0b8 | 782 | } |
b0b5e591 AD |
783 | |
784 | if (val & CXL_VSEC_PROTOCOL_ENABLE) { | |
785 | dev_info(&dev->dev, "Card is already in CXL mode\n"); | |
786 | return 0; | |
787 | } | |
788 | ||
789 | dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread " | |
790 | "to switch to CXL mode\n"); | |
791 | ||
792 | work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL); | |
793 | if (!work) | |
794 | return -ENOMEM; | |
795 | ||
796 | pci_dev_get(dev); | |
797 | work->dev = dev; | |
798 | work->vsec = vsec; | |
799 | work->mode = mode; | |
800 | INIT_WORK(&work->work, switch_card_to_cxl); | |
801 | ||
802 | schedule_work(&work->work); | |
803 | ||
f204e0b8 | 804 | /* |
b0b5e591 AD |
805 | * We return a failure now to abort the driver init. Once the |
806 | * link has been cycled and the card is in cxl mode we will | |
807 | * come back (possibly using the generic cxl driver), but | |
808 | * return success as the card should then be in cxl mode. | |
809 | * | |
810 | * TODO: What if the card comes back in PCI mode even after | |
811 | * the switch? Don't want to spin endlessly. | |
f204e0b8 | 812 | */ |
b0b5e591 AD |
813 | return -EBUSY; |
814 | } | |
815 | EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode); | |
816 | ||
817 | #endif /* CONFIG_CXL_BIMODAL */ | |
818 | ||
819 | static int setup_cxl_protocol_area(struct pci_dev *dev) | |
820 | { | |
821 | u8 val; | |
822 | int rc; | |
823 | int vsec = find_cxl_vsec(dev); | |
824 | ||
825 | if (!vsec) { | |
826 | dev_info(&dev->dev, "CXL VSEC not found\n"); | |
827 | return -ENODEV; | |
828 | } | |
829 | ||
830 | rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val); | |
831 | if (rc) { | |
832 | dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc); | |
833 | return rc; | |
834 | } | |
835 | ||
836 | if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) { | |
837 | dev_err(&dev->dev, "Card not in CAPI mode!\n"); | |
838 | return -EIO; | |
839 | } | |
840 | ||
841 | if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) { | |
842 | val &= ~CXL_VSEC_PROTOCOL_MASK; | |
843 | val |= CXL_VSEC_PROTOCOL_256TB; | |
844 | rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val); | |
845 | if (rc) { | |
846 | dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc); | |
847 | return rc; | |
848 | } | |
849 | } | |
f204e0b8 IM |
850 | |
851 | return 0; | |
852 | } | |
853 | ||
2b04cf31 | 854 | static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) |
f204e0b8 IM |
855 | { |
856 | u64 p1n_base, p2n_base, afu_desc; | |
857 | const u64 p1n_size = 0x100; | |
858 | const u64 p2n_size = 0x1000; | |
859 | ||
860 | p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); | |
861 | p2n_base = p2_base(dev) + (afu->slice * p2n_size); | |
cbffa3a5 CL |
862 | afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); |
863 | afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size); | |
f204e0b8 | 864 | |
cbffa3a5 | 865 | if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size))) |
f204e0b8 IM |
866 | goto err; |
867 | if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) | |
868 | goto err1; | |
869 | if (afu_desc) { | |
cbffa3a5 | 870 | if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size))) |
f204e0b8 IM |
871 | goto err2; |
872 | } | |
873 | ||
874 | return 0; | |
875 | err2: | |
876 | iounmap(afu->p2n_mmio); | |
877 | err1: | |
cbffa3a5 | 878 | iounmap(afu->native->p1n_mmio); |
f204e0b8 IM |
879 | err: |
880 | dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); | |
881 | return -ENOMEM; | |
882 | } | |
883 | ||
2b04cf31 | 884 | static void pci_unmap_slice_regs(struct cxl_afu *afu) |
f204e0b8 | 885 | { |
575e6986 | 886 | if (afu->p2n_mmio) { |
f204e0b8 | 887 | iounmap(afu->p2n_mmio); |
575e6986 DA |
888 | afu->p2n_mmio = NULL; |
889 | } | |
cbffa3a5 CL |
890 | if (afu->native->p1n_mmio) { |
891 | iounmap(afu->native->p1n_mmio); | |
892 | afu->native->p1n_mmio = NULL; | |
575e6986 | 893 | } |
cbffa3a5 CL |
894 | if (afu->native->afu_desc_mmio) { |
895 | iounmap(afu->native->afu_desc_mmio); | |
896 | afu->native->afu_desc_mmio = NULL; | |
575e6986 | 897 | } |
f204e0b8 IM |
898 | } |
899 | ||
2b04cf31 | 900 | void cxl_pci_release_afu(struct device *dev) |
f204e0b8 IM |
901 | { |
902 | struct cxl_afu *afu = to_cxl_afu(dev); | |
903 | ||
2b04cf31 | 904 | pr_devel("%s\n", __func__); |
f204e0b8 | 905 | |
bd664f89 | 906 | idr_destroy(&afu->contexts_idr); |
05155772 DA |
907 | cxl_release_spa(afu); |
908 | ||
cbffa3a5 | 909 | kfree(afu->native); |
f204e0b8 IM |
910 | kfree(afu); |
911 | } | |
912 | ||
f204e0b8 IM |
913 | /* Expects AFU struct to have recently been zeroed out */ |
914 | static int cxl_read_afu_descriptor(struct cxl_afu *afu) | |
915 | { | |
916 | u64 val; | |
917 | ||
918 | val = AFUD_READ_INFO(afu); | |
919 | afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); | |
920 | afu->max_procs_virtualised = AFUD_NUM_PROCS(val); | |
b087e619 | 921 | afu->crs_num = AFUD_NUM_CRS(val); |
f204e0b8 IM |
922 | |
923 | if (AFUD_AFU_DIRECTED(val)) | |
924 | afu->modes_supported |= CXL_MODE_DIRECTED; | |
925 | if (AFUD_DEDICATED_PROCESS(val)) | |
926 | afu->modes_supported |= CXL_MODE_DEDICATED; | |
927 | if (AFUD_TIME_SLICED(val)) | |
928 | afu->modes_supported |= CXL_MODE_TIME_SLICED; | |
929 | ||
930 | val = AFUD_READ_PPPSA(afu); | |
931 | afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; | |
932 | afu->psa = AFUD_PPPSA_PSA(val); | |
933 | if ((afu->pp_psa = AFUD_PPPSA_PP(val))) | |
cbffa3a5 | 934 | afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); |
f204e0b8 | 935 | |
b087e619 IM |
936 | val = AFUD_READ_CR(afu); |
937 | afu->crs_len = AFUD_CR_LEN(val) * 256; | |
938 | afu->crs_offset = AFUD_READ_CR_OFF(afu); | |
939 | ||
e36f6fe1 VJ |
940 | |
941 | /* eb_len is in multiple of 4K */ | |
942 | afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; | |
943 | afu->eb_offset = AFUD_READ_EB_OFF(afu); | |
944 | ||
945 | /* eb_off is 4K aligned so lower 12 bits are always zero */ | |
946 | if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { | |
947 | dev_warn(&afu->dev, | |
948 | "Invalid AFU error buffer offset %Lx\n", | |
949 | afu->eb_offset); | |
950 | dev_info(&afu->dev, | |
951 | "Ignoring AFU error buffer in the descriptor\n"); | |
952 | /* indicate that no afu buffer exists */ | |
953 | afu->eb_len = 0; | |
954 | } | |
955 | ||
f204e0b8 IM |
956 | return 0; |
957 | } | |
958 | ||
959 | static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) | |
960 | { | |
5be587b1 FB |
961 | int i, rc; |
962 | u32 val; | |
3d5be039 | 963 | |
f204e0b8 | 964 | if (afu->psa && afu->adapter->ps_size < |
cbffa3a5 | 965 | (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { |
f204e0b8 IM |
966 | dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); |
967 | return -ENODEV; | |
968 | } | |
969 | ||
970 | if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) | |
971 | dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!"); | |
972 | ||
3d5be039 | 973 | for (i = 0; i < afu->crs_num; i++) { |
5be587b1 FB |
974 | rc = cxl_ops->afu_cr_read32(afu, i, 0, &val); |
975 | if (rc || val == 0) { | |
3d5be039 IM |
976 | dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); |
977 | return -EINVAL; | |
978 | } | |
979 | } | |
49e9c99f IM |
980 | |
981 | if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) { | |
982 | /* | |
983 | * We could also check this for the dedicated process model | |
984 | * since the architecture indicates it should be set to 1, but | |
985 | * in that case we ignore the value and I'd rather not risk | |
986 | * breaking any existing dedicated process AFUs that left it as | |
987 | * 0 (not that I'm aware of any). It is clearly an error for an | |
988 | * AFU directed AFU to set this to 0, and would have previously | |
989 | * triggered a bug resulting in the maximum not being enforced | |
990 | * at all since idr_alloc treats 0 as no maximum. | |
991 | */ | |
992 | dev_err(&afu->dev, "AFU does not support any processes\n"); | |
993 | return -EINVAL; | |
994 | } | |
3d5be039 | 995 | |
f204e0b8 IM |
996 | return 0; |
997 | } | |
998 | ||
999 | static int sanitise_afu_regs(struct cxl_afu *afu) | |
1000 | { | |
1001 | u64 reg; | |
1002 | ||
1003 | /* | |
1004 | * Clear out any regs that contain either an IVTE or address or may be | |
1005 | * waiting on an acknowledgement to try to be a bit safer as we bring | |
1006 | * it online | |
1007 | */ | |
1008 | reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
1009 | if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { | |
de369538 | 1010 | dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); |
5be587b1 | 1011 | if (cxl_ops->afu_reset(afu)) |
f204e0b8 IM |
1012 | return -EIO; |
1013 | if (cxl_afu_disable(afu)) | |
1014 | return -EIO; | |
1015 | if (cxl_psl_purge(afu)) | |
1016 | return -EIO; | |
1017 | } | |
1018 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); | |
1019 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); | |
1020 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); | |
1021 | cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); | |
1022 | cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); | |
1023 | cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); | |
1024 | cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); | |
1025 | cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); | |
1026 | cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); | |
1027 | cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); | |
1028 | cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); | |
1029 | reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1030 | if (reg) { | |
de369538 | 1031 | dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); |
f204e0b8 IM |
1032 | if (reg & CXL_PSL_DSISR_TRANS) |
1033 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
1034 | else | |
1035 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
1036 | } | |
6d382616 FB |
1037 | if (afu->adapter->native->sl_ops->register_serr_irq) { |
1038 | reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
1039 | if (reg) { | |
1040 | if (reg & ~0xffff) | |
1041 | dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); | |
1042 | cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); | |
1043 | } | |
f204e0b8 IM |
1044 | } |
1045 | reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
1046 | if (reg) { | |
de369538 | 1047 | dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); |
f204e0b8 IM |
1048 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); |
1049 | } | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
e36f6fe1 VJ |
1054 | #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE |
1055 | /* | |
1056 | * afu_eb_read: | |
1057 | * Called from sysfs and reads the afu error info buffer. The h/w only supports | |
1058 | * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte | |
1059 | * aligned the function uses a bounce buffer which can be max PAGE_SIZE. | |
1060 | */ | |
2b04cf31 | 1061 | ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, |
e36f6fe1 VJ |
1062 | loff_t off, size_t count) |
1063 | { | |
1064 | loff_t aligned_start, aligned_end; | |
1065 | size_t aligned_length; | |
1066 | void *tbuf; | |
cbffa3a5 | 1067 | const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset; |
e36f6fe1 VJ |
1068 | |
1069 | if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) | |
1070 | return 0; | |
1071 | ||
1072 | /* calculate aligned read window */ | |
1073 | count = min((size_t)(afu->eb_len - off), count); | |
1074 | aligned_start = round_down(off, 8); | |
1075 | aligned_end = round_up(off + count, 8); | |
1076 | aligned_length = aligned_end - aligned_start; | |
1077 | ||
1078 | /* max we can copy in one read is PAGE_SIZE */ | |
1079 | if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) { | |
1080 | aligned_length = ERR_BUFF_MAX_COPY_SIZE; | |
1081 | count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); | |
1082 | } | |
1083 | ||
1084 | /* use bounce buffer for copy */ | |
1085 | tbuf = (void *)__get_free_page(GFP_TEMPORARY); | |
1086 | if (!tbuf) | |
1087 | return -ENOMEM; | |
1088 | ||
1089 | /* perform aligned read from the mmio region */ | |
1090 | memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length); | |
1091 | memcpy(buf, tbuf + (off & 0x7), count); | |
1092 | ||
1093 | free_page((unsigned long)tbuf); | |
1094 | ||
1095 | return count; | |
1096 | } | |
1097 | ||
2b04cf31 | 1098 | static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) |
f204e0b8 | 1099 | { |
f204e0b8 IM |
1100 | int rc; |
1101 | ||
2b04cf31 | 1102 | if ((rc = pci_map_slice_regs(afu, adapter, dev))) |
d76427b0 | 1103 | return rc; |
f204e0b8 IM |
1104 | |
1105 | if ((rc = sanitise_afu_regs(afu))) | |
d76427b0 | 1106 | goto err1; |
f204e0b8 IM |
1107 | |
1108 | /* We need to reset the AFU before we can read the AFU descriptor */ | |
5be587b1 | 1109 | if ((rc = cxl_ops->afu_reset(afu))) |
d76427b0 | 1110 | goto err1; |
f204e0b8 IM |
1111 | |
1112 | if (cxl_verbose) | |
1113 | dump_afu_descriptor(afu); | |
1114 | ||
1115 | if ((rc = cxl_read_afu_descriptor(afu))) | |
d76427b0 | 1116 | goto err1; |
f204e0b8 IM |
1117 | |
1118 | if ((rc = cxl_afu_descriptor_looks_ok(afu))) | |
d76427b0 | 1119 | goto err1; |
f204e0b8 | 1120 | |
6d382616 FB |
1121 | if (adapter->native->sl_ops->afu_regs_init) |
1122 | if ((rc = adapter->native->sl_ops->afu_regs_init(afu))) | |
1123 | goto err1; | |
f204e0b8 | 1124 | |
6d382616 FB |
1125 | if (adapter->native->sl_ops->register_serr_irq) |
1126 | if ((rc = adapter->native->sl_ops->register_serr_irq(afu))) | |
1127 | goto err1; | |
f204e0b8 | 1128 | |
2b04cf31 | 1129 | if ((rc = cxl_native_register_psl_irq(afu))) |
d76427b0 DA |
1130 | goto err2; |
1131 | ||
1132 | return 0; | |
1133 | ||
1134 | err2: | |
6d382616 FB |
1135 | if (adapter->native->sl_ops->release_serr_irq) |
1136 | adapter->native->sl_ops->release_serr_irq(afu); | |
d76427b0 | 1137 | err1: |
2b04cf31 | 1138 | pci_unmap_slice_regs(afu); |
d76427b0 DA |
1139 | return rc; |
1140 | } | |
1141 | ||
2b04cf31 | 1142 | static void pci_deconfigure_afu(struct cxl_afu *afu) |
d76427b0 | 1143 | { |
2b04cf31 | 1144 | cxl_native_release_psl_irq(afu); |
6d382616 FB |
1145 | if (afu->adapter->native->sl_ops->release_serr_irq) |
1146 | afu->adapter->native->sl_ops->release_serr_irq(afu); | |
2b04cf31 | 1147 | pci_unmap_slice_regs(afu); |
d76427b0 DA |
1148 | } |
1149 | ||
2b04cf31 | 1150 | static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) |
d76427b0 DA |
1151 | { |
1152 | struct cxl_afu *afu; | |
cbffa3a5 | 1153 | int rc = -ENOMEM; |
d76427b0 DA |
1154 | |
1155 | afu = cxl_alloc_afu(adapter, slice); | |
1156 | if (!afu) | |
1157 | return -ENOMEM; | |
1158 | ||
cbffa3a5 CL |
1159 | afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL); |
1160 | if (!afu->native) | |
1161 | goto err_free_afu; | |
1162 | ||
1163 | mutex_init(&afu->native->spa_mutex); | |
1164 | ||
d76427b0 DA |
1165 | rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); |
1166 | if (rc) | |
cbffa3a5 | 1167 | goto err_free_native; |
d76427b0 | 1168 | |
2b04cf31 | 1169 | rc = pci_configure_afu(afu, adapter, dev); |
d76427b0 | 1170 | if (rc) |
cbffa3a5 | 1171 | goto err_free_native; |
f204e0b8 IM |
1172 | |
1173 | /* Don't care if this fails */ | |
1174 | cxl_debugfs_afu_add(afu); | |
1175 | ||
1176 | /* | |
1177 | * After we call this function we must not free the afu directly, even | |
1178 | * if it returns an error! | |
1179 | */ | |
1180 | if ((rc = cxl_register_afu(afu))) | |
1181 | goto err_put1; | |
1182 | ||
1183 | if ((rc = cxl_sysfs_afu_add(afu))) | |
1184 | goto err_put1; | |
1185 | ||
f204e0b8 IM |
1186 | adapter->afu[afu->slice] = afu; |
1187 | ||
6f7f0b3d MN |
1188 | if ((rc = cxl_pci_vphb_add(afu))) |
1189 | dev_info(&afu->dev, "Can't register vPHB\n"); | |
1190 | ||
f204e0b8 IM |
1191 | return 0; |
1192 | ||
f204e0b8 | 1193 | err_put1: |
2b04cf31 | 1194 | pci_deconfigure_afu(afu); |
f204e0b8 | 1195 | cxl_debugfs_afu_remove(afu); |
d76427b0 | 1196 | device_unregister(&afu->dev); |
f204e0b8 | 1197 | return rc; |
d76427b0 | 1198 | |
cbffa3a5 CL |
1199 | err_free_native: |
1200 | kfree(afu->native); | |
1201 | err_free_afu: | |
d76427b0 DA |
1202 | kfree(afu); |
1203 | return rc; | |
1204 | ||
f204e0b8 IM |
1205 | } |
1206 | ||
2b04cf31 | 1207 | static void cxl_pci_remove_afu(struct cxl_afu *afu) |
f204e0b8 | 1208 | { |
2b04cf31 | 1209 | pr_devel("%s\n", __func__); |
f204e0b8 IM |
1210 | |
1211 | if (!afu) | |
1212 | return; | |
1213 | ||
d601ea91 | 1214 | cxl_pci_vphb_remove(afu); |
f204e0b8 IM |
1215 | cxl_sysfs_afu_remove(afu); |
1216 | cxl_debugfs_afu_remove(afu); | |
1217 | ||
1218 | spin_lock(&afu->adapter->afu_list_lock); | |
1219 | afu->adapter->afu[afu->slice] = NULL; | |
1220 | spin_unlock(&afu->adapter->afu_list_lock); | |
1221 | ||
1222 | cxl_context_detach_all(afu); | |
5be587b1 | 1223 | cxl_ops->afu_deactivate_mode(afu, afu->current_mode); |
f204e0b8 | 1224 | |
2b04cf31 | 1225 | pci_deconfigure_afu(afu); |
f204e0b8 IM |
1226 | device_unregister(&afu->dev); |
1227 | } | |
1228 | ||
2b04cf31 | 1229 | int cxl_pci_reset(struct cxl *adapter) |
62fa19d4 RG |
1230 | { |
1231 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
1232 | int rc; | |
62fa19d4 | 1233 | |
13e68d8b DA |
1234 | if (adapter->perst_same_image) { |
1235 | dev_warn(&dev->dev, | |
1236 | "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n"); | |
1237 | return -EINVAL; | |
1238 | } | |
1239 | ||
62fa19d4 RG |
1240 | dev_info(&dev->dev, "CXL reset\n"); |
1241 | ||
62fa19d4 RG |
1242 | /* pcie_warm_reset requests a fundamental pci reset which includes a |
1243 | * PERST assert/deassert. PERST triggers a loading of the image | |
1244 | * if "user" or "factory" is selected in sysfs */ | |
1245 | if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { | |
1246 | dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); | |
1247 | return rc; | |
1248 | } | |
1249 | ||
62fa19d4 RG |
1250 | return rc; |
1251 | } | |
f204e0b8 IM |
1252 | |
1253 | static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) | |
1254 | { | |
1255 | if (pci_request_region(dev, 2, "priv 2 regs")) | |
1256 | goto err1; | |
1257 | if (pci_request_region(dev, 0, "priv 1 regs")) | |
1258 | goto err2; | |
1259 | ||
de369538 | 1260 | pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx", |
f204e0b8 IM |
1261 | p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); |
1262 | ||
cbffa3a5 | 1263 | if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) |
f204e0b8 IM |
1264 | goto err3; |
1265 | ||
cbffa3a5 | 1266 | if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) |
f204e0b8 IM |
1267 | goto err4; |
1268 | ||
1269 | return 0; | |
1270 | ||
1271 | err4: | |
cbffa3a5 CL |
1272 | iounmap(adapter->native->p1_mmio); |
1273 | adapter->native->p1_mmio = NULL; | |
f204e0b8 IM |
1274 | err3: |
1275 | pci_release_region(dev, 0); | |
1276 | err2: | |
1277 | pci_release_region(dev, 2); | |
1278 | err1: | |
1279 | return -ENOMEM; | |
1280 | } | |
1281 | ||
1282 | static void cxl_unmap_adapter_regs(struct cxl *adapter) | |
1283 | { | |
cbffa3a5 CL |
1284 | if (adapter->native->p1_mmio) { |
1285 | iounmap(adapter->native->p1_mmio); | |
1286 | adapter->native->p1_mmio = NULL; | |
575e6986 DA |
1287 | pci_release_region(to_pci_dev(adapter->dev.parent), 2); |
1288 | } | |
cbffa3a5 CL |
1289 | if (adapter->native->p2_mmio) { |
1290 | iounmap(adapter->native->p2_mmio); | |
1291 | adapter->native->p2_mmio = NULL; | |
575e6986 DA |
1292 | pci_release_region(to_pci_dev(adapter->dev.parent), 0); |
1293 | } | |
f204e0b8 IM |
1294 | } |
1295 | ||
1296 | static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) | |
1297 | { | |
1298 | int vsec; | |
1299 | u32 afu_desc_off, afu_desc_size; | |
1300 | u32 ps_off, ps_size; | |
1301 | u16 vseclen; | |
1302 | u8 image_state; | |
1303 | ||
1304 | if (!(vsec = find_cxl_vsec(dev))) { | |
bee30c70 | 1305 | dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); |
f204e0b8 IM |
1306 | return -ENODEV; |
1307 | } | |
1308 | ||
1309 | CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); | |
1310 | if (vseclen < CXL_VSEC_MIN_SIZE) { | |
bee30c70 | 1311 | dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); |
f204e0b8 IM |
1312 | return -EINVAL; |
1313 | } | |
1314 | ||
1315 | CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); | |
1316 | CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); | |
1317 | CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); | |
1318 | CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); | |
1319 | CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); | |
1320 | CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); | |
1321 | adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); | |
4beb5421 | 1322 | adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); |
f204e0b8 IM |
1323 | |
1324 | CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); | |
1325 | CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); | |
1326 | CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); | |
1327 | CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); | |
1328 | CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); | |
1329 | ||
1330 | /* Convert everything to bytes, because there is NO WAY I'd look at the | |
1331 | * code a month later and forget what units these are in ;-) */ | |
cbffa3a5 | 1332 | adapter->native->ps_off = ps_off * 64 * 1024; |
f204e0b8 | 1333 | adapter->ps_size = ps_size * 64 * 1024; |
cbffa3a5 CL |
1334 | adapter->native->afu_desc_off = afu_desc_off * 64 * 1024; |
1335 | adapter->native->afu_desc_size = afu_desc_size * 64 * 1024; | |
f204e0b8 IM |
1336 | |
1337 | /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ | |
1338 | adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
d79e6801 PB |
1343 | /* |
1344 | * Workaround a PCIe Host Bridge defect on some cards, that can cause | |
1345 | * malformed Transaction Layer Packet (TLP) errors to be erroneously | |
1346 | * reported. Mask this error in the Uncorrectable Error Mask Register. | |
1347 | * | |
1348 | * The upper nibble of the PSL revision is used to distinguish between | |
1349 | * different cards. The affected ones have it set to 0. | |
1350 | */ | |
1351 | static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev) | |
1352 | { | |
1353 | int aer; | |
1354 | u32 data; | |
1355 | ||
1356 | if (adapter->psl_rev & 0xf000) | |
1357 | return; | |
1358 | if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))) | |
1359 | return; | |
1360 | pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data); | |
1361 | if (data & PCI_ERR_UNC_MALF_TLP) | |
1362 | if (data & PCI_ERR_UNC_INTN) | |
1363 | return; | |
1364 | data |= PCI_ERR_UNC_MALF_TLP; | |
1365 | data |= PCI_ERR_UNC_INTN; | |
1366 | pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data); | |
1367 | } | |
1368 | ||
f204e0b8 IM |
1369 | static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) |
1370 | { | |
1371 | if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) | |
1372 | return -EBUSY; | |
1373 | ||
1374 | if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { | |
bee30c70 | 1375 | dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); |
f204e0b8 IM |
1376 | return -EINVAL; |
1377 | } | |
1378 | ||
1379 | if (!adapter->slices) { | |
1380 | /* Once we support dynamic reprogramming we can use the card if | |
1381 | * it supports loadable AFUs */ | |
bee30c70 | 1382 | dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); |
f204e0b8 IM |
1383 | return -EINVAL; |
1384 | } | |
1385 | ||
cbffa3a5 | 1386 | if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) { |
bee30c70 | 1387 | dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); |
f204e0b8 IM |
1388 | return -EINVAL; |
1389 | } | |
1390 | ||
cbffa3a5 | 1391 | if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) { |
bee30c70 | 1392 | dev_err(&dev->dev, "ABORTING: Problem state size larger than " |
f204e0b8 | 1393 | "available in BAR2: 0x%llx > 0x%llx\n", |
cbffa3a5 | 1394 | adapter->ps_size, p2_size(dev) - adapter->native->ps_off); |
f204e0b8 IM |
1395 | return -EINVAL; |
1396 | } | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
d601ea91 FB |
1401 | ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len) |
1402 | { | |
1403 | return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf); | |
1404 | } | |
1405 | ||
f204e0b8 IM |
1406 | static void cxl_release_adapter(struct device *dev) |
1407 | { | |
1408 | struct cxl *adapter = to_cxl_adapter(dev); | |
1409 | ||
1410 | pr_devel("cxl_release_adapter\n"); | |
1411 | ||
c044c415 DA |
1412 | cxl_remove_adapter_nr(adapter); |
1413 | ||
cbffa3a5 | 1414 | kfree(adapter->native); |
f204e0b8 IM |
1415 | kfree(adapter); |
1416 | } | |
1417 | ||
390fd592 PB |
1418 | #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31)) |
1419 | ||
f204e0b8 IM |
1420 | static int sanitise_adapter_regs(struct cxl *adapter) |
1421 | { | |
390fd592 PB |
1422 | /* Clear PSL tberror bit by writing 1 to it */ |
1423 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror); | |
f204e0b8 IM |
1424 | return cxl_tlb_slb_invalidate(adapter); |
1425 | } | |
1426 | ||
c044c415 DA |
1427 | /* This should contain *only* operations that can safely be done in |
1428 | * both creation and recovery. | |
1429 | */ | |
1430 | static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev) | |
f204e0b8 | 1431 | { |
f204e0b8 IM |
1432 | int rc; |
1433 | ||
c044c415 DA |
1434 | adapter->dev.parent = &dev->dev; |
1435 | adapter->dev.release = cxl_release_adapter; | |
1436 | pci_set_drvdata(dev, adapter); | |
f204e0b8 | 1437 | |
c044c415 DA |
1438 | rc = pci_enable_device(dev); |
1439 | if (rc) { | |
1440 | dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); | |
1441 | return rc; | |
1442 | } | |
f204e0b8 | 1443 | |
bee30c70 | 1444 | if ((rc = cxl_read_vsec(adapter, dev))) |
c044c415 | 1445 | return rc; |
bee30c70 IM |
1446 | |
1447 | if ((rc = cxl_vsec_looks_ok(adapter, dev))) | |
c044c415 | 1448 | return rc; |
bee30c70 | 1449 | |
d79e6801 PB |
1450 | cxl_fixup_malformed_tlp(adapter, dev); |
1451 | ||
bee30c70 | 1452 | if ((rc = setup_cxl_bars(dev))) |
c044c415 | 1453 | return rc; |
bee30c70 | 1454 | |
b0b5e591 | 1455 | if ((rc = setup_cxl_protocol_area(dev))) |
c044c415 | 1456 | return rc; |
f204e0b8 | 1457 | |
4beb5421 | 1458 | if ((rc = cxl_update_image_control(adapter))) |
c044c415 | 1459 | return rc; |
4beb5421 | 1460 | |
f204e0b8 | 1461 | if ((rc = cxl_map_adapter_regs(adapter, dev))) |
c044c415 | 1462 | return rc; |
f204e0b8 IM |
1463 | |
1464 | if ((rc = sanitise_adapter_regs(adapter))) | |
c044c415 | 1465 | goto err; |
f204e0b8 | 1466 | |
6d382616 | 1467 | if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev))) |
c044c415 | 1468 | goto err; |
f204e0b8 | 1469 | |
48b3adf3 IM |
1470 | /* Required for devices using CAPP DMA mode, harmless for others */ |
1471 | pci_set_master(dev); | |
1472 | ||
b385c9e9 | 1473 | if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode))) |
c044c415 | 1474 | goto err; |
f204e0b8 | 1475 | |
1212aa1c RG |
1476 | /* If recovery happened, the last step is to turn on snooping. |
1477 | * In the non-recovery case this has no effect */ | |
c044c415 DA |
1478 | if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) |
1479 | goto err; | |
1212aa1c | 1480 | |
e009a7e8 FB |
1481 | /* Ignore error, adapter init is not dependant on timebase sync */ |
1482 | cxl_setup_psl_timebase(adapter, dev); | |
390fd592 | 1483 | |
2b04cf31 | 1484 | if ((rc = cxl_native_register_psl_err_irq(adapter))) |
c044c415 DA |
1485 | goto err; |
1486 | ||
1487 | return 0; | |
1488 | ||
1489 | err: | |
1490 | cxl_unmap_adapter_regs(adapter); | |
1491 | return rc; | |
1492 | ||
1493 | } | |
1494 | ||
1495 | static void cxl_deconfigure_adapter(struct cxl *adapter) | |
1496 | { | |
1497 | struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); | |
1498 | ||
2b04cf31 | 1499 | cxl_native_release_psl_err_irq(adapter); |
c044c415 DA |
1500 | cxl_unmap_adapter_regs(adapter); |
1501 | ||
1502 | pci_disable_device(pdev); | |
1503 | } | |
1504 | ||
6d382616 FB |
1505 | static const struct cxl_service_layer_ops psl_ops = { |
1506 | .adapter_regs_init = init_implementation_adapter_psl_regs, | |
1507 | .afu_regs_init = init_implementation_afu_psl_regs, | |
1508 | .register_serr_irq = cxl_native_register_serr_irq, | |
1509 | .release_serr_irq = cxl_native_release_serr_irq, | |
1510 | .debugfs_add_adapter_sl_regs = cxl_debugfs_add_adapter_psl_regs, | |
1511 | .debugfs_add_afu_sl_regs = cxl_debugfs_add_afu_psl_regs, | |
1512 | .psl_irq_dump_registers = cxl_native_psl_irq_dump_regs, | |
1513 | .err_irq_dump_registers = cxl_native_err_irq_dump_regs, | |
1514 | .debugfs_stop_trace = cxl_stop_trace, | |
1515 | .write_timebase_ctrl = write_timebase_ctrl_psl, | |
1516 | .timebase_read = timebase_read_psl, | |
b385c9e9 | 1517 | .capi_mode = OPAL_PHB_CAPI_MODE_CAPI, |
5e7823c9 | 1518 | .needs_reset_before_disable = true, |
6d382616 FB |
1519 | }; |
1520 | ||
1521 | static const struct cxl_service_layer_ops xsl_ops = { | |
1522 | .adapter_regs_init = init_implementation_adapter_xsl_regs, | |
1523 | .debugfs_add_adapter_sl_regs = cxl_debugfs_add_adapter_xsl_regs, | |
1524 | .write_timebase_ctrl = write_timebase_ctrl_xsl, | |
1525 | .timebase_read = timebase_read_xsl, | |
b385c9e9 | 1526 | .capi_mode = OPAL_PHB_CAPI_MODE_DMA, |
6d382616 FB |
1527 | }; |
1528 | ||
1529 | static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev) | |
1530 | { | |
1531 | if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) { | |
16479337 | 1532 | /* Mellanox CX-4 */ |
6d382616 FB |
1533 | dev_info(&adapter->dev, "Device uses an XSL\n"); |
1534 | adapter->native->sl_ops = &xsl_ops; | |
16479337 | 1535 | adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */ |
6d382616 FB |
1536 | } else { |
1537 | dev_info(&adapter->dev, "Device uses a PSL\n"); | |
1538 | adapter->native->sl_ops = &psl_ops; | |
1539 | } | |
1540 | } | |
1541 | ||
1542 | ||
2b04cf31 | 1543 | static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev) |
c044c415 DA |
1544 | { |
1545 | struct cxl *adapter; | |
1546 | int rc; | |
1547 | ||
1548 | adapter = cxl_alloc_adapter(); | |
1549 | if (!adapter) | |
1550 | return ERR_PTR(-ENOMEM); | |
1551 | ||
cbffa3a5 CL |
1552 | adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL); |
1553 | if (!adapter->native) { | |
1554 | rc = -ENOMEM; | |
1555 | goto err_release; | |
1556 | } | |
1557 | ||
6d382616 FB |
1558 | set_sl_ops(adapter, dev); |
1559 | ||
c044c415 DA |
1560 | /* Set defaults for parameters which need to persist over |
1561 | * configure/reconfigure | |
1562 | */ | |
1563 | adapter->perst_loads_image = true; | |
13e68d8b | 1564 | adapter->perst_same_image = false; |
c044c415 DA |
1565 | |
1566 | rc = cxl_configure_adapter(adapter, dev); | |
1567 | if (rc) { | |
1568 | pci_disable_device(dev); | |
cbffa3a5 | 1569 | goto err_release; |
c044c415 | 1570 | } |
f204e0b8 IM |
1571 | |
1572 | /* Don't care if this one fails: */ | |
1573 | cxl_debugfs_adapter_add(adapter); | |
1574 | ||
1575 | /* | |
1576 | * After we call this function we must not free the adapter directly, | |
1577 | * even if it returns an error! | |
1578 | */ | |
1579 | if ((rc = cxl_register_adapter(adapter))) | |
1580 | goto err_put1; | |
1581 | ||
1582 | if ((rc = cxl_sysfs_adapter_add(adapter))) | |
1583 | goto err_put1; | |
1584 | ||
1585 | return adapter; | |
1586 | ||
1587 | err_put1: | |
c044c415 DA |
1588 | /* This should mirror cxl_remove_adapter, except without the |
1589 | * sysfs parts | |
1590 | */ | |
f204e0b8 | 1591 | cxl_debugfs_adapter_remove(adapter); |
c044c415 DA |
1592 | cxl_deconfigure_adapter(adapter); |
1593 | device_unregister(&adapter->dev); | |
f204e0b8 | 1594 | return ERR_PTR(rc); |
cbffa3a5 CL |
1595 | |
1596 | err_release: | |
1597 | cxl_release_adapter(&adapter->dev); | |
1598 | return ERR_PTR(rc); | |
f204e0b8 IM |
1599 | } |
1600 | ||
2b04cf31 | 1601 | static void cxl_pci_remove_adapter(struct cxl *adapter) |
f204e0b8 | 1602 | { |
c044c415 | 1603 | pr_devel("cxl_remove_adapter\n"); |
f204e0b8 IM |
1604 | |
1605 | cxl_sysfs_adapter_remove(adapter); | |
1606 | cxl_debugfs_adapter_remove(adapter); | |
f204e0b8 | 1607 | |
c044c415 | 1608 | cxl_deconfigure_adapter(adapter); |
f204e0b8 | 1609 | |
c044c415 | 1610 | device_unregister(&adapter->dev); |
f204e0b8 IM |
1611 | } |
1612 | ||
3b3dcd61 PB |
1613 | #define CXL_MAX_PCIEX_PARENT 2 |
1614 | ||
1615 | static int cxl_slot_is_switched(struct pci_dev *dev) | |
1616 | { | |
1617 | struct device_node *np; | |
1618 | int depth = 0; | |
1619 | const __be32 *prop; | |
1620 | ||
1621 | if (!(np = pci_device_to_OF_node(dev))) { | |
1622 | pr_err("cxl: np = NULL\n"); | |
1623 | return -ENODEV; | |
1624 | } | |
1625 | of_node_get(np); | |
1626 | while (np) { | |
1627 | np = of_get_next_parent(np); | |
1628 | prop = of_get_property(np, "device_type", NULL); | |
1629 | if (!prop || strcmp((char *)prop, "pciex")) | |
1630 | break; | |
1631 | depth++; | |
1632 | } | |
1633 | of_node_put(np); | |
1634 | return (depth > CXL_MAX_PCIEX_PARENT); | |
1635 | } | |
1636 | ||
4e56f858 IM |
1637 | bool cxl_slot_is_supported(struct pci_dev *dev, int flags) |
1638 | { | |
1639 | if (!cpu_has_feature(CPU_FTR_HVMODE)) | |
1640 | return false; | |
1641 | ||
1642 | if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) { | |
1643 | /* | |
1644 | * CAPP DMA mode is technically supported on regular P8, but | |
1645 | * will EEH if the card attempts to access memory < 4GB, which | |
1646 | * we cannot realistically avoid. We might be able to work | |
1647 | * around the issue, but until then return unsupported: | |
1648 | */ | |
1649 | return false; | |
1650 | } | |
1651 | ||
1652 | if (cxl_slot_is_switched(dev)) | |
1653 | return false; | |
1654 | ||
1655 | /* | |
1656 | * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since | |
1657 | * the CAPP can be connected to PHB 0, 1 or 2 on a first come first | |
1658 | * served basis, which is racy to check from here. If we need to | |
1659 | * support this in future we might need to consider having this | |
1660 | * function effectively reserve it ahead of time. | |
1661 | * | |
1662 | * Currently, the only user of this API is the Mellanox CX4, which is | |
1663 | * only supported on P8NVL due to the above mentioned limitation of | |
1664 | * CAPP DMA mode and therefore does not need to worry about this. If the | |
1665 | * issue with CAPP DMA mode is later worked around on P8 we might need | |
1666 | * to revisit this. | |
1667 | */ | |
1668 | ||
1669 | return true; | |
1670 | } | |
1671 | EXPORT_SYMBOL_GPL(cxl_slot_is_supported); | |
1672 | ||
1673 | ||
f204e0b8 IM |
1674 | static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1675 | { | |
1676 | struct cxl *adapter; | |
1677 | int slice; | |
1678 | int rc; | |
1679 | ||
17eb3eef VJ |
1680 | if (cxl_pci_is_vphb_device(dev)) { |
1681 | dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n"); | |
1682 | return -ENODEV; | |
1683 | } | |
1684 | ||
3b3dcd61 PB |
1685 | if (cxl_slot_is_switched(dev)) { |
1686 | dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n"); | |
1687 | return -ENODEV; | |
1688 | } | |
1689 | ||
f204e0b8 IM |
1690 | if (cxl_verbose) |
1691 | dump_cxl_config_space(dev); | |
1692 | ||
2b04cf31 | 1693 | adapter = cxl_pci_init_adapter(dev); |
f204e0b8 IM |
1694 | if (IS_ERR(adapter)) { |
1695 | dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); | |
1696 | return PTR_ERR(adapter); | |
1697 | } | |
1698 | ||
1699 | for (slice = 0; slice < adapter->slices; slice++) { | |
2b04cf31 | 1700 | if ((rc = pci_init_afu(adapter, slice, dev))) { |
f204e0b8 | 1701 | dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); |
d76427b0 DA |
1702 | continue; |
1703 | } | |
1704 | ||
1705 | rc = cxl_afu_select_best_mode(adapter->afu[slice]); | |
1706 | if (rc) | |
1707 | dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); | |
f204e0b8 IM |
1708 | } |
1709 | ||
317f5ef1 IM |
1710 | if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1) |
1711 | pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]); | |
1712 | ||
f204e0b8 IM |
1713 | return 0; |
1714 | } | |
1715 | ||
1716 | static void cxl_remove(struct pci_dev *dev) | |
1717 | { | |
1718 | struct cxl *adapter = pci_get_drvdata(dev); | |
6f7f0b3d MN |
1719 | struct cxl_afu *afu; |
1720 | int i; | |
f204e0b8 | 1721 | |
f204e0b8 IM |
1722 | /* |
1723 | * Lock to prevent someone grabbing a ref through the adapter list as | |
1724 | * we are removing it | |
1725 | */ | |
6f7f0b3d MN |
1726 | for (i = 0; i < adapter->slices; i++) { |
1727 | afu = adapter->afu[i]; | |
2b04cf31 | 1728 | cxl_pci_remove_afu(afu); |
6f7f0b3d | 1729 | } |
2b04cf31 | 1730 | cxl_pci_remove_adapter(adapter); |
f204e0b8 IM |
1731 | } |
1732 | ||
9e8df8a2 DA |
1733 | static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu, |
1734 | pci_channel_state_t state) | |
1735 | { | |
1736 | struct pci_dev *afu_dev; | |
1737 | pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; | |
1738 | pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET; | |
1739 | ||
1740 | /* There should only be one entry, but go through the list | |
1741 | * anyway | |
1742 | */ | |
1743 | list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { | |
1744 | if (!afu_dev->driver) | |
1745 | continue; | |
1746 | ||
1747 | afu_dev->error_state = state; | |
1748 | ||
1749 | if (afu_dev->driver->err_handler) | |
1750 | afu_result = afu_dev->driver->err_handler->error_detected(afu_dev, | |
1751 | state); | |
1752 | /* Disconnect trumps all, NONE trumps NEED_RESET */ | |
1753 | if (afu_result == PCI_ERS_RESULT_DISCONNECT) | |
1754 | result = PCI_ERS_RESULT_DISCONNECT; | |
1755 | else if ((afu_result == PCI_ERS_RESULT_NONE) && | |
1756 | (result == PCI_ERS_RESULT_NEED_RESET)) | |
1757 | result = PCI_ERS_RESULT_NONE; | |
1758 | } | |
1759 | return result; | |
1760 | } | |
1761 | ||
1762 | static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, | |
1763 | pci_channel_state_t state) | |
1764 | { | |
1765 | struct cxl *adapter = pci_get_drvdata(pdev); | |
1766 | struct cxl_afu *afu; | |
1767 | pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; | |
1768 | int i; | |
1769 | ||
1770 | /* At this point, we could still have an interrupt pending. | |
1771 | * Let's try to get them out of the way before they do | |
1772 | * anything we don't like. | |
1773 | */ | |
1774 | schedule(); | |
1775 | ||
1776 | /* If we're permanently dead, give up. */ | |
1777 | if (state == pci_channel_io_perm_failure) { | |
1778 | /* Tell the AFU drivers; but we don't care what they | |
1779 | * say, we're going away. | |
1780 | */ | |
1781 | for (i = 0; i < adapter->slices; i++) { | |
1782 | afu = adapter->afu[i]; | |
e4f5fc00 IM |
1783 | /* Only participate in EEH if we are on a virtual PHB */ |
1784 | if (afu->phb == NULL) | |
1785 | return PCI_ERS_RESULT_NONE; | |
9e8df8a2 DA |
1786 | cxl_vphb_error_detected(afu, state); |
1787 | } | |
1788 | return PCI_ERS_RESULT_DISCONNECT; | |
1789 | } | |
1790 | ||
1791 | /* Are we reflashing? | |
1792 | * | |
1793 | * If we reflash, we could come back as something entirely | |
1794 | * different, including a non-CAPI card. As such, by default | |
1795 | * we don't participate in the process. We'll be unbound and | |
1796 | * the slot re-probed. (TODO: check EEH doesn't blindly rebind | |
1797 | * us!) | |
1798 | * | |
1799 | * However, this isn't the entire story: for reliablity | |
1800 | * reasons, we usually want to reflash the FPGA on PERST in | |
1801 | * order to get back to a more reliable known-good state. | |
1802 | * | |
1803 | * This causes us a bit of a problem: if we reflash we can't | |
1804 | * trust that we'll come back the same - we could have a new | |
1805 | * image and been PERSTed in order to load that | |
1806 | * image. However, most of the time we actually *will* come | |
1807 | * back the same - for example a regular EEH event. | |
1808 | * | |
1809 | * Therefore, we allow the user to assert that the image is | |
1810 | * indeed the same and that we should continue on into EEH | |
1811 | * anyway. | |
1812 | */ | |
1813 | if (adapter->perst_loads_image && !adapter->perst_same_image) { | |
1814 | /* TODO take the PHB out of CXL mode */ | |
1815 | dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); | |
1816 | return PCI_ERS_RESULT_NONE; | |
1817 | } | |
1818 | ||
1819 | /* | |
1820 | * At this point, we want to try to recover. We'll always | |
1821 | * need a complete slot reset: we don't trust any other reset. | |
1822 | * | |
1823 | * Now, we go through each AFU: | |
1824 | * - We send the driver, if bound, an error_detected callback. | |
1825 | * We expect it to clean up, but it can also tell us to give | |
1826 | * up and permanently detach the card. To simplify things, if | |
1827 | * any bound AFU driver doesn't support EEH, we give up on EEH. | |
1828 | * | |
1829 | * - We detach all contexts associated with the AFU. This | |
1830 | * does not free them, but puts them into a CLOSED state | |
1831 | * which causes any the associated files to return useful | |
1832 | * errors to userland. It also unmaps, but does not free, | |
1833 | * any IRQs. | |
1834 | * | |
1835 | * - We clean up our side: releasing and unmapping resources we hold | |
1836 | * so we can wire them up again when the hardware comes back up. | |
1837 | * | |
1838 | * Driver authors should note: | |
1839 | * | |
1840 | * - Any contexts you create in your kernel driver (except | |
1841 | * those associated with anonymous file descriptors) are | |
1842 | * your responsibility to free and recreate. Likewise with | |
1843 | * any attached resources. | |
1844 | * | |
1845 | * - We will take responsibility for re-initialising the | |
1846 | * device context (the one set up for you in | |
1847 | * cxl_pci_enable_device_hook and accessed through | |
1848 | * cxl_get_context). If you've attached IRQs or other | |
1849 | * resources to it, they remains yours to free. | |
1850 | * | |
1851 | * You can call the same functions to release resources as you | |
1852 | * normally would: we make sure that these functions continue | |
1853 | * to work when the hardware is down. | |
1854 | * | |
1855 | * Two examples: | |
1856 | * | |
1857 | * 1) If you normally free all your resources at the end of | |
1858 | * each request, or if you use anonymous FDs, your | |
1859 | * error_detected callback can simply set a flag to tell | |
1860 | * your driver not to start any new calls. You can then | |
1861 | * clear the flag in the resume callback. | |
1862 | * | |
1863 | * 2) If you normally allocate your resources on startup: | |
1864 | * * Set a flag in error_detected as above. | |
1865 | * * Let CXL detach your contexts. | |
1866 | * * In slot_reset, free the old resources and allocate new ones. | |
1867 | * * In resume, clear the flag to allow things to start. | |
1868 | */ | |
1869 | for (i = 0; i < adapter->slices; i++) { | |
1870 | afu = adapter->afu[i]; | |
1871 | ||
1872 | result = cxl_vphb_error_detected(afu, state); | |
1873 | ||
1874 | /* Only continue if everyone agrees on NEED_RESET */ | |
1875 | if (result != PCI_ERS_RESULT_NEED_RESET) | |
1876 | return result; | |
1877 | ||
1878 | cxl_context_detach_all(afu); | |
5be587b1 | 1879 | cxl_ops->afu_deactivate_mode(afu, afu->current_mode); |
2b04cf31 | 1880 | pci_deconfigure_afu(afu); |
9e8df8a2 DA |
1881 | } |
1882 | cxl_deconfigure_adapter(adapter); | |
1883 | ||
1884 | return result; | |
1885 | } | |
1886 | ||
1887 | static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev) | |
1888 | { | |
1889 | struct cxl *adapter = pci_get_drvdata(pdev); | |
1890 | struct cxl_afu *afu; | |
1891 | struct cxl_context *ctx; | |
1892 | struct pci_dev *afu_dev; | |
1893 | pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED; | |
1894 | pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; | |
1895 | int i; | |
1896 | ||
1897 | if (cxl_configure_adapter(adapter, pdev)) | |
1898 | goto err; | |
1899 | ||
1900 | for (i = 0; i < adapter->slices; i++) { | |
1901 | afu = adapter->afu[i]; | |
1902 | ||
2b04cf31 | 1903 | if (pci_configure_afu(afu, adapter, pdev)) |
9e8df8a2 DA |
1904 | goto err; |
1905 | ||
1906 | if (cxl_afu_select_best_mode(afu)) | |
1907 | goto err; | |
1908 | ||
9e8df8a2 DA |
1909 | list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { |
1910 | /* Reset the device context. | |
1911 | * TODO: make this less disruptive | |
1912 | */ | |
1913 | ctx = cxl_get_context(afu_dev); | |
1914 | ||
1915 | if (ctx && cxl_release_context(ctx)) | |
1916 | goto err; | |
1917 | ||
1918 | ctx = cxl_dev_context_init(afu_dev); | |
1919 | if (!ctx) | |
1920 | goto err; | |
1921 | ||
1922 | afu_dev->dev.archdata.cxl_ctx = ctx; | |
1923 | ||
5be587b1 | 1924 | if (cxl_ops->afu_check_and_enable(afu)) |
9e8df8a2 DA |
1925 | goto err; |
1926 | ||
1927 | afu_dev->error_state = pci_channel_io_normal; | |
1928 | ||
1929 | /* If there's a driver attached, allow it to | |
1930 | * chime in on recovery. Drivers should check | |
1931 | * if everything has come back OK, but | |
1932 | * shouldn't start new work until we call | |
1933 | * their resume function. | |
1934 | */ | |
1935 | if (!afu_dev->driver) | |
1936 | continue; | |
1937 | ||
1938 | if (afu_dev->driver->err_handler && | |
1939 | afu_dev->driver->err_handler->slot_reset) | |
1940 | afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev); | |
1941 | ||
1942 | if (afu_result == PCI_ERS_RESULT_DISCONNECT) | |
1943 | result = PCI_ERS_RESULT_DISCONNECT; | |
1944 | } | |
1945 | } | |
1946 | return result; | |
1947 | ||
1948 | err: | |
1949 | /* All the bits that happen in both error_detected and cxl_remove | |
1950 | * should be idempotent, so we don't need to worry about leaving a mix | |
1951 | * of unconfigured and reconfigured resources. | |
1952 | */ | |
1953 | dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); | |
1954 | return PCI_ERS_RESULT_DISCONNECT; | |
1955 | } | |
1956 | ||
1957 | static void cxl_pci_resume(struct pci_dev *pdev) | |
1958 | { | |
1959 | struct cxl *adapter = pci_get_drvdata(pdev); | |
1960 | struct cxl_afu *afu; | |
1961 | struct pci_dev *afu_dev; | |
1962 | int i; | |
1963 | ||
1964 | /* Everything is back now. Drivers should restart work now. | |
1965 | * This is not the place to be checking if everything came back up | |
1966 | * properly, because there's no return value: do that in slot_reset. | |
1967 | */ | |
1968 | for (i = 0; i < adapter->slices; i++) { | |
1969 | afu = adapter->afu[i]; | |
1970 | ||
1971 | list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { | |
1972 | if (afu_dev->driver && afu_dev->driver->err_handler && | |
1973 | afu_dev->driver->err_handler->resume) | |
1974 | afu_dev->driver->err_handler->resume(afu_dev); | |
1975 | } | |
1976 | } | |
1977 | } | |
1978 | ||
1979 | static const struct pci_error_handlers cxl_err_handler = { | |
1980 | .error_detected = cxl_pci_error_detected, | |
1981 | .slot_reset = cxl_pci_slot_reset, | |
1982 | .resume = cxl_pci_resume, | |
1983 | }; | |
1984 | ||
f204e0b8 IM |
1985 | struct pci_driver cxl_pci_driver = { |
1986 | .name = "cxl-pci", | |
1987 | .id_table = cxl_pci_tbl, | |
1988 | .probe = cxl_probe, | |
1989 | .remove = cxl_remove, | |
aa70775e | 1990 | .shutdown = cxl_remove, |
9e8df8a2 | 1991 | .err_handler = &cxl_err_handler, |
f204e0b8 | 1992 | }; |