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cxl: Enable CAPP recovery
[deliverable/linux.git] / drivers / misc / cxl / pci.c
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/pci_regs.h>
11#include <linux/pci_ids.h>
12#include <linux/device.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/sort.h>
17#include <linux/pci.h>
18#include <linux/of.h>
19#include <linux/delay.h>
20#include <asm/opal.h>
21#include <asm/msi_bitmap.h>
22#include <asm/pci-bridge.h> /* for struct pci_controller */
23#include <asm/pnv-pci.h>
24
25#include "cxl.h"
26
27
28#define CXL_PCI_VSEC_ID 0x1280
29#define CXL_VSEC_MIN_SIZE 0x80
30
31#define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
32 { \
33 pci_read_config_word(dev, vsec + 0x6, dest); \
34 *dest >>= 4; \
35 }
36#define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
37 pci_read_config_byte(dev, vsec + 0x8, dest)
38
39#define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
40 pci_read_config_byte(dev, vsec + 0x9, dest)
41#define CXL_STATUS_SECOND_PORT 0x80
42#define CXL_STATUS_MSI_X_FULL 0x40
43#define CXL_STATUS_MSI_X_SINGLE 0x20
44#define CXL_STATUS_FLASH_RW 0x08
45#define CXL_STATUS_FLASH_RO 0x04
46#define CXL_STATUS_LOADABLE_AFU 0x02
47#define CXL_STATUS_LOADABLE_PSL 0x01
48/* If we see these features we won't try to use the card */
49#define CXL_UNSUPPORTED_FEATURES \
50 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
51
52#define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
53 pci_read_config_byte(dev, vsec + 0xa, dest)
54#define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
55 pci_write_config_byte(dev, vsec + 0xa, val)
56#define CXL_VSEC_PROTOCOL_MASK 0xe0
57#define CXL_VSEC_PROTOCOL_1024TB 0x80
58#define CXL_VSEC_PROTOCOL_512TB 0x40
59#define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */
60#define CXL_VSEC_PROTOCOL_ENABLE 0x01
61
62#define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
63 pci_read_config_word(dev, vsec + 0xc, dest)
64#define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
65 pci_read_config_byte(dev, vsec + 0xe, dest)
66#define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
67 pci_read_config_byte(dev, vsec + 0xf, dest)
68#define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
69 pci_read_config_word(dev, vsec + 0x10, dest)
70
71#define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
72 pci_read_config_byte(dev, vsec + 0x13, dest)
73#define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
74 pci_write_config_byte(dev, vsec + 0x13, val)
75#define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
76#define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
77#define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
78
79#define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
80 pci_read_config_dword(dev, vsec + 0x20, dest)
81#define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
82 pci_read_config_dword(dev, vsec + 0x24, dest)
83#define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x28, dest)
85#define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x2c, dest)
87
88
89/* This works a little different than the p1/p2 register accesses to make it
90 * easier to pull out individual fields */
91#define AFUD_READ(afu, off) in_be64(afu->afu_desc_mmio + off)
92#define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
93#define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
94
95#define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
96#define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
97#define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
98#define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
99#define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
100#define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
101#define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
102#define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
103#define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
104#define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
105#define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
106#define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
107#define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
108#define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
109#define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
110#define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111#define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
112#define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
113#define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
114#define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
115
116static DEFINE_PCI_DEVICE_TABLE(cxl_pci_tbl) = {
117 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
118 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
119 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
120 { PCI_DEVICE_CLASS(0x120000, ~0), },
121
122 { }
123};
124MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
125
126
127/*
128 * Mostly using these wrappers to avoid confusion:
129 * priv 1 is BAR2, while priv 2 is BAR0
130 */
131static inline resource_size_t p1_base(struct pci_dev *dev)
132{
133 return pci_resource_start(dev, 2);
134}
135
136static inline resource_size_t p1_size(struct pci_dev *dev)
137{
138 return pci_resource_len(dev, 2);
139}
140
141static inline resource_size_t p2_base(struct pci_dev *dev)
142{
143 return pci_resource_start(dev, 0);
144}
145
146static inline resource_size_t p2_size(struct pci_dev *dev)
147{
148 return pci_resource_len(dev, 0);
149}
150
151static int find_cxl_vsec(struct pci_dev *dev)
152{
153 int vsec = 0;
154 u16 val;
155
156 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
157 pci_read_config_word(dev, vsec + 0x4, &val);
158 if (val == CXL_PCI_VSEC_ID)
159 return vsec;
160 }
161 return 0;
162
163}
164
165static void dump_cxl_config_space(struct pci_dev *dev)
166{
167 int vsec;
168 u32 val;
169
170 dev_info(&dev->dev, "dump_cxl_config_space\n");
171
172 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
173 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
174 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
175 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
177 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
179 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
181 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
183 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
184
185 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
186 p1_base(dev), p1_size(dev));
187 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
188 p1_base(dev), p2_size(dev));
189 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
190 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
191
192 if (!(vsec = find_cxl_vsec(dev)))
193 return;
194
195#define show_reg(name, what) \
196 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
197
198 pci_read_config_dword(dev, vsec + 0x0, &val);
199 show_reg("Cap ID", (val >> 0) & 0xffff);
200 show_reg("Cap Ver", (val >> 16) & 0xf);
201 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
202 pci_read_config_dword(dev, vsec + 0x4, &val);
203 show_reg("VSEC ID", (val >> 0) & 0xffff);
204 show_reg("VSEC Rev", (val >> 16) & 0xf);
205 show_reg("VSEC Length", (val >> 20) & 0xfff);
206 pci_read_config_dword(dev, vsec + 0x8, &val);
207 show_reg("Num AFUs", (val >> 0) & 0xff);
208 show_reg("Status", (val >> 8) & 0xff);
209 show_reg("Mode Control", (val >> 16) & 0xff);
210 show_reg("Reserved", (val >> 24) & 0xff);
211 pci_read_config_dword(dev, vsec + 0xc, &val);
212 show_reg("PSL Rev", (val >> 0) & 0xffff);
213 show_reg("CAIA Ver", (val >> 16) & 0xffff);
214 pci_read_config_dword(dev, vsec + 0x10, &val);
215 show_reg("Base Image Rev", (val >> 0) & 0xffff);
216 show_reg("Reserved", (val >> 16) & 0x0fff);
217 show_reg("Image Control", (val >> 28) & 0x3);
218 show_reg("Reserved", (val >> 30) & 0x1);
219 show_reg("Image Loaded", (val >> 31) & 0x1);
220
221 pci_read_config_dword(dev, vsec + 0x14, &val);
222 show_reg("Reserved", val);
223 pci_read_config_dword(dev, vsec + 0x18, &val);
224 show_reg("Reserved", val);
225 pci_read_config_dword(dev, vsec + 0x1c, &val);
226 show_reg("Reserved", val);
227
228 pci_read_config_dword(dev, vsec + 0x20, &val);
229 show_reg("AFU Descriptor Offset", val);
230 pci_read_config_dword(dev, vsec + 0x24, &val);
231 show_reg("AFU Descriptor Size", val);
232 pci_read_config_dword(dev, vsec + 0x28, &val);
233 show_reg("Problem State Offset", val);
234 pci_read_config_dword(dev, vsec + 0x2c, &val);
235 show_reg("Problem State Size", val);
236
237 pci_read_config_dword(dev, vsec + 0x30, &val);
238 show_reg("Reserved", val);
239 pci_read_config_dword(dev, vsec + 0x34, &val);
240 show_reg("Reserved", val);
241 pci_read_config_dword(dev, vsec + 0x38, &val);
242 show_reg("Reserved", val);
243 pci_read_config_dword(dev, vsec + 0x3c, &val);
244 show_reg("Reserved", val);
245
246 pci_read_config_dword(dev, vsec + 0x40, &val);
247 show_reg("PSL Programming Port", val);
248 pci_read_config_dword(dev, vsec + 0x44, &val);
249 show_reg("PSL Programming Control", val);
250
251 pci_read_config_dword(dev, vsec + 0x48, &val);
252 show_reg("Reserved", val);
253 pci_read_config_dword(dev, vsec + 0x4c, &val);
254 show_reg("Reserved", val);
255
256 pci_read_config_dword(dev, vsec + 0x50, &val);
257 show_reg("Flash Address Register", val);
258 pci_read_config_dword(dev, vsec + 0x54, &val);
259 show_reg("Flash Size Register", val);
260 pci_read_config_dword(dev, vsec + 0x58, &val);
261 show_reg("Flash Status/Control Register", val);
262 pci_read_config_dword(dev, vsec + 0x58, &val);
263 show_reg("Flash Data Port", val);
264
265#undef show_reg
266}
267
268static void dump_afu_descriptor(struct cxl_afu *afu)
269{
270 u64 val;
271
272#define show_reg(name, what) \
273 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
274
275 val = AFUD_READ_INFO(afu);
276 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
277 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
278 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
279 show_reg("req_prog_mode", val & 0xffffULL);
280
281 val = AFUD_READ(afu, 0x8);
282 show_reg("Reserved", val);
283 val = AFUD_READ(afu, 0x10);
284 show_reg("Reserved", val);
285 val = AFUD_READ(afu, 0x18);
286 show_reg("Reserved", val);
287
288 val = AFUD_READ_CR(afu);
289 show_reg("Reserved", (val >> (63-7)) & 0xff);
290 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
291
292 val = AFUD_READ_CR_OFF(afu);
293 show_reg("AFU_CR_offset", val);
294
295 val = AFUD_READ_PPPSA(afu);
296 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
297 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
298
299 val = AFUD_READ_PPPSA_OFF(afu);
300 show_reg("PerProcessPSA_offset", val);
301
302 val = AFUD_READ_EB(afu);
303 show_reg("Reserved", (val >> (63-7)) & 0xff);
304 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
305
306 val = AFUD_READ_EB_OFF(afu);
307 show_reg("AFU_EB_offset", val);
308
309#undef show_reg
310}
311
312static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
313{
314 struct device_node *np;
315 const __be32 *prop;
316 u64 psl_dsnctl;
317 u64 chipid;
318
319 if (!(np = pnv_pci_to_phb_node(dev)))
320 return -ENODEV;
321
322 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
323 np = of_get_next_parent(np);
324 if (!np)
325 return -ENODEV;
326 chipid = be32_to_cpup(prop);
327 of_node_put(np);
328
329 /* Tell PSL where to route data to */
330 psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5));
331 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
332 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
333 /* snoop write mask */
334 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
335 /* set fir_accum */
336 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL);
337 /* for debugging with trace arrays */
338 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
339
340 return 0;
341}
342
343static int init_implementation_afu_regs(struct cxl_afu *afu)
344{
345 /* read/write masks for this slice */
346 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
347 /* APC read/write masks for this slice */
348 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
349 /* for debugging with trace arrays */
350 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
d6a6af2c 351 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
f204e0b8
IM		 352
353 return 0;
354}
355
356int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq,
357 unsigned int virq)
358{
359 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
360
361 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
362}
363
4beb5421
RG		 364int cxl_update_image_control(struct cxl *adapter)
365{
366 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
367 int rc;
368 int vsec;
369 u8 image_state;
370
371 if (!(vsec = find_cxl_vsec(dev))) {
372 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
373 return -ENODEV;
374 }
375
376 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
377 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
378 return rc;
379 }
380
381 if (adapter->perst_loads_image)
382 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
383 else
384 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
385
386 if (adapter->perst_select_user)
387 image_state |= CXL_VSEC_PERST_SELECT_USER;
388 else
389 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
390
391 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
392 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
393 return rc;
394 }
395
396 return 0;
397}
398
f204e0b8
IM		 399int cxl_alloc_one_irq(struct cxl *adapter)
400{
401 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
402
403 return pnv_cxl_alloc_hwirqs(dev, 1);
404}
405
406void cxl_release_one_irq(struct cxl *adapter, int hwirq)
407{
408 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
409
410 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
411}
412
413int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num)
414{
415 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
416
417 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
418}
419
420void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter)
421{
422 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
423
424 pnv_cxl_release_hwirq_ranges(irqs, dev);
425}
426
427static int setup_cxl_bars(struct pci_dev *dev)
428{
429 /* Safety check in case we get backported to < 3.17 without M64 */
430 if ((p1_base(dev) < 0x100000000ULL) ||
431 (p2_base(dev) < 0x100000000ULL)) {
432 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
433 return -ENODEV;
434 }
435
436 /*
437 * BAR 4/5 has a special meaning for CXL and must be programmed with a
438 * special value corresponding to the CXL protocol address range.
439 * For POWER 8 that means bits 48:49 must be set to 10
440 */
441 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
442 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
443
444 return 0;
445}
446
447/* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
448static int switch_card_to_cxl(struct pci_dev *dev)
449{
450 int vsec;
451 u8 val;
452 int rc;
453
454 dev_info(&dev->dev, "switch card to CXL\n");
455
456 if (!(vsec = find_cxl_vsec(dev))) {
457 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
458 return -ENODEV;
459 }
460
461 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
462 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
463 return rc;
464 }
465 val &= ~CXL_VSEC_PROTOCOL_MASK;
466 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
467 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
468 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
469 return rc;
470 }
471 /*
472 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
473 * we must wait 100ms after this mode switch before touching
474 * PCIe config space.
475 */
476 msleep(100);
477
478 return 0;
479}
480
481static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
482{
483 u64 p1n_base, p2n_base, afu_desc;
484 const u64 p1n_size = 0x100;
485 const u64 p2n_size = 0x1000;
486
487 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
488 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
489 afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size));
490 afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size);
491
492 if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size)))
493 goto err;
494 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
495 goto err1;
496 if (afu_desc) {
497 if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size)))
498 goto err2;
499 }
500
501 return 0;
502err2:
503 iounmap(afu->p2n_mmio);
504err1:
505 iounmap(afu->p1n_mmio);
506err:
507 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
508 return -ENOMEM;
509}
510
511static void cxl_unmap_slice_regs(struct cxl_afu *afu)
512{
513 if (afu->p1n_mmio)
514 iounmap(afu->p2n_mmio);
515 if (afu->p1n_mmio)
516 iounmap(afu->p1n_mmio);
517}
518
519static void cxl_release_afu(struct device *dev)
520{
521 struct cxl_afu *afu = to_cxl_afu(dev);
522
523 pr_devel("cxl_release_afu\n");
524
525 kfree(afu);
526}
527
528static struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
529{
530 struct cxl_afu *afu;
531
532 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
533 return NULL;
534
535 afu->adapter = adapter;
536 afu->dev.parent = &adapter->dev;
537 afu->dev.release = cxl_release_afu;
538 afu->slice = slice;
539 idr_init(&afu->contexts_idr);
ee41d11d 540 mutex_init(&afu->contexts_lock);
f204e0b8
IM		 541 spin_lock_init(&afu->afu_cntl_lock);
542 mutex_init(&afu->spa_mutex);
543
544 afu->prefault_mode = CXL_PREFAULT_NONE;
545 afu->irqs_max = afu->adapter->user_irqs;
546
547 return afu;
548}
549
550/* Expects AFU struct to have recently been zeroed out */
551static int cxl_read_afu_descriptor(struct cxl_afu *afu)
552{
553 u64 val;
554
555 val = AFUD_READ_INFO(afu);
556 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
557 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
558
559 if (AFUD_AFU_DIRECTED(val))
560 afu->modes_supported |= CXL_MODE_DIRECTED;
561 if (AFUD_DEDICATED_PROCESS(val))
562 afu->modes_supported |= CXL_MODE_DEDICATED;
563 if (AFUD_TIME_SLICED(val))
564 afu->modes_supported |= CXL_MODE_TIME_SLICED;
565
566 val = AFUD_READ_PPPSA(afu);
567 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
568 afu->psa = AFUD_PPPSA_PSA(val);
569 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
570 afu->pp_offset = AFUD_READ_PPPSA_OFF(afu);
571
572 return 0;
573}
574
575static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
576{
577 if (afu->psa && afu->adapter->ps_size <
578 (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
579 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
580 return -ENODEV;
581 }
582
583 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
584 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!");
585
586 return 0;
587}
588
589static int sanitise_afu_regs(struct cxl_afu *afu)
590{
591 u64 reg;
592
593 /*
594 * Clear out any regs that contain either an IVTE or address or may be
595 * waiting on an acknowledgement to try to be a bit safer as we bring
596 * it online
597 */
598 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
599 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
600 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg);
601 if (cxl_afu_reset(afu))
602 return -EIO;
603 if (cxl_afu_disable(afu))
604 return -EIO;
605 if (cxl_psl_purge(afu))
606 return -EIO;
607 }
608 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
609 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
610 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
611 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
612 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
613 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
614 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
615 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
616 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
617 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
618 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
619 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
620 if (reg) {
621 dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg);
622 if (reg & CXL_PSL_DSISR_TRANS)
623 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
624 else
625 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
626 }
627 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
628 if (reg) {
629 if (reg & ~0xffff)
630 dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg);
631 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
632 }
633 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
634 if (reg) {
635 dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg);
636 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
637 }
638
639 return 0;
640}
641
642static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
643{
644 struct cxl_afu *afu;
645 bool free = true;
646 int rc;
647
648 if (!(afu = cxl_alloc_afu(adapter, slice)))
649 return -ENOMEM;
650
651 if ((rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice)))
652 goto err1;
653
654 if ((rc = cxl_map_slice_regs(afu, adapter, dev)))
655 goto err1;
656
657 if ((rc = sanitise_afu_regs(afu)))
658 goto err2;
659
660 /* We need to reset the AFU before we can read the AFU descriptor */
661 if ((rc = cxl_afu_reset(afu)))
662 goto err2;
663
664 if (cxl_verbose)
665 dump_afu_descriptor(afu);
666
667 if ((rc = cxl_read_afu_descriptor(afu)))
668 goto err2;
669
670 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
671 goto err2;
672
673 if ((rc = init_implementation_afu_regs(afu)))
674 goto err2;
675
676 if ((rc = cxl_register_serr_irq(afu)))
677 goto err2;
678
679 if ((rc = cxl_register_psl_irq(afu)))
680 goto err3;
681
682 /* Don't care if this fails */
683 cxl_debugfs_afu_add(afu);
684
685 /*
686 * After we call this function we must not free the afu directly, even
687 * if it returns an error!
688 */
689 if ((rc = cxl_register_afu(afu)))
690 goto err_put1;
691
692 if ((rc = cxl_sysfs_afu_add(afu)))
693 goto err_put1;
694
695
696 if ((rc = cxl_afu_select_best_mode(afu)))
697 goto err_put2;
698
699 adapter->afu[afu->slice] = afu;
700
701 return 0;
702
703err_put2:
704 cxl_sysfs_afu_remove(afu);
705err_put1:
706 device_unregister(&afu->dev);
707 free = false;
708 cxl_debugfs_afu_remove(afu);
709 cxl_release_psl_irq(afu);
710err3:
711 cxl_release_serr_irq(afu);
712err2:
713 cxl_unmap_slice_regs(afu);
714err1:
715 if (free)
716 kfree(afu);
717 return rc;
718}
719
720static void cxl_remove_afu(struct cxl_afu *afu)
721{
722 pr_devel("cxl_remove_afu\n");
723
724 if (!afu)
725 return;
726
727 cxl_sysfs_afu_remove(afu);
728 cxl_debugfs_afu_remove(afu);
729
730 spin_lock(&afu->adapter->afu_list_lock);
731 afu->adapter->afu[afu->slice] = NULL;
732 spin_unlock(&afu->adapter->afu_list_lock);
733
734 cxl_context_detach_all(afu);
735 cxl_afu_deactivate_mode(afu);
736
737 cxl_release_psl_irq(afu);
738 cxl_release_serr_irq(afu);
739 cxl_unmap_slice_regs(afu);
740
741 device_unregister(&afu->dev);
742}
743
744
745static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
746{
747 if (pci_request_region(dev, 2, "priv 2 regs"))
748 goto err1;
749 if (pci_request_region(dev, 0, "priv 1 regs"))
750 goto err2;
751
752 pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx",
753 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
754
755 if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
756 goto err3;
757
758 if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
759 goto err4;
760
761 return 0;
762
763err4:
764 iounmap(adapter->p1_mmio);
765 adapter->p1_mmio = NULL;
766err3:
767 pci_release_region(dev, 0);
768err2:
769 pci_release_region(dev, 2);
770err1:
771 return -ENOMEM;
772}
773
774static void cxl_unmap_adapter_regs(struct cxl *adapter)
775{
776 if (adapter->p1_mmio)
777 iounmap(adapter->p1_mmio);
778 if (adapter->p2_mmio)
779 iounmap(adapter->p2_mmio);
780}
781
782static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
783{
784 int vsec;
785 u32 afu_desc_off, afu_desc_size;
786 u32 ps_off, ps_size;
787 u16 vseclen;
788 u8 image_state;
789
790 if (!(vsec = find_cxl_vsec(dev))) {
791 dev_err(&adapter->dev, "ABORTING: CXL VSEC not found!\n");
792 return -ENODEV;
793 }
794
795 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
796 if (vseclen < CXL_VSEC_MIN_SIZE) {
797 pr_err("ABORTING: CXL VSEC too short\n");
798 return -EINVAL;
799 }
800
801 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
802 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
803 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
804 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
805 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
806 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
807 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
4beb5421
RG		 808 adapter->perst_loads_image = true;
809 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
f204e0b8
IM		 810
811 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
812 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
813 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
814 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
815 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
816
817 /* Convert everything to bytes, because there is NO WAY I'd look at the
818 * code a month later and forget what units these are in ;-) */
819 adapter->ps_off = ps_off * 64 * 1024;
820 adapter->ps_size = ps_size * 64 * 1024;
821 adapter->afu_desc_off = afu_desc_off * 64 * 1024;
822 adapter->afu_desc_size = afu_desc_size *64 * 1024;
823
824 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
825 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
826
827 return 0;
828}
829
830static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
831{
832 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
833 return -EBUSY;
834
835 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
836 dev_err(&adapter->dev, "ABORTING: CXL requires unsupported features\n");
837 return -EINVAL;
838 }
839
840 if (!adapter->slices) {
841 /* Once we support dynamic reprogramming we can use the card if
842 * it supports loadable AFUs */
843 dev_err(&adapter->dev, "ABORTING: Device has no AFUs\n");
844 return -EINVAL;
845 }
846
847 if (!adapter->afu_desc_off || !adapter->afu_desc_size) {
848 dev_err(&adapter->dev, "ABORTING: VSEC shows no AFU descriptors\n");
849 return -EINVAL;
850 }
851
852 if (adapter->ps_size > p2_size(dev) - adapter->ps_off) {
853 dev_err(&adapter->dev, "ABORTING: Problem state size larger than "
854 "available in BAR2: 0x%llx > 0x%llx\n",
855 adapter->ps_size, p2_size(dev) - adapter->ps_off);
856 return -EINVAL;
857 }
858
859 return 0;
860}
861
862static void cxl_release_adapter(struct device *dev)
863{
864 struct cxl *adapter = to_cxl_adapter(dev);
865
866 pr_devel("cxl_release_adapter\n");
867
868 kfree(adapter);
869}
870
871static struct cxl *cxl_alloc_adapter(struct pci_dev *dev)
872{
873 struct cxl *adapter;
874
875 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
876 return NULL;
877
878 adapter->dev.parent = &dev->dev;
879 adapter->dev.release = cxl_release_adapter;
880 pci_set_drvdata(dev, adapter);
881 spin_lock_init(&adapter->afu_list_lock);
882
883 return adapter;
884}
885
886static int sanitise_adapter_regs(struct cxl *adapter)
887{
888 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
889 return cxl_tlb_slb_invalidate(adapter);
890}
891
892static struct cxl *cxl_init_adapter(struct pci_dev *dev)
893{
894 struct cxl *adapter;
895 bool free = true;
896 int rc;
897
898
899 if (!(adapter = cxl_alloc_adapter(dev)))
900 return ERR_PTR(-ENOMEM);
901
902 if ((rc = switch_card_to_cxl(dev)))
903 goto err1;
904
905 if ((rc = cxl_alloc_adapter_nr(adapter)))
906 goto err1;
907
908 if ((rc = dev_set_name(&adapter->dev, "card%i", adapter->adapter_num)))
909 goto err2;
910
911 if ((rc = cxl_read_vsec(adapter, dev)))
912 goto err2;
913
914 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
915 goto err2;
916
4beb5421
RG		 917 if ((rc = cxl_update_image_control(adapter)))
918 goto err2;
919
f204e0b8
IM		 920 if ((rc = cxl_map_adapter_regs(adapter, dev)))
921 goto err2;
922
923 if ((rc = sanitise_adapter_regs(adapter)))
924 goto err2;
925
926 if ((rc = init_implementation_adapter_regs(adapter, dev)))
927 goto err3;
928
1212aa1c 929 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))
f204e0b8
IM		 930 goto err3;
931
1212aa1c
RG		 932 /* If recovery happened, the last step is to turn on snooping.
933 * In the non-recovery case this has no effect */
934 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) {
935 goto err3;
936 }
937
f204e0b8
IM		 938 if ((rc = cxl_register_psl_err_irq(adapter)))
939 goto err3;
940
941 /* Don't care if this one fails: */
942 cxl_debugfs_adapter_add(adapter);
943
944 /*
945 * After we call this function we must not free the adapter directly,
946 * even if it returns an error!
947 */
948 if ((rc = cxl_register_adapter(adapter)))
949 goto err_put1;
950
951 if ((rc = cxl_sysfs_adapter_add(adapter)))
952 goto err_put1;
953
954 return adapter;
955
956err_put1:
957 device_unregister(&adapter->dev);
958 free = false;
959 cxl_debugfs_adapter_remove(adapter);
960 cxl_release_psl_err_irq(adapter);
961err3:
962 cxl_unmap_adapter_regs(adapter);
963err2:
964 cxl_remove_adapter_nr(adapter);
965err1:
966 if (free)
967 kfree(adapter);
968 return ERR_PTR(rc);
969}
970
971static void cxl_remove_adapter(struct cxl *adapter)
972{
973 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
974
975 pr_devel("cxl_release_adapter\n");
976
977 cxl_sysfs_adapter_remove(adapter);
978 cxl_debugfs_adapter_remove(adapter);
979 cxl_release_psl_err_irq(adapter);
980 cxl_unmap_adapter_regs(adapter);
981 cxl_remove_adapter_nr(adapter);
982
983 device_unregister(&adapter->dev);
984
985 pci_release_region(pdev, 0);
986 pci_release_region(pdev, 2);
987 pci_disable_device(pdev);
988}
989
990static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
991{
992 struct cxl *adapter;
993 int slice;
994 int rc;
995
996 pci_dev_get(dev);
997
998 if (cxl_verbose)
999 dump_cxl_config_space(dev);
1000
1001 if ((rc = setup_cxl_bars(dev)))
1002 return rc;
1003
1004 if ((rc = pci_enable_device(dev))) {
1005 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1006 return rc;
1007 }
1008
1009 adapter = cxl_init_adapter(dev);
1010 if (IS_ERR(adapter)) {
1011 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1012 return PTR_ERR(adapter);
1013 }
1014
1015 for (slice = 0; slice < adapter->slices; slice++) {
1016 if ((rc = cxl_init_afu(adapter, slice, dev)))
1017 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1018 }
1019
1020 return 0;
1021}
1022
1023static void cxl_remove(struct pci_dev *dev)
1024{
1025 struct cxl *adapter = pci_get_drvdata(dev);
1026 int afu;
1027
1028 dev_warn(&dev->dev, "pci remove\n");
1029
1030 /*
1031 * Lock to prevent someone grabbing a ref through the adapter list as
1032 * we are removing it
1033 */
1034 for (afu = 0; afu < adapter->slices; afu++)
1035 cxl_remove_afu(adapter->afu[afu]);
1036 cxl_remove_adapter(adapter);
1037}
1038
1039struct pci_driver cxl_pci_driver = {
1040 .name = "cxl-pci",
1041 .id_table = cxl_pci_tbl,
1042 .probe = cxl_probe,
1043 .remove = cxl_remove,
1044};
Linux kernel - Deliverables
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