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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/pci_regs.h> | |
11 | #include <linux/pci_ids.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/sort.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/delay.h> | |
20 | #include <asm/opal.h> | |
21 | #include <asm/msi_bitmap.h> | |
22 | #include <asm/pci-bridge.h> /* for struct pci_controller */ | |
23 | #include <asm/pnv-pci.h> | |
62fa19d4 | 24 | #include <asm/io.h> |
f204e0b8 IM |
25 | |
26 | #include "cxl.h" | |
27 | ||
28 | ||
29 | #define CXL_PCI_VSEC_ID 0x1280 | |
30 | #define CXL_VSEC_MIN_SIZE 0x80 | |
31 | ||
32 | #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ | |
33 | { \ | |
34 | pci_read_config_word(dev, vsec + 0x6, dest); \ | |
35 | *dest >>= 4; \ | |
36 | } | |
37 | #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ | |
38 | pci_read_config_byte(dev, vsec + 0x8, dest) | |
39 | ||
40 | #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ | |
41 | pci_read_config_byte(dev, vsec + 0x9, dest) | |
42 | #define CXL_STATUS_SECOND_PORT 0x80 | |
43 | #define CXL_STATUS_MSI_X_FULL 0x40 | |
44 | #define CXL_STATUS_MSI_X_SINGLE 0x20 | |
45 | #define CXL_STATUS_FLASH_RW 0x08 | |
46 | #define CXL_STATUS_FLASH_RO 0x04 | |
47 | #define CXL_STATUS_LOADABLE_AFU 0x02 | |
48 | #define CXL_STATUS_LOADABLE_PSL 0x01 | |
49 | /* If we see these features we won't try to use the card */ | |
50 | #define CXL_UNSUPPORTED_FEATURES \ | |
51 | (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) | |
52 | ||
53 | #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ | |
54 | pci_read_config_byte(dev, vsec + 0xa, dest) | |
55 | #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ | |
56 | pci_write_config_byte(dev, vsec + 0xa, val) | |
57 | #define CXL_VSEC_PROTOCOL_MASK 0xe0 | |
58 | #define CXL_VSEC_PROTOCOL_1024TB 0x80 | |
59 | #define CXL_VSEC_PROTOCOL_512TB 0x40 | |
60 | #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */ | |
61 | #define CXL_VSEC_PROTOCOL_ENABLE 0x01 | |
62 | ||
63 | #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ | |
64 | pci_read_config_word(dev, vsec + 0xc, dest) | |
65 | #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ | |
66 | pci_read_config_byte(dev, vsec + 0xe, dest) | |
67 | #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ | |
68 | pci_read_config_byte(dev, vsec + 0xf, dest) | |
69 | #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ | |
70 | pci_read_config_word(dev, vsec + 0x10, dest) | |
71 | ||
72 | #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ | |
73 | pci_read_config_byte(dev, vsec + 0x13, dest) | |
74 | #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ | |
75 | pci_write_config_byte(dev, vsec + 0x13, val) | |
76 | #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ | |
77 | #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ | |
78 | #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ | |
79 | ||
80 | #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ | |
81 | pci_read_config_dword(dev, vsec + 0x20, dest) | |
82 | #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ | |
83 | pci_read_config_dword(dev, vsec + 0x24, dest) | |
84 | #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ | |
85 | pci_read_config_dword(dev, vsec + 0x28, dest) | |
86 | #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ | |
87 | pci_read_config_dword(dev, vsec + 0x2c, dest) | |
88 | ||
89 | ||
90 | /* This works a little different than the p1/p2 register accesses to make it | |
91 | * easier to pull out individual fields */ | |
92 | #define AFUD_READ(afu, off) in_be64(afu->afu_desc_mmio + off) | |
93 | #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) | |
94 | #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) | |
95 | ||
96 | #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) | |
97 | #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) | |
98 | #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) | |
99 | #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) | |
100 | #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) | |
101 | #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) | |
102 | #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) | |
103 | #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) | |
104 | #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) | |
105 | #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) | |
106 | #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
107 | #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) | |
108 | #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) | |
109 | #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) | |
110 | #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) | |
111 | #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
112 | #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) | |
113 | #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) | |
114 | #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
115 | #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) | |
116 | ||
b087e619 IM |
117 | u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off) |
118 | { | |
119 | u64 aligned_off = off & ~0x3L; | |
120 | u32 val; | |
121 | ||
122 | val = cxl_afu_cr_read32(afu, cr, aligned_off); | |
123 | return (val >> ((off & 0x2) * 8)) & 0xffff; | |
124 | } | |
125 | ||
126 | u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off) | |
127 | { | |
128 | u64 aligned_off = off & ~0x3L; | |
129 | u32 val; | |
130 | ||
131 | val = cxl_afu_cr_read32(afu, cr, aligned_off); | |
132 | return (val >> ((off & 0x3) * 8)) & 0xff; | |
133 | } | |
134 | ||
f204e0b8 IM |
135 | static DEFINE_PCI_DEVICE_TABLE(cxl_pci_tbl) = { |
136 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, | |
137 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, | |
138 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, | |
139 | { PCI_DEVICE_CLASS(0x120000, ~0), }, | |
140 | ||
141 | { } | |
142 | }; | |
143 | MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); | |
144 | ||
145 | ||
146 | /* | |
147 | * Mostly using these wrappers to avoid confusion: | |
148 | * priv 1 is BAR2, while priv 2 is BAR0 | |
149 | */ | |
150 | static inline resource_size_t p1_base(struct pci_dev *dev) | |
151 | { | |
152 | return pci_resource_start(dev, 2); | |
153 | } | |
154 | ||
155 | static inline resource_size_t p1_size(struct pci_dev *dev) | |
156 | { | |
157 | return pci_resource_len(dev, 2); | |
158 | } | |
159 | ||
160 | static inline resource_size_t p2_base(struct pci_dev *dev) | |
161 | { | |
162 | return pci_resource_start(dev, 0); | |
163 | } | |
164 | ||
165 | static inline resource_size_t p2_size(struct pci_dev *dev) | |
166 | { | |
167 | return pci_resource_len(dev, 0); | |
168 | } | |
169 | ||
170 | static int find_cxl_vsec(struct pci_dev *dev) | |
171 | { | |
172 | int vsec = 0; | |
173 | u16 val; | |
174 | ||
175 | while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { | |
176 | pci_read_config_word(dev, vsec + 0x4, &val); | |
177 | if (val == CXL_PCI_VSEC_ID) | |
178 | return vsec; | |
179 | } | |
180 | return 0; | |
181 | ||
182 | } | |
183 | ||
184 | static void dump_cxl_config_space(struct pci_dev *dev) | |
185 | { | |
186 | int vsec; | |
187 | u32 val; | |
188 | ||
189 | dev_info(&dev->dev, "dump_cxl_config_space\n"); | |
190 | ||
191 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); | |
192 | dev_info(&dev->dev, "BAR0: %#.8x\n", val); | |
193 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); | |
194 | dev_info(&dev->dev, "BAR1: %#.8x\n", val); | |
195 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); | |
196 | dev_info(&dev->dev, "BAR2: %#.8x\n", val); | |
197 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); | |
198 | dev_info(&dev->dev, "BAR3: %#.8x\n", val); | |
199 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); | |
200 | dev_info(&dev->dev, "BAR4: %#.8x\n", val); | |
201 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); | |
202 | dev_info(&dev->dev, "BAR5: %#.8x\n", val); | |
203 | ||
204 | dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", | |
205 | p1_base(dev), p1_size(dev)); | |
206 | dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", | |
207 | p1_base(dev), p2_size(dev)); | |
208 | dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", | |
209 | pci_resource_start(dev, 4), pci_resource_len(dev, 4)); | |
210 | ||
211 | if (!(vsec = find_cxl_vsec(dev))) | |
212 | return; | |
213 | ||
214 | #define show_reg(name, what) \ | |
215 | dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) | |
216 | ||
217 | pci_read_config_dword(dev, vsec + 0x0, &val); | |
218 | show_reg("Cap ID", (val >> 0) & 0xffff); | |
219 | show_reg("Cap Ver", (val >> 16) & 0xf); | |
220 | show_reg("Next Cap Ptr", (val >> 20) & 0xfff); | |
221 | pci_read_config_dword(dev, vsec + 0x4, &val); | |
222 | show_reg("VSEC ID", (val >> 0) & 0xffff); | |
223 | show_reg("VSEC Rev", (val >> 16) & 0xf); | |
224 | show_reg("VSEC Length", (val >> 20) & 0xfff); | |
225 | pci_read_config_dword(dev, vsec + 0x8, &val); | |
226 | show_reg("Num AFUs", (val >> 0) & 0xff); | |
227 | show_reg("Status", (val >> 8) & 0xff); | |
228 | show_reg("Mode Control", (val >> 16) & 0xff); | |
229 | show_reg("Reserved", (val >> 24) & 0xff); | |
230 | pci_read_config_dword(dev, vsec + 0xc, &val); | |
231 | show_reg("PSL Rev", (val >> 0) & 0xffff); | |
232 | show_reg("CAIA Ver", (val >> 16) & 0xffff); | |
233 | pci_read_config_dword(dev, vsec + 0x10, &val); | |
234 | show_reg("Base Image Rev", (val >> 0) & 0xffff); | |
235 | show_reg("Reserved", (val >> 16) & 0x0fff); | |
236 | show_reg("Image Control", (val >> 28) & 0x3); | |
237 | show_reg("Reserved", (val >> 30) & 0x1); | |
238 | show_reg("Image Loaded", (val >> 31) & 0x1); | |
239 | ||
240 | pci_read_config_dword(dev, vsec + 0x14, &val); | |
241 | show_reg("Reserved", val); | |
242 | pci_read_config_dword(dev, vsec + 0x18, &val); | |
243 | show_reg("Reserved", val); | |
244 | pci_read_config_dword(dev, vsec + 0x1c, &val); | |
245 | show_reg("Reserved", val); | |
246 | ||
247 | pci_read_config_dword(dev, vsec + 0x20, &val); | |
248 | show_reg("AFU Descriptor Offset", val); | |
249 | pci_read_config_dword(dev, vsec + 0x24, &val); | |
250 | show_reg("AFU Descriptor Size", val); | |
251 | pci_read_config_dword(dev, vsec + 0x28, &val); | |
252 | show_reg("Problem State Offset", val); | |
253 | pci_read_config_dword(dev, vsec + 0x2c, &val); | |
254 | show_reg("Problem State Size", val); | |
255 | ||
256 | pci_read_config_dword(dev, vsec + 0x30, &val); | |
257 | show_reg("Reserved", val); | |
258 | pci_read_config_dword(dev, vsec + 0x34, &val); | |
259 | show_reg("Reserved", val); | |
260 | pci_read_config_dword(dev, vsec + 0x38, &val); | |
261 | show_reg("Reserved", val); | |
262 | pci_read_config_dword(dev, vsec + 0x3c, &val); | |
263 | show_reg("Reserved", val); | |
264 | ||
265 | pci_read_config_dword(dev, vsec + 0x40, &val); | |
266 | show_reg("PSL Programming Port", val); | |
267 | pci_read_config_dword(dev, vsec + 0x44, &val); | |
268 | show_reg("PSL Programming Control", val); | |
269 | ||
270 | pci_read_config_dword(dev, vsec + 0x48, &val); | |
271 | show_reg("Reserved", val); | |
272 | pci_read_config_dword(dev, vsec + 0x4c, &val); | |
273 | show_reg("Reserved", val); | |
274 | ||
275 | pci_read_config_dword(dev, vsec + 0x50, &val); | |
276 | show_reg("Flash Address Register", val); | |
277 | pci_read_config_dword(dev, vsec + 0x54, &val); | |
278 | show_reg("Flash Size Register", val); | |
279 | pci_read_config_dword(dev, vsec + 0x58, &val); | |
280 | show_reg("Flash Status/Control Register", val); | |
281 | pci_read_config_dword(dev, vsec + 0x58, &val); | |
282 | show_reg("Flash Data Port", val); | |
283 | ||
284 | #undef show_reg | |
285 | } | |
286 | ||
287 | static void dump_afu_descriptor(struct cxl_afu *afu) | |
288 | { | |
289 | u64 val; | |
290 | ||
291 | #define show_reg(name, what) \ | |
292 | dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) | |
293 | ||
294 | val = AFUD_READ_INFO(afu); | |
295 | show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); | |
296 | show_reg("num_of_processes", AFUD_NUM_PROCS(val)); | |
297 | show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); | |
298 | show_reg("req_prog_mode", val & 0xffffULL); | |
299 | ||
300 | val = AFUD_READ(afu, 0x8); | |
301 | show_reg("Reserved", val); | |
302 | val = AFUD_READ(afu, 0x10); | |
303 | show_reg("Reserved", val); | |
304 | val = AFUD_READ(afu, 0x18); | |
305 | show_reg("Reserved", val); | |
306 | ||
307 | val = AFUD_READ_CR(afu); | |
308 | show_reg("Reserved", (val >> (63-7)) & 0xff); | |
309 | show_reg("AFU_CR_len", AFUD_CR_LEN(val)); | |
310 | ||
311 | val = AFUD_READ_CR_OFF(afu); | |
312 | show_reg("AFU_CR_offset", val); | |
313 | ||
314 | val = AFUD_READ_PPPSA(afu); | |
315 | show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); | |
316 | show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); | |
317 | ||
318 | val = AFUD_READ_PPPSA_OFF(afu); | |
319 | show_reg("PerProcessPSA_offset", val); | |
320 | ||
321 | val = AFUD_READ_EB(afu); | |
322 | show_reg("Reserved", (val >> (63-7)) & 0xff); | |
323 | show_reg("AFU_EB_len", AFUD_EB_LEN(val)); | |
324 | ||
325 | val = AFUD_READ_EB_OFF(afu); | |
326 | show_reg("AFU_EB_offset", val); | |
327 | ||
328 | #undef show_reg | |
329 | } | |
330 | ||
331 | static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev) | |
332 | { | |
333 | struct device_node *np; | |
334 | const __be32 *prop; | |
335 | u64 psl_dsnctl; | |
336 | u64 chipid; | |
337 | ||
6f963ec2 | 338 | if (!(np = pnv_pci_get_phb_node(dev))) |
f204e0b8 IM |
339 | return -ENODEV; |
340 | ||
341 | while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) | |
342 | np = of_get_next_parent(np); | |
343 | if (!np) | |
344 | return -ENODEV; | |
345 | chipid = be32_to_cpup(prop); | |
346 | of_node_put(np); | |
347 | ||
348 | /* Tell PSL where to route data to */ | |
349 | psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5)); | |
350 | cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); | |
351 | cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); | |
352 | /* snoop write mask */ | |
353 | cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); | |
354 | /* set fir_accum */ | |
355 | cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL); | |
356 | /* for debugging with trace arrays */ | |
357 | cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int init_implementation_afu_regs(struct cxl_afu *afu) | |
363 | { | |
364 | /* read/write masks for this slice */ | |
365 | cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); | |
366 | /* APC read/write masks for this slice */ | |
367 | cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); | |
368 | /* for debugging with trace arrays */ | |
369 | cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); | |
d6a6af2c | 370 | cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S); |
f204e0b8 IM |
371 | |
372 | return 0; | |
373 | } | |
374 | ||
375 | int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, | |
376 | unsigned int virq) | |
377 | { | |
378 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
379 | ||
380 | return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); | |
381 | } | |
382 | ||
4beb5421 RG |
383 | int cxl_update_image_control(struct cxl *adapter) |
384 | { | |
385 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
386 | int rc; | |
387 | int vsec; | |
388 | u8 image_state; | |
389 | ||
390 | if (!(vsec = find_cxl_vsec(dev))) { | |
391 | dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); | |
392 | return -ENODEV; | |
393 | } | |
394 | ||
395 | if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { | |
396 | dev_err(&dev->dev, "failed to read image state: %i\n", rc); | |
397 | return rc; | |
398 | } | |
399 | ||
400 | if (adapter->perst_loads_image) | |
401 | image_state |= CXL_VSEC_PERST_LOADS_IMAGE; | |
402 | else | |
403 | image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE; | |
404 | ||
405 | if (adapter->perst_select_user) | |
406 | image_state |= CXL_VSEC_PERST_SELECT_USER; | |
407 | else | |
408 | image_state &= ~CXL_VSEC_PERST_SELECT_USER; | |
409 | ||
410 | if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { | |
411 | dev_err(&dev->dev, "failed to update image control: %i\n", rc); | |
412 | return rc; | |
413 | } | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
f204e0b8 IM |
418 | int cxl_alloc_one_irq(struct cxl *adapter) |
419 | { | |
420 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
421 | ||
422 | return pnv_cxl_alloc_hwirqs(dev, 1); | |
423 | } | |
424 | ||
425 | void cxl_release_one_irq(struct cxl *adapter, int hwirq) | |
426 | { | |
427 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
428 | ||
429 | return pnv_cxl_release_hwirqs(dev, hwirq, 1); | |
430 | } | |
431 | ||
432 | int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num) | |
433 | { | |
434 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
435 | ||
436 | return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); | |
437 | } | |
438 | ||
439 | void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter) | |
440 | { | |
441 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
442 | ||
443 | pnv_cxl_release_hwirq_ranges(irqs, dev); | |
444 | } | |
445 | ||
446 | static int setup_cxl_bars(struct pci_dev *dev) | |
447 | { | |
448 | /* Safety check in case we get backported to < 3.17 without M64 */ | |
449 | if ((p1_base(dev) < 0x100000000ULL) || | |
450 | (p2_base(dev) < 0x100000000ULL)) { | |
451 | dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); | |
452 | return -ENODEV; | |
453 | } | |
454 | ||
455 | /* | |
456 | * BAR 4/5 has a special meaning for CXL and must be programmed with a | |
457 | * special value corresponding to the CXL protocol address range. | |
458 | * For POWER 8 that means bits 48:49 must be set to 10 | |
459 | */ | |
460 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); | |
461 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */ | |
467 | static int switch_card_to_cxl(struct pci_dev *dev) | |
468 | { | |
469 | int vsec; | |
470 | u8 val; | |
471 | int rc; | |
472 | ||
473 | dev_info(&dev->dev, "switch card to CXL\n"); | |
474 | ||
475 | if (!(vsec = find_cxl_vsec(dev))) { | |
476 | dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); | |
477 | return -ENODEV; | |
478 | } | |
479 | ||
480 | if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { | |
481 | dev_err(&dev->dev, "failed to read current mode control: %i", rc); | |
482 | return rc; | |
483 | } | |
484 | val &= ~CXL_VSEC_PROTOCOL_MASK; | |
485 | val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; | |
486 | if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { | |
487 | dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc); | |
488 | return rc; | |
489 | } | |
490 | /* | |
491 | * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states | |
492 | * we must wait 100ms after this mode switch before touching | |
493 | * PCIe config space. | |
494 | */ | |
495 | msleep(100); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) | |
501 | { | |
502 | u64 p1n_base, p2n_base, afu_desc; | |
503 | const u64 p1n_size = 0x100; | |
504 | const u64 p2n_size = 0x1000; | |
505 | ||
506 | p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); | |
507 | p2n_base = p2_base(dev) + (afu->slice * p2n_size); | |
508 | afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size)); | |
509 | afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size); | |
510 | ||
511 | if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size))) | |
512 | goto err; | |
513 | if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) | |
514 | goto err1; | |
515 | if (afu_desc) { | |
516 | if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size))) | |
517 | goto err2; | |
518 | } | |
519 | ||
520 | return 0; | |
521 | err2: | |
522 | iounmap(afu->p2n_mmio); | |
523 | err1: | |
524 | iounmap(afu->p1n_mmio); | |
525 | err: | |
526 | dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); | |
527 | return -ENOMEM; | |
528 | } | |
529 | ||
530 | static void cxl_unmap_slice_regs(struct cxl_afu *afu) | |
531 | { | |
532 | if (afu->p1n_mmio) | |
533 | iounmap(afu->p2n_mmio); | |
534 | if (afu->p1n_mmio) | |
535 | iounmap(afu->p1n_mmio); | |
536 | } | |
537 | ||
538 | static void cxl_release_afu(struct device *dev) | |
539 | { | |
540 | struct cxl_afu *afu = to_cxl_afu(dev); | |
541 | ||
542 | pr_devel("cxl_release_afu\n"); | |
543 | ||
544 | kfree(afu); | |
545 | } | |
546 | ||
547 | static struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice) | |
548 | { | |
549 | struct cxl_afu *afu; | |
550 | ||
551 | if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL))) | |
552 | return NULL; | |
553 | ||
554 | afu->adapter = adapter; | |
555 | afu->dev.parent = &adapter->dev; | |
556 | afu->dev.release = cxl_release_afu; | |
557 | afu->slice = slice; | |
558 | idr_init(&afu->contexts_idr); | |
ee41d11d | 559 | mutex_init(&afu->contexts_lock); |
f204e0b8 IM |
560 | spin_lock_init(&afu->afu_cntl_lock); |
561 | mutex_init(&afu->spa_mutex); | |
562 | ||
563 | afu->prefault_mode = CXL_PREFAULT_NONE; | |
564 | afu->irqs_max = afu->adapter->user_irqs; | |
565 | ||
566 | return afu; | |
567 | } | |
568 | ||
569 | /* Expects AFU struct to have recently been zeroed out */ | |
570 | static int cxl_read_afu_descriptor(struct cxl_afu *afu) | |
571 | { | |
572 | u64 val; | |
573 | ||
574 | val = AFUD_READ_INFO(afu); | |
575 | afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); | |
576 | afu->max_procs_virtualised = AFUD_NUM_PROCS(val); | |
b087e619 | 577 | afu->crs_num = AFUD_NUM_CRS(val); |
f204e0b8 IM |
578 | |
579 | if (AFUD_AFU_DIRECTED(val)) | |
580 | afu->modes_supported |= CXL_MODE_DIRECTED; | |
581 | if (AFUD_DEDICATED_PROCESS(val)) | |
582 | afu->modes_supported |= CXL_MODE_DEDICATED; | |
583 | if (AFUD_TIME_SLICED(val)) | |
584 | afu->modes_supported |= CXL_MODE_TIME_SLICED; | |
585 | ||
586 | val = AFUD_READ_PPPSA(afu); | |
587 | afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; | |
588 | afu->psa = AFUD_PPPSA_PSA(val); | |
589 | if ((afu->pp_psa = AFUD_PPPSA_PP(val))) | |
590 | afu->pp_offset = AFUD_READ_PPPSA_OFF(afu); | |
591 | ||
b087e619 IM |
592 | val = AFUD_READ_CR(afu); |
593 | afu->crs_len = AFUD_CR_LEN(val) * 256; | |
594 | afu->crs_offset = AFUD_READ_CR_OFF(afu); | |
595 | ||
f204e0b8 IM |
596 | return 0; |
597 | } | |
598 | ||
599 | static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) | |
600 | { | |
3d5be039 IM |
601 | int i; |
602 | ||
f204e0b8 IM |
603 | if (afu->psa && afu->adapter->ps_size < |
604 | (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { | |
605 | dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); | |
606 | return -ENODEV; | |
607 | } | |
608 | ||
609 | if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) | |
610 | dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!"); | |
611 | ||
3d5be039 IM |
612 | for (i = 0; i < afu->crs_num; i++) { |
613 | if ((cxl_afu_cr_read32(afu, i, 0) == 0)) { | |
614 | dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); | |
615 | return -EINVAL; | |
616 | } | |
617 | } | |
618 | ||
f204e0b8 IM |
619 | return 0; |
620 | } | |
621 | ||
622 | static int sanitise_afu_regs(struct cxl_afu *afu) | |
623 | { | |
624 | u64 reg; | |
625 | ||
626 | /* | |
627 | * Clear out any regs that contain either an IVTE or address or may be | |
628 | * waiting on an acknowledgement to try to be a bit safer as we bring | |
629 | * it online | |
630 | */ | |
631 | reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
632 | if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { | |
633 | dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg); | |
634 | if (cxl_afu_reset(afu)) | |
635 | return -EIO; | |
636 | if (cxl_afu_disable(afu)) | |
637 | return -EIO; | |
638 | if (cxl_psl_purge(afu)) | |
639 | return -EIO; | |
640 | } | |
641 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); | |
642 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); | |
643 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); | |
644 | cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); | |
645 | cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); | |
646 | cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); | |
647 | cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); | |
648 | cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); | |
649 | cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); | |
650 | cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); | |
651 | cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); | |
652 | reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
653 | if (reg) { | |
654 | dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg); | |
655 | if (reg & CXL_PSL_DSISR_TRANS) | |
656 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
657 | else | |
658 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
659 | } | |
660 | reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
661 | if (reg) { | |
662 | if (reg & ~0xffff) | |
663 | dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg); | |
664 | cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); | |
665 | } | |
666 | reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
667 | if (reg) { | |
668 | dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg); | |
669 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); | |
670 | } | |
671 | ||
672 | return 0; | |
673 | } | |
674 | ||
675 | static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) | |
676 | { | |
677 | struct cxl_afu *afu; | |
678 | bool free = true; | |
679 | int rc; | |
680 | ||
681 | if (!(afu = cxl_alloc_afu(adapter, slice))) | |
682 | return -ENOMEM; | |
683 | ||
684 | if ((rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice))) | |
685 | goto err1; | |
686 | ||
687 | if ((rc = cxl_map_slice_regs(afu, adapter, dev))) | |
688 | goto err1; | |
689 | ||
690 | if ((rc = sanitise_afu_regs(afu))) | |
691 | goto err2; | |
692 | ||
693 | /* We need to reset the AFU before we can read the AFU descriptor */ | |
694 | if ((rc = cxl_afu_reset(afu))) | |
695 | goto err2; | |
696 | ||
697 | if (cxl_verbose) | |
698 | dump_afu_descriptor(afu); | |
699 | ||
700 | if ((rc = cxl_read_afu_descriptor(afu))) | |
701 | goto err2; | |
702 | ||
703 | if ((rc = cxl_afu_descriptor_looks_ok(afu))) | |
704 | goto err2; | |
705 | ||
706 | if ((rc = init_implementation_afu_regs(afu))) | |
707 | goto err2; | |
708 | ||
709 | if ((rc = cxl_register_serr_irq(afu))) | |
710 | goto err2; | |
711 | ||
712 | if ((rc = cxl_register_psl_irq(afu))) | |
713 | goto err3; | |
714 | ||
715 | /* Don't care if this fails */ | |
716 | cxl_debugfs_afu_add(afu); | |
717 | ||
718 | /* | |
719 | * After we call this function we must not free the afu directly, even | |
720 | * if it returns an error! | |
721 | */ | |
722 | if ((rc = cxl_register_afu(afu))) | |
723 | goto err_put1; | |
724 | ||
725 | if ((rc = cxl_sysfs_afu_add(afu))) | |
726 | goto err_put1; | |
727 | ||
728 | ||
729 | if ((rc = cxl_afu_select_best_mode(afu))) | |
730 | goto err_put2; | |
731 | ||
732 | adapter->afu[afu->slice] = afu; | |
733 | ||
734 | return 0; | |
735 | ||
736 | err_put2: | |
737 | cxl_sysfs_afu_remove(afu); | |
738 | err_put1: | |
739 | device_unregister(&afu->dev); | |
740 | free = false; | |
741 | cxl_debugfs_afu_remove(afu); | |
742 | cxl_release_psl_irq(afu); | |
743 | err3: | |
744 | cxl_release_serr_irq(afu); | |
745 | err2: | |
746 | cxl_unmap_slice_regs(afu); | |
747 | err1: | |
748 | if (free) | |
749 | kfree(afu); | |
750 | return rc; | |
751 | } | |
752 | ||
753 | static void cxl_remove_afu(struct cxl_afu *afu) | |
754 | { | |
755 | pr_devel("cxl_remove_afu\n"); | |
756 | ||
757 | if (!afu) | |
758 | return; | |
759 | ||
760 | cxl_sysfs_afu_remove(afu); | |
761 | cxl_debugfs_afu_remove(afu); | |
762 | ||
763 | spin_lock(&afu->adapter->afu_list_lock); | |
764 | afu->adapter->afu[afu->slice] = NULL; | |
765 | spin_unlock(&afu->adapter->afu_list_lock); | |
766 | ||
767 | cxl_context_detach_all(afu); | |
768 | cxl_afu_deactivate_mode(afu); | |
769 | ||
770 | cxl_release_psl_irq(afu); | |
771 | cxl_release_serr_irq(afu); | |
772 | cxl_unmap_slice_regs(afu); | |
773 | ||
774 | device_unregister(&afu->dev); | |
775 | } | |
776 | ||
62fa19d4 RG |
777 | int cxl_reset(struct cxl *adapter) |
778 | { | |
779 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
780 | int rc; | |
781 | int i; | |
782 | u32 val; | |
783 | ||
784 | dev_info(&dev->dev, "CXL reset\n"); | |
785 | ||
786 | for (i = 0; i < adapter->slices; i++) | |
787 | cxl_remove_afu(adapter->afu[i]); | |
788 | ||
789 | /* pcie_warm_reset requests a fundamental pci reset which includes a | |
790 | * PERST assert/deassert. PERST triggers a loading of the image | |
791 | * if "user" or "factory" is selected in sysfs */ | |
792 | if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { | |
793 | dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); | |
794 | return rc; | |
795 | } | |
796 | ||
797 | /* the PERST done above fences the PHB. So, reset depends on EEH | |
798 | * to unbind the driver, tell Sapphire to reinit the PHB, and rebind | |
799 | * the driver. Do an mmio read explictly to ensure EEH notices the | |
800 | * fenced PHB. Retry for a few seconds before giving up. */ | |
801 | i = 0; | |
802 | while (((val = mmio_read32be(adapter->p1_mmio)) != 0xffffffff) && | |
803 | (i < 5)) { | |
804 | msleep(500); | |
805 | i++; | |
806 | } | |
807 | ||
808 | if (val != 0xffffffff) | |
809 | dev_err(&dev->dev, "cxl: PERST failed to trigger EEH\n"); | |
810 | ||
811 | return rc; | |
812 | } | |
f204e0b8 IM |
813 | |
814 | static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) | |
815 | { | |
816 | if (pci_request_region(dev, 2, "priv 2 regs")) | |
817 | goto err1; | |
818 | if (pci_request_region(dev, 0, "priv 1 regs")) | |
819 | goto err2; | |
820 | ||
821 | pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx", | |
822 | p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); | |
823 | ||
824 | if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) | |
825 | goto err3; | |
826 | ||
827 | if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) | |
828 | goto err4; | |
829 | ||
830 | return 0; | |
831 | ||
832 | err4: | |
833 | iounmap(adapter->p1_mmio); | |
834 | adapter->p1_mmio = NULL; | |
835 | err3: | |
836 | pci_release_region(dev, 0); | |
837 | err2: | |
838 | pci_release_region(dev, 2); | |
839 | err1: | |
840 | return -ENOMEM; | |
841 | } | |
842 | ||
843 | static void cxl_unmap_adapter_regs(struct cxl *adapter) | |
844 | { | |
845 | if (adapter->p1_mmio) | |
846 | iounmap(adapter->p1_mmio); | |
847 | if (adapter->p2_mmio) | |
848 | iounmap(adapter->p2_mmio); | |
849 | } | |
850 | ||
851 | static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) | |
852 | { | |
853 | int vsec; | |
854 | u32 afu_desc_off, afu_desc_size; | |
855 | u32 ps_off, ps_size; | |
856 | u16 vseclen; | |
857 | u8 image_state; | |
858 | ||
859 | if (!(vsec = find_cxl_vsec(dev))) { | |
860 | dev_err(&adapter->dev, "ABORTING: CXL VSEC not found!\n"); | |
861 | return -ENODEV; | |
862 | } | |
863 | ||
864 | CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); | |
865 | if (vseclen < CXL_VSEC_MIN_SIZE) { | |
866 | pr_err("ABORTING: CXL VSEC too short\n"); | |
867 | return -EINVAL; | |
868 | } | |
869 | ||
870 | CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); | |
871 | CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); | |
872 | CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); | |
873 | CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); | |
874 | CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); | |
875 | CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); | |
876 | adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); | |
4beb5421 RG |
877 | adapter->perst_loads_image = true; |
878 | adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); | |
f204e0b8 IM |
879 | |
880 | CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); | |
881 | CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); | |
882 | CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); | |
883 | CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); | |
884 | CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); | |
885 | ||
886 | /* Convert everything to bytes, because there is NO WAY I'd look at the | |
887 | * code a month later and forget what units these are in ;-) */ | |
888 | adapter->ps_off = ps_off * 64 * 1024; | |
889 | adapter->ps_size = ps_size * 64 * 1024; | |
890 | adapter->afu_desc_off = afu_desc_off * 64 * 1024; | |
891 | adapter->afu_desc_size = afu_desc_size *64 * 1024; | |
892 | ||
893 | /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ | |
894 | adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) | |
900 | { | |
901 | if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) | |
902 | return -EBUSY; | |
903 | ||
904 | if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { | |
905 | dev_err(&adapter->dev, "ABORTING: CXL requires unsupported features\n"); | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | if (!adapter->slices) { | |
910 | /* Once we support dynamic reprogramming we can use the card if | |
911 | * it supports loadable AFUs */ | |
912 | dev_err(&adapter->dev, "ABORTING: Device has no AFUs\n"); | |
913 | return -EINVAL; | |
914 | } | |
915 | ||
916 | if (!adapter->afu_desc_off || !adapter->afu_desc_size) { | |
917 | dev_err(&adapter->dev, "ABORTING: VSEC shows no AFU descriptors\n"); | |
918 | return -EINVAL; | |
919 | } | |
920 | ||
921 | if (adapter->ps_size > p2_size(dev) - adapter->ps_off) { | |
922 | dev_err(&adapter->dev, "ABORTING: Problem state size larger than " | |
923 | "available in BAR2: 0x%llx > 0x%llx\n", | |
924 | adapter->ps_size, p2_size(dev) - adapter->ps_off); | |
925 | return -EINVAL; | |
926 | } | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
931 | static void cxl_release_adapter(struct device *dev) | |
932 | { | |
933 | struct cxl *adapter = to_cxl_adapter(dev); | |
934 | ||
935 | pr_devel("cxl_release_adapter\n"); | |
936 | ||
937 | kfree(adapter); | |
938 | } | |
939 | ||
940 | static struct cxl *cxl_alloc_adapter(struct pci_dev *dev) | |
941 | { | |
942 | struct cxl *adapter; | |
943 | ||
944 | if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL))) | |
945 | return NULL; | |
946 | ||
947 | adapter->dev.parent = &dev->dev; | |
948 | adapter->dev.release = cxl_release_adapter; | |
949 | pci_set_drvdata(dev, adapter); | |
950 | spin_lock_init(&adapter->afu_list_lock); | |
951 | ||
952 | return adapter; | |
953 | } | |
954 | ||
955 | static int sanitise_adapter_regs(struct cxl *adapter) | |
956 | { | |
957 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); | |
958 | return cxl_tlb_slb_invalidate(adapter); | |
959 | } | |
960 | ||
961 | static struct cxl *cxl_init_adapter(struct pci_dev *dev) | |
962 | { | |
963 | struct cxl *adapter; | |
964 | bool free = true; | |
965 | int rc; | |
966 | ||
967 | ||
968 | if (!(adapter = cxl_alloc_adapter(dev))) | |
969 | return ERR_PTR(-ENOMEM); | |
970 | ||
971 | if ((rc = switch_card_to_cxl(dev))) | |
972 | goto err1; | |
973 | ||
974 | if ((rc = cxl_alloc_adapter_nr(adapter))) | |
975 | goto err1; | |
976 | ||
977 | if ((rc = dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))) | |
978 | goto err2; | |
979 | ||
980 | if ((rc = cxl_read_vsec(adapter, dev))) | |
981 | goto err2; | |
982 | ||
983 | if ((rc = cxl_vsec_looks_ok(adapter, dev))) | |
984 | goto err2; | |
985 | ||
4beb5421 RG |
986 | if ((rc = cxl_update_image_control(adapter))) |
987 | goto err2; | |
988 | ||
f204e0b8 IM |
989 | if ((rc = cxl_map_adapter_regs(adapter, dev))) |
990 | goto err2; | |
991 | ||
992 | if ((rc = sanitise_adapter_regs(adapter))) | |
993 | goto err2; | |
994 | ||
995 | if ((rc = init_implementation_adapter_regs(adapter, dev))) | |
996 | goto err3; | |
997 | ||
1212aa1c | 998 | if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI))) |
f204e0b8 IM |
999 | goto err3; |
1000 | ||
1212aa1c RG |
1001 | /* If recovery happened, the last step is to turn on snooping. |
1002 | * In the non-recovery case this has no effect */ | |
1003 | if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) { | |
1004 | goto err3; | |
1005 | } | |
1006 | ||
f204e0b8 IM |
1007 | if ((rc = cxl_register_psl_err_irq(adapter))) |
1008 | goto err3; | |
1009 | ||
1010 | /* Don't care if this one fails: */ | |
1011 | cxl_debugfs_adapter_add(adapter); | |
1012 | ||
1013 | /* | |
1014 | * After we call this function we must not free the adapter directly, | |
1015 | * even if it returns an error! | |
1016 | */ | |
1017 | if ((rc = cxl_register_adapter(adapter))) | |
1018 | goto err_put1; | |
1019 | ||
1020 | if ((rc = cxl_sysfs_adapter_add(adapter))) | |
1021 | goto err_put1; | |
1022 | ||
1023 | return adapter; | |
1024 | ||
1025 | err_put1: | |
1026 | device_unregister(&adapter->dev); | |
1027 | free = false; | |
1028 | cxl_debugfs_adapter_remove(adapter); | |
1029 | cxl_release_psl_err_irq(adapter); | |
1030 | err3: | |
1031 | cxl_unmap_adapter_regs(adapter); | |
1032 | err2: | |
1033 | cxl_remove_adapter_nr(adapter); | |
1034 | err1: | |
1035 | if (free) | |
1036 | kfree(adapter); | |
1037 | return ERR_PTR(rc); | |
1038 | } | |
1039 | ||
1040 | static void cxl_remove_adapter(struct cxl *adapter) | |
1041 | { | |
1042 | struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); | |
1043 | ||
1044 | pr_devel("cxl_release_adapter\n"); | |
1045 | ||
1046 | cxl_sysfs_adapter_remove(adapter); | |
1047 | cxl_debugfs_adapter_remove(adapter); | |
1048 | cxl_release_psl_err_irq(adapter); | |
1049 | cxl_unmap_adapter_regs(adapter); | |
1050 | cxl_remove_adapter_nr(adapter); | |
1051 | ||
1052 | device_unregister(&adapter->dev); | |
1053 | ||
1054 | pci_release_region(pdev, 0); | |
1055 | pci_release_region(pdev, 2); | |
1056 | pci_disable_device(pdev); | |
1057 | } | |
1058 | ||
1059 | static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
1060 | { | |
1061 | struct cxl *adapter; | |
1062 | int slice; | |
1063 | int rc; | |
1064 | ||
1065 | pci_dev_get(dev); | |
1066 | ||
1067 | if (cxl_verbose) | |
1068 | dump_cxl_config_space(dev); | |
1069 | ||
1070 | if ((rc = setup_cxl_bars(dev))) | |
1071 | return rc; | |
1072 | ||
1073 | if ((rc = pci_enable_device(dev))) { | |
1074 | dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); | |
1075 | return rc; | |
1076 | } | |
1077 | ||
1078 | adapter = cxl_init_adapter(dev); | |
1079 | if (IS_ERR(adapter)) { | |
1080 | dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); | |
1081 | return PTR_ERR(adapter); | |
1082 | } | |
1083 | ||
1084 | for (slice = 0; slice < adapter->slices; slice++) { | |
1085 | if ((rc = cxl_init_afu(adapter, slice, dev))) | |
1086 | dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); | |
1087 | } | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static void cxl_remove(struct pci_dev *dev) | |
1093 | { | |
1094 | struct cxl *adapter = pci_get_drvdata(dev); | |
1095 | int afu; | |
1096 | ||
1097 | dev_warn(&dev->dev, "pci remove\n"); | |
1098 | ||
1099 | /* | |
1100 | * Lock to prevent someone grabbing a ref through the adapter list as | |
1101 | * we are removing it | |
1102 | */ | |
1103 | for (afu = 0; afu < adapter->slices; afu++) | |
1104 | cxl_remove_afu(adapter->afu[afu]); | |
1105 | cxl_remove_adapter(adapter); | |
1106 | } | |
1107 | ||
1108 | struct pci_driver cxl_pci_driver = { | |
1109 | .name = "cxl-pci", | |
1110 | .id_table = cxl_pci_tbl, | |
1111 | .probe = cxl_probe, | |
1112 | .remove = cxl_remove, | |
1113 | }; |