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6f7f0b3d MN |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/pci.h> | |
11 | #include <misc/cxl.h> | |
12 | #include "cxl.h" | |
13 | ||
14 | static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) | |
15 | { | |
16 | if (dma_mask < DMA_BIT_MASK(64)) { | |
17 | pr_info("%s only 64bit DMA supported on CXL", __func__); | |
18 | return -EIO; | |
19 | } | |
20 | ||
21 | *(pdev->dev.dma_mask) = dma_mask; | |
22 | return 0; | |
23 | } | |
24 | ||
25 | static int cxl_pci_probe_mode(struct pci_bus *bus) | |
26 | { | |
27 | return PCI_PROBE_NORMAL; | |
28 | } | |
29 | ||
30 | static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
31 | { | |
32 | return -ENODEV; | |
33 | } | |
34 | ||
35 | static void cxl_teardown_msi_irqs(struct pci_dev *pdev) | |
36 | { | |
37 | /* | |
38 | * MSI should never be set but need still need to provide this call | |
39 | * back. | |
40 | */ | |
41 | } | |
42 | ||
43 | static bool cxl_pci_enable_device_hook(struct pci_dev *dev) | |
44 | { | |
45 | struct pci_controller *phb; | |
46 | struct cxl_afu *afu; | |
47 | struct cxl_context *ctx; | |
48 | ||
49 | phb = pci_bus_to_host(dev->bus); | |
50 | afu = (struct cxl_afu *)phb->private_data; | |
51 | set_dma_ops(&dev->dev, &dma_direct_ops); | |
52 | set_dma_offset(&dev->dev, PAGE_OFFSET); | |
53 | ||
54 | /* | |
55 | * Allocate a context to do cxl things too. If we eventually do real | |
56 | * DMA ops, we'll need a default context to attach them to | |
57 | */ | |
58 | ctx = cxl_dev_context_init(dev); | |
59 | if (!ctx) | |
60 | return false; | |
61 | dev->dev.archdata.cxl_ctx = ctx; | |
62 | ||
63 | return (cxl_afu_check_and_enable(afu) == 0); | |
64 | } | |
65 | ||
66 | static void cxl_pci_disable_device(struct pci_dev *dev) | |
67 | { | |
68 | struct cxl_context *ctx = cxl_get_context(dev); | |
69 | ||
70 | if (ctx) { | |
71 | if (ctx->status == STARTED) { | |
72 | dev_err(&dev->dev, "Default context started\n"); | |
73 | return; | |
74 | } | |
75 | cxl_release_context(ctx); | |
76 | } | |
77 | } | |
78 | ||
79 | static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus, | |
80 | unsigned long type) | |
81 | { | |
82 | return 1; | |
83 | } | |
84 | ||
85 | static void cxl_pci_reset_secondary_bus(struct pci_dev *dev) | |
86 | { | |
87 | /* Should we do an AFU reset here ? */ | |
88 | } | |
89 | ||
90 | static int cxl_pcie_cfg_record(u8 bus, u8 devfn) | |
91 | { | |
92 | return (bus << 8) + devfn; | |
93 | } | |
94 | ||
95 | static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb, | |
96 | u8 bus, u8 devfn, int offset) | |
97 | { | |
98 | int record = cxl_pcie_cfg_record(bus, devfn); | |
99 | ||
100 | return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset; | |
101 | } | |
102 | ||
103 | ||
104 | static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn, | |
105 | int offset, int len, | |
106 | volatile void __iomem **ioaddr, | |
107 | u32 *mask, int *shift) | |
108 | { | |
109 | struct pci_controller *phb; | |
110 | struct cxl_afu *afu; | |
111 | unsigned long addr; | |
112 | ||
113 | phb = pci_bus_to_host(bus); | |
114 | afu = (struct cxl_afu *)phb->private_data; | |
115 | if (phb == NULL) | |
116 | return PCIBIOS_DEVICE_NOT_FOUND; | |
117 | if (cxl_pcie_cfg_record(bus->number, devfn) > afu->crs_num) | |
118 | return PCIBIOS_DEVICE_NOT_FOUND; | |
119 | if (offset >= (unsigned long)phb->cfg_data) | |
120 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
121 | addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset); | |
122 | ||
123 | *ioaddr = (void *)(addr & ~0x3ULL); | |
124 | *shift = ((addr & 0x3) * 8); | |
125 | switch (len) { | |
126 | case 1: | |
127 | *mask = 0xff; | |
128 | break; | |
129 | case 2: | |
130 | *mask = 0xffff; | |
131 | break; | |
132 | default: | |
133 | *mask = 0xffffffff; | |
134 | break; | |
135 | } | |
136 | return 0; | |
137 | } | |
138 | ||
139 | static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn, | |
140 | int offset, int len, u32 *val) | |
141 | { | |
142 | volatile void __iomem *ioaddr; | |
143 | int shift, rc; | |
144 | u32 mask; | |
145 | ||
146 | rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr, | |
147 | &mask, &shift); | |
148 | if (rc) | |
149 | return rc; | |
150 | ||
151 | /* Can only read 32 bits */ | |
152 | *val = (in_le32(ioaddr) >> shift) & mask; | |
153 | return PCIBIOS_SUCCESSFUL; | |
154 | } | |
155 | ||
156 | static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn, | |
157 | int offset, int len, u32 val) | |
158 | { | |
159 | volatile void __iomem *ioaddr; | |
160 | u32 v, mask; | |
161 | int shift, rc; | |
162 | ||
163 | rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr, | |
164 | &mask, &shift); | |
165 | if (rc) | |
166 | return rc; | |
167 | ||
168 | /* Can only write 32 bits so do read-modify-write */ | |
169 | mask <<= shift; | |
170 | val <<= shift; | |
171 | ||
172 | v = (in_le32(ioaddr) & ~mask) || (val & mask); | |
173 | ||
174 | out_le32(ioaddr, v); | |
175 | return PCIBIOS_SUCCESSFUL; | |
176 | } | |
177 | ||
178 | static struct pci_ops cxl_pcie_pci_ops = | |
179 | { | |
180 | .read = cxl_pcie_read_config, | |
181 | .write = cxl_pcie_write_config, | |
182 | }; | |
183 | ||
184 | ||
185 | static struct pci_controller_ops cxl_pci_controller_ops = | |
186 | { | |
187 | .probe_mode = cxl_pci_probe_mode, | |
188 | .enable_device_hook = cxl_pci_enable_device_hook, | |
189 | .disable_device = cxl_pci_disable_device, | |
190 | .release_device = cxl_pci_disable_device, | |
191 | .window_alignment = cxl_pci_window_alignment, | |
192 | .reset_secondary_bus = cxl_pci_reset_secondary_bus, | |
193 | .setup_msi_irqs = cxl_setup_msi_irqs, | |
194 | .teardown_msi_irqs = cxl_teardown_msi_irqs, | |
195 | .dma_set_mask = cxl_dma_set_mask, | |
196 | }; | |
197 | ||
198 | int cxl_pci_vphb_add(struct cxl_afu *afu) | |
199 | { | |
200 | struct pci_dev *phys_dev; | |
201 | struct pci_controller *phb, *phys_phb; | |
202 | ||
203 | phys_dev = to_pci_dev(afu->adapter->dev.parent); | |
204 | phys_phb = pci_bus_to_host(phys_dev->bus); | |
205 | ||
206 | /* Alloc and setup PHB data structure */ | |
207 | phb = pcibios_alloc_controller(phys_phb->dn); | |
208 | ||
209 | if (!phb) | |
210 | return -ENODEV; | |
211 | ||
212 | /* Setup parent in sysfs */ | |
213 | phb->parent = &phys_dev->dev; | |
214 | ||
215 | /* Setup the PHB using arch provided callback */ | |
216 | phb->ops = &cxl_pcie_pci_ops; | |
217 | phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset; | |
218 | phb->cfg_data = (void *)(u64)afu->crs_len; | |
219 | phb->private_data = afu; | |
220 | phb->controller_ops = cxl_pci_controller_ops; | |
221 | ||
222 | /* Scan the bus */ | |
223 | pcibios_scan_phb(phb); | |
224 | if (phb->bus == NULL) | |
225 | return -ENXIO; | |
226 | ||
227 | /* Claim resources. This might need some rework as well depending | |
228 | * whether we are doing probe-only or not, like assigning unassigned | |
229 | * resources etc... | |
230 | */ | |
231 | pcibios_claim_one_bus(phb->bus); | |
232 | ||
233 | /* Add probed PCI devices to the device model */ | |
234 | pci_bus_add_devices(phb->bus); | |
235 | ||
236 | afu->phb = phb; | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
241 | ||
242 | void cxl_pci_vphb_remove(struct cxl_afu *afu) | |
243 | { | |
244 | struct pci_controller *phb; | |
245 | ||
246 | /* If there is no configuration record we won't have one of these */ | |
247 | if (!afu || !afu->phb) | |
248 | return; | |
249 | ||
250 | phb = afu->phb; | |
251 | ||
252 | pci_remove_root_bus(phb->bus); | |
253 | } | |
254 | ||
255 | struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev) | |
256 | { | |
257 | struct pci_controller *phb; | |
258 | ||
259 | phb = pci_bus_to_host(dev->bus); | |
260 | ||
261 | return (struct cxl_afu *)phb->private_data; | |
262 | } | |
263 | EXPORT_SYMBOL_GPL(cxl_pci_to_afu); | |
264 | ||
265 | unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev) | |
266 | { | |
267 | return cxl_pcie_cfg_record(dev->bus->number, dev->devfn); | |
268 | } | |
269 | EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record); |