[deliverable/linux.git] / drivers / misc / eeprom / at25.c

/*
 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
 *
 * Copyright (C) 2006 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/sched.h>

#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>


/*
 * NOTE: this is an *EEPROM* driver.  The vagaries of product naming
 * mean that some AT25 products are EEPROMs, and others are FLASH.
 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
 * not this one!
 */

struct at25_data {
	struct spi_device	*spi;
	struct memory_accessor	mem;
	struct mutex		lock;
	struct spi_eeprom	chip;
	struct bin_attribute	bin;
	unsigned		addrlen;
};

#define	AT25_WREN	0x06		/* latch the write enable */
#define	AT25_WRDI	0x04		/* reset the write enable */
#define	AT25_RDSR	0x05		/* read status register */
#define	AT25_WRSR	0x01		/* write status register */
#define	AT25_READ	0x03		/* read byte(s) */
#define	AT25_WRITE	0x02		/* write byte(s)/sector */

#define	AT25_SR_nRDY	0x01		/* nRDY = write-in-progress */
#define	AT25_SR_WEN	0x02		/* write enable (latched) */
#define	AT25_SR_BP0	0x04		/* BP for software writeprotect */
#define	AT25_SR_BP1	0x08
#define	AT25_SR_WPEN	0x80		/* writeprotect enable */

#define	AT25_INSTR_BIT3	0x08		/* Additional address bit in instr */

#define EE_MAXADDRLEN	3		/* 24 bit addresses, up to 2 MBytes */

/* Specs often allow 5 msec for a page write, sometimes 20 msec;
 * it's important to recover from write timeouts.
 */
#define	EE_TIMEOUT	25

/*-------------------------------------------------------------------------*/

#define	io_limit	PAGE_SIZE	/* bytes */

static ssize_t
at25_ee_read(
	struct at25_data	*at25,
	char			*buf,
	unsigned		offset,
	size_t			count
)
{
	u8			command[EE_MAXADDRLEN + 1];
	u8			*cp;
	ssize_t			status;
	struct spi_transfer	t[2];
	struct spi_message	m;
	u8			instr;

	if (unlikely(offset >= at25->bin.size))
		return 0;
	if ((offset + count) > at25->bin.size)
		count = at25->bin.size - offset;
	if (unlikely(!count))
		return count;

	cp = command;

	instr = AT25_READ;
	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
		if (offset >= (1U << (at25->addrlen * 8)))
			instr |= AT25_INSTR_BIT3;
	*cp++ = instr;

	/* 8/16/24-bit address is written MSB first */
	switch (at25->addrlen) {
	default:	/* case 3 */
		*cp++ = offset >> 16;
	case 2:
		*cp++ = offset >> 8;
	case 1:
	case 0:	/* can't happen: for better codegen */
		*cp++ = offset >> 0;
	}

	spi_message_init(&m);
	memset(t, 0, sizeof t);

	t[0].tx_buf = command;
	t[0].len = at25->addrlen + 1;
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = count;
	spi_message_add_tail(&t[1], &m);

	mutex_lock(&at25->lock);

	/* Read it all at once.
	 *
	 * REVISIT that's potentially a problem with large chips, if
	 * other devices on the bus need to be accessed regularly or
	 * this chip is clocked very slowly
	 */
	status = spi_sync(at25->spi, &m);
	dev_dbg(&at25->spi->dev,
		"read %Zd bytes at %d --> %d\n",
		count, offset, (int) status);

	mutex_unlock(&at25->lock);
	return status ? status : count;
}

static ssize_t
at25_bin_read(struct file *filp, struct kobject *kobj,
	      struct bin_attribute *bin_attr,
	      char *buf, loff_t off, size_t count)
{
	struct device		*dev;
	struct at25_data	*at25;

	dev = container_of(kobj, struct device, kobj);
	at25 = dev_get_drvdata(dev);

	return at25_ee_read(at25, buf, off, count);
}


static ssize_t
at25_ee_write(struct at25_data *at25, const char *buf, loff_t off,
	      size_t count)
{
	ssize_t			status = 0;
	unsigned		written = 0;
	unsigned		buf_size;
	u8			*bounce;

	if (unlikely(off >= at25->bin.size))
		return -EFBIG;
	if ((off + count) > at25->bin.size)
		count = at25->bin.size - off;
	if (unlikely(!count))
		return count;

	/* Temp buffer starts with command and address */
	buf_size = at25->chip.page_size;
	if (buf_size > io_limit)
		buf_size = io_limit;
	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	if (!bounce)
		return -ENOMEM;

	/* For write, rollover is within the page ... so we write at
	 * most one page, then manually roll over to the next page.
	 */
	mutex_lock(&at25->lock);
	do {
		unsigned long	timeout, retries;
		unsigned	segment;
		unsigned	offset = (unsigned) off;
		u8		*cp = bounce;
		int		sr;
		u8		instr;

		*cp = AT25_WREN;
		status = spi_write(at25->spi, cp, 1);
		if (status < 0) {
			dev_dbg(&at25->spi->dev, "WREN --> %d\n",
					(int) status);
			break;
		}

		instr = AT25_WRITE;
		if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
			if (offset >= (1U << (at25->addrlen * 8)))
				instr |= AT25_INSTR_BIT3;
		*cp++ = instr;

		/* 8/16/24-bit address is written MSB first */
		switch (at25->addrlen) {
		default:	/* case 3 */
			*cp++ = offset >> 16;
		case 2:
			*cp++ = offset >> 8;
		case 1:
		case 0:	/* can't happen: for better codegen */
			*cp++ = offset >> 0;
		}

		/* Write as much of a page as we can */
		segment = buf_size - (offset % buf_size);
		if (segment > count)
			segment = count;
		memcpy(cp, buf, segment);
		status = spi_write(at25->spi, bounce,
				segment + at25->addrlen + 1);
		dev_dbg(&at25->spi->dev,
				"write %u bytes at %u --> %d\n",
				segment, offset, (int) status);
		if (status < 0)
			break;

		/* REVISIT this should detect (or prevent) failed writes
		 * to readonly sections of the EEPROM...
		 */

		/* Wait for non-busy status */
		timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
		retries = 0;
		do {

			sr = spi_w8r8(at25->spi, AT25_RDSR);
			if (sr < 0 || (sr & AT25_SR_nRDY)) {
				dev_dbg(&at25->spi->dev,
					"rdsr --> %d (%02x)\n", sr, sr);
				/* at HZ=100, this is sloooow */
				msleep(1);
				continue;
			}
			if (!(sr & AT25_SR_nRDY))
				break;
		} while (retries++ < 3 || time_before_eq(jiffies, timeout));

		if ((sr < 0) || (sr & AT25_SR_nRDY)) {
			dev_err(&at25->spi->dev,
				"write %d bytes offset %d, "
				"timeout after %u msecs\n",
				segment, offset,
				jiffies_to_msecs(jiffies -
					(timeout - EE_TIMEOUT)));
			status = -ETIMEDOUT;
			break;
		}

		off += segment;
		buf += segment;
		count -= segment;
		written += segment;

	} while (count > 0);

	mutex_unlock(&at25->lock);

	kfree(bounce);
	return written ? written : status;
}

static ssize_t
at25_bin_write(struct file *filp, struct kobject *kobj,
	       struct bin_attribute *bin_attr,
	       char *buf, loff_t off, size_t count)
{
	struct device		*dev;
	struct at25_data	*at25;

	dev = container_of(kobj, struct device, kobj);
	at25 = dev_get_drvdata(dev);

	return at25_ee_write(at25, buf, off, count);
}

/*-------------------------------------------------------------------------*/

/* Let in-kernel code access the eeprom data. */

static ssize_t at25_mem_read(struct memory_accessor *mem, char *buf,
			 off_t offset, size_t count)
{
	struct at25_data *at25 = container_of(mem, struct at25_data, mem);

	return at25_ee_read(at25, buf, offset, count);
}

static ssize_t at25_mem_write(struct memory_accessor *mem, const char *buf,
			  off_t offset, size_t count)
{
	struct at25_data *at25 = container_of(mem, struct at25_data, mem);

	return at25_ee_write(at25, buf, offset, count);
}

/*-------------------------------------------------------------------------*/

static int at25_probe(struct spi_device *spi)
{
	struct at25_data	*at25 = NULL;
	const struct spi_eeprom *chip;
	int			err;
	int			sr;
	int			addrlen;

	/* Chip description */
	chip = spi->dev.platform_data;
	if (!chip) {
		dev_dbg(&spi->dev, "no chip description\n");
		err = -ENODEV;
		goto fail;
	}

	/* For now we only support 8/16/24 bit addressing */
	if (chip->flags & EE_ADDR1)
		addrlen = 1;
	else if (chip->flags & EE_ADDR2)
		addrlen = 2;
	else if (chip->flags & EE_ADDR3)
		addrlen = 3;
	else {
		dev_dbg(&spi->dev, "unsupported address type\n");
		err = -EINVAL;
		goto fail;
	}

	/* Ping the chip ... the status register is pretty portable,
	 * unlike probing manufacturer IDs.  We do expect that system
	 * firmware didn't write it in the past few milliseconds!
	 */
	sr = spi_w8r8(spi, AT25_RDSR);
	if (sr < 0 || sr & AT25_SR_nRDY) {
		dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
		err = -ENXIO;
		goto fail;
	}

	if (!(at25 = kzalloc(sizeof *at25, GFP_KERNEL))) {
		err = -ENOMEM;
		goto fail;
	}

	mutex_init(&at25->lock);
	at25->chip = *chip;
	at25->spi = spi_dev_get(spi);
	dev_set_drvdata(&spi->dev, at25);
	at25->addrlen = addrlen;

	/* Export the EEPROM bytes through sysfs, since that's convenient.
	 * And maybe to other kernel code; it might hold a board's Ethernet
	 * address, or board-specific calibration data generated on the
	 * manufacturing floor.
	 *
	 * Default to root-only access to the data; EEPROMs often hold data
	 * that's sensitive for read and/or write, like ethernet addresses,
	 * security codes, board-specific manufacturing calibrations, etc.
	 */
	sysfs_bin_attr_init(&at25->bin);
	at25->bin.attr.name = "eeprom";
	at25->bin.attr.mode = S_IRUSR;
	at25->bin.read = at25_bin_read;
	at25->mem.read = at25_mem_read;

	at25->bin.size = at25->chip.byte_len;
	if (!(chip->flags & EE_READONLY)) {
		at25->bin.write = at25_bin_write;
		at25->bin.attr.mode |= S_IWUSR;
		at25->mem.write = at25_mem_write;
	}

	err = sysfs_create_bin_file(&spi->dev.kobj, &at25->bin);
	if (err)
		goto fail;

	if (chip->setup)
		chip->setup(&at25->mem, chip->context);

	dev_info(&spi->dev, "%Zd %s %s eeprom%s, pagesize %u\n",
		(at25->bin.size < 1024)
			? at25->bin.size
			: (at25->bin.size / 1024),
		(at25->bin.size < 1024) ? "Byte" : "KByte",
		at25->chip.name,
		(chip->flags & EE_READONLY) ? " (readonly)" : "",
		at25->chip.page_size);
	return 0;
fail:
	dev_dbg(&spi->dev, "probe err %d\n", err);
	kfree(at25);
	return err;
}

static int __devexit at25_remove(struct spi_device *spi)
{
	struct at25_data	*at25;

	at25 = dev_get_drvdata(&spi->dev);
	sysfs_remove_bin_file(&spi->dev.kobj, &at25->bin);
	kfree(at25);
	return 0;
}

/*-------------------------------------------------------------------------*/

static struct spi_driver at25_driver = {
	.driver = {
		.name		= "at25",
		.owner		= THIS_MODULE,
	},
	.probe		= at25_probe,
	.remove		= __devexit_p(at25_remove),
};

module_spi_driver(at25_driver);

MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
MODULE_AUTHOR("David Brownell");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:at25");
Commit	Line	Data
b587b13a DB	1	/*
	2	* at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
	3	*
	4	* Copyright (C) 2006 David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/delay.h>
	17	#include <linux/device.h>
	18	#include <linux/sched.h>
	19
	20	#include <linux/spi/spi.h>
	21	#include <linux/spi/eeprom.h>
	22
	23
3f86f14c DB	24	/*
	25	* NOTE: this is an EEPROM driver. The vagaries of product naming
	26	* mean that some AT25 products are EEPROMs, and others are FLASH.
	27	* Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
	28	* not this one!
	29	*/
	30
b587b13a DB	31	struct at25_data {
b587b13a DB	32	struct spi_device *spi;
14dd1ff0	33	struct memory_accessor mem;
b587b13a DB	34	struct mutex lock;
	35	struct spi_eeprom chip;
	36	struct bin_attribute bin;
	37	unsigned addrlen;
	38	};
	39
	40	#define AT25_WREN 0x06 /* latch the write enable */
	41	#define AT25_WRDI 0x04 /* reset the write enable */
	42	#define AT25_RDSR 0x05 /* read status register */
	43	#define AT25_WRSR 0x01 /* write status register */
	44	#define AT25_READ 0x03 /* read byte(s) */
	45	#define AT25_WRITE 0x02 /* write byte(s)/sector */
	46
	47	#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
	48	#define AT25_SR_WEN 0x02 /* write enable (latched) */
	49	#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
	50	#define AT25_SR_BP1 0x08
	51	#define AT25_SR_WPEN 0x80 /* writeprotect enable */
	52
b4161f0b	53	#define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
b587b13a DB	54
	55	#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
	56
	57	/* Specs often allow 5 msec for a page write, sometimes 20 msec;
	58	* it's important to recover from write timeouts.
	59	*/
	60	#define EE_TIMEOUT 25
	61
	62	/-------------------------------------------------------------------------/
	63
	64	#define io_limit PAGE_SIZE /* bytes */
	65
	66	static ssize_t
	67	at25_ee_read(
	68	struct at25_data *at25,
	69	char *buf,
	70	unsigned offset,
	71	size_t count
	72	)
	73	{
	74	u8 command[EE_MAXADDRLEN + 1];
	75	u8 *cp;
	76	ssize_t status;
	77	struct spi_transfer t[2];
	78	struct spi_message m;
b4161f0b	79	u8 instr;
b587b13a	80
14dd1ff0 DB	81	if (unlikely(offset >= at25->bin.size))
	82	return 0;
	83	if ((offset + count) > at25->bin.size)
	84	count = at25->bin.size - offset;
	85	if (unlikely(!count))
	86	return count;
	87
b587b13a	88	cp = command;
b4161f0b IS	89
	90	instr = AT25_READ;
	91	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	92	if (offset >= (1U << (at25->addrlen * 8)))
	93	instr \|= AT25_INSTR_BIT3;
	94	*cp++ = instr;
b587b13a DB	95
	96	/* 8/16/24-bit address is written MSB first */
	97	switch (at25->addrlen) {
	98	default: /* case 3 */
	99	*cp++ = offset >> 16;
	100	case 2:
	101	*cp++ = offset >> 8;
	102	case 1:
	103	case 0: /* can't happen: for better codegen */
	104	*cp++ = offset >> 0;
	105	}
	106
	107	spi_message_init(&m);
	108	memset(t, 0, sizeof t);
	109
	110	t[0].tx_buf = command;
	111	t[0].len = at25->addrlen + 1;
	112	spi_message_add_tail(&t[0], &m);
	113
	114	t[1].rx_buf = buf;
	115	t[1].len = count;
	116	spi_message_add_tail(&t[1], &m);
	117
	118	mutex_lock(&at25->lock);
	119
	120	/* Read it all at once.
	121	*
	122	* REVISIT that's potentially a problem with large chips, if
	123	* other devices on the bus need to be accessed regularly or
	124	* this chip is clocked very slowly
	125	*/
	126	status = spi_sync(at25->spi, &m);
	127	dev_dbg(&at25->spi->dev,
	128	"read %Zd bytes at %d --> %d\n",
	129	count, offset, (int) status);
	130
	131	mutex_unlock(&at25->lock);
	132	return status ? status : count;
	133	}
	134
	135	static ssize_t
2c3c8bea CW	136	at25_bin_read(struct file filp, struct kobject kobj,
2c3c8bea CW	137	struct bin_attribute *bin_attr,
91a69029	138	char *buf, loff_t off, size_t count)
b587b13a DB	139	{
	140	struct device *dev;
	141	struct at25_data *at25;
	142
	143	dev = container_of(kobj, struct device, kobj);
	144	at25 = dev_get_drvdata(dev);
	145
b587b13a DB	146	return at25_ee_read(at25, buf, off, count);
	147	}
	148
	149
	150	static ssize_t
4cafbd0b GU	151	at25_ee_write(struct at25_data at25, const char buf, loff_t off,
4cafbd0b GU	152	size_t count)
b587b13a DB	153	{
	154	ssize_t status = 0;
	155	unsigned written = 0;
	156	unsigned buf_size;
	157	u8 *bounce;
	158
14dd1ff0 DB	159	if (unlikely(off >= at25->bin.size))
	160	return -EFBIG;
	161	if ((off + count) > at25->bin.size)
	162	count = at25->bin.size - off;
	163	if (unlikely(!count))
	164	return count;
	165
b587b13a DB	166	/* Temp buffer starts with command and address */
	167	buf_size = at25->chip.page_size;
	168	if (buf_size > io_limit)
	169	buf_size = io_limit;
	170	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	171	if (!bounce)
	172	return -ENOMEM;
	173
	174	/* For write, rollover is within the page ... so we write at
	175	* most one page, then manually roll over to the next page.
	176	*/
b587b13a DB	177	mutex_lock(&at25->lock);
	178	do {
	179	unsigned long timeout, retries;
	180	unsigned segment;
	181	unsigned offset = (unsigned) off;
b4161f0b	182	u8 *cp = bounce;
f0d83679	183	int sr;
b4161f0b	184	u8 instr;
b587b13a DB	185
	186	*cp = AT25_WREN;
	187	status = spi_write(at25->spi, cp, 1);
	188	if (status < 0) {
	189	dev_dbg(&at25->spi->dev, "WREN --> %d\n",
	190	(int) status);
	191	break;
	192	}
	193
b4161f0b IS	194	instr = AT25_WRITE;
	195	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	196	if (offset >= (1U << (at25->addrlen * 8)))
	197	instr \|= AT25_INSTR_BIT3;
	198	*cp++ = instr;
	199
b587b13a DB	200	/* 8/16/24-bit address is written MSB first */
	201	switch (at25->addrlen) {
	202	default: /* case 3 */
	203	*cp++ = offset >> 16;
	204	case 2:
	205	*cp++ = offset >> 8;
	206	case 1:
	207	case 0: /* can't happen: for better codegen */
	208	*cp++ = offset >> 0;
	209	}
	210
	211	/* Write as much of a page as we can */
	212	segment = buf_size - (offset % buf_size);
	213	if (segment > count)
	214	segment = count;
	215	memcpy(cp, buf, segment);
	216	status = spi_write(at25->spi, bounce,
	217	segment + at25->addrlen + 1);
	218	dev_dbg(&at25->spi->dev,
	219	"write %u bytes at %u --> %d\n",
	220	segment, offset, (int) status);
	221	if (status < 0)
	222	break;
	223
	224	/* REVISIT this should detect (or prevent) failed writes
	225	* to readonly sections of the EEPROM...
	226	*/
	227
	228	/* Wait for non-busy status */
	229	timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
	230	retries = 0;
	231	do {
b587b13a DB	232
	233	sr = spi_w8r8(at25->spi, AT25_RDSR);
	234	if (sr < 0 \|\| (sr & AT25_SR_nRDY)) {
	235	dev_dbg(&at25->spi->dev,
	236	"rdsr --> %d (%02x)\n", sr, sr);
	237	/* at HZ=100, this is sloooow */
	238	msleep(1);
	239	continue;
	240	}
	241	if (!(sr & AT25_SR_nRDY))
	242	break;
	243	} while (retries++ < 3 \|\| time_before_eq(jiffies, timeout));
	244
f0d83679	245	if ((sr < 0) \|\| (sr & AT25_SR_nRDY)) {
b587b13a DB	246	dev_err(&at25->spi->dev,
	247	"write %d bytes offset %d, "
	248	"timeout after %u msecs\n",
	249	segment, offset,
	250	jiffies_to_msecs(jiffies -
	251	(timeout - EE_TIMEOUT)));
	252	status = -ETIMEDOUT;
	253	break;
	254	}
	255
	256	off += segment;
	257	buf += segment;
	258	count -= segment;
	259	written += segment;
	260
	261	} while (count > 0);
	262
	263	mutex_unlock(&at25->lock);
	264
	265	kfree(bounce);
	266	return written ? written : status;
	267	}
	268
	269	static ssize_t
2c3c8bea CW	270	at25_bin_write(struct file filp, struct kobject kobj,
2c3c8bea CW	271	struct bin_attribute *bin_attr,
91a69029	272	char *buf, loff_t off, size_t count)
b587b13a DB	273	{
	274	struct device *dev;
	275	struct at25_data *at25;
	276
	277	dev = container_of(kobj, struct device, kobj);
	278	at25 = dev_get_drvdata(dev);
	279
b587b13a DB	280	return at25_ee_write(at25, buf, off, count);
	281	}
	282
	283	/-------------------------------------------------------------------------/
	284
14dd1ff0 DB	285	/* Let in-kernel code access the eeprom data. */
	286
	287	static ssize_t at25_mem_read(struct memory_accessor mem, char buf,
	288	off_t offset, size_t count)
	289	{
	290	struct at25_data *at25 = container_of(mem, struct at25_data, mem);
	291
	292	return at25_ee_read(at25, buf, offset, count);
	293	}
	294
4cafbd0b	295	static ssize_t at25_mem_write(struct memory_accessor mem, const char buf,
14dd1ff0 DB	296	off_t offset, size_t count)
	297	{
	298	struct at25_data *at25 = container_of(mem, struct at25_data, mem);
	299
	300	return at25_ee_write(at25, buf, offset, count);
	301	}
	302
	303	/-------------------------------------------------------------------------/
	304
b587b13a DB	305	static int at25_probe(struct spi_device *spi)
	306	{
	307	struct at25_data *at25 = NULL;
	308	const struct spi_eeprom *chip;
	309	int err;
	310	int sr;
	311	int addrlen;
	312
	313	/* Chip description */
	314	chip = spi->dev.platform_data;
	315	if (!chip) {
	316	dev_dbg(&spi->dev, "no chip description\n");
	317	err = -ENODEV;
	318	goto fail;
	319	}
	320
	321	/* For now we only support 8/16/24 bit addressing */
	322	if (chip->flags & EE_ADDR1)
	323	addrlen = 1;
	324	else if (chip->flags & EE_ADDR2)
	325	addrlen = 2;
	326	else if (chip->flags & EE_ADDR3)
	327	addrlen = 3;
	328	else {
	329	dev_dbg(&spi->dev, "unsupported address type\n");
	330	err = -EINVAL;
	331	goto fail;
	332	}
	333
	334	/* Ping the chip ... the status register is pretty portable,
	335	* unlike probing manufacturer IDs. We do expect that system
	336	* firmware didn't write it in the past few milliseconds!
	337	*/
	338	sr = spi_w8r8(spi, AT25_RDSR);
	339	if (sr < 0 \|\| sr & AT25_SR_nRDY) {
c6ca97d2	340	dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
b587b13a DB	341	err = -ENXIO;
	342	goto fail;
	343	}
	344
	345	if (!(at25 = kzalloc(sizeof *at25, GFP_KERNEL))) {
	346	err = -ENOMEM;
	347	goto fail;
	348	}
	349
	350	mutex_init(&at25->lock);
	351	at25->chip = *chip;
	352	at25->spi = spi_dev_get(spi);
	353	dev_set_drvdata(&spi->dev, at25);
	354	at25->addrlen = addrlen;
	355
	356	/* Export the EEPROM bytes through sysfs, since that's convenient.
14dd1ff0 DB	357	* And maybe to other kernel code; it might hold a board's Ethernet
	358	* address, or board-specific calibration data generated on the
	359	* manufacturing floor.
	360	*
b587b13a DB	361	* Default to root-only access to the data; EEPROMs often hold data
	362	* that's sensitive for read and/or write, like ethernet addresses,
	363	* security codes, board-specific manufacturing calibrations, etc.
	364	*/
f937331b	365	sysfs_bin_attr_init(&at25->bin);
b587b13a DB	366	at25->bin.attr.name = "eeprom";
b587b13a DB	367	at25->bin.attr.mode = S_IRUSR;
b587b13a	368	at25->bin.read = at25_bin_read;
14dd1ff0	369	at25->mem.read = at25_mem_read;
b587b13a DB	370
	371	at25->bin.size = at25->chip.byte_len;
	372	if (!(chip->flags & EE_READONLY)) {
	373	at25->bin.write = at25_bin_write;
	374	at25->bin.attr.mode \|= S_IWUSR;
14dd1ff0	375	at25->mem.write = at25_mem_write;
b587b13a DB	376	}
	377
	378	err = sysfs_create_bin_file(&spi->dev.kobj, &at25->bin);
	379	if (err)
	380	goto fail;
	381
14dd1ff0 DB	382	if (chip->setup)
	383	chip->setup(&at25->mem, chip->context);
	384
b587b13a DB	385	dev_info(&spi->dev, "%Zd %s %s eeprom%s, pagesize %u\n",
	386	(at25->bin.size < 1024)
	387	? at25->bin.size
	388	: (at25->bin.size / 1024),
	389	(at25->bin.size < 1024) ? "Byte" : "KByte",
	390	at25->chip.name,
	391	(chip->flags & EE_READONLY) ? " (readonly)" : "",
	392	at25->chip.page_size);
	393	return 0;
	394	fail:
	395	dev_dbg(&spi->dev, "probe err %d\n", err);
	396	kfree(at25);
	397	return err;
	398	}
	399
	400	static int __devexit at25_remove(struct spi_device *spi)
	401	{
	402	struct at25_data *at25;
	403
	404	at25 = dev_get_drvdata(&spi->dev);
	405	sysfs_remove_bin_file(&spi->dev.kobj, &at25->bin);
	406	kfree(at25);
	407	return 0;
	408	}
	409
	410	/-------------------------------------------------------------------------/
	411
	412	static struct spi_driver at25_driver = {
	413	.driver = {
	414	.name = "at25",
	415	.owner = THIS_MODULE,
	416	},
	417	.probe = at25_probe,
	418	.remove = __devexit_p(at25_remove),
	419	};
	420
a3dc3c9e	421	module_spi_driver(at25_driver);
b587b13a DB	422
	423	MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
	424	MODULE_AUTHOR("David Brownell");
	425	MODULE_LICENSE("GPL");
e0626e38	426	MODULE_ALIAS("spi:at25");