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1 | /* |
2 | * linux/drivers/char/hpilo.h | |
3 | * | |
4 | * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. | |
5 | * David Altobelli <david.altobelli@hp.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __HPILO_H | |
12 | #define __HPILO_H | |
13 | ||
14 | #define ILO_NAME "hpilo" | |
15 | ||
16 | /* max number of open channel control blocks per device, hw limited to 32 */ | |
17 | #define MAX_CCB 8 | |
18 | /* max number of supported devices */ | |
19 | #define MAX_ILO_DEV 1 | |
20 | /* max number of files */ | |
21 | #define MAX_OPEN (MAX_CCB * MAX_ILO_DEV) | |
891f7d73 DA |
22 | /* total wait time in usec */ |
23 | #define MAX_WAIT_TIME 10000 | |
24 | /* per spin wait time in usec */ | |
25 | #define WAIT_TIME 10 | |
c073b2db | 26 | /* spin counter for open/close delay */ |
891f7d73 | 27 | #define MAX_WAIT (MAX_WAIT_TIME / WAIT_TIME) |
89bcb05d DA |
28 | |
29 | /* | |
30 | * Per device, used to track global memory allocations. | |
31 | */ | |
32 | struct ilo_hwinfo { | |
33 | /* mmio registers on device */ | |
34 | char __iomem *mmio_vaddr; | |
35 | ||
36 | /* doorbell registers on device */ | |
37 | char __iomem *db_vaddr; | |
38 | ||
39 | /* shared memory on device used for channel control blocks */ | |
40 | char __iomem *ram_vaddr; | |
41 | ||
42 | /* files corresponding to this device */ | |
43 | struct ccb_data *ccb_alloc[MAX_CCB]; | |
44 | ||
45 | struct pci_dev *ilo_dev; | |
46 | ||
47 | spinlock_t alloc_lock; | |
48 | spinlock_t fifo_lock; | |
9f704841 | 49 | spinlock_t open_lock; |
89bcb05d DA |
50 | |
51 | struct cdev cdev; | |
52 | }; | |
53 | ||
9f704841 DA |
54 | /* offset from mmio_vaddr for enabling doorbell interrupts */ |
55 | #define DB_IRQ 0xB2 | |
56 | /* offset from mmio_vaddr for outbound communications */ | |
89bcb05d DA |
57 | #define DB_OUT 0xD4 |
58 | /* DB_OUT reset bit */ | |
59 | #define DB_RESET 26 | |
60 | ||
61 | /* | |
62 | * Channel control block. Used to manage hardware queues. | |
63 | * The format must match hw's version. The hw ccb is 128 bytes, | |
64 | * but the context area shouldn't be touched by the driver. | |
65 | */ | |
66 | #define ILOSW_CCB_SZ 64 | |
67 | #define ILOHW_CCB_SZ 128 | |
68 | struct ccb { | |
69 | union { | |
70 | char *send_fifobar; | |
71 | u64 padding1; | |
72 | } ccb_u1; | |
73 | union { | |
74 | char *send_desc; | |
75 | u64 padding2; | |
76 | } ccb_u2; | |
77 | u64 send_ctrl; | |
78 | ||
79 | union { | |
80 | char *recv_fifobar; | |
81 | u64 padding3; | |
82 | } ccb_u3; | |
83 | union { | |
84 | char *recv_desc; | |
85 | u64 padding4; | |
86 | } ccb_u4; | |
87 | u64 recv_ctrl; | |
88 | ||
89 | union { | |
90 | char __iomem *db_base; | |
91 | u64 padding5; | |
92 | } ccb_u5; | |
93 | ||
94 | u64 channel; | |
95 | ||
96 | /* unused context area (64 bytes) */ | |
97 | }; | |
98 | ||
99 | /* ccb queue parameters */ | |
100 | #define SENDQ 1 | |
101 | #define RECVQ 2 | |
102 | #define NR_QENTRY 4 | |
103 | #define L2_QENTRY_SZ 12 | |
104 | ||
105 | /* ccb ctrl bitfields */ | |
106 | #define CTRL_BITPOS_L2SZ 0 | |
107 | #define CTRL_BITPOS_FIFOINDEXMASK 4 | |
108 | #define CTRL_BITPOS_DESCLIMIT 18 | |
109 | #define CTRL_BITPOS_A 30 | |
110 | #define CTRL_BITPOS_G 31 | |
111 | ||
112 | /* ccb doorbell macros */ | |
113 | #define L2_DB_SIZE 14 | |
114 | #define ONE_DB_SIZE (1 << L2_DB_SIZE) | |
115 | ||
116 | /* | |
117 | * Per fd structure used to track the ccb allocated to that dev file. | |
118 | */ | |
119 | struct ccb_data { | |
120 | /* software version of ccb, using virtual addrs */ | |
121 | struct ccb driver_ccb; | |
122 | ||
123 | /* hardware version of ccb, using physical addrs */ | |
124 | struct ccb ilo_ccb; | |
125 | ||
126 | /* hardware ccb is written to this shared mapped device memory */ | |
127 | struct ccb __iomem *mapped_ccb; | |
128 | ||
129 | /* dma'able memory used for send/recv queues */ | |
130 | void *dma_va; | |
131 | dma_addr_t dma_pa; | |
132 | size_t dma_size; | |
133 | ||
134 | /* pointer to hardware device info */ | |
135 | struct ilo_hwinfo *ilo_hw; | |
136 | ||
9f704841 DA |
137 | /* queue for this ccb to wait for recv data */ |
138 | wait_queue_head_t ccb_waitq; | |
139 | ||
89bcb05d DA |
140 | /* usage count, to allow for shared ccb's */ |
141 | int ccb_cnt; | |
142 | ||
143 | /* open wanted exclusive access to this ccb */ | |
144 | int ccb_excl; | |
145 | }; | |
146 | ||
147 | /* | |
148 | * FIFO queue structure, shared with hw. | |
149 | */ | |
150 | #define ILO_START_ALIGN 4096 | |
151 | #define ILO_CACHE_SZ 128 | |
152 | struct fifo { | |
153 | u64 nrents; /* user requested number of fifo entries */ | |
154 | u64 imask; /* mask to extract valid fifo index */ | |
155 | u64 merge; /* O/C bits to merge in during enqueue operation */ | |
156 | u64 reset; /* set to non-zero when the target device resets */ | |
157 | u8 pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)]; | |
158 | ||
159 | u64 head; | |
160 | u8 pad_1[ILO_CACHE_SZ - (sizeof(u64))]; | |
161 | ||
162 | u64 tail; | |
163 | u8 pad_2[ILO_CACHE_SZ - (sizeof(u64))]; | |
164 | ||
165 | u64 fifobar[1]; | |
166 | }; | |
167 | ||
168 | /* convert between struct fifo, and the fifobar, which is saved in the ccb */ | |
169 | #define FIFOHANDLESIZE (sizeof(struct fifo) - sizeof(u64)) | |
170 | #define FIFOBARTOHANDLE(_fifo) \ | |
171 | ((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE)) | |
172 | ||
173 | /* the number of qwords to consume from the entry descriptor */ | |
174 | #define ENTRY_BITPOS_QWORDS 0 | |
175 | /* descriptor index number (within a specified queue) */ | |
176 | #define ENTRY_BITPOS_DESCRIPTOR 10 | |
177 | /* state bit, fifo entry consumed by consumer */ | |
178 | #define ENTRY_BITPOS_C 22 | |
179 | /* state bit, fifo entry is occupied */ | |
180 | #define ENTRY_BITPOS_O 23 | |
181 | ||
182 | #define ENTRY_BITS_QWORDS 10 | |
183 | #define ENTRY_BITS_DESCRIPTOR 12 | |
184 | #define ENTRY_BITS_C 1 | |
185 | #define ENTRY_BITS_O 1 | |
186 | #define ENTRY_BITS_TOTAL \ | |
187 | (ENTRY_BITS_C + ENTRY_BITS_O + \ | |
188 | ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR) | |
189 | ||
190 | /* extract various entry fields */ | |
191 | #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1) | |
192 | #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C) | |
193 | #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O) | |
194 | #define ENTRY_MASK_QWORDS \ | |
195 | (((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS) | |
196 | #define ENTRY_MASK_DESCRIPTOR \ | |
197 | (((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR) | |
198 | ||
199 | #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O)) | |
200 | ||
201 | #endif /* __HPILO_H */ |