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1 | /****************************************************************************** |
2 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
3 | * Intel MEI Interface Header | |
4 | * | |
5 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
6 | * redistributing this file, you may do so under either license. | |
7 | * | |
8 | * GPL LICENSE SUMMARY | |
9 | * | |
10 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of version 2 of the GNU General Public License as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
24 | * USA | |
25 | * | |
26 | * The full GNU General Public License is included in this distribution | |
27 | * in the file called LICENSE.GPL. | |
28 | * | |
29 | * Contact Information: | |
30 | * Intel Corporation. | |
31 | * linux-mei@linux.intel.com | |
32 | * http://www.intel.com | |
33 | * | |
34 | * BSD LICENSE | |
35 | * | |
36 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. | |
37 | * All rights reserved. | |
38 | * | |
39 | * Redistribution and use in source and binary forms, with or without | |
40 | * modification, are permitted provided that the following conditions | |
41 | * are met: | |
42 | * | |
43 | * * Redistributions of source code must retain the above copyright | |
44 | * notice, this list of conditions and the following disclaimer. | |
45 | * * Redistributions in binary form must reproduce the above copyright | |
46 | * notice, this list of conditions and the following disclaimer in | |
47 | * the documentation and/or other materials provided with the | |
48 | * distribution. | |
49 | * * Neither the name Intel Corporation nor the names of its | |
50 | * contributors may be used to endorse or promote products derived | |
51 | * from this software without specific prior written permission. | |
52 | * | |
53 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
54 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
55 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
56 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
57 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
58 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
59 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
60 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
61 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
62 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
64 | * | |
65 | *****************************************************************************/ | |
66 | #ifndef _MEI_HW_MEI_REGS_H_ | |
67 | #define _MEI_HW_MEI_REGS_H_ | |
68 | ||
69 | /* | |
70 | * MEI device IDs | |
71 | */ | |
72 | #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */ | |
73 | #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */ | |
74 | #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */ | |
75 | #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */ | |
76 | ||
77 | #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */ | |
78 | #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */ | |
79 | ||
80 | #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */ | |
81 | #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */ | |
82 | #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */ | |
83 | #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */ | |
84 | #define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */ | |
85 | ||
86 | #define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */ | |
87 | #define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */ | |
88 | #define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */ | |
89 | #define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */ | |
90 | #define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */ | |
91 | ||
92 | #define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */ | |
93 | #define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */ | |
94 | #define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */ | |
95 | #define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */ | |
96 | ||
97 | #define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */ | |
98 | #define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */ | |
99 | #define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */ | |
100 | #define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */ | |
101 | ||
102 | #define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */ | |
103 | #define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */ | |
104 | ||
105 | #define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */ | |
106 | #define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */ | |
107 | ||
108 | #define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */ | |
109 | #define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */ | |
110 | #define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */ | |
111 | ||
76a96359 | 112 | #define MEI_DEV_ID_LPT_H 0x8C3A /* Lynx Point H */ |
838b3a6d | 113 | #define MEI_DEV_ID_LPT_W 0x8D3A /* Lynx Point - Wellsburg */ |
9dc64d6a | 114 | #define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */ |
76a96359 TW |
115 | #define MEI_DEV_ID_LPT_HR 0x8CBA /* Lynx Point H Refresh */ |
116 | ||
117 | #define MEI_DEV_ID_WPT_LP 0x9CBA /* Wildcat Point LP */ | |
d238a0ec | 118 | #define MEI_DEV_ID_WPT_LP_2 0x9CBB /* Wildcat Point LP 2 */ |
5e6533a6 | 119 | |
1625c7ec TW |
120 | #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */ |
121 | #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */ | |
122 | #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */ | |
123 | #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */ | |
dd16f6cd TW |
124 | |
125 | #define MEI_DEV_ID_BXT_M 0x1A9A /* Broxton M */ | |
126 | #define MEI_DEV_ID_APL_I 0x5A9A /* Apollo Lake I */ | |
127 | ||
9dc64d6a TW |
128 | /* |
129 | * MEI HW Section | |
130 | */ | |
131 | ||
edca5ea3 AU |
132 | /* Host Firmware Status Registers in PCI Config Space */ |
133 | #define PCI_CFG_HFS_1 0x40 | |
bb9f4d26 | 134 | # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000 |
edca5ea3 AU |
135 | #define PCI_CFG_HFS_2 0x48 |
136 | #define PCI_CFG_HFS_3 0x60 | |
137 | #define PCI_CFG_HFS_4 0x64 | |
138 | #define PCI_CFG_HFS_5 0x68 | |
139 | #define PCI_CFG_HFS_6 0x6C | |
140 | ||
9dc64d6a TW |
141 | /* MEI registers */ |
142 | /* H_CB_WW - Host Circular Buffer (CB) Write Window register */ | |
143 | #define H_CB_WW 0 | |
144 | /* H_CSR - Host Control Status register */ | |
145 | #define H_CSR 4 | |
146 | /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */ | |
147 | #define ME_CB_RW 8 | |
148 | /* ME_CSR_HA - ME Control Status Host Access register (read only) */ | |
149 | #define ME_CSR_HA 0xC | |
ad4d355b TW |
150 | /* H_HGC_CSR - PGI register */ |
151 | #define H_HPG_CSR 0x10 | |
11830486 TW |
152 | /* H_D0I3C - D0I3 Control */ |
153 | #define H_D0I3C 0x800 | |
9dc64d6a TW |
154 | |
155 | /* register bits of H_CSR (Host Control Status register) */ | |
156 | /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ | |
157 | #define H_CBD 0xFF000000 | |
158 | /* Host Circular Buffer Write Pointer */ | |
159 | #define H_CBWP 0x00FF0000 | |
160 | /* Host Circular Buffer Read Pointer */ | |
161 | #define H_CBRP 0x0000FF00 | |
162 | /* Host Reset */ | |
163 | #define H_RST 0x00000010 | |
164 | /* Host Ready */ | |
165 | #define H_RDY 0x00000008 | |
166 | /* Host Interrupt Generate */ | |
167 | #define H_IG 0x00000004 | |
168 | /* Host Interrupt Status */ | |
169 | #define H_IS 0x00000002 | |
170 | /* Host Interrupt Enable */ | |
171 | #define H_IE 0x00000001 | |
11830486 TW |
172 | /* Host D0I3 Interrupt Enable */ |
173 | #define H_D0I3C_IE 0x00000020 | |
174 | /* Host D0I3 Interrupt Status */ | |
175 | #define H_D0I3C_IS 0x00000040 | |
9dc64d6a | 176 | |
1fa55b4e AU |
177 | /* H_CSR masks */ |
178 | #define H_CSR_IE_MASK (H_IE | H_D0I3C_IE) | |
179 | #define H_CSR_IS_MASK (H_IS | H_D0I3C_IS) | |
180 | ||
9dc64d6a TW |
181 | /* register bits of ME_CSR_HA (ME Control Status Host Access register) */ |
182 | /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only | |
183 | access to ME_CBD */ | |
184 | #define ME_CBD_HRA 0xFF000000 | |
185 | /* ME CB Write Pointer HRA - host read only access to ME_CBWP */ | |
186 | #define ME_CBWP_HRA 0x00FF0000 | |
187 | /* ME CB Read Pointer HRA - host read only access to ME_CBRP */ | |
188 | #define ME_CBRP_HRA 0x0000FF00 | |
ad4d355b TW |
189 | /* ME Power Gate Isolation Capability HRA - host ready only access */ |
190 | #define ME_PGIC_HRA 0x00000040 | |
9dc64d6a TW |
191 | /* ME Reset HRA - host read only access to ME_RST */ |
192 | #define ME_RST_HRA 0x00000010 | |
193 | /* ME Ready HRA - host read only access to ME_RDY */ | |
194 | #define ME_RDY_HRA 0x00000008 | |
195 | /* ME Interrupt Generate HRA - host read only access to ME_IG */ | |
196 | #define ME_IG_HRA 0x00000004 | |
197 | /* ME Interrupt Status HRA - host read only access to ME_IS */ | |
198 | #define ME_IS_HRA 0x00000002 | |
199 | /* ME Interrupt Enable HRA - host read only access to ME_IE */ | |
200 | #define ME_IE_HRA 0x00000001 | |
201 | ||
ad4d355b | 202 | |
11830486 TW |
203 | /* H_HPG_CSR register bits */ |
204 | #define H_HPG_CSR_PGIHEXR 0x00000001 | |
205 | #define H_HPG_CSR_PGI 0x00000002 | |
206 | ||
207 | /* H_D0I3C register bits */ | |
208 | #define H_D0I3C_CIP 0x00000001 | |
209 | #define H_D0I3C_IR 0x00000002 | |
210 | #define H_D0I3C_I3 0x00000004 | |
211 | #define H_D0I3C_RR 0x00000008 | |
ad4d355b | 212 | |
9dc64d6a | 213 | #endif /* _MEI_HW_MEI_REGS_H_ */ |