Commit | Line | Data |
---|---|---|
3ce72726 OW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
733ba91c | 4 | * Copyright (c) 2003-2012, Intel Corporation. |
3ce72726 OW |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
06ecd645 TW |
18 | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/interrupt.h> | |
47a73801 TW |
21 | |
22 | #include "mei_dev.h" | |
06ecd645 TW |
23 | #include "hbm.h" |
24 | ||
6e4cd27a TW |
25 | #include "hw-me.h" |
26 | #include "hw-me-regs.h" | |
06ecd645 | 27 | |
a0a927d0 TW |
28 | #include "mei-trace.h" |
29 | ||
3a65dd4e | 30 | /** |
b68301e9 | 31 | * mei_me_reg_read - Reads 32bit data from the mei device |
3a65dd4e | 32 | * |
a8605ea2 | 33 | * @hw: the me hardware structure |
3a65dd4e TW |
34 | * @offset: offset from which to read the data |
35 | * | |
a8605ea2 | 36 | * Return: register value (u32) |
3a65dd4e | 37 | */ |
b68301e9 | 38 | static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, |
3a65dd4e TW |
39 | unsigned long offset) |
40 | { | |
52c34561 | 41 | return ioread32(hw->mem_addr + offset); |
3a65dd4e TW |
42 | } |
43 | ||
44 | ||
45 | /** | |
b68301e9 | 46 | * mei_me_reg_write - Writes 32bit data to the mei device |
3a65dd4e | 47 | * |
a8605ea2 | 48 | * @hw: the me hardware structure |
3a65dd4e TW |
49 | * @offset: offset from which to write the data |
50 | * @value: register value to write (u32) | |
51 | */ | |
b68301e9 | 52 | static inline void mei_me_reg_write(const struct mei_me_hw *hw, |
3a65dd4e TW |
53 | unsigned long offset, u32 value) |
54 | { | |
52c34561 | 55 | iowrite32(value, hw->mem_addr + offset); |
3a65dd4e | 56 | } |
3ce72726 | 57 | |
3a65dd4e | 58 | /** |
b68301e9 | 59 | * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer |
d025284d | 60 | * read window register |
3a65dd4e TW |
61 | * |
62 | * @dev: the device structure | |
63 | * | |
a8605ea2 | 64 | * Return: ME_CB_RW register value (u32) |
3a65dd4e | 65 | */ |
381a58c7 | 66 | static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) |
3a65dd4e | 67 | { |
b68301e9 | 68 | return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); |
3a65dd4e | 69 | } |
381a58c7 TW |
70 | |
71 | /** | |
72 | * mei_me_hcbww_write - write 32bit data to the host circular buffer | |
73 | * | |
74 | * @dev: the device structure | |
75 | * @data: 32bit data to be written to the host circular buffer | |
76 | */ | |
77 | static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) | |
78 | { | |
79 | mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); | |
80 | } | |
81 | ||
3a65dd4e | 82 | /** |
b68301e9 | 83 | * mei_me_mecsr_read - Reads 32bit data from the ME CSR |
3a65dd4e | 84 | * |
381a58c7 | 85 | * @dev: the device structure |
3a65dd4e | 86 | * |
a8605ea2 | 87 | * Return: ME_CSR_HA register value (u32) |
3a65dd4e | 88 | */ |
381a58c7 | 89 | static inline u32 mei_me_mecsr_read(const struct mei_device *dev) |
3a65dd4e | 90 | { |
a0a927d0 TW |
91 | u32 reg; |
92 | ||
93 | reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); | |
94 | trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); | |
95 | ||
96 | return reg; | |
3a65dd4e | 97 | } |
3ce72726 OW |
98 | |
99 | /** | |
d025284d TW |
100 | * mei_hcsr_read - Reads 32bit data from the host CSR |
101 | * | |
381a58c7 | 102 | * @dev: the device structure |
d025284d | 103 | * |
a8605ea2 | 104 | * Return: H_CSR register value (u32) |
d025284d | 105 | */ |
381a58c7 | 106 | static inline u32 mei_hcsr_read(const struct mei_device *dev) |
d025284d | 107 | { |
a0a927d0 TW |
108 | u32 reg; |
109 | ||
110 | reg = mei_me_reg_read(to_me_hw(dev), H_CSR); | |
111 | trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); | |
112 | ||
113 | return reg; | |
381a58c7 TW |
114 | } |
115 | ||
116 | /** | |
117 | * mei_hcsr_write - writes H_CSR register to the mei device | |
118 | * | |
119 | * @dev: the device structure | |
120 | * @reg: new register value | |
121 | */ | |
122 | static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) | |
123 | { | |
a0a927d0 | 124 | trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); |
381a58c7 | 125 | mei_me_reg_write(to_me_hw(dev), H_CSR, reg); |
d025284d TW |
126 | } |
127 | ||
128 | /** | |
129 | * mei_hcsr_set - writes H_CSR register to the mei device, | |
3ce72726 OW |
130 | * and ignores the H_IS bit for it is write-one-to-zero. |
131 | * | |
381a58c7 TW |
132 | * @dev: the device structure |
133 | * @reg: new register value | |
3ce72726 | 134 | */ |
381a58c7 | 135 | static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) |
3ce72726 | 136 | { |
381a58c7 TW |
137 | reg &= ~H_IS; |
138 | mei_hcsr_write(dev, reg); | |
3ce72726 OW |
139 | } |
140 | ||
1bd30b6a TW |
141 | /** |
142 | * mei_me_fw_status - read fw status register from pci config space | |
143 | * | |
144 | * @dev: mei device | |
145 | * @fw_status: fw status register values | |
ce23139c AU |
146 | * |
147 | * Return: 0 on success, error otherwise | |
1bd30b6a TW |
148 | */ |
149 | static int mei_me_fw_status(struct mei_device *dev, | |
150 | struct mei_fw_status *fw_status) | |
151 | { | |
1bd30b6a | 152 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
4ad96db6 TW |
153 | struct mei_me_hw *hw = to_me_hw(dev); |
154 | const struct mei_fw_status *fw_src = &hw->cfg->fw_status; | |
1bd30b6a TW |
155 | int ret; |
156 | int i; | |
157 | ||
158 | if (!fw_status) | |
159 | return -EINVAL; | |
160 | ||
161 | fw_status->count = fw_src->count; | |
162 | for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { | |
163 | ret = pci_read_config_dword(pdev, | |
164 | fw_src->status[i], &fw_status->status[i]); | |
165 | if (ret) | |
166 | return ret; | |
167 | } | |
168 | ||
169 | return 0; | |
170 | } | |
e7e0c231 TW |
171 | |
172 | /** | |
393b148f | 173 | * mei_me_hw_config - configure hw dependent settings |
e7e0c231 TW |
174 | * |
175 | * @dev: mei device | |
176 | */ | |
827eef51 | 177 | static void mei_me_hw_config(struct mei_device *dev) |
e7e0c231 | 178 | { |
ba9cdd0e | 179 | struct mei_me_hw *hw = to_me_hw(dev); |
381a58c7 | 180 | u32 hcsr = mei_hcsr_read(dev); |
e7e0c231 TW |
181 | /* Doesn't change in runtime */ |
182 | dev->hbuf_depth = (hcsr & H_CBD) >> 24; | |
ba9cdd0e TW |
183 | |
184 | hw->pg_state = MEI_PG_OFF; | |
e7e0c231 | 185 | } |
964a2331 TW |
186 | |
187 | /** | |
188 | * mei_me_pg_state - translate internal pg state | |
189 | * to the mei power gating state | |
190 | * | |
ce23139c AU |
191 | * @dev: mei device |
192 | * | |
193 | * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise | |
964a2331 TW |
194 | */ |
195 | static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) | |
196 | { | |
ba9cdd0e | 197 | struct mei_me_hw *hw = to_me_hw(dev); |
92db1555 | 198 | |
ba9cdd0e | 199 | return hw->pg_state; |
964a2331 TW |
200 | } |
201 | ||
3ce72726 | 202 | /** |
ce23139c | 203 | * mei_me_intr_clear - clear and stop interrupts |
3a65dd4e TW |
204 | * |
205 | * @dev: the device structure | |
206 | */ | |
827eef51 | 207 | static void mei_me_intr_clear(struct mei_device *dev) |
3a65dd4e | 208 | { |
381a58c7 | 209 | u32 hcsr = mei_hcsr_read(dev); |
92db1555 | 210 | |
9ea73ddd | 211 | if ((hcsr & H_IS) == H_IS) |
381a58c7 | 212 | mei_hcsr_write(dev, hcsr); |
3a65dd4e | 213 | } |
3a65dd4e | 214 | /** |
827eef51 | 215 | * mei_me_intr_enable - enables mei device interrupts |
3ce72726 OW |
216 | * |
217 | * @dev: the device structure | |
218 | */ | |
827eef51 | 219 | static void mei_me_intr_enable(struct mei_device *dev) |
3ce72726 | 220 | { |
381a58c7 | 221 | u32 hcsr = mei_hcsr_read(dev); |
92db1555 | 222 | |
9ea73ddd | 223 | hcsr |= H_IE; |
381a58c7 | 224 | mei_hcsr_set(dev, hcsr); |
3ce72726 OW |
225 | } |
226 | ||
227 | /** | |
ce23139c | 228 | * mei_me_intr_disable - disables mei device interrupts |
3ce72726 OW |
229 | * |
230 | * @dev: the device structure | |
231 | */ | |
827eef51 | 232 | static void mei_me_intr_disable(struct mei_device *dev) |
3ce72726 | 233 | { |
381a58c7 | 234 | u32 hcsr = mei_hcsr_read(dev); |
92db1555 | 235 | |
9ea73ddd | 236 | hcsr &= ~H_IE; |
381a58c7 | 237 | mei_hcsr_set(dev, hcsr); |
3ce72726 OW |
238 | } |
239 | ||
68f8ea18 TW |
240 | /** |
241 | * mei_me_hw_reset_release - release device from the reset | |
242 | * | |
243 | * @dev: the device structure | |
244 | */ | |
245 | static void mei_me_hw_reset_release(struct mei_device *dev) | |
246 | { | |
381a58c7 | 247 | u32 hcsr = mei_hcsr_read(dev); |
68f8ea18 TW |
248 | |
249 | hcsr |= H_IG; | |
250 | hcsr &= ~H_RST; | |
381a58c7 | 251 | mei_hcsr_set(dev, hcsr); |
b04ada92 TW |
252 | |
253 | /* complete this write before we set host ready on another CPU */ | |
254 | mmiowb(); | |
68f8ea18 | 255 | } |
adfba322 | 256 | /** |
827eef51 | 257 | * mei_me_hw_reset - resets fw via mei csr register. |
adfba322 TW |
258 | * |
259 | * @dev: the device structure | |
393b148f | 260 | * @intr_enable: if interrupt should be enabled after reset. |
ce23139c AU |
261 | * |
262 | * Return: always 0 | |
adfba322 | 263 | */ |
c20c68d5 | 264 | static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) |
adfba322 | 265 | { |
381a58c7 | 266 | u32 hcsr = mei_hcsr_read(dev); |
adfba322 | 267 | |
b13a65ef AU |
268 | /* H_RST may be found lit before reset is started, |
269 | * for example if preceding reset flow hasn't completed. | |
270 | * In that case asserting H_RST will be ignored, therefore | |
271 | * we need to clean H_RST bit to start a successful reset sequence. | |
272 | */ | |
273 | if ((hcsr & H_RST) == H_RST) { | |
274 | dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); | |
275 | hcsr &= ~H_RST; | |
381a58c7 TW |
276 | mei_hcsr_set(dev, hcsr); |
277 | hcsr = mei_hcsr_read(dev); | |
b13a65ef AU |
278 | } |
279 | ||
ff96066e | 280 | hcsr |= H_RST | H_IG | H_IS; |
adfba322 TW |
281 | |
282 | if (intr_enable) | |
283 | hcsr |= H_IE; | |
284 | else | |
ff96066e | 285 | hcsr &= ~H_IE; |
adfba322 | 286 | |
07cd7be3 | 287 | dev->recvd_hw_ready = false; |
381a58c7 | 288 | mei_hcsr_write(dev, hcsr); |
adfba322 | 289 | |
c40765d9 TW |
290 | /* |
291 | * Host reads the H_CSR once to ensure that the | |
292 | * posted write to H_CSR completes. | |
293 | */ | |
381a58c7 | 294 | hcsr = mei_hcsr_read(dev); |
c40765d9 TW |
295 | |
296 | if ((hcsr & H_RST) == 0) | |
2bf94cab | 297 | dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); |
c40765d9 TW |
298 | |
299 | if ((hcsr & H_RDY) == H_RDY) | |
2bf94cab | 300 | dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); |
c40765d9 | 301 | |
33ec0826 | 302 | if (intr_enable == false) |
68f8ea18 | 303 | mei_me_hw_reset_release(dev); |
adfba322 | 304 | |
c20c68d5 | 305 | return 0; |
adfba322 TW |
306 | } |
307 | ||
115ba28c | 308 | /** |
827eef51 | 309 | * mei_me_host_set_ready - enable device |
115ba28c | 310 | * |
ce23139c | 311 | * @dev: mei device |
115ba28c | 312 | */ |
827eef51 | 313 | static void mei_me_host_set_ready(struct mei_device *dev) |
115ba28c | 314 | { |
381a58c7 | 315 | u32 hcsr = mei_hcsr_read(dev); |
92db1555 | 316 | |
18caeb70 | 317 | hcsr |= H_IE | H_IG | H_RDY; |
381a58c7 | 318 | mei_hcsr_set(dev, hcsr); |
115ba28c | 319 | } |
ce23139c | 320 | |
115ba28c | 321 | /** |
827eef51 | 322 | * mei_me_host_is_ready - check whether the host has turned ready |
115ba28c | 323 | * |
a8605ea2 AU |
324 | * @dev: mei device |
325 | * Return: bool | |
115ba28c | 326 | */ |
827eef51 | 327 | static bool mei_me_host_is_ready(struct mei_device *dev) |
115ba28c | 328 | { |
381a58c7 | 329 | u32 hcsr = mei_hcsr_read(dev); |
92db1555 | 330 | |
18caeb70 | 331 | return (hcsr & H_RDY) == H_RDY; |
115ba28c TW |
332 | } |
333 | ||
334 | /** | |
827eef51 | 335 | * mei_me_hw_is_ready - check whether the me(hw) has turned ready |
115ba28c | 336 | * |
a8605ea2 AU |
337 | * @dev: mei device |
338 | * Return: bool | |
115ba28c | 339 | */ |
827eef51 | 340 | static bool mei_me_hw_is_ready(struct mei_device *dev) |
115ba28c | 341 | { |
381a58c7 | 342 | u32 mecsr = mei_me_mecsr_read(dev); |
92db1555 | 343 | |
18caeb70 | 344 | return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; |
115ba28c | 345 | } |
3a65dd4e | 346 | |
ce23139c AU |
347 | /** |
348 | * mei_me_hw_ready_wait - wait until the me(hw) has turned ready | |
349 | * or timeout is reached | |
350 | * | |
351 | * @dev: mei device | |
352 | * Return: 0 on success, error otherwise | |
353 | */ | |
aafae7ec TW |
354 | static int mei_me_hw_ready_wait(struct mei_device *dev) |
355 | { | |
aafae7ec | 356 | mutex_unlock(&dev->device_lock); |
2c2b93ec | 357 | wait_event_timeout(dev->wait_hw_ready, |
dab9bf41 | 358 | dev->recvd_hw_ready, |
7d93e58d | 359 | mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); |
aafae7ec | 360 | mutex_lock(&dev->device_lock); |
2c2b93ec | 361 | if (!dev->recvd_hw_ready) { |
2bf94cab | 362 | dev_err(dev->dev, "wait hw ready failed\n"); |
2c2b93ec | 363 | return -ETIME; |
aafae7ec TW |
364 | } |
365 | ||
663b7ee9 | 366 | mei_me_hw_reset_release(dev); |
aafae7ec TW |
367 | dev->recvd_hw_ready = false; |
368 | return 0; | |
369 | } | |
370 | ||
ce23139c AU |
371 | /** |
372 | * mei_me_hw_start - hw start routine | |
373 | * | |
374 | * @dev: mei device | |
375 | * Return: 0 on success, error otherwise | |
376 | */ | |
aafae7ec TW |
377 | static int mei_me_hw_start(struct mei_device *dev) |
378 | { | |
379 | int ret = mei_me_hw_ready_wait(dev); | |
92db1555 | 380 | |
aafae7ec TW |
381 | if (ret) |
382 | return ret; | |
2bf94cab | 383 | dev_dbg(dev->dev, "hw is ready\n"); |
aafae7ec TW |
384 | |
385 | mei_me_host_set_ready(dev); | |
386 | return ret; | |
387 | } | |
388 | ||
389 | ||
3ce72726 | 390 | /** |
726917f0 | 391 | * mei_hbuf_filled_slots - gets number of device filled buffer slots |
3ce72726 | 392 | * |
7353f85c | 393 | * @dev: the device structure |
3ce72726 | 394 | * |
a8605ea2 | 395 | * Return: number of filled slots |
3ce72726 | 396 | */ |
726917f0 | 397 | static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) |
3ce72726 | 398 | { |
18caeb70 | 399 | u32 hcsr; |
3ce72726 OW |
400 | char read_ptr, write_ptr; |
401 | ||
381a58c7 | 402 | hcsr = mei_hcsr_read(dev); |
726917f0 | 403 | |
18caeb70 TW |
404 | read_ptr = (char) ((hcsr & H_CBRP) >> 8); |
405 | write_ptr = (char) ((hcsr & H_CBWP) >> 16); | |
3ce72726 OW |
406 | |
407 | return (unsigned char) (write_ptr - read_ptr); | |
408 | } | |
409 | ||
410 | /** | |
393b148f | 411 | * mei_me_hbuf_is_empty - checks if host buffer is empty. |
3ce72726 OW |
412 | * |
413 | * @dev: the device structure | |
414 | * | |
a8605ea2 | 415 | * Return: true if empty, false - otherwise. |
3ce72726 | 416 | */ |
827eef51 | 417 | static bool mei_me_hbuf_is_empty(struct mei_device *dev) |
3ce72726 | 418 | { |
726917f0 | 419 | return mei_hbuf_filled_slots(dev) == 0; |
3ce72726 OW |
420 | } |
421 | ||
422 | /** | |
827eef51 | 423 | * mei_me_hbuf_empty_slots - counts write empty slots. |
3ce72726 OW |
424 | * |
425 | * @dev: the device structure | |
426 | * | |
a8605ea2 | 427 | * Return: -EOVERFLOW if overflow, otherwise empty slots count |
3ce72726 | 428 | */ |
827eef51 | 429 | static int mei_me_hbuf_empty_slots(struct mei_device *dev) |
3ce72726 | 430 | { |
24aadc80 | 431 | unsigned char filled_slots, empty_slots; |
3ce72726 | 432 | |
726917f0 | 433 | filled_slots = mei_hbuf_filled_slots(dev); |
24aadc80 | 434 | empty_slots = dev->hbuf_depth - filled_slots; |
3ce72726 OW |
435 | |
436 | /* check for overflow */ | |
24aadc80 | 437 | if (filled_slots > dev->hbuf_depth) |
3ce72726 OW |
438 | return -EOVERFLOW; |
439 | ||
440 | return empty_slots; | |
441 | } | |
442 | ||
ce23139c AU |
443 | /** |
444 | * mei_me_hbuf_max_len - returns size of hw buffer. | |
445 | * | |
446 | * @dev: the device structure | |
447 | * | |
448 | * Return: size of hw buffer in bytes | |
449 | */ | |
827eef51 TW |
450 | static size_t mei_me_hbuf_max_len(const struct mei_device *dev) |
451 | { | |
452 | return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); | |
453 | } | |
454 | ||
455 | ||
3ce72726 | 456 | /** |
7ca96aa2 | 457 | * mei_me_write_message - writes a message to mei device. |
3ce72726 OW |
458 | * |
459 | * @dev: the device structure | |
7353f85c | 460 | * @header: mei HECI header of message |
438763f3 | 461 | * @buf: message payload will be written |
3ce72726 | 462 | * |
a8605ea2 | 463 | * Return: -EIO if write has failed |
3ce72726 | 464 | */ |
827eef51 TW |
465 | static int mei_me_write_message(struct mei_device *dev, |
466 | struct mei_msg_hdr *header, | |
467 | unsigned char *buf) | |
3ce72726 | 468 | { |
c8c8d080 | 469 | unsigned long rem; |
438763f3 | 470 | unsigned long length = header->length; |
169d1338 | 471 | u32 *reg_buf = (u32 *)buf; |
88eb99f2 | 472 | u32 hcsr; |
c8c8d080 | 473 | u32 dw_cnt; |
169d1338 TW |
474 | int i; |
475 | int empty_slots; | |
3ce72726 | 476 | |
2bf94cab | 477 | dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); |
3ce72726 | 478 | |
726917f0 | 479 | empty_slots = mei_hbuf_empty_slots(dev); |
2bf94cab | 480 | dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); |
3ce72726 | 481 | |
7bdf72d3 | 482 | dw_cnt = mei_data2slots(length); |
169d1338 | 483 | if (empty_slots < 0 || dw_cnt > empty_slots) |
9d098192 | 484 | return -EMSGSIZE; |
3ce72726 | 485 | |
381a58c7 | 486 | mei_me_hcbww_write(dev, *((u32 *) header)); |
3ce72726 | 487 | |
169d1338 | 488 | for (i = 0; i < length / 4; i++) |
381a58c7 | 489 | mei_me_hcbww_write(dev, reg_buf[i]); |
3ce72726 | 490 | |
169d1338 TW |
491 | rem = length & 0x3; |
492 | if (rem > 0) { | |
493 | u32 reg = 0; | |
92db1555 | 494 | |
169d1338 | 495 | memcpy(®, &buf[length - rem], rem); |
381a58c7 | 496 | mei_me_hcbww_write(dev, reg); |
3ce72726 OW |
497 | } |
498 | ||
381a58c7 TW |
499 | hcsr = mei_hcsr_read(dev) | H_IG; |
500 | mei_hcsr_set(dev, hcsr); | |
827eef51 | 501 | if (!mei_me_hw_is_ready(dev)) |
1ccb7b62 | 502 | return -EIO; |
3ce72726 | 503 | |
1ccb7b62 | 504 | return 0; |
3ce72726 OW |
505 | } |
506 | ||
507 | /** | |
827eef51 | 508 | * mei_me_count_full_read_slots - counts read full slots. |
3ce72726 OW |
509 | * |
510 | * @dev: the device structure | |
511 | * | |
a8605ea2 | 512 | * Return: -EOVERFLOW if overflow, otherwise filled slots count |
3ce72726 | 513 | */ |
827eef51 | 514 | static int mei_me_count_full_read_slots(struct mei_device *dev) |
3ce72726 | 515 | { |
18caeb70 | 516 | u32 me_csr; |
3ce72726 OW |
517 | char read_ptr, write_ptr; |
518 | unsigned char buffer_depth, filled_slots; | |
519 | ||
381a58c7 | 520 | me_csr = mei_me_mecsr_read(dev); |
18caeb70 TW |
521 | buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); |
522 | read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); | |
523 | write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); | |
3ce72726 OW |
524 | filled_slots = (unsigned char) (write_ptr - read_ptr); |
525 | ||
526 | /* check for overflow */ | |
527 | if (filled_slots > buffer_depth) | |
528 | return -EOVERFLOW; | |
529 | ||
2bf94cab | 530 | dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); |
3ce72726 OW |
531 | return (int)filled_slots; |
532 | } | |
533 | ||
534 | /** | |
827eef51 | 535 | * mei_me_read_slots - reads a message from mei device. |
3ce72726 OW |
536 | * |
537 | * @dev: the device structure | |
538 | * @buffer: message buffer will be written | |
539 | * @buffer_length: message size will be read | |
ce23139c AU |
540 | * |
541 | * Return: always 0 | |
3ce72726 | 542 | */ |
827eef51 | 543 | static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, |
edf1eed4 | 544 | unsigned long buffer_length) |
3ce72726 | 545 | { |
edf1eed4 | 546 | u32 *reg_buf = (u32 *)buffer; |
88eb99f2 | 547 | u32 hcsr; |
3ce72726 | 548 | |
edf1eed4 | 549 | for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32)) |
827eef51 | 550 | *reg_buf++ = mei_me_mecbrw_read(dev); |
3ce72726 OW |
551 | |
552 | if (buffer_length > 0) { | |
827eef51 | 553 | u32 reg = mei_me_mecbrw_read(dev); |
92db1555 | 554 | |
edf1eed4 | 555 | memcpy(reg_buf, ®, buffer_length); |
3ce72726 OW |
556 | } |
557 | ||
381a58c7 TW |
558 | hcsr = mei_hcsr_read(dev) | H_IG; |
559 | mei_hcsr_set(dev, hcsr); | |
827eef51 | 560 | return 0; |
3ce72726 OW |
561 | } |
562 | ||
b16c3571 | 563 | /** |
2d1995fc | 564 | * mei_me_pg_set - write pg enter register |
b16c3571 TW |
565 | * |
566 | * @dev: the device structure | |
567 | */ | |
2d1995fc | 568 | static void mei_me_pg_set(struct mei_device *dev) |
b16c3571 TW |
569 | { |
570 | struct mei_me_hw *hw = to_me_hw(dev); | |
a0a927d0 TW |
571 | u32 reg; |
572 | ||
573 | reg = mei_me_reg_read(hw, H_HPG_CSR); | |
574 | trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); | |
92db1555 | 575 | |
b16c3571 | 576 | reg |= H_HPG_CSR_PGI; |
a0a927d0 TW |
577 | |
578 | trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); | |
b16c3571 TW |
579 | mei_me_reg_write(hw, H_HPG_CSR, reg); |
580 | } | |
581 | ||
582 | /** | |
2d1995fc | 583 | * mei_me_pg_unset - write pg exit register |
b16c3571 TW |
584 | * |
585 | * @dev: the device structure | |
586 | */ | |
2d1995fc | 587 | static void mei_me_pg_unset(struct mei_device *dev) |
b16c3571 TW |
588 | { |
589 | struct mei_me_hw *hw = to_me_hw(dev); | |
a0a927d0 TW |
590 | u32 reg; |
591 | ||
592 | reg = mei_me_reg_read(hw, H_HPG_CSR); | |
593 | trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); | |
b16c3571 TW |
594 | |
595 | WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); | |
596 | ||
597 | reg |= H_HPG_CSR_PGIHEXR; | |
a0a927d0 TW |
598 | |
599 | trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); | |
b16c3571 TW |
600 | mei_me_reg_write(hw, H_HPG_CSR, reg); |
601 | } | |
602 | ||
ba9cdd0e | 603 | /** |
2d1995fc | 604 | * mei_me_pg_enter_sync - perform pg entry procedure |
ba9cdd0e TW |
605 | * |
606 | * @dev: the device structure | |
607 | * | |
a8605ea2 | 608 | * Return: 0 on success an error code otherwise |
ba9cdd0e | 609 | */ |
2d1995fc | 610 | int mei_me_pg_enter_sync(struct mei_device *dev) |
ba9cdd0e TW |
611 | { |
612 | struct mei_me_hw *hw = to_me_hw(dev); | |
613 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); | |
614 | int ret; | |
615 | ||
616 | dev->pg_event = MEI_PG_EVENT_WAIT; | |
617 | ||
618 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); | |
619 | if (ret) | |
620 | return ret; | |
621 | ||
622 | mutex_unlock(&dev->device_lock); | |
623 | wait_event_timeout(dev->wait_pg, | |
624 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
625 | mutex_lock(&dev->device_lock); | |
626 | ||
627 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { | |
2d1995fc | 628 | mei_me_pg_set(dev); |
ba9cdd0e TW |
629 | ret = 0; |
630 | } else { | |
631 | ret = -ETIME; | |
632 | } | |
633 | ||
634 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
635 | hw->pg_state = MEI_PG_ON; | |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | /** | |
2d1995fc | 641 | * mei_me_pg_exit_sync - perform pg exit procedure |
ba9cdd0e TW |
642 | * |
643 | * @dev: the device structure | |
644 | * | |
a8605ea2 | 645 | * Return: 0 on success an error code otherwise |
ba9cdd0e | 646 | */ |
2d1995fc | 647 | int mei_me_pg_exit_sync(struct mei_device *dev) |
ba9cdd0e TW |
648 | { |
649 | struct mei_me_hw *hw = to_me_hw(dev); | |
650 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); | |
651 | int ret; | |
652 | ||
653 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) | |
654 | goto reply; | |
655 | ||
656 | dev->pg_event = MEI_PG_EVENT_WAIT; | |
657 | ||
2d1995fc | 658 | mei_me_pg_unset(dev); |
ba9cdd0e TW |
659 | |
660 | mutex_unlock(&dev->device_lock); | |
661 | wait_event_timeout(dev->wait_pg, | |
662 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
663 | mutex_lock(&dev->device_lock); | |
664 | ||
665 | reply: | |
3dc196ea AU |
666 | if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { |
667 | ret = -ETIME; | |
668 | goto out; | |
669 | } | |
670 | ||
671 | dev->pg_event = MEI_PG_EVENT_INTR_WAIT; | |
672 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); | |
673 | if (ret) | |
674 | return ret; | |
675 | ||
676 | mutex_unlock(&dev->device_lock); | |
677 | wait_event_timeout(dev->wait_pg, | |
678 | dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); | |
679 | mutex_lock(&dev->device_lock); | |
680 | ||
681 | if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) | |
682 | ret = 0; | |
ba9cdd0e TW |
683 | else |
684 | ret = -ETIME; | |
685 | ||
3dc196ea | 686 | out: |
ba9cdd0e TW |
687 | dev->pg_event = MEI_PG_EVENT_IDLE; |
688 | hw->pg_state = MEI_PG_OFF; | |
689 | ||
690 | return ret; | |
691 | } | |
692 | ||
3dc196ea AU |
693 | /** |
694 | * mei_me_pg_in_transition - is device now in pg transition | |
695 | * | |
696 | * @dev: the device structure | |
697 | * | |
698 | * Return: true if in pg transition, false otherwise | |
699 | */ | |
700 | static bool mei_me_pg_in_transition(struct mei_device *dev) | |
701 | { | |
702 | return dev->pg_event >= MEI_PG_EVENT_WAIT && | |
703 | dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; | |
704 | } | |
705 | ||
ee7e5afd TW |
706 | /** |
707 | * mei_me_pg_is_enabled - detect if PG is supported by HW | |
708 | * | |
709 | * @dev: the device structure | |
710 | * | |
a8605ea2 | 711 | * Return: true is pg supported, false otherwise |
ee7e5afd TW |
712 | */ |
713 | static bool mei_me_pg_is_enabled(struct mei_device *dev) | |
714 | { | |
381a58c7 | 715 | u32 reg = mei_me_mecsr_read(dev); |
ee7e5afd TW |
716 | |
717 | if ((reg & ME_PGIC_HRA) == 0) | |
718 | goto notsupported; | |
719 | ||
bae1cc7d | 720 | if (!dev->hbm_f_pg_supported) |
ee7e5afd TW |
721 | goto notsupported; |
722 | ||
723 | return true; | |
724 | ||
725 | notsupported: | |
2bf94cab | 726 | dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n", |
ee7e5afd TW |
727 | !!(reg & ME_PGIC_HRA), |
728 | dev->version.major_version, | |
729 | dev->version.minor_version, | |
730 | HBM_MAJOR_VERSION_PGI, | |
731 | HBM_MINOR_VERSION_PGI); | |
732 | ||
733 | return false; | |
734 | } | |
735 | ||
3dc196ea AU |
736 | /** |
737 | * mei_me_pg_intr - perform pg processing in interrupt thread handler | |
738 | * | |
739 | * @dev: the device structure | |
740 | */ | |
741 | static void mei_me_pg_intr(struct mei_device *dev) | |
742 | { | |
743 | struct mei_me_hw *hw = to_me_hw(dev); | |
744 | ||
745 | if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) | |
746 | return; | |
747 | ||
748 | dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; | |
749 | hw->pg_state = MEI_PG_OFF; | |
750 | if (waitqueue_active(&dev->wait_pg)) | |
751 | wake_up(&dev->wait_pg); | |
752 | } | |
753 | ||
06ecd645 TW |
754 | /** |
755 | * mei_me_irq_quick_handler - The ISR of the MEI device | |
756 | * | |
757 | * @irq: The irq number | |
758 | * @dev_id: pointer to the device structure | |
759 | * | |
a8605ea2 | 760 | * Return: irqreturn_t |
06ecd645 TW |
761 | */ |
762 | ||
763 | irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) | |
764 | { | |
765 | struct mei_device *dev = (struct mei_device *) dev_id; | |
381a58c7 | 766 | u32 hcsr = mei_hcsr_read(dev); |
06ecd645 | 767 | |
381a58c7 | 768 | if ((hcsr & H_IS) != H_IS) |
06ecd645 TW |
769 | return IRQ_NONE; |
770 | ||
771 | /* clear H_IS bit in H_CSR */ | |
381a58c7 | 772 | mei_hcsr_write(dev, hcsr); |
06ecd645 TW |
773 | |
774 | return IRQ_WAKE_THREAD; | |
775 | } | |
776 | ||
777 | /** | |
778 | * mei_me_irq_thread_handler - function called after ISR to handle the interrupt | |
779 | * processing. | |
780 | * | |
781 | * @irq: The irq number | |
782 | * @dev_id: pointer to the device structure | |
783 | * | |
a8605ea2 | 784 | * Return: irqreturn_t |
06ecd645 TW |
785 | * |
786 | */ | |
787 | irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) | |
788 | { | |
789 | struct mei_device *dev = (struct mei_device *) dev_id; | |
790 | struct mei_cl_cb complete_list; | |
06ecd645 | 791 | s32 slots; |
544f9460 | 792 | int rets = 0; |
06ecd645 | 793 | |
2bf94cab | 794 | dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); |
06ecd645 TW |
795 | /* initialize our complete list */ |
796 | mutex_lock(&dev->device_lock); | |
797 | mei_io_list_init(&complete_list); | |
798 | ||
799 | /* Ack the interrupt here | |
800 | * In case of MSI we don't go through the quick handler */ | |
d08b8fc0 | 801 | if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) |
06ecd645 TW |
802 | mei_clear_interrupts(dev); |
803 | ||
804 | /* check if ME wants a reset */ | |
33ec0826 | 805 | if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { |
2bf94cab | 806 | dev_warn(dev->dev, "FW not ready: resetting.\n"); |
544f9460 TW |
807 | schedule_work(&dev->reset_work); |
808 | goto end; | |
06ecd645 TW |
809 | } |
810 | ||
3dc196ea AU |
811 | mei_me_pg_intr(dev); |
812 | ||
06ecd645 TW |
813 | /* check if we need to start the dev */ |
814 | if (!mei_host_is_ready(dev)) { | |
815 | if (mei_hw_is_ready(dev)) { | |
2bf94cab | 816 | dev_dbg(dev->dev, "we need to start the dev.\n"); |
aafae7ec | 817 | dev->recvd_hw_ready = true; |
2c2b93ec | 818 | wake_up(&dev->wait_hw_ready); |
06ecd645 | 819 | } else { |
2bf94cab | 820 | dev_dbg(dev->dev, "Spurious Interrupt\n"); |
06ecd645 | 821 | } |
544f9460 | 822 | goto end; |
06ecd645 TW |
823 | } |
824 | /* check slots available for reading */ | |
825 | slots = mei_count_full_read_slots(dev); | |
826 | while (slots > 0) { | |
2bf94cab | 827 | dev_dbg(dev->dev, "slots to read = %08x\n", slots); |
06ecd645 | 828 | rets = mei_irq_read_handler(dev, &complete_list, &slots); |
b1b94b5d TW |
829 | /* There is a race between ME write and interrupt delivery: |
830 | * Not all data is always available immediately after the | |
831 | * interrupt, so try to read again on the next interrupt. | |
832 | */ | |
833 | if (rets == -ENODATA) | |
834 | break; | |
835 | ||
33ec0826 | 836 | if (rets && dev->dev_state != MEI_DEV_RESETTING) { |
2bf94cab | 837 | dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", |
b1b94b5d | 838 | rets); |
544f9460 | 839 | schedule_work(&dev->reset_work); |
06ecd645 | 840 | goto end; |
544f9460 | 841 | } |
06ecd645 | 842 | } |
544f9460 | 843 | |
6aae48ff TW |
844 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); |
845 | ||
ba9cdd0e TW |
846 | /* |
847 | * During PG handshake only allowed write is the replay to the | |
848 | * PG exit message, so block calling write function | |
3dc196ea | 849 | * if the pg event is in PG handshake |
ba9cdd0e | 850 | */ |
3dc196ea AU |
851 | if (dev->pg_event != MEI_PG_EVENT_WAIT && |
852 | dev->pg_event != MEI_PG_EVENT_RECEIVED) { | |
ba9cdd0e TW |
853 | rets = mei_irq_write_handler(dev, &complete_list); |
854 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
855 | } | |
06ecd645 | 856 | |
4c6e22b8 | 857 | mei_irq_compl_handler(dev, &complete_list); |
06ecd645 | 858 | |
544f9460 | 859 | end: |
2bf94cab | 860 | dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); |
544f9460 | 861 | mutex_unlock(&dev->device_lock); |
06ecd645 TW |
862 | return IRQ_HANDLED; |
863 | } | |
04dd3661 | 864 | |
827eef51 TW |
865 | static const struct mei_hw_ops mei_me_hw_ops = { |
866 | ||
1bd30b6a | 867 | .fw_status = mei_me_fw_status, |
964a2331 TW |
868 | .pg_state = mei_me_pg_state, |
869 | ||
827eef51 TW |
870 | .host_is_ready = mei_me_host_is_ready, |
871 | ||
872 | .hw_is_ready = mei_me_hw_is_ready, | |
873 | .hw_reset = mei_me_hw_reset, | |
aafae7ec TW |
874 | .hw_config = mei_me_hw_config, |
875 | .hw_start = mei_me_hw_start, | |
827eef51 | 876 | |
3dc196ea | 877 | .pg_in_transition = mei_me_pg_in_transition, |
ee7e5afd TW |
878 | .pg_is_enabled = mei_me_pg_is_enabled, |
879 | ||
827eef51 TW |
880 | .intr_clear = mei_me_intr_clear, |
881 | .intr_enable = mei_me_intr_enable, | |
882 | .intr_disable = mei_me_intr_disable, | |
883 | ||
884 | .hbuf_free_slots = mei_me_hbuf_empty_slots, | |
885 | .hbuf_is_ready = mei_me_hbuf_is_empty, | |
886 | .hbuf_max_len = mei_me_hbuf_max_len, | |
887 | ||
888 | .write = mei_me_write_message, | |
889 | ||
890 | .rdbuf_full_slots = mei_me_count_full_read_slots, | |
891 | .read_hdr = mei_me_mecbrw_read, | |
892 | .read = mei_me_read_slots | |
893 | }; | |
894 | ||
c919951d TW |
895 | static bool mei_me_fw_type_nm(struct pci_dev *pdev) |
896 | { | |
897 | u32 reg; | |
92db1555 | 898 | |
c919951d TW |
899 | pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); |
900 | /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ | |
901 | return (reg & 0x600) == 0x200; | |
902 | } | |
903 | ||
904 | #define MEI_CFG_FW_NM \ | |
905 | .quirk_probe = mei_me_fw_type_nm | |
906 | ||
907 | static bool mei_me_fw_type_sps(struct pci_dev *pdev) | |
908 | { | |
909 | u32 reg; | |
910 | /* Read ME FW Status check for SPS Firmware */ | |
911 | pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); | |
912 | /* if bits [19:16] = 15, running SPS Firmware */ | |
913 | return (reg & 0xf0000) == 0xf0000; | |
914 | } | |
915 | ||
916 | #define MEI_CFG_FW_SPS \ | |
917 | .quirk_probe = mei_me_fw_type_sps | |
918 | ||
919 | ||
8d929d48 AU |
920 | #define MEI_CFG_LEGACY_HFS \ |
921 | .fw_status.count = 0 | |
922 | ||
923 | #define MEI_CFG_ICH_HFS \ | |
924 | .fw_status.count = 1, \ | |
925 | .fw_status.status[0] = PCI_CFG_HFS_1 | |
926 | ||
927 | #define MEI_CFG_PCH_HFS \ | |
928 | .fw_status.count = 2, \ | |
929 | .fw_status.status[0] = PCI_CFG_HFS_1, \ | |
930 | .fw_status.status[1] = PCI_CFG_HFS_2 | |
931 | ||
edca5ea3 AU |
932 | #define MEI_CFG_PCH8_HFS \ |
933 | .fw_status.count = 6, \ | |
934 | .fw_status.status[0] = PCI_CFG_HFS_1, \ | |
935 | .fw_status.status[1] = PCI_CFG_HFS_2, \ | |
936 | .fw_status.status[2] = PCI_CFG_HFS_3, \ | |
937 | .fw_status.status[3] = PCI_CFG_HFS_4, \ | |
938 | .fw_status.status[4] = PCI_CFG_HFS_5, \ | |
939 | .fw_status.status[5] = PCI_CFG_HFS_6 | |
8d929d48 AU |
940 | |
941 | /* ICH Legacy devices */ | |
942 | const struct mei_cfg mei_me_legacy_cfg = { | |
943 | MEI_CFG_LEGACY_HFS, | |
944 | }; | |
945 | ||
946 | /* ICH devices */ | |
947 | const struct mei_cfg mei_me_ich_cfg = { | |
948 | MEI_CFG_ICH_HFS, | |
949 | }; | |
950 | ||
951 | /* PCH devices */ | |
952 | const struct mei_cfg mei_me_pch_cfg = { | |
953 | MEI_CFG_PCH_HFS, | |
954 | }; | |
955 | ||
c919951d TW |
956 | |
957 | /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ | |
958 | const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { | |
959 | MEI_CFG_PCH_HFS, | |
960 | MEI_CFG_FW_NM, | |
961 | }; | |
962 | ||
edca5ea3 AU |
963 | /* PCH8 Lynx Point and newer devices */ |
964 | const struct mei_cfg mei_me_pch8_cfg = { | |
965 | MEI_CFG_PCH8_HFS, | |
966 | }; | |
967 | ||
968 | /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ | |
969 | const struct mei_cfg mei_me_pch8_sps_cfg = { | |
970 | MEI_CFG_PCH8_HFS, | |
c919951d TW |
971 | MEI_CFG_FW_SPS, |
972 | }; | |
973 | ||
52c34561 | 974 | /** |
393b148f | 975 | * mei_me_dev_init - allocates and initializes the mei device structure |
52c34561 TW |
976 | * |
977 | * @pdev: The pci device structure | |
8d929d48 | 978 | * @cfg: per device generation config |
52c34561 | 979 | * |
a8605ea2 | 980 | * Return: The mei_device_device pointer on success, NULL on failure. |
52c34561 | 981 | */ |
8d929d48 AU |
982 | struct mei_device *mei_me_dev_init(struct pci_dev *pdev, |
983 | const struct mei_cfg *cfg) | |
52c34561 TW |
984 | { |
985 | struct mei_device *dev; | |
4ad96db6 | 986 | struct mei_me_hw *hw; |
52c34561 TW |
987 | |
988 | dev = kzalloc(sizeof(struct mei_device) + | |
989 | sizeof(struct mei_me_hw), GFP_KERNEL); | |
990 | if (!dev) | |
991 | return NULL; | |
4ad96db6 | 992 | hw = to_me_hw(dev); |
52c34561 | 993 | |
3a7e9b6c | 994 | mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); |
4ad96db6 | 995 | hw->cfg = cfg; |
52c34561 TW |
996 | return dev; |
997 | } | |
06ecd645 | 998 |