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32e2b59f TW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
4 | * Copyright (c) 2013-2014, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
18 | #include <linux/jiffies.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/kthread.h> | |
4a22176a | 21 | #include <linux/irqreturn.h> |
32e2b59f TW |
22 | |
23 | #include <linux/mei.h> | |
24 | ||
25 | #include "mei_dev.h" | |
26 | #include "hw-txe.h" | |
27 | #include "client.h" | |
28 | #include "hbm.h" | |
29 | ||
30 | /** | |
31 | * mei_txe_reg_read - Reads 32bit data from the device | |
32 | * | |
33 | * @base_addr: registers base address | |
34 | * @offset: register offset | |
35 | * | |
36 | */ | |
37 | static inline u32 mei_txe_reg_read(void __iomem *base_addr, | |
38 | unsigned long offset) | |
39 | { | |
40 | return ioread32(base_addr + offset); | |
41 | } | |
42 | ||
43 | /** | |
44 | * mei_txe_reg_write - Writes 32bit data to the device | |
45 | * | |
46 | * @base_addr: registers base address | |
47 | * @offset: register offset | |
48 | * @value: the value to write | |
49 | */ | |
50 | static inline void mei_txe_reg_write(void __iomem *base_addr, | |
51 | unsigned long offset, u32 value) | |
52 | { | |
53 | iowrite32(value, base_addr + offset); | |
54 | } | |
55 | ||
56 | /** | |
57 | * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR | |
58 | * | |
59 | * @dev: the device structure | |
60 | * @offset: register offset | |
61 | * | |
62 | * Doesn't check for aliveness while Reads 32bit data from the SeC BAR | |
63 | */ | |
64 | static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, | |
65 | unsigned long offset) | |
66 | { | |
67 | return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); | |
68 | } | |
69 | ||
70 | /** | |
71 | * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR | |
72 | * | |
73 | * @dev: the device structure | |
74 | * @offset: register offset | |
75 | * | |
76 | * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set | |
77 | */ | |
78 | static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, | |
79 | unsigned long offset) | |
80 | { | |
81 | WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); | |
82 | return mei_txe_sec_reg_read_silent(hw, offset); | |
83 | } | |
84 | /** | |
85 | * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR | |
86 | * doesn't check for aliveness | |
87 | * | |
88 | * @dev: the device structure | |
89 | * @offset: register offset | |
90 | * @value: value to write | |
91 | * | |
92 | * Doesn't check for aliveness while writes 32bit data from to the SeC BAR | |
93 | */ | |
94 | static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, | |
95 | unsigned long offset, u32 value) | |
96 | { | |
97 | mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); | |
98 | } | |
99 | ||
100 | /** | |
101 | * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR | |
102 | * | |
103 | * @dev: the device structure | |
104 | * @offset: register offset | |
105 | * @value: value to write | |
106 | * | |
107 | * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set | |
108 | */ | |
109 | static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, | |
110 | unsigned long offset, u32 value) | |
111 | { | |
112 | WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); | |
113 | mei_txe_sec_reg_write_silent(hw, offset, value); | |
114 | } | |
115 | /** | |
116 | * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR | |
117 | * | |
118 | * @hw: the device structure | |
119 | * @offset: offset from which to read the data | |
120 | * | |
121 | */ | |
122 | static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, | |
123 | unsigned long offset) | |
124 | { | |
125 | return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); | |
126 | } | |
127 | ||
128 | /** | |
129 | * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR | |
130 | * | |
131 | * @hw: the device structure | |
132 | * @offset: offset from which to write the data | |
133 | * @value: the byte to write | |
134 | */ | |
135 | static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, | |
136 | unsigned long offset, u32 value) | |
137 | { | |
138 | mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); | |
139 | } | |
140 | ||
141 | /** | |
142 | * mei_txe_aliveness_set - request for aliveness change | |
143 | * | |
144 | * @dev: the device structure | |
145 | * @req: requested aliveness value | |
146 | * | |
147 | * Request for aliveness change and returns true if the change is | |
148 | * really needed and false if aliveness is already | |
149 | * in the requested state | |
150 | * Requires device lock to be held | |
151 | */ | |
152 | static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req) | |
153 | { | |
154 | ||
155 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
156 | bool do_req = hw->aliveness != req; | |
157 | ||
158 | dev_dbg(&dev->pdev->dev, "Aliveness current=%d request=%d\n", | |
159 | hw->aliveness, req); | |
160 | if (do_req) { | |
964a2331 | 161 | dev->pg_event = MEI_PG_EVENT_WAIT; |
32e2b59f TW |
162 | mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); |
163 | } | |
164 | return do_req; | |
165 | } | |
166 | ||
167 | ||
168 | /** | |
169 | * mei_txe_aliveness_req_get - get aliveness requested register value | |
170 | * | |
171 | * @dev: the device structure | |
172 | * | |
173 | * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from | |
174 | * from HICR_HOST_ALIVENESS_REQ register value | |
175 | */ | |
176 | static u32 mei_txe_aliveness_req_get(struct mei_device *dev) | |
177 | { | |
178 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
179 | u32 reg; | |
92db1555 | 180 | |
32e2b59f TW |
181 | reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); |
182 | return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; | |
183 | } | |
184 | ||
185 | /** | |
186 | * mei_txe_aliveness_get - get aliveness response register value | |
187 | * @dev: the device structure | |
188 | * | |
189 | * Extract HICR_HOST_ALIVENESS_RESP_ACK bit | |
190 | * from HICR_HOST_ALIVENESS_RESP register value | |
191 | */ | |
192 | static u32 mei_txe_aliveness_get(struct mei_device *dev) | |
193 | { | |
194 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
195 | u32 reg; | |
92db1555 | 196 | |
32e2b59f TW |
197 | reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); |
198 | return reg & HICR_HOST_ALIVENESS_RESP_ACK; | |
199 | } | |
200 | ||
201 | /** | |
202 | * mei_txe_aliveness_poll - waits for aliveness to settle | |
203 | * | |
204 | * @dev: the device structure | |
205 | * @expected: expected aliveness value | |
206 | * | |
207 | * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set | |
208 | * returns > 0 if the expected value was received, -ETIME otherwise | |
209 | */ | |
210 | static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected) | |
211 | { | |
212 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
213 | int t = 0; | |
214 | ||
215 | do { | |
216 | hw->aliveness = mei_txe_aliveness_get(dev); | |
217 | if (hw->aliveness == expected) { | |
964a2331 | 218 | dev->pg_event = MEI_PG_EVENT_IDLE; |
32e2b59f TW |
219 | dev_dbg(&dev->pdev->dev, |
220 | "aliveness settled after %d msecs\n", t); | |
221 | return t; | |
222 | } | |
223 | mutex_unlock(&dev->device_lock); | |
224 | msleep(MSEC_PER_SEC / 5); | |
225 | mutex_lock(&dev->device_lock); | |
226 | t += MSEC_PER_SEC / 5; | |
227 | } while (t < SEC_ALIVENESS_WAIT_TIMEOUT); | |
228 | ||
964a2331 | 229 | dev->pg_event = MEI_PG_EVENT_IDLE; |
32e2b59f TW |
230 | dev_err(&dev->pdev->dev, "aliveness timed out\n"); |
231 | return -ETIME; | |
232 | } | |
233 | ||
234 | /** | |
235 | * mei_txe_aliveness_wait - waits for aliveness to settle | |
236 | * | |
237 | * @dev: the device structure | |
238 | * @expected: expected aliveness value | |
239 | * | |
240 | * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set | |
241 | * returns returns 0 on success and < 0 otherwise | |
242 | */ | |
243 | static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected) | |
244 | { | |
245 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
246 | const unsigned long timeout = | |
247 | msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT); | |
248 | long err; | |
249 | int ret; | |
250 | ||
251 | hw->aliveness = mei_txe_aliveness_get(dev); | |
252 | if (hw->aliveness == expected) | |
253 | return 0; | |
254 | ||
255 | mutex_unlock(&dev->device_lock); | |
964a2331 TW |
256 | err = wait_event_timeout(hw->wait_aliveness_resp, |
257 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
32e2b59f TW |
258 | mutex_lock(&dev->device_lock); |
259 | ||
260 | hw->aliveness = mei_txe_aliveness_get(dev); | |
261 | ret = hw->aliveness == expected ? 0 : -ETIME; | |
262 | ||
263 | if (ret) | |
964a2331 TW |
264 | dev_warn(&dev->pdev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", |
265 | err, hw->aliveness, dev->pg_event); | |
32e2b59f | 266 | else |
964a2331 TW |
267 | dev_dbg(&dev->pdev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", |
268 | jiffies_to_msecs(timeout - err), | |
269 | hw->aliveness, dev->pg_event); | |
270 | ||
271 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
32e2b59f TW |
272 | return ret; |
273 | } | |
274 | ||
275 | /** | |
276 | * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete | |
277 | * | |
278 | * @dev: the device structure | |
279 | * | |
280 | * returns returns 0 on success and < 0 otherwise | |
281 | */ | |
282 | int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req) | |
283 | { | |
284 | if (mei_txe_aliveness_set(dev, req)) | |
285 | return mei_txe_aliveness_wait(dev, req); | |
286 | return 0; | |
287 | } | |
288 | ||
ee7e5afd TW |
289 | /** |
290 | * mei_txe_pg_is_enabled - detect if PG is supported by HW | |
291 | * | |
292 | * @dev: the device structure | |
293 | * | |
294 | * returns: true is pg supported, false otherwise | |
295 | */ | |
296 | static bool mei_txe_pg_is_enabled(struct mei_device *dev) | |
297 | { | |
298 | return true; | |
299 | } | |
300 | ||
964a2331 TW |
301 | /** |
302 | * mei_txe_pg_state - translate aliveness register value | |
303 | * to the mei power gating state | |
304 | * | |
305 | * @dev: the device structure | |
306 | * | |
307 | * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise | |
308 | */ | |
309 | static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev) | |
310 | { | |
311 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 312 | |
964a2331 TW |
313 | return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; |
314 | } | |
315 | ||
32e2b59f TW |
316 | /** |
317 | * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt | |
318 | * | |
319 | * @dev: the device structure | |
320 | */ | |
321 | static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev) | |
322 | { | |
323 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
324 | u32 hintmsk; | |
325 | /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */ | |
326 | hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); | |
327 | hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY; | |
328 | mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); | |
329 | } | |
330 | ||
331 | /** | |
332 | * mei_txe_input_doorbell_set | |
333 | * - Sets bit 0 in SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL. | |
334 | * @dev: the device structure | |
335 | */ | |
336 | static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) | |
337 | { | |
338 | /* Clear the interrupt cause */ | |
339 | clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); | |
340 | mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); | |
341 | } | |
342 | ||
343 | /** | |
344 | * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1 | |
345 | * | |
346 | * @dev: the device structure | |
347 | */ | |
348 | static void mei_txe_output_ready_set(struct mei_txe_hw *hw) | |
349 | { | |
350 | mei_txe_br_reg_write(hw, | |
351 | SICR_SEC_IPC_OUTPUT_STATUS_REG, | |
352 | SEC_IPC_OUTPUT_STATUS_RDY); | |
353 | } | |
354 | ||
355 | /** | |
356 | * mei_txe_is_input_ready - check if TXE is ready for receiving data | |
357 | * | |
358 | * @dev: the device structure | |
359 | */ | |
360 | static bool mei_txe_is_input_ready(struct mei_device *dev) | |
361 | { | |
362 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
363 | u32 status; | |
92db1555 | 364 | |
32e2b59f TW |
365 | status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); |
366 | return !!(SEC_IPC_INPUT_STATUS_RDY & status); | |
367 | } | |
368 | ||
369 | /** | |
370 | * mei_txe_intr_clear - clear all interrupts | |
371 | * | |
372 | * @dev: the device structure | |
373 | */ | |
374 | static inline void mei_txe_intr_clear(struct mei_device *dev) | |
375 | { | |
376 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 377 | |
32e2b59f TW |
378 | mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, |
379 | SEC_IPC_HOST_INT_STATUS_PENDING); | |
380 | mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); | |
381 | mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); | |
382 | } | |
383 | ||
384 | /** | |
385 | * mei_txe_intr_disable - disable all interrupts | |
386 | * | |
387 | * @dev: the device structure | |
388 | */ | |
389 | static void mei_txe_intr_disable(struct mei_device *dev) | |
390 | { | |
391 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 392 | |
32e2b59f TW |
393 | mei_txe_br_reg_write(hw, HHIER_REG, 0); |
394 | mei_txe_br_reg_write(hw, HIER_REG, 0); | |
395 | } | |
396 | /** | |
397 | * mei_txe_intr_disable - enable all interrupts | |
398 | * | |
399 | * @dev: the device structure | |
400 | */ | |
401 | static void mei_txe_intr_enable(struct mei_device *dev) | |
402 | { | |
403 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 404 | |
32e2b59f TW |
405 | mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); |
406 | mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); | |
407 | } | |
408 | ||
409 | /** | |
410 | * mei_txe_pending_interrupts - check if there are pending interrupts | |
411 | * only Aliveness, Input ready, and output doorbell are of relevance | |
412 | * | |
413 | * @dev: the device structure | |
414 | * | |
415 | * Checks if there are pending interrupts | |
416 | * only Aliveness, Readiness, Input ready, and Output doorbell are relevant | |
417 | */ | |
418 | static bool mei_txe_pending_interrupts(struct mei_device *dev) | |
419 | { | |
420 | ||
421 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
422 | bool ret = (hw->intr_cause & (TXE_INTR_READINESS | | |
423 | TXE_INTR_ALIVENESS | | |
424 | TXE_INTR_IN_READY | | |
425 | TXE_INTR_OUT_DB)); | |
426 | ||
427 | if (ret) { | |
428 | dev_dbg(&dev->pdev->dev, | |
429 | "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n", | |
430 | !!(hw->intr_cause & TXE_INTR_IN_READY), | |
431 | !!(hw->intr_cause & TXE_INTR_READINESS), | |
432 | !!(hw->intr_cause & TXE_INTR_ALIVENESS), | |
433 | !!(hw->intr_cause & TXE_INTR_OUT_DB)); | |
434 | } | |
435 | return ret; | |
436 | } | |
437 | ||
438 | /** | |
439 | * mei_txe_input_payload_write - write a dword to the host buffer | |
440 | * at offset idx | |
441 | * | |
442 | * @dev: the device structure | |
443 | * @idx: index in the host buffer | |
444 | * @value: value | |
445 | */ | |
446 | static void mei_txe_input_payload_write(struct mei_device *dev, | |
447 | unsigned long idx, u32 value) | |
448 | { | |
449 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 450 | |
32e2b59f TW |
451 | mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + |
452 | (idx * sizeof(u32)), value); | |
453 | } | |
454 | ||
455 | /** | |
456 | * mei_txe_out_data_read - read dword from the device buffer | |
457 | * at offset idx | |
458 | * | |
459 | * @dev: the device structure | |
460 | * @idx: index in the device buffer | |
461 | * | |
462 | * returns register value at index | |
463 | */ | |
464 | static u32 mei_txe_out_data_read(const struct mei_device *dev, | |
465 | unsigned long idx) | |
466 | { | |
467 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 468 | |
32e2b59f TW |
469 | return mei_txe_br_reg_read(hw, |
470 | BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32))); | |
471 | } | |
472 | ||
473 | /* Readiness */ | |
474 | ||
475 | /** | |
476 | * mei_txe_readiness_set_host_rdy | |
477 | * | |
478 | * @dev: the device structure | |
479 | */ | |
480 | static void mei_txe_readiness_set_host_rdy(struct mei_device *dev) | |
481 | { | |
482 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 483 | |
32e2b59f TW |
484 | mei_txe_br_reg_write(hw, |
485 | SICR_HOST_IPC_READINESS_REQ_REG, | |
486 | SICR_HOST_IPC_READINESS_HOST_RDY); | |
487 | } | |
488 | ||
489 | /** | |
490 | * mei_txe_readiness_clear | |
491 | * | |
492 | * @dev: the device structure | |
493 | */ | |
494 | static void mei_txe_readiness_clear(struct mei_device *dev) | |
495 | { | |
496 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 497 | |
32e2b59f TW |
498 | mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, |
499 | SICR_HOST_IPC_READINESS_RDY_CLR); | |
500 | } | |
501 | /** | |
502 | * mei_txe_readiness_get - Reads and returns | |
503 | * the HICR_SEC_IPC_READINESS register value | |
504 | * | |
505 | * @dev: the device structure | |
506 | */ | |
507 | static u32 mei_txe_readiness_get(struct mei_device *dev) | |
508 | { | |
509 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 510 | |
32e2b59f TW |
511 | return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); |
512 | } | |
513 | ||
514 | ||
515 | /** | |
516 | * mei_txe_readiness_is_sec_rdy - check readiness | |
517 | * for HICR_SEC_IPC_READINESS_SEC_RDY | |
518 | * | |
519 | * @readiness - cached readiness state | |
520 | */ | |
521 | static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness) | |
522 | { | |
523 | return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY); | |
524 | } | |
525 | ||
526 | /** | |
527 | * mei_txe_hw_is_ready - check if the hw is ready | |
528 | * | |
529 | * @dev: the device structure | |
530 | */ | |
531 | static bool mei_txe_hw_is_ready(struct mei_device *dev) | |
532 | { | |
533 | u32 readiness = mei_txe_readiness_get(dev); | |
92db1555 | 534 | |
32e2b59f TW |
535 | return mei_txe_readiness_is_sec_rdy(readiness); |
536 | } | |
537 | ||
538 | /** | |
539 | * mei_txe_host_is_ready - check if the host is ready | |
540 | * | |
541 | * @dev: the device structure | |
542 | */ | |
543 | static inline bool mei_txe_host_is_ready(struct mei_device *dev) | |
544 | { | |
545 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
546 | u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); | |
92db1555 | 547 | |
32e2b59f TW |
548 | return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); |
549 | } | |
550 | ||
551 | /** | |
552 | * mei_txe_readiness_wait - wait till readiness settles | |
553 | * | |
554 | * @dev: the device structure | |
555 | * | |
556 | * returns 0 on success and -ETIME on timeout | |
557 | */ | |
558 | static int mei_txe_readiness_wait(struct mei_device *dev) | |
559 | { | |
560 | if (mei_txe_hw_is_ready(dev)) | |
561 | return 0; | |
562 | ||
563 | mutex_unlock(&dev->device_lock); | |
564 | wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, | |
565 | msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT)); | |
566 | mutex_lock(&dev->device_lock); | |
567 | if (!dev->recvd_hw_ready) { | |
568 | dev_err(&dev->pdev->dev, "wait for readiness failed\n"); | |
569 | return -ETIME; | |
570 | } | |
571 | ||
572 | dev->recvd_hw_ready = false; | |
573 | return 0; | |
574 | } | |
575 | ||
576 | /** | |
577 | * mei_txe_hw_config - configure hardware at the start of the devices | |
578 | * | |
579 | * @dev: the device structure | |
580 | * | |
581 | * Configure hardware at the start of the device should be done only | |
582 | * once at the device probe time | |
583 | */ | |
584 | static void mei_txe_hw_config(struct mei_device *dev) | |
585 | { | |
586 | ||
587 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 588 | |
32e2b59f TW |
589 | /* Doesn't change in runtime */ |
590 | dev->hbuf_depth = PAYLOAD_SIZE / 4; | |
591 | ||
592 | hw->aliveness = mei_txe_aliveness_get(dev); | |
593 | hw->readiness = mei_txe_readiness_get(dev); | |
594 | ||
595 | dev_dbg(&dev->pdev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", | |
596 | hw->aliveness, hw->readiness); | |
597 | } | |
598 | ||
599 | ||
600 | /** | |
601 | * mei_txe_write - writes a message to device. | |
602 | * | |
603 | * @dev: the device structure | |
604 | * @header: header of message | |
605 | * @buf: message buffer will be written | |
606 | * returns 1 if success, 0 - otherwise. | |
607 | */ | |
608 | ||
609 | static int mei_txe_write(struct mei_device *dev, | |
610 | struct mei_msg_hdr *header, unsigned char *buf) | |
611 | { | |
612 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
613 | unsigned long rem; | |
614 | unsigned long length; | |
9d098192 | 615 | int slots = dev->hbuf_depth; |
32e2b59f | 616 | u32 *reg_buf = (u32 *)buf; |
9d098192 | 617 | u32 dw_cnt; |
32e2b59f TW |
618 | int i; |
619 | ||
620 | if (WARN_ON(!header || !buf)) | |
621 | return -EINVAL; | |
622 | ||
623 | length = header->length; | |
624 | ||
625 | dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); | |
626 | ||
9d098192 TW |
627 | dw_cnt = mei_data2slots(length); |
628 | if (dw_cnt > slots) | |
629 | return -EMSGSIZE; | |
32e2b59f TW |
630 | |
631 | if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) | |
632 | return -EAGAIN; | |
633 | ||
634 | /* Enable Input Ready Interrupt. */ | |
635 | mei_txe_input_ready_interrupt_enable(dev); | |
636 | ||
637 | if (!mei_txe_is_input_ready(dev)) { | |
04dd3661 | 638 | struct mei_fw_status fw_status; |
92db1555 | 639 | |
04dd3661 AU |
640 | mei_fw_status(dev, &fw_status); |
641 | dev_err(&dev->pdev->dev, "Input is not ready " FW_STS_FMT "\n", | |
642 | FW_STS_PRM(fw_status)); | |
32e2b59f TW |
643 | return -EAGAIN; |
644 | } | |
645 | ||
646 | mei_txe_input_payload_write(dev, 0, *((u32 *)header)); | |
647 | ||
648 | for (i = 0; i < length / 4; i++) | |
649 | mei_txe_input_payload_write(dev, i + 1, reg_buf[i]); | |
650 | ||
651 | rem = length & 0x3; | |
652 | if (rem > 0) { | |
653 | u32 reg = 0; | |
92db1555 | 654 | |
32e2b59f TW |
655 | memcpy(®, &buf[length - rem], rem); |
656 | mei_txe_input_payload_write(dev, i + 1, reg); | |
657 | } | |
658 | ||
9d098192 TW |
659 | /* after each write the whole buffer is consumed */ |
660 | hw->slots = 0; | |
661 | ||
32e2b59f TW |
662 | /* Set Input-Doorbell */ |
663 | mei_txe_input_doorbell_set(hw); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | /** | |
669 | * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer | |
670 | * | |
671 | * @dev: the device structure | |
672 | * | |
673 | * returns the PAYLOAD_SIZE - 4 | |
674 | */ | |
675 | static size_t mei_txe_hbuf_max_len(const struct mei_device *dev) | |
676 | { | |
677 | return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr); | |
678 | } | |
679 | ||
680 | /** | |
681 | * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer | |
682 | * | |
683 | * @dev: the device structure | |
684 | * | |
685 | * returns always hbuf_depth | |
686 | */ | |
687 | static int mei_txe_hbuf_empty_slots(struct mei_device *dev) | |
688 | { | |
9d098192 | 689 | struct mei_txe_hw *hw = to_txe_hw(dev); |
92db1555 | 690 | |
9d098192 | 691 | return hw->slots; |
32e2b59f TW |
692 | } |
693 | ||
694 | /** | |
695 | * mei_txe_count_full_read_slots - mimics the me device circular buffer | |
696 | * | |
697 | * @dev: the device structure | |
698 | * | |
699 | * returns always buffer size in dwords count | |
700 | */ | |
701 | static int mei_txe_count_full_read_slots(struct mei_device *dev) | |
702 | { | |
703 | /* read buffers has static size */ | |
704 | return PAYLOAD_SIZE / 4; | |
705 | } | |
706 | ||
707 | /** | |
708 | * mei_txe_read_hdr - read message header which is always in 4 first bytes | |
709 | * | |
710 | * @dev: the device structure | |
711 | * | |
712 | * returns mei message header | |
713 | */ | |
714 | ||
715 | static u32 mei_txe_read_hdr(const struct mei_device *dev) | |
716 | { | |
717 | return mei_txe_out_data_read(dev, 0); | |
718 | } | |
719 | /** | |
720 | * mei_txe_read - reads a message from the txe device. | |
721 | * | |
722 | * @dev: the device structure | |
723 | * @buf: message buffer will be written | |
724 | * @len: message size will be read | |
725 | * | |
726 | * returns -EINVAL on error wrong argument and 0 on success | |
727 | */ | |
728 | static int mei_txe_read(struct mei_device *dev, | |
729 | unsigned char *buf, unsigned long len) | |
730 | { | |
731 | ||
732 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 TW |
733 | u32 *reg_buf, reg; |
734 | u32 rem; | |
32e2b59f | 735 | u32 i; |
32e2b59f TW |
736 | |
737 | if (WARN_ON(!buf || !len)) | |
738 | return -EINVAL; | |
739 | ||
92db1555 TW |
740 | reg_buf = (u32 *)buf; |
741 | rem = len & 0x3; | |
742 | ||
32e2b59f TW |
743 | dev_dbg(&dev->pdev->dev, |
744 | "buffer-length = %lu buf[0]0x%08X\n", | |
745 | len, mei_txe_out_data_read(dev, 0)); | |
746 | ||
747 | for (i = 0; i < len / 4; i++) { | |
748 | /* skip header: index starts from 1 */ | |
92db1555 | 749 | reg = mei_txe_out_data_read(dev, i + 1); |
32e2b59f TW |
750 | dev_dbg(&dev->pdev->dev, "buf[%d] = 0x%08X\n", i, reg); |
751 | *reg_buf++ = reg; | |
752 | } | |
753 | ||
754 | if (rem) { | |
92db1555 | 755 | reg = mei_txe_out_data_read(dev, i + 1); |
32e2b59f TW |
756 | memcpy(reg_buf, ®, rem); |
757 | } | |
758 | ||
759 | mei_txe_output_ready_set(hw); | |
760 | return 0; | |
761 | } | |
762 | ||
763 | /** | |
764 | * mei_txe_hw_reset - resets host and fw. | |
765 | * | |
766 | * @dev: the device structure | |
767 | * @intr_enable: if interrupt should be enabled after reset. | |
768 | * | |
769 | * returns 0 on success and < 0 in case of error | |
770 | */ | |
771 | static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable) | |
772 | { | |
773 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
774 | ||
775 | u32 aliveness_req; | |
776 | /* | |
777 | * read input doorbell to ensure consistency between Bridge and SeC | |
778 | * return value might be garbage return | |
779 | */ | |
780 | (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); | |
781 | ||
782 | aliveness_req = mei_txe_aliveness_req_get(dev); | |
783 | hw->aliveness = mei_txe_aliveness_get(dev); | |
784 | ||
785 | /* Disable interrupts in this stage we will poll */ | |
786 | mei_txe_intr_disable(dev); | |
787 | ||
788 | /* | |
789 | * If Aliveness Request and Aliveness Response are not equal then | |
790 | * wait for them to be equal | |
791 | * Since we might have interrupts disabled - poll for it | |
792 | */ | |
793 | if (aliveness_req != hw->aliveness) | |
794 | if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) { | |
795 | dev_err(&dev->pdev->dev, | |
796 | "wait for aliveness settle failed ... bailing out\n"); | |
797 | return -EIO; | |
798 | } | |
799 | ||
800 | /* | |
801 | * If Aliveness Request and Aliveness Response are set then clear them | |
802 | */ | |
803 | if (aliveness_req) { | |
804 | mei_txe_aliveness_set(dev, 0); | |
805 | if (mei_txe_aliveness_poll(dev, 0) < 0) { | |
806 | dev_err(&dev->pdev->dev, | |
807 | "wait for aliveness failed ... bailing out\n"); | |
808 | return -EIO; | |
809 | } | |
810 | } | |
811 | ||
812 | /* | |
813 | * Set rediness RDY_CLR bit | |
814 | */ | |
815 | mei_txe_readiness_clear(dev); | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
820 | /** | |
821 | * mei_txe_hw_start - start the hardware after reset | |
822 | * | |
823 | * @dev: the device structure | |
824 | * | |
825 | * returns 0 on success and < 0 in case of error | |
826 | */ | |
827 | static int mei_txe_hw_start(struct mei_device *dev) | |
828 | { | |
829 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
830 | int ret; | |
831 | ||
832 | u32 hisr; | |
833 | ||
834 | /* bring back interrupts */ | |
835 | mei_txe_intr_enable(dev); | |
836 | ||
837 | ret = mei_txe_readiness_wait(dev); | |
838 | if (ret < 0) { | |
839 | dev_err(&dev->pdev->dev, "wating for readiness failed\n"); | |
840 | return ret; | |
841 | } | |
842 | ||
843 | /* | |
844 | * If HISR.INT2_STS interrupt status bit is set then clear it. | |
845 | */ | |
846 | hisr = mei_txe_br_reg_read(hw, HISR_REG); | |
847 | if (hisr & HISR_INT_2_STS) | |
848 | mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); | |
849 | ||
850 | /* Clear the interrupt cause of OutputDoorbell */ | |
851 | clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); | |
852 | ||
853 | ret = mei_txe_aliveness_set_sync(dev, 1); | |
854 | if (ret < 0) { | |
855 | dev_err(&dev->pdev->dev, "wait for aliveness failed ... bailing out\n"); | |
856 | return ret; | |
857 | } | |
858 | ||
859 | /* enable input ready interrupts: | |
860 | * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK | |
861 | */ | |
862 | mei_txe_input_ready_interrupt_enable(dev); | |
863 | ||
864 | ||
865 | /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */ | |
866 | mei_txe_output_ready_set(hw); | |
867 | ||
868 | /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY | |
869 | */ | |
870 | mei_txe_readiness_set_host_rdy(dev); | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
875 | /** | |
876 | * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into | |
877 | * single bit mask and acknowledge the interrupts | |
878 | * | |
879 | * @dev: the device structure | |
880 | * @do_ack: acknowledge interrupts | |
881 | */ | |
882 | static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack) | |
883 | { | |
884 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
885 | u32 hisr; | |
886 | u32 hhisr; | |
887 | u32 ipc_isr; | |
888 | u32 aliveness; | |
889 | bool generated; | |
890 | ||
891 | /* read interrupt registers */ | |
892 | hhisr = mei_txe_br_reg_read(hw, HHISR_REG); | |
893 | generated = (hhisr & IPC_HHIER_MSK); | |
894 | if (!generated) | |
895 | goto out; | |
896 | ||
897 | hisr = mei_txe_br_reg_read(hw, HISR_REG); | |
898 | ||
899 | aliveness = mei_txe_aliveness_get(dev); | |
900 | if (hhisr & IPC_HHIER_SEC && aliveness) | |
901 | ipc_isr = mei_txe_sec_reg_read_silent(hw, | |
902 | SEC_IPC_HOST_INT_STATUS_REG); | |
903 | else | |
904 | ipc_isr = 0; | |
905 | ||
906 | generated = generated || | |
907 | (hisr & HISR_INT_STS_MSK) || | |
908 | (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING); | |
909 | ||
910 | if (generated && do_ack) { | |
911 | /* Save the interrupt causes */ | |
912 | hw->intr_cause |= hisr & HISR_INT_STS_MSK; | |
913 | if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY) | |
914 | hw->intr_cause |= TXE_INTR_IN_READY; | |
915 | ||
916 | ||
917 | mei_txe_intr_disable(dev); | |
918 | /* Clear the interrupts in hierarchy: | |
919 | * IPC and Bridge, than the High Level */ | |
920 | mei_txe_sec_reg_write_silent(hw, | |
921 | SEC_IPC_HOST_INT_STATUS_REG, ipc_isr); | |
922 | mei_txe_br_reg_write(hw, HISR_REG, hisr); | |
923 | mei_txe_br_reg_write(hw, HHISR_REG, hhisr); | |
924 | } | |
925 | ||
926 | out: | |
927 | return generated; | |
928 | } | |
929 | ||
930 | /** | |
931 | * mei_txe_irq_quick_handler - The ISR of the MEI device | |
932 | * | |
933 | * @irq: The irq number | |
934 | * @dev_id: pointer to the device structure | |
935 | * | |
936 | * returns irqreturn_t | |
937 | */ | |
938 | irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id) | |
939 | { | |
940 | struct mei_device *dev = dev_id; | |
941 | ||
942 | if (mei_txe_check_and_ack_intrs(dev, true)) | |
943 | return IRQ_WAKE_THREAD; | |
944 | return IRQ_NONE; | |
945 | } | |
946 | ||
947 | ||
948 | /** | |
949 | * mei_txe_irq_thread_handler - txe interrupt thread | |
950 | * | |
951 | * @irq: The irq number | |
952 | * @dev_id: pointer to the device structure | |
953 | * | |
954 | * returns irqreturn_t | |
955 | * | |
956 | */ | |
957 | irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id) | |
958 | { | |
959 | struct mei_device *dev = (struct mei_device *) dev_id; | |
960 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
961 | struct mei_cl_cb complete_list; | |
962 | s32 slots; | |
963 | int rets = 0; | |
964 | ||
965 | dev_dbg(&dev->pdev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", | |
966 | mei_txe_br_reg_read(hw, HHISR_REG), | |
967 | mei_txe_br_reg_read(hw, HISR_REG), | |
968 | mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); | |
969 | ||
970 | ||
971 | /* initialize our complete list */ | |
972 | mutex_lock(&dev->device_lock); | |
973 | mei_io_list_init(&complete_list); | |
974 | ||
975 | if (pci_dev_msi_enabled(dev->pdev)) | |
976 | mei_txe_check_and_ack_intrs(dev, true); | |
977 | ||
978 | /* show irq events */ | |
979 | mei_txe_pending_interrupts(dev); | |
980 | ||
981 | hw->aliveness = mei_txe_aliveness_get(dev); | |
982 | hw->readiness = mei_txe_readiness_get(dev); | |
983 | ||
984 | /* Readiness: | |
985 | * Detection of TXE driver going through reset | |
986 | * or TXE driver resetting the HECI interface. | |
987 | */ | |
988 | if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { | |
989 | dev_dbg(&dev->pdev->dev, "Readiness Interrupt was received...\n"); | |
990 | ||
991 | /* Check if SeC is going through reset */ | |
992 | if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { | |
993 | dev_dbg(&dev->pdev->dev, "we need to start the dev.\n"); | |
994 | dev->recvd_hw_ready = true; | |
995 | } else { | |
996 | dev->recvd_hw_ready = false; | |
997 | if (dev->dev_state != MEI_DEV_RESETTING) { | |
998 | ||
999 | dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n"); | |
1000 | schedule_work(&dev->reset_work); | |
1001 | goto end; | |
1002 | ||
1003 | } | |
1004 | } | |
1005 | wake_up(&dev->wait_hw_ready); | |
1006 | } | |
1007 | ||
1008 | /************************************************************/ | |
1009 | /* Check interrupt cause: | |
1010 | * Aliveness: Detection of SeC acknowledge of host request that | |
1011 | * it remain alive or host cancellation of that request. | |
1012 | */ | |
1013 | ||
1014 | if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { | |
1015 | /* Clear the interrupt cause */ | |
1016 | dev_dbg(&dev->pdev->dev, | |
1017 | "Aliveness Interrupt: Status: %d\n", hw->aliveness); | |
964a2331 TW |
1018 | dev->pg_event = MEI_PG_EVENT_RECEIVED; |
1019 | if (waitqueue_active(&hw->wait_aliveness_resp)) | |
1020 | wake_up(&hw->wait_aliveness_resp); | |
32e2b59f TW |
1021 | } |
1022 | ||
1023 | ||
1024 | /* Output Doorbell: | |
1025 | * Detection of SeC having sent output to host | |
1026 | */ | |
1027 | slots = mei_count_full_read_slots(dev); | |
1028 | if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { | |
1029 | /* Read from TXE */ | |
1030 | rets = mei_irq_read_handler(dev, &complete_list, &slots); | |
1031 | if (rets && dev->dev_state != MEI_DEV_RESETTING) { | |
1032 | dev_err(&dev->pdev->dev, | |
1033 | "mei_irq_read_handler ret = %d.\n", rets); | |
1034 | ||
1035 | schedule_work(&dev->reset_work); | |
1036 | goto end; | |
1037 | } | |
1038 | } | |
1039 | /* Input Ready: Detection if host can write to SeC */ | |
9d098192 | 1040 | if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { |
32e2b59f | 1041 | dev->hbuf_is_ready = true; |
9d098192 TW |
1042 | hw->slots = dev->hbuf_depth; |
1043 | } | |
32e2b59f TW |
1044 | |
1045 | if (hw->aliveness && dev->hbuf_is_ready) { | |
6aae48ff TW |
1046 | /* get the real register value */ |
1047 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
32e2b59f | 1048 | rets = mei_irq_write_handler(dev, &complete_list); |
6aae48ff TW |
1049 | if (rets && rets != -EMSGSIZE) |
1050 | dev_err(&dev->pdev->dev, "mei_irq_write_handler ret = %d.\n", | |
1051 | rets); | |
1052 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
32e2b59f TW |
1053 | } |
1054 | ||
32e2b59f TW |
1055 | mei_irq_compl_handler(dev, &complete_list); |
1056 | ||
1057 | end: | |
1058 | dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets); | |
1059 | ||
1060 | mutex_unlock(&dev->device_lock); | |
1061 | ||
1062 | mei_enable_interrupts(dev); | |
1063 | return IRQ_HANDLED; | |
1064 | } | |
1065 | ||
1066 | static const struct mei_hw_ops mei_txe_hw_ops = { | |
1067 | ||
1068 | .host_is_ready = mei_txe_host_is_ready, | |
1069 | ||
964a2331 TW |
1070 | .pg_state = mei_txe_pg_state, |
1071 | ||
32e2b59f TW |
1072 | .hw_is_ready = mei_txe_hw_is_ready, |
1073 | .hw_reset = mei_txe_hw_reset, | |
1074 | .hw_config = mei_txe_hw_config, | |
1075 | .hw_start = mei_txe_hw_start, | |
1076 | ||
ee7e5afd TW |
1077 | .pg_is_enabled = mei_txe_pg_is_enabled, |
1078 | ||
32e2b59f TW |
1079 | .intr_clear = mei_txe_intr_clear, |
1080 | .intr_enable = mei_txe_intr_enable, | |
1081 | .intr_disable = mei_txe_intr_disable, | |
1082 | ||
1083 | .hbuf_free_slots = mei_txe_hbuf_empty_slots, | |
1084 | .hbuf_is_ready = mei_txe_is_input_ready, | |
1085 | .hbuf_max_len = mei_txe_hbuf_max_len, | |
1086 | ||
1087 | .write = mei_txe_write, | |
1088 | ||
1089 | .rdbuf_full_slots = mei_txe_count_full_read_slots, | |
1090 | .read_hdr = mei_txe_read_hdr, | |
1091 | ||
1092 | .read = mei_txe_read, | |
1093 | ||
1094 | }; | |
1095 | ||
8d929d48 AU |
1096 | #define MEI_CFG_TXE_FW_STS \ |
1097 | .fw_status.count = 2, \ | |
1098 | .fw_status.status[0] = PCI_CFG_TXE_FW_STS0, \ | |
1099 | .fw_status.status[1] = PCI_CFG_TXE_FW_STS1 | |
1100 | ||
1101 | const struct mei_cfg mei_txe_cfg = { | |
1102 | MEI_CFG_TXE_FW_STS, | |
1103 | }; | |
1104 | ||
1105 | ||
32e2b59f TW |
1106 | /** |
1107 | * mei_txe_dev_init - allocates and initializes txe hardware specific structure | |
1108 | * | |
1109 | * @pdev - pci device | |
8d929d48 AU |
1110 | * @cfg - per device generation config |
1111 | * | |
32e2b59f TW |
1112 | * returns struct mei_device * on success or NULL; |
1113 | * | |
1114 | */ | |
8d929d48 AU |
1115 | struct mei_device *mei_txe_dev_init(struct pci_dev *pdev, |
1116 | const struct mei_cfg *cfg) | |
32e2b59f TW |
1117 | { |
1118 | struct mei_device *dev; | |
1119 | struct mei_txe_hw *hw; | |
1120 | ||
1121 | dev = kzalloc(sizeof(struct mei_device) + | |
1122 | sizeof(struct mei_txe_hw), GFP_KERNEL); | |
1123 | if (!dev) | |
1124 | return NULL; | |
1125 | ||
3a7e9b6c | 1126 | mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); |
32e2b59f TW |
1127 | |
1128 | hw = to_txe_hw(dev); | |
1129 | ||
964a2331 | 1130 | init_waitqueue_head(&hw->wait_aliveness_resp); |
32e2b59f | 1131 | |
3a7e9b6c | 1132 | dev->cfg = cfg; |
32e2b59f TW |
1133 | dev->pdev = pdev; |
1134 | return dev; | |
1135 | } | |
1136 | ||
1137 | /** | |
1138 | * mei_txe_setup_satt2 - SATT2 configuration for DMA support. | |
1139 | * | |
1140 | * @dev: the device structure | |
1141 | * @addr: physical address start of the range | |
1142 | * @range: physical range size | |
1143 | */ | |
1144 | int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range) | |
1145 | { | |
1146 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
1147 | ||
1148 | u32 lo32 = lower_32_bits(addr); | |
1149 | u32 hi32 = upper_32_bits(addr); | |
1150 | u32 ctrl; | |
1151 | ||
1152 | /* SATT is limited to 36 Bits */ | |
1153 | if (hi32 & ~0xF) | |
1154 | return -EINVAL; | |
1155 | ||
1156 | /* SATT has to be 16Byte aligned */ | |
1157 | if (lo32 & 0xF) | |
1158 | return -EINVAL; | |
1159 | ||
1160 | /* SATT range has to be 4Bytes aligned */ | |
1161 | if (range & 0x4) | |
1162 | return -EINVAL; | |
1163 | ||
1164 | /* SATT is limited to 32 MB range*/ | |
1165 | if (range > SATT_RANGE_MAX) | |
1166 | return -EINVAL; | |
1167 | ||
1168 | ctrl = SATT2_CTRL_VALID_MSK; | |
1169 | ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT; | |
1170 | ||
1171 | mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); | |
1172 | mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); | |
1173 | mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); | |
1174 | dev_dbg(&dev->pdev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", | |
1175 | range, lo32, ctrl); | |
1176 | ||
1177 | return 0; | |
1178 | } |