[deliverable/linux.git] / drivers / misc / sgi-gru / grufile.c

/*
 * SN Platform GRU Driver
 *
 *              FILE OPERATIONS & DRIVER INITIALIZATION
 *
 * This file supports the user system call for file open, close, mmap, etc.
 * This also incudes the driver initialization code.
 *
 *  Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/miscdevice.h>
#include <linux/interrupt.h>
#include <linux/proc_fs.h>
#include <linux/uaccess.h>
#ifdef CONFIG_X86_64
#include <asm/uv/uv_irq.h>
#endif
#include <asm/uv/uv.h>
#include "gru.h"
#include "grulib.h"
#include "grutables.h"

#include <asm/uv/uv_hub.h>
#include <asm/uv/uv_mmrs.h>

struct gru_blade_state *gru_base[GRU_MAX_BLADES] __read_mostly;
unsigned long gru_start_paddr __read_mostly;
void *gru_start_vaddr __read_mostly;
unsigned long gru_end_paddr __read_mostly;
unsigned int gru_max_gids __read_mostly;
struct gru_stats_s gru_stats;

/* Guaranteed user available resources on each node */
static int max_user_cbrs, max_user_dsr_bytes;

static struct miscdevice gru_miscdev;


/*
 * gru_vma_close
 *
 * Called when unmapping a device mapping. Frees all gru resources
 * and tables belonging to the vma.
 */
static void gru_vma_close(struct vm_area_struct *vma)
{
	struct gru_vma_data *vdata;
	struct gru_thread_state *gts;
	struct list_head *entry, *next;

	if (!vma->vm_private_data)
		return;

	vdata = vma->vm_private_data;
	vma->vm_private_data = NULL;
	gru_dbg(grudev, "vma %p, file %p, vdata %p\n", vma, vma->vm_file,
				vdata);
	list_for_each_safe(entry, next, &vdata->vd_head) {
		gts =
		    list_entry(entry, struct gru_thread_state, ts_next);
		list_del(&gts->ts_next);
		mutex_lock(&gts->ts_ctxlock);
		if (gts->ts_gru)
			gru_unload_context(gts, 0);
		mutex_unlock(&gts->ts_ctxlock);
		gts_drop(gts);
	}
	kfree(vdata);
	STAT(vdata_free);
}

/*
 * gru_file_mmap
 *
 * Called when mmapping the device.  Initializes the vma with a fault handler
 * and private data structure necessary to allocate, track, and free the
 * underlying pages.
 */
static int gru_file_mmap(struct file *file, struct vm_area_struct *vma)
{
	if ((vma->vm_flags & (VM_SHARED | VM_WRITE)) != (VM_SHARED | VM_WRITE))
		return -EPERM;

	if (vma->vm_start & (GRU_GSEG_PAGESIZE - 1) ||
				vma->vm_end & (GRU_GSEG_PAGESIZE - 1))
		return -EINVAL;

	vma->vm_flags |= VM_IO | VM_PFNMAP | VM_LOCKED |
			 VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP;
	vma->vm_page_prot = PAGE_SHARED;
	vma->vm_ops = &gru_vm_ops;

	vma->vm_private_data = gru_alloc_vma_data(vma, 0);
	if (!vma->vm_private_data)
		return -ENOMEM;

	gru_dbg(grudev, "file %p, vaddr 0x%lx, vma %p, vdata %p\n",
		file, vma->vm_start, vma, vma->vm_private_data);
	return 0;
}

/*
 * Create a new GRU context
 */
static int gru_create_new_context(unsigned long arg)
{
	struct gru_create_context_req req;
	struct vm_area_struct *vma;
	struct gru_vma_data *vdata;
	int ret = -EINVAL;

	if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
		return -EFAULT;

	if (req.data_segment_bytes > max_user_dsr_bytes)
		return -EINVAL;
	if (req.control_blocks > max_user_cbrs || !req.maximum_thread_count)
		return -EINVAL;

	if (!(req.options & GRU_OPT_MISS_MASK))
		req.options |= GRU_OPT_MISS_FMM_INTR;

	down_write(&current->mm->mmap_sem);
	vma = gru_find_vma(req.gseg);
	if (vma) {
		vdata = vma->vm_private_data;
		vdata->vd_user_options = req.options;
		vdata->vd_dsr_au_count =
		    GRU_DS_BYTES_TO_AU(req.data_segment_bytes);
		vdata->vd_cbr_au_count = GRU_CB_COUNT_TO_AU(req.control_blocks);
		vdata->vd_tlb_preload_count = req.tlb_preload_count;
		ret = 0;
	}
	up_write(&current->mm->mmap_sem);

	return ret;
}

/*
 * Get GRU configuration info (temp - for emulator testing)
 */
static long gru_get_config_info(unsigned long arg)
{
	struct gru_config_info info;
	int nodesperblade;

	if (num_online_nodes() > 1 &&
			(uv_node_to_blade_id(1) == uv_node_to_blade_id(0)))
		nodesperblade = 2;
	else
		nodesperblade = 1;
	info.cpus = num_online_cpus();
	info.nodes = num_online_nodes();
	info.blades = info.nodes / nodesperblade;
	info.chiplets = GRU_CHIPLETS_PER_BLADE * info.blades;

	if (copy_to_user((void __user *)arg, &info, sizeof(info)))
		return -EFAULT;
	return 0;
}

/*
 * gru_file_unlocked_ioctl
 *
 * Called to update file attributes via IOCTL calls.
 */
static long gru_file_unlocked_ioctl(struct file *file, unsigned int req,
				    unsigned long arg)
{
	int err = -EBADRQC;

	gru_dbg(grudev, "file %p, req 0x%x, 0x%lx\n", file, req, arg);

	switch (req) {
	case GRU_CREATE_CONTEXT:
		err = gru_create_new_context(arg);
		break;
	case GRU_SET_CONTEXT_OPTION:
		err = gru_set_context_option(arg);
		break;
	case GRU_USER_GET_EXCEPTION_DETAIL:
		err = gru_get_exception_detail(arg);
		break;
	case GRU_USER_UNLOAD_CONTEXT:
		err = gru_user_unload_context(arg);
		break;
	case GRU_USER_FLUSH_TLB:
		err = gru_user_flush_tlb(arg);
		break;
	case GRU_USER_CALL_OS:
		err = gru_handle_user_call_os(arg);
		break;
	case GRU_GET_GSEG_STATISTICS:
		err = gru_get_gseg_statistics(arg);
		break;
	case GRU_KTEST:
		err = gru_ktest(arg);
		break;
	case GRU_GET_CONFIG_INFO:
		err = gru_get_config_info(arg);
		break;
	case GRU_DUMP_CHIPLET_STATE:
		err = gru_dump_chiplet_request(arg);
		break;
	}
	return err;
}

/*
 * Called at init time to build tables for all GRUs that are present in the
 * system.
 */
static void gru_init_chiplet(struct gru_state *gru, unsigned long paddr,
			     void *vaddr, int blade_id, int chiplet_id)
{
	spin_lock_init(&gru->gs_lock);
	spin_lock_init(&gru->gs_asid_lock);
	gru->gs_gru_base_paddr = paddr;
	gru->gs_gru_base_vaddr = vaddr;
	gru->gs_gid = blade_id * GRU_CHIPLETS_PER_BLADE + chiplet_id;
	gru->gs_blade = gru_base[blade_id];
	gru->gs_blade_id = blade_id;
	gru->gs_chiplet_id = chiplet_id;
	gru->gs_cbr_map = (GRU_CBR_AU == 64) ? ~0 : (1UL << GRU_CBR_AU) - 1;
	gru->gs_dsr_map = (1UL << GRU_DSR_AU) - 1;
	gru->gs_asid_limit = MAX_ASID;
	gru_tgh_flush_init(gru);
	if (gru->gs_gid >= gru_max_gids)
		gru_max_gids = gru->gs_gid + 1;
	gru_dbg(grudev, "bid %d, gid %d, vaddr %p (0x%lx)\n",
		blade_id, gru->gs_gid, gru->gs_gru_base_vaddr,
		gru->gs_gru_base_paddr);
}

static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
{
	int pnode, nid, bid, chip;
	int cbrs, dsrbytes, n;
	int order = get_order(sizeof(struct gru_blade_state));
	struct page *page;
	struct gru_state *gru;
	unsigned long paddr;
	void *vaddr;

	max_user_cbrs = GRU_NUM_CB;
	max_user_dsr_bytes = GRU_NUM_DSR_BYTES;
	for_each_possible_blade(bid) {
		pnode = uv_blade_to_pnode(bid);
		nid = uv_blade_to_memory_nid(bid);/* -1 if no memory on blade */
		page = alloc_pages_node(nid, GFP_KERNEL, order);
		if (!page)
			goto fail;
		gru_base[bid] = page_address(page);
		memset(gru_base[bid], 0, sizeof(struct gru_blade_state));
		gru_base[bid]->bs_lru_gru = &gru_base[bid]->bs_grus[0];
		spin_lock_init(&gru_base[bid]->bs_lock);
		init_rwsem(&gru_base[bid]->bs_kgts_sema);

		dsrbytes = 0;
		cbrs = 0;
		for (gru = gru_base[bid]->bs_grus, chip = 0;
				chip < GRU_CHIPLETS_PER_BLADE;
				chip++, gru++) {
			paddr = gru_chiplet_paddr(gru_base_paddr, pnode, chip);
			vaddr = gru_chiplet_vaddr(gru_base_vaddr, pnode, chip);
			gru_init_chiplet(gru, paddr, vaddr, bid, chip);
			n = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
			cbrs = max(cbrs, n);
			n = hweight64(gru->gs_dsr_map) * GRU_DSR_AU_BYTES;
			dsrbytes = max(dsrbytes, n);
		}
		max_user_cbrs = min(max_user_cbrs, cbrs);
		max_user_dsr_bytes = min(max_user_dsr_bytes, dsrbytes);
	}

	return 0;

fail:
	for (bid--; bid >= 0; bid--)
		free_pages((unsigned long)gru_base[bid], order);
	return -ENOMEM;
}

static void gru_free_tables(void)
{
	int bid;
	int order = get_order(sizeof(struct gru_state) *
			      GRU_CHIPLETS_PER_BLADE);

	for (bid = 0; bid < GRU_MAX_BLADES; bid++)
		free_pages((unsigned long)gru_base[bid], order);
}

static unsigned long gru_chiplet_cpu_to_mmr(int chiplet, int cpu, int *corep)
{
	unsigned long mmr = 0;
	int core;

	/*
	 * We target the cores of a blade and not the hyperthreads themselves.
	 * There is a max of 8 cores per socket and 2 sockets per blade,
	 * making for a max total of 16 cores (i.e., 16 CPUs without
	 * hyperthreading and 32 CPUs with hyperthreading).
	 */
	core = uv_cpu_core_number(cpu) + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
	if (core >= GRU_NUM_TFM || uv_cpu_ht_number(cpu))
		return 0;

	if (chiplet == 0) {
		mmr = UVH_GR0_TLB_INT0_CONFIG +
		    core * (UVH_GR0_TLB_INT1_CONFIG - UVH_GR0_TLB_INT0_CONFIG);
	} else if (chiplet == 1) {
		mmr = UVH_GR1_TLB_INT0_CONFIG +
		    core * (UVH_GR1_TLB_INT1_CONFIG - UVH_GR1_TLB_INT0_CONFIG);
	} else {
		BUG();
	}

	*corep = core;
	return mmr;
}

#ifdef CONFIG_IA64

static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];

static void gru_noop(struct irq_data *d)
{
}

static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
	[0 ... GRU_CHIPLETS_PER_BLADE - 1] {
		.irq_mask	= gru_noop,
		.irq_unmask	= gru_noop,
		.irq_ack	= gru_noop
	}
};

static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
			irq_handler_t irq_handler, int cpu, int blade)
{
	unsigned long mmr;
	int irq = IRQ_GRU + chiplet;
	int ret, core;

	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	if (mmr == 0)
		return 0;

	if (gru_irq_count[chiplet] == 0) {
		gru_chip[chiplet].name = irq_name;
		ret = irq_set_chip(irq, &gru_chip[chiplet]);
		if (ret) {
			printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
			       GRU_DRIVER_ID_STR, -ret);
			return ret;
		}

		ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
		if (ret) {
			printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
			       GRU_DRIVER_ID_STR, -ret);
			return ret;
		}
	}
	gru_irq_count[chiplet]++;

	return 0;
}

static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
{
	unsigned long mmr;
	int core, irq = IRQ_GRU + chiplet;

	if (gru_irq_count[chiplet] == 0)
		return;

	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	if (mmr == 0)
		return;

	if (--gru_irq_count[chiplet] == 0)
		free_irq(irq, NULL);
}

#elif defined CONFIG_X86_64

static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
			irq_handler_t irq_handler, int cpu, int blade)
{
	unsigned long mmr;
	int irq, core;
	int ret;

	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	if (mmr == 0)
		return 0;

	irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
	if (irq < 0) {
		printk(KERN_ERR "%s: uv_setup_irq failed, errno=%d\n",
		       GRU_DRIVER_ID_STR, -irq);
		return irq;
	}

	ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
	if (ret) {
		uv_teardown_irq(irq);
		printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
		       GRU_DRIVER_ID_STR, -ret);
		return ret;
	}
	gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
	return 0;
}

static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
{
	int irq, core;
	unsigned long mmr;

	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	if (mmr) {
		irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
		if (irq) {
			free_irq(irq, NULL);
			uv_teardown_irq(irq);
		}
	}
}

#endif

static void gru_teardown_tlb_irqs(void)
{
	int blade;
	int cpu;

	for_each_online_cpu(cpu) {
		blade = uv_cpu_to_blade_id(cpu);
		gru_chiplet_teardown_tlb_irq(0, cpu, blade);
		gru_chiplet_teardown_tlb_irq(1, cpu, blade);
	}
	for_each_possible_blade(blade) {
		if (uv_blade_nr_possible_cpus(blade))
			continue;
		gru_chiplet_teardown_tlb_irq(0, 0, blade);
		gru_chiplet_teardown_tlb_irq(1, 0, blade);
	}
}

static int gru_setup_tlb_irqs(void)
{
	int blade;
	int cpu;
	int ret;

	for_each_online_cpu(cpu) {
		blade = uv_cpu_to_blade_id(cpu);
		ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
		if (ret != 0)
			goto exit1;

		ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
		if (ret != 0)
			goto exit1;
	}
	for_each_possible_blade(blade) {
		if (uv_blade_nr_possible_cpus(blade))
			continue;
		ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
		if (ret != 0)
			goto exit1;

		ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);
		if (ret != 0)
			goto exit1;
	}

	return 0;

exit1:
	gru_teardown_tlb_irqs();
	return ret;
}

/*
 * gru_init
 *
 * Called at boot or module load time to initialize the GRUs.
 */
static int __init gru_init(void)
{
	int ret;

	if (!is_uv_system())
		return 0;

#if defined CONFIG_IA64
	gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
#else
	gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR) &
				0x7fffffffffffUL;
#endif
	gru_start_vaddr = __va(gru_start_paddr);
	gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
	printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
	       gru_start_paddr, gru_end_paddr);
	ret = misc_register(&gru_miscdev);
	if (ret) {
		printk(KERN_ERR "%s: misc_register failed\n",
		       GRU_DRIVER_ID_STR);
		goto exit0;
	}

	ret = gru_proc_init();
	if (ret) {
		printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
		goto exit1;
	}

	ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
	if (ret) {
		printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
		goto exit2;
	}

	ret = gru_setup_tlb_irqs();
	if (ret != 0)
		goto exit3;

	gru_kservices_init();

	printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
	       GRU_DRIVER_VERSION_STR);
	return 0;

exit3:
	gru_free_tables();
exit2:
	gru_proc_exit();
exit1:
	misc_deregister(&gru_miscdev);
exit0:
	return ret;

}

static void __exit gru_exit(void)
{
	if (!is_uv_system())
		return;

	gru_teardown_tlb_irqs();
	gru_kservices_exit();
	gru_free_tables();
	misc_deregister(&gru_miscdev);
	gru_proc_exit();
}

static const struct file_operations gru_fops = {
	.owner		= THIS_MODULE,
	.unlocked_ioctl	= gru_file_unlocked_ioctl,
	.mmap		= gru_file_mmap,
	.llseek		= noop_llseek,
};

static struct miscdevice gru_miscdev = {
	.minor		= MISC_DYNAMIC_MINOR,
	.name		= "gru",
	.fops		= &gru_fops,
};

const struct vm_operations_struct gru_vm_ops = {
	.close		= gru_vma_close,
	.fault		= gru_fault,
};

#ifndef MODULE
fs_initcall(gru_init);
#else
module_init(gru_init);
#endif
module_exit(gru_exit);

module_param(gru_options, ulong, 0644);
MODULE_PARM_DESC(gru_options, "Various debug options");

MODULE_AUTHOR("Silicon Graphics, Inc.");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION(GRU_DRIVER_ID_STR GRU_DRIVER_VERSION_STR);
MODULE_VERSION(GRU_DRIVER_VERSION_STR);
Commit	Line	Data
78cf1de4 JS	1	/*
	2	* SN Platform GRU Driver
	3	*
	4	* FILE OPERATIONS & DRIVER INITIALIZATION
	5	*
	6	* This file supports the user system call for file open, close, mmap, etc.
	7	* This also incudes the driver initialization code.
	8	*
	9	* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	24	*/
	25
	26	#include <linux/module.h>
	27	#include <linux/kernel.h>
	28	#include <linux/errno.h>
	29	#include <linux/slab.h>
	30	#include <linux/mm.h>
	31	#include <linux/io.h>
78cf1de4 JS	32	#include <linux/spinlock.h>
	33	#include <linux/device.h>
	34	#include <linux/miscdevice.h>
	35	#include <linux/interrupt.h>
	36	#include <linux/proc_fs.h>
	37	#include <linux/uaccess.h>
4107e1d3 JS	38	#ifdef CONFIG_X86_64
	39	#include <asm/uv/uv_irq.h>
	40	#endif
1c004004	41	#include <asm/uv/uv.h>
78cf1de4 JS	42	#include "gru.h"
	43	#include "grulib.h"
	44	#include "grutables.h"
	45
78cf1de4 JS	46	#include <asm/uv/uv_hub.h>
	47	#include <asm/uv/uv_mmrs.h>
	48
	49	struct gru_blade_state *gru_base[GRU_MAX_BLADES] __read_mostly;
fe5bb6b0	50	unsigned long gru_start_paddr __read_mostly;
1a2c09e3	51	void *gru_start_vaddr __read_mostly;
fe5bb6b0	52	unsigned long gru_end_paddr __read_mostly;
e1c3219d	53	unsigned int gru_max_gids __read_mostly;
78cf1de4 JS	54	struct gru_stats_s gru_stats;
	55
	56	/* Guaranteed user available resources on each node */
	57	static int max_user_cbrs, max_user_dsr_bytes;
	58
78cf1de4 JS	59	static struct miscdevice gru_miscdev;
	60
	61
	62	/*
	63	* gru_vma_close
	64	*
	65	* Called when unmapping a device mapping. Frees all gru resources
	66	* and tables belonging to the vma.
	67	*/
	68	static void gru_vma_close(struct vm_area_struct *vma)
	69	{
	70	struct gru_vma_data *vdata;
	71	struct gru_thread_state *gts;
	72	struct list_head entry, next;
	73
	74	if (!vma->vm_private_data)
	75	return;
	76
	77	vdata = vma->vm_private_data;
	78	vma->vm_private_data = NULL;
	79	gru_dbg(grudev, "vma %p, file %p, vdata %p\n", vma, vma->vm_file,
	80	vdata);
	81	list_for_each_safe(entry, next, &vdata->vd_head) {
	82	gts =
	83	list_entry(entry, struct gru_thread_state, ts_next);
	84	list_del(&gts->ts_next);
	85	mutex_lock(&gts->ts_ctxlock);
	86	if (gts->ts_gru)
	87	gru_unload_context(gts, 0);
	88	mutex_unlock(&gts->ts_ctxlock);
	89	gts_drop(gts);
	90	}
	91	kfree(vdata);
	92	STAT(vdata_free);
	93	}
	94
	95	/*
	96	* gru_file_mmap
	97	*
af901ca1	98	* Called when mmapping the device. Initializes the vma with a fault handler
78cf1de4 JS	99	* and private data structure necessary to allocate, track, and free the
	100	* underlying pages.
	101	*/
	102	static int gru_file_mmap(struct file file, struct vm_area_struct vma)
	103	{
	104	if ((vma->vm_flags & (VM_SHARED \| VM_WRITE)) != (VM_SHARED \| VM_WRITE))
	105	return -EPERM;
	106
9ca8e40c	107	if (vma->vm_start & (GRU_GSEG_PAGESIZE - 1) \|\|
fe5bb6b0	108	vma->vm_end & (GRU_GSEG_PAGESIZE - 1))
9ca8e40c JS	109	return -EINVAL;
9ca8e40c JS	110
314e51b9 KK	111	vma->vm_flags \|= VM_IO \| VM_PFNMAP \| VM_LOCKED \|
314e51b9 KK	112	VM_DONTCOPY \| VM_DONTEXPAND \| VM_DONTDUMP;
78cf1de4 JS	113	vma->vm_page_prot = PAGE_SHARED;
	114	vma->vm_ops = &gru_vm_ops;
	115
	116	vma->vm_private_data = gru_alloc_vma_data(vma, 0);
	117	if (!vma->vm_private_data)
	118	return -ENOMEM;
	119
	120	gru_dbg(grudev, "file %p, vaddr 0x%lx, vma %p, vdata %p\n",
	121	file, vma->vm_start, vma, vma->vm_private_data);
	122	return 0;
	123	}
	124
	125	/*
	126	* Create a new GRU context
	127	*/
	128	static int gru_create_new_context(unsigned long arg)
	129	{
	130	struct gru_create_context_req req;
	131	struct vm_area_struct *vma;
	132	struct gru_vma_data *vdata;
	133	int ret = -EINVAL;
	134
78cf1de4 JS	135	if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
	136	return -EFAULT;
	137
3eac2e95	138	if (req.data_segment_bytes > max_user_dsr_bytes)
78cf1de4	139	return -EINVAL;
3eac2e95	140	if (req.control_blocks > max_user_cbrs \|\| !req.maximum_thread_count)
78cf1de4 JS	141	return -EINVAL;
	142
	143	if (!(req.options & GRU_OPT_MISS_MASK))
	144	req.options \|= GRU_OPT_MISS_FMM_INTR;
	145
	146	down_write(&current->mm->mmap_sem);
	147	vma = gru_find_vma(req.gseg);
	148	if (vma) {
	149	vdata = vma->vm_private_data;
	150	vdata->vd_user_options = req.options;
	151	vdata->vd_dsr_au_count =
	152	GRU_DS_BYTES_TO_AU(req.data_segment_bytes);
	153	vdata->vd_cbr_au_count = GRU_CB_COUNT_TO_AU(req.control_blocks);
c550222f	154	vdata->vd_tlb_preload_count = req.tlb_preload_count;
78cf1de4 JS	155	ret = 0;
	156	}
	157	up_write(&current->mm->mmap_sem);
	158
	159	return ret;
	160	}
	161
	162	/*
	163	* Get GRU configuration info (temp - for emulator testing)
	164	*/
	165	static long gru_get_config_info(unsigned long arg)
	166	{
	167	struct gru_config_info info;
	168	int nodesperblade;
	169
	170	if (num_online_nodes() > 1 &&
	171	(uv_node_to_blade_id(1) == uv_node_to_blade_id(0)))
	172	nodesperblade = 2;
	173	else
	174	nodesperblade = 1;
	175	info.cpus = num_online_cpus();
	176	info.nodes = num_online_nodes();
	177	info.blades = info.nodes / nodesperblade;
	178	info.chiplets = GRU_CHIPLETS_PER_BLADE * info.blades;
	179
	180	if (copy_to_user((void __user *)arg, &info, sizeof(info)))
	181	return -EFAULT;
	182	return 0;
	183	}
	184
78cf1de4 JS	185	/*
	186	* gru_file_unlocked_ioctl
	187	*
	188	* Called to update file attributes via IOCTL calls.
	189	*/
	190	static long gru_file_unlocked_ioctl(struct file *file, unsigned int req,
	191	unsigned long arg)
	192	{
	193	int err = -EBADRQC;
	194
563447d7	195	gru_dbg(grudev, "file %p, req 0x%x, 0x%lx\n", file, req, arg);
78cf1de4 JS	196
	197	switch (req) {
	198	case GRU_CREATE_CONTEXT:
	199	err = gru_create_new_context(arg);
	200	break;
92b39388 JS	201	case GRU_SET_CONTEXT_OPTION:
92b39388 JS	202	err = gru_set_context_option(arg);
78cf1de4 JS	203	break;
	204	case GRU_USER_GET_EXCEPTION_DETAIL:
	205	err = gru_get_exception_detail(arg);
	206	break;
	207	case GRU_USER_UNLOAD_CONTEXT:
	208	err = gru_user_unload_context(arg);
	209	break;
78cf1de4 JS	210	case GRU_USER_FLUSH_TLB:
	211	err = gru_user_flush_tlb(arg);
	212	break;
	213	case GRU_USER_CALL_OS:
	214	err = gru_handle_user_call_os(arg);
	215	break;
7e796a72 JS	216	case GRU_GET_GSEG_STATISTICS:
	217	err = gru_get_gseg_statistics(arg);
	218	break;
eb5bd5e5 JS	219	case GRU_KTEST:
	220	err = gru_ktest(arg);
	221	break;
78cf1de4 JS	222	case GRU_GET_CONFIG_INFO:
	223	err = gru_get_config_info(arg);
	224	break;
9cc9b056 JS	225	case GRU_DUMP_CHIPLET_STATE:
	226	err = gru_dump_chiplet_request(arg);
	227	break;
78cf1de4 JS	228	}
	229	return err;
	230	}
	231
	232	/*
	233	* Called at init time to build tables for all GRUs that are present in the
	234	* system.
	235	*/
	236	static void gru_init_chiplet(struct gru_state *gru, unsigned long paddr,
55484c45	237	void *vaddr, int blade_id, int chiplet_id)
78cf1de4 JS	238	{
	239	spin_lock_init(&gru->gs_lock);
	240	spin_lock_init(&gru->gs_asid_lock);
	241	gru->gs_gru_base_paddr = paddr;
	242	gru->gs_gru_base_vaddr = vaddr;
55484c45 JS	243	gru->gs_gid = blade_id * GRU_CHIPLETS_PER_BLADE + chiplet_id;
	244	gru->gs_blade = gru_base[blade_id];
	245	gru->gs_blade_id = blade_id;
	246	gru->gs_chiplet_id = chiplet_id;
78cf1de4 JS	247	gru->gs_cbr_map = (GRU_CBR_AU == 64) ? ~0 : (1UL << GRU_CBR_AU) - 1;
78cf1de4 JS	248	gru->gs_dsr_map = (1UL << GRU_DSR_AU) - 1;
87419412	249	gru->gs_asid_limit = MAX_ASID;
78cf1de4	250	gru_tgh_flush_init(gru);
e1c3219d JS	251	if (gru->gs_gid >= gru_max_gids)
e1c3219d JS	252	gru_max_gids = gru->gs_gid + 1;
55484c45 JS	253	gru_dbg(grudev, "bid %d, gid %d, vaddr %p (0x%lx)\n",
55484c45 JS	254	blade_id, gru->gs_gid, gru->gs_gru_base_vaddr,
78cf1de4	255	gru->gs_gru_base_paddr);
78cf1de4 JS	256	}
	257
	258	static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
	259	{
	260	int pnode, nid, bid, chip;
	261	int cbrs, dsrbytes, n;
	262	int order = get_order(sizeof(struct gru_blade_state));
	263	struct page *page;
	264	struct gru_state *gru;
	265	unsigned long paddr;
	266	void *vaddr;
	267
	268	max_user_cbrs = GRU_NUM_CB;
	269	max_user_dsr_bytes = GRU_NUM_DSR_BYTES;
827f02fe JS	270	for_each_possible_blade(bid) {
827f02fe JS	271	pnode = uv_blade_to_pnode(bid);
9178052f JS	272	nid = uv_blade_to_memory_nid(bid);/* -1 if no memory on blade */
9178052f JS	273	page = alloc_pages_node(nid, GFP_KERNEL, order);
78cf1de4 JS	274	if (!page)
	275	goto fail;
	276	gru_base[bid] = page_address(page);
	277	memset(gru_base[bid], 0, sizeof(struct gru_blade_state));
	278	gru_base[bid]->bs_lru_gru = &gru_base[bid]->bs_grus[0];
	279	spin_lock_init(&gru_base[bid]->bs_lock);
d5826dd6	280	init_rwsem(&gru_base[bid]->bs_kgts_sema);
78cf1de4 JS	281
	282	dsrbytes = 0;
	283	cbrs = 0;
	284	for (gru = gru_base[bid]->bs_grus, chip = 0;
fe5bb6b0	285	chip < GRU_CHIPLETS_PER_BLADE;
78cf1de4 JS	286	chip++, gru++) {
	287	paddr = gru_chiplet_paddr(gru_base_paddr, pnode, chip);
	288	vaddr = gru_chiplet_vaddr(gru_base_vaddr, pnode, chip);
55484c45	289	gru_init_chiplet(gru, paddr, vaddr, bid, chip);
78cf1de4 JS	290	n = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
	291	cbrs = max(cbrs, n);
	292	n = hweight64(gru->gs_dsr_map) * GRU_DSR_AU_BYTES;
	293	dsrbytes = max(dsrbytes, n);
	294	}
	295	max_user_cbrs = min(max_user_cbrs, cbrs);
	296	max_user_dsr_bytes = min(max_user_dsr_bytes, dsrbytes);
	297	}
	298
	299	return 0;
	300
	301	fail:
827f02fe JS	302	for (bid--; bid >= 0; bid--)
827f02fe JS	303	free_pages((unsigned long)gru_base[bid], order);
78cf1de4 JS	304	return -ENOMEM;
	305	}
	306
4107e1d3 JS	307	static void gru_free_tables(void)
	308	{
	309	int bid;
	310	int order = get_order(sizeof(struct gru_state) *
	311	GRU_CHIPLETS_PER_BLADE);
78cf1de4	312
4107e1d3 JS	313	for (bid = 0; bid < GRU_MAX_BLADES; bid++)
	314	free_pages((unsigned long)gru_base[bid], order);
	315	}
	316
	317	static unsigned long gru_chiplet_cpu_to_mmr(int chiplet, int cpu, int *corep)
78cf1de4	318	{
4107e1d3 JS	319	unsigned long mmr = 0;
	320	int core;
	321
	322	/*
	323	* We target the cores of a blade and not the hyperthreads themselves.
	324	* There is a max of 8 cores per socket and 2 sockets per blade,
	325	* making for a max total of 16 cores (i.e., 16 CPUs without
	326	* hyperthreading and 32 CPUs with hyperthreading).
	327	*/
	328	core = uv_cpu_core_number(cpu) + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
	329	if (core >= GRU_NUM_TFM \|\| uv_cpu_ht_number(cpu))
	330	return 0;
	331
	332	if (chiplet == 0) {
	333	mmr = UVH_GR0_TLB_INT0_CONFIG +
	334	core * (UVH_GR0_TLB_INT1_CONFIG - UVH_GR0_TLB_INT0_CONFIG);
	335	} else if (chiplet == 1) {
	336	mmr = UVH_GR1_TLB_INT0_CONFIG +
	337	core * (UVH_GR1_TLB_INT1_CONFIG - UVH_GR1_TLB_INT0_CONFIG);
	338	} else {
	339	BUG();
	340	}
	341
	342	*corep = core;
	343	return mmr;
78cf1de4 JS	344	}
78cf1de4 JS	345
4107e1d3 JS	346	#ifdef CONFIG_IA64
	347
	348	static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];
78cf1de4	349
5de1743e	350	static void gru_noop(struct irq_data *d)
78cf1de4 JS	351	{
	352	}
	353
4107e1d3 JS	354	static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
4107e1d3 JS	355	[0 ... GRU_CHIPLETS_PER_BLADE - 1] {
5de1743e WG	356	.irq_mask = gru_noop,
	357	.irq_unmask = gru_noop,
	358	.irq_ack = gru_noop
4107e1d3	359	}
78cf1de4 JS	360	};
78cf1de4 JS	361
4107e1d3 JS	362	static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
	363	irq_handler_t irq_handler, int cpu, int blade)
	364	{
	365	unsigned long mmr;
	366	int irq = IRQ_GRU + chiplet;
	367	int ret, core;
	368
	369	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	370	if (mmr == 0)
	371	return 0;
	372
	373	if (gru_irq_count[chiplet] == 0) {
	374	gru_chip[chiplet].name = irq_name;
dced35ae	375	ret = irq_set_chip(irq, &gru_chip[chiplet]);
4107e1d3 JS	376	if (ret) {
	377	printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
	378	GRU_DRIVER_ID_STR, -ret);
	379	return ret;
	380	}
	381
	382	ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
	383	if (ret) {
	384	printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
	385	GRU_DRIVER_ID_STR, -ret);
	386	return ret;
	387	}
	388	}
	389	gru_irq_count[chiplet]++;
	390
	391	return 0;
	392	}
	393
	394	static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
	395	{
	396	unsigned long mmr;
	397	int core, irq = IRQ_GRU + chiplet;
	398
	399	if (gru_irq_count[chiplet] == 0)
	400	return;
	401
	402	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	403	if (mmr == 0)
	404	return;
	405
	406	if (--gru_irq_count[chiplet] == 0)
	407	free_irq(irq, NULL);
	408	}
	409
	410	#elif defined CONFIG_X86_64
	411
	412	static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
	413	irq_handler_t irq_handler, int cpu, int blade)
	414	{
	415	unsigned long mmr;
	416	int irq, core;
	417	int ret;
	418
	419	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	420	if (mmr == 0)
	421	return 0;
	422
	423	irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
	424	if (irq < 0) {
	425	printk(KERN_ERR "%s: uv_setup_irq failed, errno=%d\n",
	426	GRU_DRIVER_ID_STR, -irq);
	427	return irq;
	428	}
	429
	430	ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
	431	if (ret) {
	432	uv_teardown_irq(irq);
	433	printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
	434	GRU_DRIVER_ID_STR, -ret);
	435	return ret;
	436	}
	437	gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
	438	return 0;
	439	}
440
441	static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
78cf1de4	442	{
4107e1d3 JS	443	int irq, core;
	444	unsigned long mmr;
	445
	446	mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
	447	if (mmr) {
	448	irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
	449	if (irq) {
	450	free_irq(irq, NULL);
	451	uv_teardown_irq(irq);
	452	}
	453	}
78cf1de4	454	}
4107e1d3	455
78cf1de4 JS	456	#endif
78cf1de4 JS	457
4107e1d3 JS	458	static void gru_teardown_tlb_irqs(void)
	459	{
	460	int blade;
	461	int cpu;
	462
	463	for_each_online_cpu(cpu) {
	464	blade = uv_cpu_to_blade_id(cpu);
	465	gru_chiplet_teardown_tlb_irq(0, cpu, blade);
	466	gru_chiplet_teardown_tlb_irq(1, cpu, blade);
	467	}
	468	for_each_possible_blade(blade) {
	469	if (uv_blade_nr_possible_cpus(blade))
	470	continue;
	471	gru_chiplet_teardown_tlb_irq(0, 0, blade);
	472	gru_chiplet_teardown_tlb_irq(1, 0, blade);
	473	}
	474	}
	475
	476	static int gru_setup_tlb_irqs(void)
	477	{
	478	int blade;
	479	int cpu;
	480	int ret;
	481
	482	for_each_online_cpu(cpu) {
	483	blade = uv_cpu_to_blade_id(cpu);
	484	ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
	485	if (ret != 0)
	486	goto exit1;
	487
	488	ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
	489	if (ret != 0)
	490	goto exit1;
	491	}
	492	for_each_possible_blade(blade) {
	493	if (uv_blade_nr_possible_cpus(blade))
	494	continue;
	495	ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
	496	if (ret != 0)
	497	goto exit1;
	498
	499	ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);
	500	if (ret != 0)
	501	goto exit1;
	502	}
	503
	504	return 0;
	505
	506	exit1:
	507	gru_teardown_tlb_irqs();
	508	return ret;
	509	}
	510
78cf1de4 JS	511	/*
	512	* gru_init
	513	*
	514	* Called at boot or module load time to initialize the GRUs.
	515	*/
	516	static int __init gru_init(void)
	517	{
4107e1d3	518	int ret;
78cf1de4	519
1c004004	520	if (!is_uv_system())
e873cff0	521	return 0;
78cf1de4 JS	522
	523	#if defined CONFIG_IA64
	524	gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
	525	#else
	526	gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR) &
	527	0x7fffffffffffUL;
78cf1de4 JS	528	#endif
78cf1de4 JS	529	gru_start_vaddr = __va(gru_start_paddr);
fe5bb6b0	530	gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
78cf1de4 JS	531	printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
78cf1de4 JS	532	gru_start_paddr, gru_end_paddr);
78cf1de4 JS	533	ret = misc_register(&gru_miscdev);
	534	if (ret) {
	535	printk(KERN_ERR "%s: misc_register failed\n",
	536	GRU_DRIVER_ID_STR);
4107e1d3	537	goto exit0;
78cf1de4 JS	538	}
	539
	540	ret = gru_proc_init();
	541	if (ret) {
	542	printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
4107e1d3	543	goto exit1;
78cf1de4 JS	544	}
	545
	546	ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
	547	if (ret) {
	548	printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
4107e1d3	549	goto exit2;
78cf1de4	550	}
4107e1d3 JS	551
	552	ret = gru_setup_tlb_irqs();
	553	if (ret != 0)
	554	goto exit3;
	555
d5826dd6	556	gru_kservices_init();
78cf1de4 JS	557
	558	printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
	559	GRU_DRIVER_VERSION_STR);
	560	return 0;
	561
	562	exit3:
4107e1d3	563	gru_free_tables();
78cf1de4	564	exit2:
4107e1d3	565	gru_proc_exit();
78cf1de4	566	exit1:
4107e1d3 JS	567	misc_deregister(&gru_miscdev);
4107e1d3 JS	568	exit0:
78cf1de4 JS	569	return ret;
	570
	571	}
	572
	573	static void __exit gru_exit(void)
	574	{
1c004004	575	if (!is_uv_system())
8275d102 RH	576	return;
8275d102 RH	577
4107e1d3	578	gru_teardown_tlb_irqs();
d5826dd6	579	gru_kservices_exit();
4107e1d3	580	gru_free_tables();
78cf1de4 JS	581	misc_deregister(&gru_miscdev);
	582	gru_proc_exit();
	583	}
	584
828c0950	585	static const struct file_operations gru_fops = {
78cf1de4 JS	586	.owner = THIS_MODULE,
	587	.unlocked_ioctl = gru_file_unlocked_ioctl,
	588	.mmap = gru_file_mmap,
6038f373	589	.llseek = noop_llseek,
78cf1de4 JS	590	};
	591
	592	static struct miscdevice gru_miscdev = {
	593	.minor = MISC_DYNAMIC_MINOR,
	594	.name = "gru",
	595	.fops = &gru_fops,
	596	};
	597
f0f37e2f	598	const struct vm_operations_struct gru_vm_ops = {
78cf1de4 JS	599	.close = gru_vma_close,
	600	.fault = gru_fault,
	601	};
	602
fe5bb6b0	603	#ifndef MODULE
026bde12	604	fs_initcall(gru_init);
fe5bb6b0 JS	605	#else
	606	module_init(gru_init);
	607	#endif
78cf1de4 JS	608	module_exit(gru_exit);
78cf1de4 JS	609
9ca8e40c JS	610	module_param(gru_options, ulong, 0644);
9ca8e40c JS	611	MODULE_PARM_DESC(gru_options, "Various debug options");
78cf1de4 JS	612
	613	MODULE_AUTHOR("Silicon Graphics, Inc.");
	614	MODULE_LICENSE("GPL");
	615	MODULE_DESCRIPTION(GRU_DRIVER_ID_STR GRU_DRIVER_VERSION_STR);
	616	MODULE_VERSION(GRU_DRIVER_VERSION_STR);
	617