[deliverable/linux.git] / drivers / mmc / host / dw_mmc-exynos.c

/*
 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
 *
 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/mmc/host.h>
#include <linux/mmc/dw_mmc.h>
#include <linux/mmc/mmc.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>

#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"

#define NUM_PINS(x)			(x + 2)

#define SDMMC_CLKSEL			0x09C
#define SDMMC_CLKSEL_CCLK_SAMPLE(x)	(((x) & 7) << 0)
#define SDMMC_CLKSEL_CCLK_DRIVE(x)	(((x) & 7) << 16)
#define SDMMC_CLKSEL_CCLK_DIVIDER(x)	(((x) & 7) << 24)
#define SDMMC_CLKSEL_GET_DRV_WD3(x)	(((x) >> 16) & 0x7)
#define SDMMC_CLKSEL_TIMING(x, y, z)	(SDMMC_CLKSEL_CCLK_SAMPLE(x) |	\
					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
					SDMMC_CLKSEL_CCLK_DIVIDER(z))
#define SDMMC_CLKSEL_WAKEUP_INT		BIT(11)

#define EXYNOS4210_FIXED_CIU_CLK_DIV	2
#define EXYNOS4412_FIXED_CIU_CLK_DIV	4

/* Block number in eMMC */
#define DWMCI_BLOCK_NUM		0xFFFFFFFF

#define SDMMC_EMMCP_BASE	0x1000
#define SDMMC_MPSECURITY	(SDMMC_EMMCP_BASE + 0x0010)
#define SDMMC_MPSBEGIN0		(SDMMC_EMMCP_BASE + 0x0200)
#define SDMMC_MPSEND0		(SDMMC_EMMCP_BASE + 0x0204)
#define SDMMC_MPSCTRL0		(SDMMC_EMMCP_BASE + 0x020C)

/* SMU control bits */
#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)
#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)
#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)
#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)
#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)
#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)
#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)
#define DWMCI_MPSCTRL_VALID			BIT(0)

#define EXYNOS_CCLKIN_MIN	50000000	/* unit: HZ */

/* Variations in Exynos specific dw-mshc controller */
enum dw_mci_exynos_type {
	DW_MCI_TYPE_EXYNOS4210,
	DW_MCI_TYPE_EXYNOS4412,
	DW_MCI_TYPE_EXYNOS5250,
	DW_MCI_TYPE_EXYNOS5420,
	DW_MCI_TYPE_EXYNOS5420_SMU,
};

/* Exynos implementation specific driver private data */
struct dw_mci_exynos_priv_data {
	enum dw_mci_exynos_type		ctrl_type;
	u8				ciu_div;
	u32				sdr_timing;
	u32				ddr_timing;
	u32				cur_speed;
};

static struct dw_mci_exynos_compatible {
	char				*compatible;
	enum dw_mci_exynos_type		ctrl_type;
} exynos_compat[] = {
	{
		.compatible	= "samsung,exynos4210-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4210,
	}, {
		.compatible	= "samsung,exynos4412-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4412,
	}, {
		.compatible	= "samsung,exynos5250-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5250,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc-smu",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420_SMU,
	},
};

static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
		mci_writel(host, MPSBEGIN0, 0);
		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
			   DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
			   DWMCI_MPSCTRL_VALID |
			   DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
	}

	return 0;
}

static int dw_mci_exynos_setup_clock(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	unsigned long rate = clk_get_rate(host->ciu_clk);

	host->bus_hz = rate / (priv->ciu_div + 1);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int dw_mci_exynos_suspend(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	return dw_mci_suspend(host);
}

static int dw_mci_exynos_resume(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	dw_mci_exynos_priv_init(host);
	return dw_mci_resume(host);
}

/**
 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
 *
 * On exynos5420 there is a silicon errata that will sometimes leave the
 * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
 * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
 * interrupts from going off constantly.
 *
 * We run this code on all exynos variants because it doesn't hurt.
 */

static int dw_mci_exynos_resume_noirq(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);
	u32 clksel;

	clksel = mci_readl(host, CLKSEL);
	if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
		mci_writel(host, CLKSEL, clksel);

	return 0;
}
#else
#define dw_mci_exynos_suspend		NULL
#define dw_mci_exynos_resume		NULL
#define dw_mci_exynos_resume_noirq	NULL
#endif /* CONFIG_PM_SLEEP */

static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
{
	/*
	 * Exynos4412 and Exynos5250 extends the use of CMD register with the
	 * use of bit 29 (which is reserved on standard MSHC controllers) for
	 * optionally bypassing the HOLD register for command and data. The
	 * HOLD register should be bypassed in case there is no phase shift
	 * applied on CMD/DATA that is sent to the card.
	 */
	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
}

static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	unsigned int wanted = ios->clock;
	unsigned long actual;
	u8 div = priv->ciu_div + 1;

	if (ios->timing == MMC_TIMING_MMC_DDR52) {
		mci_writel(host, CLKSEL, priv->ddr_timing);
		/* Should be double rate for DDR mode */
		if (ios->bus_width == MMC_BUS_WIDTH_8)
			wanted <<= 1;
	} else {
		mci_writel(host, CLKSEL, priv->sdr_timing);
	}

	/* Don't care if wanted clock is zero */
	if (!wanted)
		return;

	/* Guaranteed minimum frequency for cclkin */
	if (wanted < EXYNOS_CCLKIN_MIN)
		wanted = EXYNOS_CCLKIN_MIN;

	if (wanted != priv->cur_speed) {
		int ret = clk_set_rate(host->ciu_clk, wanted * div);
		if (ret)
			dev_warn(host->dev,
				"failed to set clk-rate %u error: %d\n",
				 wanted * div, ret);
		actual = clk_get_rate(host->ciu_clk);
		host->bus_hz = actual / div;
		priv->cur_speed = wanted;
		host->current_speed = 0;
	}
}

static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv;
	struct device_node *np = host->dev->of_node;
	u32 timing[2];
	u32 div = 0;
	int idx;
	int ret;

	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(host->dev, "mem alloc failed for private data\n");
		return -ENOMEM;
	}

	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
		if (of_device_is_compatible(np, exynos_compat[idx].compatible))
			priv->ctrl_type = exynos_compat[idx].ctrl_type;
	}

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
		priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
		priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	else {
		of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
		priv->ciu_div = div;
	}

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-sdr-timing", timing, 2);
	if (ret)
		return ret;

	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-ddr-timing", timing, 2);
	if (ret)
		return ret;

	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
	host->priv = priv;
	return 0;
}

static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
{
	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
}

static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
{
	u32 clksel;
	clksel = mci_readl(host, CLKSEL);
	clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
	mci_writel(host, CLKSEL, clksel);
}

static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
{
	u32 clksel;
	u8 sample;

	clksel = mci_readl(host, CLKSEL);
	sample = (clksel + 1) & 0x7;
	clksel = (clksel & ~0x7) | sample;
	mci_writel(host, CLKSEL, clksel);
	return sample;
}

static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
{
	const u8 iter = 8;
	u8 __c;
	s8 i, loc = -1;

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0xc7) == 0xc7) {
			loc = i;
			goto out;
		}
	}

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0x83) == 0x83) {
			loc = i;
			goto out;
		}
	}

out:
	return loc;
}

static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
					struct dw_mci_tuning_data *tuning_data)
{
	struct dw_mci *host = slot->host;
	struct mmc_host *mmc = slot->mmc;
	const u8 *blk_pattern = tuning_data->blk_pattern;
	u8 *blk_test;
	unsigned int blksz = tuning_data->blksz;
	u8 start_smpl, smpl, candiates = 0;
	s8 found = -1;
	int ret = 0;

	blk_test = kmalloc(blksz, GFP_KERNEL);
	if (!blk_test)
		return -ENOMEM;

	start_smpl = dw_mci_exynos_get_clksmpl(host);

	do {
		struct mmc_request mrq = {NULL};
		struct mmc_command cmd = {0};
		struct mmc_command stop = {0};
		struct mmc_data data = {0};
		struct scatterlist sg;

		cmd.opcode = opcode;
		cmd.arg = 0;
		cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;

		stop.opcode = MMC_STOP_TRANSMISSION;
		stop.arg = 0;
		stop.flags = MMC_RSP_R1B | MMC_CMD_AC;

		data.blksz = blksz;
		data.blocks = 1;
		data.flags = MMC_DATA_READ;
		data.sg = &sg;
		data.sg_len = 1;

		sg_init_one(&sg, blk_test, blksz);
		mrq.cmd = &cmd;
		mrq.stop = &stop;
		mrq.data = &data;
		host->mrq = &mrq;

		mci_writel(host, TMOUT, ~0);
		smpl = dw_mci_exynos_move_next_clksmpl(host);

		mmc_wait_for_req(mmc, &mrq);

		if (!cmd.error && !data.error) {
			if (!memcmp(blk_pattern, blk_test, blksz))
				candiates |= (1 << smpl);
		} else {
			dev_dbg(host->dev,
				"Tuning error: cmd.error:%d, data.error:%d\n",
				cmd.error, data.error);
		}
	} while (start_smpl != smpl);

	found = dw_mci_exynos_get_best_clksmpl(candiates);
	if (found >= 0)
		dw_mci_exynos_set_clksmpl(host, found);
	else
		ret = -EIO;

	kfree(blk_test);
	return ret;
}

/* Common capabilities of Exynos4/Exynos5 SoC */
static unsigned long exynos_dwmmc_caps[4] = {
	MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
};

static const struct dw_mci_drv_data exynos_drv_data = {
	.caps			= exynos_dwmmc_caps,
	.init			= dw_mci_exynos_priv_init,
	.setup_clock		= dw_mci_exynos_setup_clock,
	.prepare_command	= dw_mci_exynos_prepare_command,
	.set_ios		= dw_mci_exynos_set_ios,
	.parse_dt		= dw_mci_exynos_parse_dt,
	.execute_tuning		= dw_mci_exynos_execute_tuning,
};

static const struct of_device_id dw_mci_exynos_match[] = {
	{ .compatible = "samsung,exynos4412-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5250-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
			.data = &exynos_drv_data, },
	{},
};
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);

static int dw_mci_exynos_probe(struct platform_device *pdev)
{
	const struct dw_mci_drv_data *drv_data;
	const struct of_device_id *match;

	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	drv_data = match->data;
	return dw_mci_pltfm_register(pdev, drv_data);
}

static const struct dev_pm_ops dw_mci_exynos_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	.resume_noirq = dw_mci_exynos_resume_noirq,
	.thaw_noirq = dw_mci_exynos_resume_noirq,
	.restore_noirq = dw_mci_exynos_resume_noirq,
};

static struct platform_driver dw_mci_exynos_pltfm_driver = {
	.probe		= dw_mci_exynos_probe,
	.remove		= __exit_p(dw_mci_pltfm_remove),
	.driver		= {
		.name		= "dwmmc_exynos",
		.of_match_table	= dw_mci_exynos_match,
		.pm		= &dw_mci_exynos_pmops,
	},
};

module_platform_driver(dw_mci_exynos_pltfm_driver);

MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dwmmc-exynos");
Commit	Line	Data
c3665006 TA	1	/*
	2	* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
	3	*
	4	* Copyright (C) 2012, Samsung Electronics Co., Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/clk.h>
	15	#include <linux/mmc/host.h>
	16	#include <linux/mmc/dw_mmc.h>
c537a1c5	17	#include <linux/mmc/mmc.h>
c3665006 TA	18	#include <linux/of.h>
c3665006 TA	19	#include <linux/of_gpio.h>
c537a1c5	20	#include <linux/slab.h>
c3665006 TA	21
	22	#include "dw_mmc.h"
	23	#include "dw_mmc-pltfm.h"
	24
	25	#define NUM_PINS(x) (x + 2)
	26
	27	#define SDMMC_CLKSEL 0x09C
	28	#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
	29	#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
	30	#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
	31	#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
	32	#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) \| \
	33	SDMMC_CLKSEL_CCLK_DRIVE(y) \| \
	34	SDMMC_CLKSEL_CCLK_DIVIDER(z))
e2c63599	35	#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
c3665006	36
c3665006 TA	37	#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
	38	#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
	39
6bce431c YK	40	/* Block number in eMMC */
	41	#define DWMCI_BLOCK_NUM 0xFFFFFFFF
	42
	43	#define SDMMC_EMMCP_BASE 0x1000
	44	#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
	45	#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
	46	#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
	47	#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
	48
	49	/* SMU control bits */
	50	#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7)
	51	#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
	52	#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
	53	#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
	54	#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
	55	#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
	56	#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
	57	#define DWMCI_MPSCTRL_VALID BIT(0)
	58
c6d9deda SJ	59	#define EXYNOS_CCLKIN_MIN 50000000 /* unit: HZ */
c6d9deda SJ	60
c3665006 TA	61	/* Variations in Exynos specific dw-mshc controller */
	62	enum dw_mci_exynos_type {
	63	DW_MCI_TYPE_EXYNOS4210,
	64	DW_MCI_TYPE_EXYNOS4412,
	65	DW_MCI_TYPE_EXYNOS5250,
00fd041b	66	DW_MCI_TYPE_EXYNOS5420,
6bce431c	67	DW_MCI_TYPE_EXYNOS5420_SMU,
c3665006 TA	68	};
	69
	70	/* Exynos implementation specific driver private data */
	71	struct dw_mci_exynos_priv_data {
	72	enum dw_mci_exynos_type ctrl_type;
	73	u8 ciu_div;
	74	u32 sdr_timing;
	75	u32 ddr_timing;
c6d9deda	76	u32 cur_speed;
c3665006 TA	77	};
	78
	79	static struct dw_mci_exynos_compatible {
	80	char *compatible;
	81	enum dw_mci_exynos_type ctrl_type;
	82	} exynos_compat[] = {
	83	{
	84	.compatible = "samsung,exynos4210-dw-mshc",
	85	.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
	86	}, {
	87	.compatible = "samsung,exynos4412-dw-mshc",
	88	.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
	89	}, {
	90	.compatible = "samsung,exynos5250-dw-mshc",
	91	.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
00fd041b YK	92	}, {
	93	.compatible = "samsung,exynos5420-dw-mshc",
	94	.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
6bce431c YK	95	}, {
	96	.compatible = "samsung,exynos5420-dw-mshc-smu",
	97	.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
c3665006 TA	98	},
	99	};
	100
	101	static int dw_mci_exynos_priv_init(struct dw_mci *host)
	102	{
e6c784ed	103	struct dw_mci_exynos_priv_data *priv = host->priv;
c3665006	104
6bce431c YK	105	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
	106	mci_writel(host, MPSBEGIN0, 0);
	107	mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
	108	mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT \|
	109	DWMCI_MPSCTRL_NON_SECURE_READ_BIT \|
	110	DWMCI_MPSCTRL_VALID \|
	111	DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
	112	}
	113
c3665006 TA	114	return 0;
	115	}
	116
	117	static int dw_mci_exynos_setup_clock(struct dw_mci *host)
	118	{
	119	struct dw_mci_exynos_priv_data *priv = host->priv;
c6d9deda	120	unsigned long rate = clk_get_rate(host->ciu_clk);
c3665006	121
c6d9deda	122	host->bus_hz = rate / (priv->ciu_div + 1);
c3665006 TA	123	return 0;
	124	}
	125
e2c63599 DA	126	#ifdef CONFIG_PM_SLEEP
	127	static int dw_mci_exynos_suspend(struct device *dev)
	128	{
	129	struct dw_mci *host = dev_get_drvdata(dev);
	130
	131	return dw_mci_suspend(host);
	132	}
	133
	134	static int dw_mci_exynos_resume(struct device *dev)
	135	{
	136	struct dw_mci *host = dev_get_drvdata(dev);
	137
6bce431c	138	dw_mci_exynos_priv_init(host);
e2c63599 DA	139	return dw_mci_resume(host);
	140	}
	141
	142	/**
	143	* dw_mci_exynos_resume_noirq - Exynos-specific resume code
	144	*
	145	* On exynos5420 there is a silicon errata that will sometimes leave the
	146	* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
	147	* that it fired and we can clear it by writing a 1 back. Clear it to prevent
	148	* interrupts from going off constantly.
	149	*
	150	* We run this code on all exynos variants because it doesn't hurt.
	151	*/
	152
	153	static int dw_mci_exynos_resume_noirq(struct device *dev)
	154	{
	155	struct dw_mci *host = dev_get_drvdata(dev);
	156	u32 clksel;
	157
	158	clksel = mci_readl(host, CLKSEL);
	159	if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
	160	mci_writel(host, CLKSEL, clksel);
	161
	162	return 0;
	163	}
	164	#else
	165	#define dw_mci_exynos_suspend NULL
	166	#define dw_mci_exynos_resume NULL
	167	#define dw_mci_exynos_resume_noirq NULL
	168	#endif /* CONFIG_PM_SLEEP */
	169
c3665006 TA	170	static void dw_mci_exynos_prepare_command(struct dw_mci host, u32 cmdr)
	171	{
	172	/*
	173	* Exynos4412 and Exynos5250 extends the use of CMD register with the
	174	* use of bit 29 (which is reserved on standard MSHC controllers) for
	175	* optionally bypassing the HOLD register for command and data. The
	176	* HOLD register should be bypassed in case there is no phase shift
	177	* applied on CMD/DATA that is sent to the card.
	178	*/
	179	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
	180	*cmdr \|= SDMMC_CMD_USE_HOLD_REG;
	181	}
	182
	183	static void dw_mci_exynos_set_ios(struct dw_mci host, struct mmc_ios ios)
	184	{
	185	struct dw_mci_exynos_priv_data *priv = host->priv;
c6d9deda SJ	186	unsigned int wanted = ios->clock;
	187	unsigned long actual;
	188	u8 div = priv->ciu_div + 1;
c3665006	189
cab3a802	190	if (ios->timing == MMC_TIMING_MMC_DDR52) {
c3665006	191	mci_writel(host, CLKSEL, priv->ddr_timing);
c6d9deda SJ	192	/* Should be double rate for DDR mode */
	193	if (ios->bus_width == MMC_BUS_WIDTH_8)
	194	wanted <<= 1;
	195	} else {
c3665006	196	mci_writel(host, CLKSEL, priv->sdr_timing);
c6d9deda SJ	197	}
	198
	199	/* Don't care if wanted clock is zero */
	200	if (!wanted)
	201	return;
	202
	203	/* Guaranteed minimum frequency for cclkin */
	204	if (wanted < EXYNOS_CCLKIN_MIN)
	205	wanted = EXYNOS_CCLKIN_MIN;
	206
	207	if (wanted != priv->cur_speed) {
	208	int ret = clk_set_rate(host->ciu_clk, wanted * div);
	209	if (ret)
	210	dev_warn(host->dev,
	211	"failed to set clk-rate %u error: %d\n",
	212	wanted * div, ret);
	213	actual = clk_get_rate(host->ciu_clk);
	214	host->bus_hz = actual / div;
	215	priv->cur_speed = wanted;
	216	host->current_speed = 0;
	217	}
c3665006 TA	218	}
	219
	220	static int dw_mci_exynos_parse_dt(struct dw_mci *host)
	221	{
e6c784ed	222	struct dw_mci_exynos_priv_data *priv;
c3665006 TA	223	struct device_node *np = host->dev->of_node;
	224	u32 timing[2];
	225	u32 div = 0;
e6c784ed	226	int idx;
c3665006 TA	227	int ret;
c3665006 TA	228
e6c784ed YK	229	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	230	if (!priv) {
	231	dev_err(host->dev, "mem alloc failed for private data\n");
	232	return -ENOMEM;
	233	}
	234
	235	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
	236	if (of_device_is_compatible(np, exynos_compat[idx].compatible))
	237	priv->ctrl_type = exynos_compat[idx].ctrl_type;
	238	}
	239
c6d9deda SJ	240	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
	241	priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	242	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
	243	priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	244	else {
	245	of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
	246	priv->ciu_div = div;
	247	}
c3665006 TA	248
	249	ret = of_property_read_u32_array(np,
	250	"samsung,dw-mshc-sdr-timing", timing, 2);
	251	if (ret)
	252	return ret;
	253
2d9f0bd1 YK	254	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
2d9f0bd1 YK	255
c3665006 TA	256	ret = of_property_read_u32_array(np,
	257	"samsung,dw-mshc-ddr-timing", timing, 2);
	258	if (ret)
	259	return ret;
	260
	261	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
e6c784ed	262	host->priv = priv;
c3665006 TA	263	return 0;
	264	}
	265
c537a1c5 SJ	266	static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
	267	{
	268	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
	269	}
	270
	271	static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
	272	{
	273	u32 clksel;
	274	clksel = mci_readl(host, CLKSEL);
	275	clksel = (clksel & ~0x7) \| SDMMC_CLKSEL_CCLK_SAMPLE(sample);
	276	mci_writel(host, CLKSEL, clksel);
	277	}
	278
	279	static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
	280	{
	281	u32 clksel;
	282	u8 sample;
	283
	284	clksel = mci_readl(host, CLKSEL);
	285	sample = (clksel + 1) & 0x7;
	286	clksel = (clksel & ~0x7) \| sample;
	287	mci_writel(host, CLKSEL, clksel);
	288	return sample;
	289	}
	290
	291	static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
	292	{
	293	const u8 iter = 8;
	294	u8 __c;
	295	s8 i, loc = -1;
	296
	297	for (i = 0; i < iter; i++) {
	298	__c = ror8(candiates, i);
	299	if ((__c & 0xc7) == 0xc7) {
	300	loc = i;
	301	goto out;
	302	}
	303	}
	304
	305	for (i = 0; i < iter; i++) {
	306	__c = ror8(candiates, i);
	307	if ((__c & 0x83) == 0x83) {
	308	loc = i;
	309	goto out;
	310	}
	311	}
	312
	313	out:
	314	return loc;
	315	}
	316
	317	static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
	318	struct dw_mci_tuning_data *tuning_data)
	319	{
	320	struct dw_mci *host = slot->host;
	321	struct mmc_host *mmc = slot->mmc;
	322	const u8 *blk_pattern = tuning_data->blk_pattern;
	323	u8 *blk_test;
	324	unsigned int blksz = tuning_data->blksz;
	325	u8 start_smpl, smpl, candiates = 0;
	326	s8 found = -1;
	327	int ret = 0;
	328
	329	blk_test = kmalloc(blksz, GFP_KERNEL);
330	if (!blk_test)
331	return -ENOMEM;
332
333	start_smpl = dw_mci_exynos_get_clksmpl(host);
334
335	do {
336	struct mmc_request mrq = {NULL};
337	struct mmc_command cmd = {0};
338	struct mmc_command stop = {0};
339	struct mmc_data data = {0};
340	struct scatterlist sg;
341
342	cmd.opcode = opcode;
343	cmd.arg = 0;
344	cmd.flags = MMC_RSP_R1 \| MMC_CMD_ADTC;
345
346	stop.opcode = MMC_STOP_TRANSMISSION;
347	stop.arg = 0;
348	stop.flags = MMC_RSP_R1B \| MMC_CMD_AC;
349
350	data.blksz = blksz;
351	data.blocks = 1;
352	data.flags = MMC_DATA_READ;
353	data.sg = &sg;
354	data.sg_len = 1;
355
356	sg_init_one(&sg, blk_test, blksz);
357	mrq.cmd = &cmd;
358	mrq.stop = &stop;
359	mrq.data = &data;
360	host->mrq = &mrq;
361
362	mci_writel(host, TMOUT, ~0);
363	smpl = dw_mci_exynos_move_next_clksmpl(host);
364
365	mmc_wait_for_req(mmc, &mrq);
366
367	if (!cmd.error && !data.error) {
368	if (!memcmp(blk_pattern, blk_test, blksz))
369	candiates \|= (1 << smpl);
370	} else {
371	dev_dbg(host->dev,
372	"Tuning error: cmd.error:%d, data.error:%d\n",
373	cmd.error, data.error);
374	}
375	} while (start_smpl != smpl);
376
377	found = dw_mci_exynos_get_best_clksmpl(candiates);
378	if (found >= 0)
379	dw_mci_exynos_set_clksmpl(host, found);
380	else
381	ret = -EIO;
382
383	kfree(blk_test);
384	return ret;
385	}
386
0f6e73d0 DK	387	/* Common capabilities of Exynos4/Exynos5 SoC */
0f6e73d0 DK	388	static unsigned long exynos_dwmmc_caps[4] = {
cab3a802	389	MMC_CAP_1_8V_DDR \| MMC_CAP_8_BIT_DATA \| MMC_CAP_CMD23,
c3665006 TA	390	MMC_CAP_CMD23,
	391	MMC_CAP_CMD23,
	392	MMC_CAP_CMD23,
	393	};
	394
0f6e73d0 DK	395	static const struct dw_mci_drv_data exynos_drv_data = {
0f6e73d0 DK	396	.caps = exynos_dwmmc_caps,
c3665006 TA	397	.init = dw_mci_exynos_priv_init,
	398	.setup_clock = dw_mci_exynos_setup_clock,
	399	.prepare_command = dw_mci_exynos_prepare_command,
	400	.set_ios = dw_mci_exynos_set_ios,
	401	.parse_dt = dw_mci_exynos_parse_dt,
c537a1c5	402	.execute_tuning = dw_mci_exynos_execute_tuning,
c3665006 TA	403	};
	404
	405	static const struct of_device_id dw_mci_exynos_match[] = {
0f6e73d0 DK	406	{ .compatible = "samsung,exynos4412-dw-mshc",
0f6e73d0 DK	407	.data = &exynos_drv_data, },
c3665006	408	{ .compatible = "samsung,exynos5250-dw-mshc",
0f6e73d0	409	.data = &exynos_drv_data, },
00fd041b YK	410	{ .compatible = "samsung,exynos5420-dw-mshc",
00fd041b YK	411	.data = &exynos_drv_data, },
6bce431c YK	412	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
6bce431c YK	413	.data = &exynos_drv_data, },
c3665006 TA	414	{},
c3665006 TA	415	};
517cb9f1	416	MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
c3665006	417
9665f7f2	418	static int dw_mci_exynos_probe(struct platform_device *pdev)
c3665006	419	{
8e2b36ea	420	const struct dw_mci_drv_data *drv_data;
c3665006 TA	421	const struct of_device_id *match;
	422
	423	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	424	drv_data = match->data;
	425	return dw_mci_pltfm_register(pdev, drv_data);
	426	}
	427
15a2e2ab	428	static const struct dev_pm_ops dw_mci_exynos_pmops = {
e2c63599 DA	429	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	430	.resume_noirq = dw_mci_exynos_resume_noirq,
	431	.thaw_noirq = dw_mci_exynos_resume_noirq,
	432	.restore_noirq = dw_mci_exynos_resume_noirq,
	433	};
	434
c3665006 TA	435	static struct platform_driver dw_mci_exynos_pltfm_driver = {
	436	.probe = dw_mci_exynos_probe,
	437	.remove = __exit_p(dw_mci_pltfm_remove),
	438	.driver = {
	439	.name = "dwmmc_exynos",
20183d50	440	.of_match_table = dw_mci_exynos_match,
e2c63599	441	.pm = &dw_mci_exynos_pmops,
c3665006 TA	442	},
	443	};
	444
	445	module_platform_driver(dw_mci_exynos_pltfm_driver);
	446
	447	MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
	448	MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
	449	MODULE_LICENSE("GPL v2");
	450	MODULE_ALIAS("platform:dwmmc-exynos");