[deliverable/linux.git] / drivers / mmc / host / dw_mmc-exynos.c

/*
 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
 *
 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/mmc/host.h>
#include <linux/mmc/dw_mmc.h>
#include <linux/mmc/mmc.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>

#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"

#define NUM_PINS(x)			(x + 2)

#define SDMMC_CLKSEL			0x09C
#define SDMMC_CLKSEL64			0x0A8
#define SDMMC_CLKSEL_CCLK_SAMPLE(x)	(((x) & 7) << 0)
#define SDMMC_CLKSEL_CCLK_DRIVE(x)	(((x) & 7) << 16)
#define SDMMC_CLKSEL_CCLK_DIVIDER(x)	(((x) & 7) << 24)
#define SDMMC_CLKSEL_GET_DRV_WD3(x)	(((x) >> 16) & 0x7)
#define SDMMC_CLKSEL_TIMING(x, y, z)	(SDMMC_CLKSEL_CCLK_SAMPLE(x) |	\
					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
					SDMMC_CLKSEL_CCLK_DIVIDER(z))
#define SDMMC_CLKSEL_WAKEUP_INT		BIT(11)

#define EXYNOS4210_FIXED_CIU_CLK_DIV	2
#define EXYNOS4412_FIXED_CIU_CLK_DIV	4

/* Block number in eMMC */
#define DWMCI_BLOCK_NUM		0xFFFFFFFF

#define SDMMC_EMMCP_BASE	0x1000
#define SDMMC_MPSECURITY	(SDMMC_EMMCP_BASE + 0x0010)
#define SDMMC_MPSBEGIN0		(SDMMC_EMMCP_BASE + 0x0200)
#define SDMMC_MPSEND0		(SDMMC_EMMCP_BASE + 0x0204)
#define SDMMC_MPSCTRL0		(SDMMC_EMMCP_BASE + 0x020C)

/* SMU control bits */
#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)
#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)
#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)
#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)
#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)
#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)
#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)
#define DWMCI_MPSCTRL_VALID			BIT(0)

#define EXYNOS_CCLKIN_MIN	50000000	/* unit: HZ */

/* Variations in Exynos specific dw-mshc controller */
enum dw_mci_exynos_type {
	DW_MCI_TYPE_EXYNOS4210,
	DW_MCI_TYPE_EXYNOS4412,
	DW_MCI_TYPE_EXYNOS5250,
	DW_MCI_TYPE_EXYNOS5420,
	DW_MCI_TYPE_EXYNOS5420_SMU,
	DW_MCI_TYPE_EXYNOS7,
	DW_MCI_TYPE_EXYNOS7_SMU,
};

/* Exynos implementation specific driver private data */
struct dw_mci_exynos_priv_data {
	enum dw_mci_exynos_type		ctrl_type;
	u8				ciu_div;
	u32				sdr_timing;
	u32				ddr_timing;
	u32				cur_speed;
};

static struct dw_mci_exynos_compatible {
	char				*compatible;
	enum dw_mci_exynos_type		ctrl_type;
} exynos_compat[] = {
	{
		.compatible	= "samsung,exynos4210-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4210,
	}, {
		.compatible	= "samsung,exynos4412-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4412,
	}, {
		.compatible	= "samsung,exynos5250-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5250,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc-smu",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420_SMU,
	}, {
		.compatible	= "samsung,exynos7-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS7,
	}, {
		.compatible	= "samsung,exynos7-dw-mshc-smu",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS7_SMU,
	},
};

static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
		mci_writel(host, MPSBEGIN0, 0);
		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
			   DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
			   DWMCI_MPSCTRL_VALID |
			   DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
	}

	return 0;
}

static int dw_mci_exynos_setup_clock(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	unsigned long rate = clk_get_rate(host->ciu_clk);

	host->bus_hz = rate / (priv->ciu_div + 1);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int dw_mci_exynos_suspend(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	return dw_mci_suspend(host);
}

static int dw_mci_exynos_resume(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	dw_mci_exynos_priv_init(host);
	return dw_mci_resume(host);
}

/**
 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
 *
 * On exynos5420 there is a silicon errata that will sometimes leave the
 * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
 * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
 * interrupts from going off constantly.
 *
 * We run this code on all exynos variants because it doesn't hurt.
 */

static int dw_mci_exynos_resume_noirq(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 clksel;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);

	if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
			mci_writel(host, CLKSEL64, clksel);
		else
			mci_writel(host, CLKSEL, clksel);
	}

	return 0;
}
#else
#define dw_mci_exynos_suspend		NULL
#define dw_mci_exynos_resume		NULL
#define dw_mci_exynos_resume_noirq	NULL
#endif /* CONFIG_PM_SLEEP */

static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	/*
	 * Exynos4412 and Exynos5250 extends the use of CMD register with the
	 * use of bit 29 (which is reserved on standard MSHC controllers) for
	 * optionally bypassing the HOLD register for command and data. The
	 * HOLD register should be bypassed in case there is no phase shift
	 * applied on CMD/DATA that is sent to the card.
	 */
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
		if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64)))
			*cmdr |= SDMMC_CMD_USE_HOLD_REG;
	 } else {
		if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
			*cmdr |= SDMMC_CMD_USE_HOLD_REG;
	}
}

static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	unsigned int wanted = ios->clock;
	unsigned long actual;
	u8 div = priv->ciu_div + 1;

	if (ios->timing == MMC_TIMING_MMC_DDR52) {
		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
			mci_writel(host, CLKSEL64, priv->ddr_timing);
		else
			mci_writel(host, CLKSEL, priv->ddr_timing);
		/* Should be double rate for DDR mode */
		if (ios->bus_width == MMC_BUS_WIDTH_8)
			wanted <<= 1;
	} else {
		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
			mci_writel(host, CLKSEL64, priv->sdr_timing);
		else
			mci_writel(host, CLKSEL, priv->sdr_timing);
	}

	/* Don't care if wanted clock is zero */
	if (!wanted)
		return;

	/* Guaranteed minimum frequency for cclkin */
	if (wanted < EXYNOS_CCLKIN_MIN)
		wanted = EXYNOS_CCLKIN_MIN;

	if (wanted != priv->cur_speed) {
		int ret = clk_set_rate(host->ciu_clk, wanted * div);
		if (ret)
			dev_warn(host->dev,
				"failed to set clk-rate %u error: %d\n",
				 wanted * div, ret);
		actual = clk_get_rate(host->ciu_clk);
		host->bus_hz = actual / div;
		priv->cur_speed = wanted;
		host->current_speed = 0;
	}
}

static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv;
	struct device_node *np = host->dev->of_node;
	u32 timing[2];
	u32 div = 0;
	int idx;
	int ret;

	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(host->dev, "mem alloc failed for private data\n");
		return -ENOMEM;
	}

	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
		if (of_device_is_compatible(np, exynos_compat[idx].compatible))
			priv->ctrl_type = exynos_compat[idx].ctrl_type;
	}

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
		priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
		priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	else {
		of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
		priv->ciu_div = div;
	}

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-sdr-timing", timing, 2);
	if (ret)
		return ret;

	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-ddr-timing", timing, 2);
	if (ret)
		return ret;

	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
	host->priv = priv;
	return 0;
}

static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
	else
		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
}

static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
{
	u32 clksel;
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);
	clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		mci_writel(host, CLKSEL64, clksel);
	else
		mci_writel(host, CLKSEL, clksel);
}

static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 clksel;
	u8 sample;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);
	sample = (clksel + 1) & 0x7;
	clksel = (clksel & ~0x7) | sample;
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		mci_writel(host, CLKSEL64, clksel);
	else
		mci_writel(host, CLKSEL, clksel);
	return sample;
}

static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
{
	const u8 iter = 8;
	u8 __c;
	s8 i, loc = -1;

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0xc7) == 0xc7) {
			loc = i;
			goto out;
		}
	}

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0x83) == 0x83) {
			loc = i;
			goto out;
		}
	}

out:
	return loc;
}

static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
					struct dw_mci_tuning_data *tuning_data)
{
	struct dw_mci *host = slot->host;
	struct mmc_host *mmc = slot->mmc;
	const u8 *blk_pattern = tuning_data->blk_pattern;
	u8 *blk_test;
	unsigned int blksz = tuning_data->blksz;
	u8 start_smpl, smpl, candiates = 0;
	s8 found = -1;
	int ret = 0;

	blk_test = kmalloc(blksz, GFP_KERNEL);
	if (!blk_test)
		return -ENOMEM;

	start_smpl = dw_mci_exynos_get_clksmpl(host);

	do {
		struct mmc_request mrq = {NULL};
		struct mmc_command cmd = {0};
		struct mmc_command stop = {0};
		struct mmc_data data = {0};
		struct scatterlist sg;

		cmd.opcode = opcode;
		cmd.arg = 0;
		cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;

		stop.opcode = MMC_STOP_TRANSMISSION;
		stop.arg = 0;
		stop.flags = MMC_RSP_R1B | MMC_CMD_AC;

		data.blksz = blksz;
		data.blocks = 1;
		data.flags = MMC_DATA_READ;
		data.sg = &sg;
		data.sg_len = 1;

		sg_init_one(&sg, blk_test, blksz);
		mrq.cmd = &cmd;
		mrq.stop = &stop;
		mrq.data = &data;
		host->mrq = &mrq;

		mci_writel(host, TMOUT, ~0);
		smpl = dw_mci_exynos_move_next_clksmpl(host);

		mmc_wait_for_req(mmc, &mrq);

		if (!cmd.error && !data.error) {
			if (!memcmp(blk_pattern, blk_test, blksz))
				candiates |= (1 << smpl);
		} else {
			dev_dbg(host->dev,
				"Tuning error: cmd.error:%d, data.error:%d\n",
				cmd.error, data.error);
		}
	} while (start_smpl != smpl);

	found = dw_mci_exynos_get_best_clksmpl(candiates);
	if (found >= 0)
		dw_mci_exynos_set_clksmpl(host, found);
	else
		ret = -EIO;

	kfree(blk_test);
	return ret;
}

/* Common capabilities of Exynos4/Exynos5 SoC */
static unsigned long exynos_dwmmc_caps[4] = {
	MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
};

static const struct dw_mci_drv_data exynos_drv_data = {
	.caps			= exynos_dwmmc_caps,
	.init			= dw_mci_exynos_priv_init,
	.setup_clock		= dw_mci_exynos_setup_clock,
	.prepare_command	= dw_mci_exynos_prepare_command,
	.set_ios		= dw_mci_exynos_set_ios,
	.parse_dt		= dw_mci_exynos_parse_dt,
	.execute_tuning		= dw_mci_exynos_execute_tuning,
};

static const struct of_device_id dw_mci_exynos_match[] = {
	{ .compatible = "samsung,exynos4412-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5250-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos7-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos7-dw-mshc-smu",
			.data = &exynos_drv_data, },
	{},
};
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);

static int dw_mci_exynos_probe(struct platform_device *pdev)
{
	const struct dw_mci_drv_data *drv_data;
	const struct of_device_id *match;

	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	drv_data = match->data;
	return dw_mci_pltfm_register(pdev, drv_data);
}

static const struct dev_pm_ops dw_mci_exynos_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	.resume_noirq = dw_mci_exynos_resume_noirq,
	.thaw_noirq = dw_mci_exynos_resume_noirq,
	.restore_noirq = dw_mci_exynos_resume_noirq,
};

static struct platform_driver dw_mci_exynos_pltfm_driver = {
	.probe		= dw_mci_exynos_probe,
	.remove		= __exit_p(dw_mci_pltfm_remove),
	.driver		= {
		.name		= "dwmmc_exynos",
		.of_match_table	= dw_mci_exynos_match,
		.pm		= &dw_mci_exynos_pmops,
	},
};

module_platform_driver(dw_mci_exynos_pltfm_driver);

MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dwmmc-exynos");
Commit	Line	Data
c3665006 TA	1	/*
	2	* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
	3	*
	4	* Copyright (C) 2012, Samsung Electronics Co., Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/clk.h>
	15	#include <linux/mmc/host.h>
	16	#include <linux/mmc/dw_mmc.h>
c537a1c5	17	#include <linux/mmc/mmc.h>
c3665006 TA	18	#include <linux/of.h>
c3665006 TA	19	#include <linux/of_gpio.h>
c537a1c5	20	#include <linux/slab.h>
c3665006 TA	21
	22	#include "dw_mmc.h"
	23	#include "dw_mmc-pltfm.h"
	24
	25	#define NUM_PINS(x) (x + 2)
	26
	27	#define SDMMC_CLKSEL 0x09C
89ad2be7	28	#define SDMMC_CLKSEL64 0x0A8
c3665006 TA	29	#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
	30	#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
	31	#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
	32	#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
	33	#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) \| \
	34	SDMMC_CLKSEL_CCLK_DRIVE(y) \| \
	35	SDMMC_CLKSEL_CCLK_DIVIDER(z))
e2c63599	36	#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
c3665006	37
c3665006 TA	38	#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
	39	#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
	40
6bce431c YK	41	/* Block number in eMMC */
	42	#define DWMCI_BLOCK_NUM 0xFFFFFFFF
	43
	44	#define SDMMC_EMMCP_BASE 0x1000
	45	#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
	46	#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
	47	#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
	48	#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
	49
	50	/* SMU control bits */
	51	#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7)
	52	#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
	53	#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
	54	#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
	55	#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
	56	#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
	57	#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
	58	#define DWMCI_MPSCTRL_VALID BIT(0)
	59
c6d9deda SJ	60	#define EXYNOS_CCLKIN_MIN 50000000 /* unit: HZ */
c6d9deda SJ	61
c3665006 TA	62	/* Variations in Exynos specific dw-mshc controller */
	63	enum dw_mci_exynos_type {
	64	DW_MCI_TYPE_EXYNOS4210,
	65	DW_MCI_TYPE_EXYNOS4412,
	66	DW_MCI_TYPE_EXYNOS5250,
00fd041b	67	DW_MCI_TYPE_EXYNOS5420,
6bce431c	68	DW_MCI_TYPE_EXYNOS5420_SMU,
89ad2be7 AK	69	DW_MCI_TYPE_EXYNOS7,
89ad2be7 AK	70	DW_MCI_TYPE_EXYNOS7_SMU,
c3665006 TA	71	};
	72
	73	/* Exynos implementation specific driver private data */
	74	struct dw_mci_exynos_priv_data {
	75	enum dw_mci_exynos_type ctrl_type;
	76	u8 ciu_div;
	77	u32 sdr_timing;
	78	u32 ddr_timing;
c6d9deda	79	u32 cur_speed;
c3665006 TA	80	};
	81
	82	static struct dw_mci_exynos_compatible {
	83	char *compatible;
	84	enum dw_mci_exynos_type ctrl_type;
	85	} exynos_compat[] = {
	86	{
	87	.compatible = "samsung,exynos4210-dw-mshc",
	88	.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
	89	}, {
	90	.compatible = "samsung,exynos4412-dw-mshc",
	91	.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
	92	}, {
	93	.compatible = "samsung,exynos5250-dw-mshc",
	94	.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
00fd041b YK	95	}, {
	96	.compatible = "samsung,exynos5420-dw-mshc",
	97	.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
6bce431c YK	98	}, {
	99	.compatible = "samsung,exynos5420-dw-mshc-smu",
	100	.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
89ad2be7 AK	101	}, {
	102	.compatible = "samsung,exynos7-dw-mshc",
	103	.ctrl_type = DW_MCI_TYPE_EXYNOS7,
	104	}, {
	105	.compatible = "samsung,exynos7-dw-mshc-smu",
	106	.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
c3665006 TA	107	},
	108	};
	109
	110	static int dw_mci_exynos_priv_init(struct dw_mci *host)
	111	{
e6c784ed	112	struct dw_mci_exynos_priv_data *priv = host->priv;
c3665006	113
89ad2be7 AK	114	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU \|\|
89ad2be7 AK	115	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
6bce431c YK	116	mci_writel(host, MPSBEGIN0, 0);
	117	mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
	118	mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT \|
	119	DWMCI_MPSCTRL_NON_SECURE_READ_BIT \|
	120	DWMCI_MPSCTRL_VALID \|
	121	DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
	122	}
	123
c3665006 TA	124	return 0;
	125	}
	126
	127	static int dw_mci_exynos_setup_clock(struct dw_mci *host)
	128	{
	129	struct dw_mci_exynos_priv_data *priv = host->priv;
c6d9deda	130	unsigned long rate = clk_get_rate(host->ciu_clk);
c3665006	131
c6d9deda	132	host->bus_hz = rate / (priv->ciu_div + 1);
c3665006 TA	133	return 0;
	134	}
	135
e2c63599 DA	136	#ifdef CONFIG_PM_SLEEP
	137	static int dw_mci_exynos_suspend(struct device *dev)
	138	{
	139	struct dw_mci *host = dev_get_drvdata(dev);
	140
	141	return dw_mci_suspend(host);
	142	}
	143
	144	static int dw_mci_exynos_resume(struct device *dev)
	145	{
	146	struct dw_mci *host = dev_get_drvdata(dev);
	147
6bce431c	148	dw_mci_exynos_priv_init(host);
e2c63599 DA	149	return dw_mci_resume(host);
	150	}
	151
	152	/**
	153	* dw_mci_exynos_resume_noirq - Exynos-specific resume code
	154	*
	155	* On exynos5420 there is a silicon errata that will sometimes leave the
	156	* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
	157	* that it fired and we can clear it by writing a 1 back. Clear it to prevent
	158	* interrupts from going off constantly.
	159	*
	160	* We run this code on all exynos variants because it doesn't hurt.
	161	*/
	162
	163	static int dw_mci_exynos_resume_noirq(struct device *dev)
	164	{
	165	struct dw_mci *host = dev_get_drvdata(dev);
89ad2be7	166	struct dw_mci_exynos_priv_data *priv = host->priv;
e2c63599 DA	167	u32 clksel;
e2c63599 DA	168
89ad2be7 AK	169	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	170	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	171	clksel = mci_readl(host, CLKSEL64);
	172	else
	173	clksel = mci_readl(host, CLKSEL);
	174
	175	if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
	176	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	177	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	178	mci_writel(host, CLKSEL64, clksel);
	179	else
	180	mci_writel(host, CLKSEL, clksel);
	181	}
e2c63599 DA	182
	183	return 0;
	184	}
	185	#else
	186	#define dw_mci_exynos_suspend NULL
	187	#define dw_mci_exynos_resume NULL
	188	#define dw_mci_exynos_resume_noirq NULL
	189	#endif /* CONFIG_PM_SLEEP */
	190
c3665006 TA	191	static void dw_mci_exynos_prepare_command(struct dw_mci host, u32 cmdr)
c3665006 TA	192	{
89ad2be7	193	struct dw_mci_exynos_priv_data *priv = host->priv;
c3665006 TA	194	/*
	195	* Exynos4412 and Exynos5250 extends the use of CMD register with the
	196	* use of bit 29 (which is reserved on standard MSHC controllers) for
	197	* optionally bypassing the HOLD register for command and data. The
	198	* HOLD register should be bypassed in case there is no phase shift
	199	* applied on CMD/DATA that is sent to the card.
	200	*/
89ad2be7 AK	201	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	202	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
	203	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64)))
	204	*cmdr \|= SDMMC_CMD_USE_HOLD_REG;
	205	} else {
	206	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
	207	*cmdr \|= SDMMC_CMD_USE_HOLD_REG;
	208	}
c3665006 TA	209	}
	210
	211	static void dw_mci_exynos_set_ios(struct dw_mci host, struct mmc_ios ios)
	212	{
	213	struct dw_mci_exynos_priv_data *priv = host->priv;
c6d9deda SJ	214	unsigned int wanted = ios->clock;
	215	unsigned long actual;
	216	u8 div = priv->ciu_div + 1;
c3665006	217
cab3a802	218	if (ios->timing == MMC_TIMING_MMC_DDR52) {
89ad2be7 AK	219	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	220	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	221	mci_writel(host, CLKSEL64, priv->ddr_timing);
	222	else
	223	mci_writel(host, CLKSEL, priv->ddr_timing);
c6d9deda SJ	224	/* Should be double rate for DDR mode */
	225	if (ios->bus_width == MMC_BUS_WIDTH_8)
	226	wanted <<= 1;
	227	} else {
89ad2be7 AK	228	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	229	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	230	mci_writel(host, CLKSEL64, priv->sdr_timing);
	231	else
	232	mci_writel(host, CLKSEL, priv->sdr_timing);
c6d9deda SJ	233	}
	234
	235	/* Don't care if wanted clock is zero */
	236	if (!wanted)
	237	return;
	238
	239	/* Guaranteed minimum frequency for cclkin */
	240	if (wanted < EXYNOS_CCLKIN_MIN)
	241	wanted = EXYNOS_CCLKIN_MIN;
	242
	243	if (wanted != priv->cur_speed) {
	244	int ret = clk_set_rate(host->ciu_clk, wanted * div);
	245	if (ret)
	246	dev_warn(host->dev,
	247	"failed to set clk-rate %u error: %d\n",
	248	wanted * div, ret);
	249	actual = clk_get_rate(host->ciu_clk);
	250	host->bus_hz = actual / div;
	251	priv->cur_speed = wanted;
	252	host->current_speed = 0;
	253	}
c3665006 TA	254	}
	255
	256	static int dw_mci_exynos_parse_dt(struct dw_mci *host)
	257	{
e6c784ed	258	struct dw_mci_exynos_priv_data *priv;
c3665006 TA	259	struct device_node *np = host->dev->of_node;
	260	u32 timing[2];
	261	u32 div = 0;
e6c784ed	262	int idx;
c3665006 TA	263	int ret;
c3665006 TA	264
e6c784ed YK	265	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	266	if (!priv) {
	267	dev_err(host->dev, "mem alloc failed for private data\n");
	268	return -ENOMEM;
	269	}
	270
	271	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
	272	if (of_device_is_compatible(np, exynos_compat[idx].compatible))
	273	priv->ctrl_type = exynos_compat[idx].ctrl_type;
	274	}
	275
c6d9deda SJ	276	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
	277	priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	278	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
	279	priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	280	else {
	281	of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
	282	priv->ciu_div = div;
	283	}
c3665006 TA	284
	285	ret = of_property_read_u32_array(np,
	286	"samsung,dw-mshc-sdr-timing", timing, 2);
	287	if (ret)
	288	return ret;
	289
2d9f0bd1 YK	290	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
2d9f0bd1 YK	291
c3665006 TA	292	ret = of_property_read_u32_array(np,
	293	"samsung,dw-mshc-ddr-timing", timing, 2);
	294	if (ret)
	295	return ret;
	296
	297	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
e6c784ed	298	host->priv = priv;
c3665006 TA	299	return 0;
	300	}
	301
c537a1c5 SJ	302	static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
c537a1c5 SJ	303	{
89ad2be7 AK	304	struct dw_mci_exynos_priv_data *priv = host->priv;
	305
	306	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	307	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	308	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
	309	else
	310	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
c537a1c5 SJ	311	}
	312
	313	static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
	314	{
	315	u32 clksel;
89ad2be7 AK	316	struct dw_mci_exynos_priv_data *priv = host->priv;
	317
	318	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	319	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	320	clksel = mci_readl(host, CLKSEL64);
	321	else
	322	clksel = mci_readl(host, CLKSEL);
c537a1c5	323	clksel = (clksel & ~0x7) \| SDMMC_CLKSEL_CCLK_SAMPLE(sample);
89ad2be7 AK	324	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	325	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	326	mci_writel(host, CLKSEL64, clksel);
	327	else
	328	mci_writel(host, CLKSEL, clksel);
c537a1c5 SJ	329	}
	330
	331	static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
	332	{
89ad2be7	333	struct dw_mci_exynos_priv_data *priv = host->priv;
c537a1c5 SJ	334	u32 clksel;
	335	u8 sample;
	336
89ad2be7 AK	337	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	338	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	339	clksel = mci_readl(host, CLKSEL64);
	340	else
	341	clksel = mci_readl(host, CLKSEL);
c537a1c5 SJ	342	sample = (clksel + 1) & 0x7;
c537a1c5 SJ	343	clksel = (clksel & ~0x7) \| sample;
89ad2be7 AK	344	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	345	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	346	mci_writel(host, CLKSEL64, clksel);
	347	else
	348	mci_writel(host, CLKSEL, clksel);
c537a1c5 SJ	349	return sample;
	350	}
	351
	352	static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
	353	{
	354	const u8 iter = 8;
	355	u8 __c;
	356	s8 i, loc = -1;
	357
	358	for (i = 0; i < iter; i++) {
	359	__c = ror8(candiates, i);
	360	if ((__c & 0xc7) == 0xc7) {
	361	loc = i;
	362	goto out;
	363	}
	364	}
	365
	366	for (i = 0; i < iter; i++) {
	367	__c = ror8(candiates, i);
	368	if ((__c & 0x83) == 0x83) {
	369	loc = i;
	370	goto out;
	371	}
	372	}
	373
	374	out:
	375	return loc;
	376	}
	377
	378	static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
	379	struct dw_mci_tuning_data *tuning_data)
	380	{
	381	struct dw_mci *host = slot->host;
	382	struct mmc_host *mmc = slot->mmc;
	383	const u8 *blk_pattern = tuning_data->blk_pattern;
	384	u8 *blk_test;
	385	unsigned int blksz = tuning_data->blksz;
	386	u8 start_smpl, smpl, candiates = 0;
	387	s8 found = -1;
	388	int ret = 0;
	389
	390	blk_test = kmalloc(blksz, GFP_KERNEL);
	391	if (!blk_test)
	392	return -ENOMEM;
	393
	394	start_smpl = dw_mci_exynos_get_clksmpl(host);
	395
	396	do {
	397	struct mmc_request mrq = {NULL};
	398	struct mmc_command cmd = {0};
	399	struct mmc_command stop = {0};
	400	struct mmc_data data = {0};
	401	struct scatterlist sg;
	402
	403	cmd.opcode = opcode;
	404	cmd.arg = 0;
	405	cmd.flags = MMC_RSP_R1 \| MMC_CMD_ADTC;
	406
	407	stop.opcode = MMC_STOP_TRANSMISSION;
	408	stop.arg = 0;
	409	stop.flags = MMC_RSP_R1B \| MMC_CMD_AC;
	410
	411	data.blksz = blksz;
	412	data.blocks = 1;
413	data.flags = MMC_DATA_READ;
414	data.sg = &sg;
415	data.sg_len = 1;
416
417	sg_init_one(&sg, blk_test, blksz);
418	mrq.cmd = &cmd;
419	mrq.stop = &stop;
420	mrq.data = &data;
421	host->mrq = &mrq;
422
423	mci_writel(host, TMOUT, ~0);
424	smpl = dw_mci_exynos_move_next_clksmpl(host);
425
426	mmc_wait_for_req(mmc, &mrq);
427
428	if (!cmd.error && !data.error) {
429	if (!memcmp(blk_pattern, blk_test, blksz))
430	candiates \|= (1 << smpl);
431	} else {
432	dev_dbg(host->dev,
433	"Tuning error: cmd.error:%d, data.error:%d\n",
434	cmd.error, data.error);
435	}
436	} while (start_smpl != smpl);
437
438	found = dw_mci_exynos_get_best_clksmpl(candiates);
439	if (found >= 0)
440	dw_mci_exynos_set_clksmpl(host, found);
441	else
442	ret = -EIO;
443
444	kfree(blk_test);
445	return ret;
446	}
447
0f6e73d0 DK	448	/* Common capabilities of Exynos4/Exynos5 SoC */
0f6e73d0 DK	449	static unsigned long exynos_dwmmc_caps[4] = {
cab3a802	450	MMC_CAP_1_8V_DDR \| MMC_CAP_8_BIT_DATA \| MMC_CAP_CMD23,
c3665006 TA	451	MMC_CAP_CMD23,
	452	MMC_CAP_CMD23,
	453	MMC_CAP_CMD23,
	454	};
	455
0f6e73d0 DK	456	static const struct dw_mci_drv_data exynos_drv_data = {
0f6e73d0 DK	457	.caps = exynos_dwmmc_caps,
c3665006 TA	458	.init = dw_mci_exynos_priv_init,
	459	.setup_clock = dw_mci_exynos_setup_clock,
	460	.prepare_command = dw_mci_exynos_prepare_command,
	461	.set_ios = dw_mci_exynos_set_ios,
	462	.parse_dt = dw_mci_exynos_parse_dt,
c537a1c5	463	.execute_tuning = dw_mci_exynos_execute_tuning,
c3665006 TA	464	};
	465
	466	static const struct of_device_id dw_mci_exynos_match[] = {
0f6e73d0 DK	467	{ .compatible = "samsung,exynos4412-dw-mshc",
0f6e73d0 DK	468	.data = &exynos_drv_data, },
c3665006	469	{ .compatible = "samsung,exynos5250-dw-mshc",
0f6e73d0	470	.data = &exynos_drv_data, },
00fd041b YK	471	{ .compatible = "samsung,exynos5420-dw-mshc",
00fd041b YK	472	.data = &exynos_drv_data, },
6bce431c YK	473	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
6bce431c YK	474	.data = &exynos_drv_data, },
89ad2be7 AK	475	{ .compatible = "samsung,exynos7-dw-mshc",
	476	.data = &exynos_drv_data, },
	477	{ .compatible = "samsung,exynos7-dw-mshc-smu",
	478	.data = &exynos_drv_data, },
c3665006 TA	479	{},
c3665006 TA	480	};
517cb9f1	481	MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
c3665006	482
9665f7f2	483	static int dw_mci_exynos_probe(struct platform_device *pdev)
c3665006	484	{
8e2b36ea	485	const struct dw_mci_drv_data *drv_data;
c3665006 TA	486	const struct of_device_id *match;
	487
	488	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	489	drv_data = match->data;
	490	return dw_mci_pltfm_register(pdev, drv_data);
	491	}
	492
15a2e2ab	493	static const struct dev_pm_ops dw_mci_exynos_pmops = {
e2c63599 DA	494	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	495	.resume_noirq = dw_mci_exynos_resume_noirq,
	496	.thaw_noirq = dw_mci_exynos_resume_noirq,
	497	.restore_noirq = dw_mci_exynos_resume_noirq,
	498	};
	499
c3665006 TA	500	static struct platform_driver dw_mci_exynos_pltfm_driver = {
	501	.probe = dw_mci_exynos_probe,
	502	.remove = __exit_p(dw_mci_pltfm_remove),
	503	.driver = {
	504	.name = "dwmmc_exynos",
20183d50	505	.of_match_table = dw_mci_exynos_match,
e2c63599	506	.pm = &dw_mci_exynos_pmops,
c3665006 TA	507	},
	508	};
	509
	510	module_platform_driver(dw_mci_exynos_pltfm_driver);
	511
	512	MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
	513	MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
	514	MODULE_LICENSE("GPL v2");
	515	MODULE_ALIAS("platform:dwmmc-exynos");