[deliverable/linux.git] / drivers / mmc / host / dw_mmc-exynos.c

/*
 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
 *
 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/mmc/host.h>
#include <linux/mmc/dw_mmc.h>
#include <linux/mmc/mmc.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>

#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
#include "dw_mmc-exynos.h"

/* Variations in Exynos specific dw-mshc controller */
enum dw_mci_exynos_type {
	DW_MCI_TYPE_EXYNOS4210,
	DW_MCI_TYPE_EXYNOS4412,
	DW_MCI_TYPE_EXYNOS5250,
	DW_MCI_TYPE_EXYNOS5420,
	DW_MCI_TYPE_EXYNOS5420_SMU,
	DW_MCI_TYPE_EXYNOS7,
	DW_MCI_TYPE_EXYNOS7_SMU,
};

/* Exynos implementation specific driver private data */
struct dw_mci_exynos_priv_data {
	enum dw_mci_exynos_type		ctrl_type;
	u8				ciu_div;
	u32				sdr_timing;
	u32				ddr_timing;
	u32				cur_speed;
};

static struct dw_mci_exynos_compatible {
	char				*compatible;
	enum dw_mci_exynos_type		ctrl_type;
} exynos_compat[] = {
	{
		.compatible	= "samsung,exynos4210-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4210,
	}, {
		.compatible	= "samsung,exynos4412-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4412,
	}, {
		.compatible	= "samsung,exynos5250-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5250,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc-smu",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420_SMU,
	}, {
		.compatible	= "samsung,exynos7-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS7,
	}, {
		.compatible	= "samsung,exynos7-dw-mshc-smu",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS7_SMU,
	},
};

static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
		mci_writel(host, MPSBEGIN0, 0);
		mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
		mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
			   SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
			   SDMMC_MPSCTRL_VALID |
			   SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
	}

	return 0;
}

static int dw_mci_exynos_setup_clock(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	host->bus_hz /= (priv->ciu_div + 1);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int dw_mci_exynos_suspend(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	return dw_mci_suspend(host);
}

static int dw_mci_exynos_resume(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	dw_mci_exynos_priv_init(host);
	return dw_mci_resume(host);
}

/**
 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
 *
 * On exynos5420 there is a silicon errata that will sometimes leave the
 * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
 * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
 * interrupts from going off constantly.
 *
 * We run this code on all exynos variants because it doesn't hurt.
 */

static int dw_mci_exynos_resume_noirq(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 clksel;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);

	if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
			mci_writel(host, CLKSEL64, clksel);
		else
			mci_writel(host, CLKSEL, clksel);
	}

	return 0;
}
#else
#define dw_mci_exynos_suspend		NULL
#define dw_mci_exynos_resume		NULL
#define dw_mci_exynos_resume_noirq	NULL
#endif /* CONFIG_PM_SLEEP */

static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	/*
	 * Exynos4412 and Exynos5250 extends the use of CMD register with the
	 * use of bit 29 (which is reserved on standard MSHC controllers) for
	 * optionally bypassing the HOLD register for command and data. The
	 * HOLD register should be bypassed in case there is no phase shift
	 * applied on CMD/DATA that is sent to the card.
	 */
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
		if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64)))
			*cmdr |= SDMMC_CMD_USE_HOLD_REG;
	 } else {
		if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
			*cmdr |= SDMMC_CMD_USE_HOLD_REG;
	}
}

static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	unsigned int wanted = ios->clock;
	unsigned long actual;
	u8 div = priv->ciu_div + 1;

	if (ios->timing == MMC_TIMING_MMC_DDR52) {
		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
			mci_writel(host, CLKSEL64, priv->ddr_timing);
		else
			mci_writel(host, CLKSEL, priv->ddr_timing);
		/* Should be double rate for DDR mode */
		if (ios->bus_width == MMC_BUS_WIDTH_8)
			wanted <<= 1;
	} else {
		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
			mci_writel(host, CLKSEL64, priv->sdr_timing);
		else
			mci_writel(host, CLKSEL, priv->sdr_timing);
	}

	/*
	 * Don't care if wanted clock is zero or
	 * ciu clock is unavailable
	 */
	if (!wanted || IS_ERR(host->ciu_clk))
		return;

	/* Guaranteed minimum frequency for cclkin */
	if (wanted < EXYNOS_CCLKIN_MIN)
		wanted = EXYNOS_CCLKIN_MIN;

	if (wanted != priv->cur_speed) {
		int ret = clk_set_rate(host->ciu_clk, wanted * div);
		if (ret)
			dev_warn(host->dev,
				"failed to set clk-rate %u error: %d\n",
				 wanted * div, ret);
		actual = clk_get_rate(host->ciu_clk);
		host->bus_hz = actual / div;
		priv->cur_speed = wanted;
		host->current_speed = 0;
	}
}

static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv;
	struct device_node *np = host->dev->of_node;
	u32 timing[2];
	u32 div = 0;
	int idx;
	int ret;

	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
		if (of_device_is_compatible(np, exynos_compat[idx].compatible))
			priv->ctrl_type = exynos_compat[idx].ctrl_type;
	}

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
		priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
		priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	else {
		of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
		priv->ciu_div = div;
	}

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-sdr-timing", timing, 2);
	if (ret)
		return ret;

	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-ddr-timing", timing, 2);
	if (ret)
		return ret;

	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
	host->priv = priv;
	return 0;
}

static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
	else
		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
}

static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
{
	u32 clksel;
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);
	clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		mci_writel(host, CLKSEL64, clksel);
	else
		mci_writel(host, CLKSEL, clksel);
}

static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 clksel;
	u8 sample;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);
	sample = (clksel + 1) & 0x7;
	clksel = (clksel & ~0x7) | sample;
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		mci_writel(host, CLKSEL64, clksel);
	else
		mci_writel(host, CLKSEL, clksel);
	return sample;
}

static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
{
	const u8 iter = 8;
	u8 __c;
	s8 i, loc = -1;

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0xc7) == 0xc7) {
			loc = i;
			goto out;
		}
	}

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0x83) == 0x83) {
			loc = i;
			goto out;
		}
	}

out:
	return loc;
}

static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot)
{
	struct dw_mci *host = slot->host;
	struct mmc_host *mmc = slot->mmc;
	u8 start_smpl, smpl, candiates = 0;
	s8 found = -1;
	int ret = 0;

	start_smpl = dw_mci_exynos_get_clksmpl(host);

	do {
		mci_writel(host, TMOUT, ~0);
		smpl = dw_mci_exynos_move_next_clksmpl(host);

		if (!mmc_send_tuning(mmc))
			candiates |= (1 << smpl);

	} while (start_smpl != smpl);

	found = dw_mci_exynos_get_best_clksmpl(candiates);
	if (found >= 0)
		dw_mci_exynos_set_clksmpl(host, found);
	else
		ret = -EIO;

	return ret;
}

/* Common capabilities of Exynos4/Exynos5 SoC */
static unsigned long exynos_dwmmc_caps[4] = {
	MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
};

static const struct dw_mci_drv_data exynos_drv_data = {
	.caps			= exynos_dwmmc_caps,
	.init			= dw_mci_exynos_priv_init,
	.setup_clock		= dw_mci_exynos_setup_clock,
	.prepare_command	= dw_mci_exynos_prepare_command,
	.set_ios		= dw_mci_exynos_set_ios,
	.parse_dt		= dw_mci_exynos_parse_dt,
	.execute_tuning		= dw_mci_exynos_execute_tuning,
};

static const struct of_device_id dw_mci_exynos_match[] = {
	{ .compatible = "samsung,exynos4412-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5250-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos7-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos7-dw-mshc-smu",
			.data = &exynos_drv_data, },
	{},
};
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);

static int dw_mci_exynos_probe(struct platform_device *pdev)
{
	const struct dw_mci_drv_data *drv_data;
	const struct of_device_id *match;

	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	drv_data = match->data;
	return dw_mci_pltfm_register(pdev, drv_data);
}

static const struct dev_pm_ops dw_mci_exynos_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	.resume_noirq = dw_mci_exynos_resume_noirq,
	.thaw_noirq = dw_mci_exynos_resume_noirq,
	.restore_noirq = dw_mci_exynos_resume_noirq,
};

static struct platform_driver dw_mci_exynos_pltfm_driver = {
	.probe		= dw_mci_exynos_probe,
	.remove		= dw_mci_pltfm_remove,
	.driver		= {
		.name		= "dwmmc_exynos",
		.of_match_table	= dw_mci_exynos_match,
		.pm		= &dw_mci_exynos_pmops,
	},
};

module_platform_driver(dw_mci_exynos_pltfm_driver);

MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dwmmc-exynos");
Commit	Line	Data
c3665006 TA	1	/*
	2	* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
	3	*
	4	* Copyright (C) 2012, Samsung Electronics Co., Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/clk.h>
	15	#include <linux/mmc/host.h>
	16	#include <linux/mmc/dw_mmc.h>
c537a1c5	17	#include <linux/mmc/mmc.h>
c3665006 TA	18	#include <linux/of.h>
c3665006 TA	19	#include <linux/of_gpio.h>
c537a1c5	20	#include <linux/slab.h>
c3665006 TA	21
	22	#include "dw_mmc.h"
	23	#include "dw_mmc-pltfm.h"
0b5fce48	24	#include "dw_mmc-exynos.h"
c6d9deda	25
c3665006 TA	26	/* Variations in Exynos specific dw-mshc controller */
	27	enum dw_mci_exynos_type {
	28	DW_MCI_TYPE_EXYNOS4210,
	29	DW_MCI_TYPE_EXYNOS4412,
	30	DW_MCI_TYPE_EXYNOS5250,
00fd041b	31	DW_MCI_TYPE_EXYNOS5420,
6bce431c	32	DW_MCI_TYPE_EXYNOS5420_SMU,
89ad2be7 AK	33	DW_MCI_TYPE_EXYNOS7,
89ad2be7 AK	34	DW_MCI_TYPE_EXYNOS7_SMU,
c3665006 TA	35	};
	36
	37	/* Exynos implementation specific driver private data */
	38	struct dw_mci_exynos_priv_data {
	39	enum dw_mci_exynos_type ctrl_type;
	40	u8 ciu_div;
	41	u32 sdr_timing;
	42	u32 ddr_timing;
c6d9deda	43	u32 cur_speed;
c3665006 TA	44	};
	45
	46	static struct dw_mci_exynos_compatible {
	47	char *compatible;
	48	enum dw_mci_exynos_type ctrl_type;
	49	} exynos_compat[] = {
	50	{
	51	.compatible = "samsung,exynos4210-dw-mshc",
	52	.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
	53	}, {
	54	.compatible = "samsung,exynos4412-dw-mshc",
	55	.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
	56	}, {
	57	.compatible = "samsung,exynos5250-dw-mshc",
	58	.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
00fd041b YK	59	}, {
	60	.compatible = "samsung,exynos5420-dw-mshc",
	61	.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
6bce431c YK	62	}, {
	63	.compatible = "samsung,exynos5420-dw-mshc-smu",
	64	.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
89ad2be7 AK	65	}, {
	66	.compatible = "samsung,exynos7-dw-mshc",
	67	.ctrl_type = DW_MCI_TYPE_EXYNOS7,
	68	}, {
	69	.compatible = "samsung,exynos7-dw-mshc-smu",
	70	.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
c3665006 TA	71	},
	72	};
	73
	74	static int dw_mci_exynos_priv_init(struct dw_mci *host)
	75	{
e6c784ed	76	struct dw_mci_exynos_priv_data *priv = host->priv;
c3665006	77
89ad2be7 AK	78	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU \|\|
89ad2be7 AK	79	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
6bce431c	80	mci_writel(host, MPSBEGIN0, 0);
0b5fce48 SJ	81	mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
	82	mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT \|
	83	SDMMC_MPSCTRL_NON_SECURE_READ_BIT \|
	84	SDMMC_MPSCTRL_VALID \|
	85	SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
6bce431c YK	86	}
6bce431c YK	87
c3665006 TA	88	return 0;
	89	}
	90
	91	static int dw_mci_exynos_setup_clock(struct dw_mci *host)
	92	{
	93	struct dw_mci_exynos_priv_data *priv = host->priv;
	94
a2a1fed8 SJ	95	host->bus_hz /= (priv->ciu_div + 1);
a2a1fed8 SJ	96
c3665006 TA	97	return 0;
	98	}
	99
e2c63599 DA	100	#ifdef CONFIG_PM_SLEEP
	101	static int dw_mci_exynos_suspend(struct device *dev)
	102	{
	103	struct dw_mci *host = dev_get_drvdata(dev);
	104
	105	return dw_mci_suspend(host);
	106	}
	107
	108	static int dw_mci_exynos_resume(struct device *dev)
	109	{
	110	struct dw_mci *host = dev_get_drvdata(dev);
	111
6bce431c	112	dw_mci_exynos_priv_init(host);
e2c63599 DA	113	return dw_mci_resume(host);
	114	}
	115
	116	/**
	117	* dw_mci_exynos_resume_noirq - Exynos-specific resume code
	118	*
	119	* On exynos5420 there is a silicon errata that will sometimes leave the
	120	* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
	121	* that it fired and we can clear it by writing a 1 back. Clear it to prevent
	122	* interrupts from going off constantly.
	123	*
	124	* We run this code on all exynos variants because it doesn't hurt.
	125	*/
	126
	127	static int dw_mci_exynos_resume_noirq(struct device *dev)
	128	{
	129	struct dw_mci *host = dev_get_drvdata(dev);
89ad2be7	130	struct dw_mci_exynos_priv_data *priv = host->priv;
e2c63599 DA	131	u32 clksel;
e2c63599 DA	132
89ad2be7 AK	133	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	134	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	135	clksel = mci_readl(host, CLKSEL64);
	136	else
	137	clksel = mci_readl(host, CLKSEL);
	138
	139	if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
	140	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	141	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	142	mci_writel(host, CLKSEL64, clksel);
	143	else
	144	mci_writel(host, CLKSEL, clksel);
	145	}
e2c63599 DA	146
	147	return 0;
	148	}
	149	#else
	150	#define dw_mci_exynos_suspend NULL
	151	#define dw_mci_exynos_resume NULL
	152	#define dw_mci_exynos_resume_noirq NULL
	153	#endif /* CONFIG_PM_SLEEP */
	154
c3665006 TA	155	static void dw_mci_exynos_prepare_command(struct dw_mci host, u32 cmdr)
c3665006 TA	156	{
89ad2be7	157	struct dw_mci_exynos_priv_data *priv = host->priv;
c3665006 TA	158	/*
	159	* Exynos4412 and Exynos5250 extends the use of CMD register with the
	160	* use of bit 29 (which is reserved on standard MSHC controllers) for
	161	* optionally bypassing the HOLD register for command and data. The
	162	* HOLD register should be bypassed in case there is no phase shift
	163	* applied on CMD/DATA that is sent to the card.
	164	*/
89ad2be7 AK	165	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	166	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
	167	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64)))
	168	*cmdr \|= SDMMC_CMD_USE_HOLD_REG;
	169	} else {
	170	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
	171	*cmdr \|= SDMMC_CMD_USE_HOLD_REG;
	172	}
c3665006 TA	173	}
	174
	175	static void dw_mci_exynos_set_ios(struct dw_mci host, struct mmc_ios ios)
	176	{
	177	struct dw_mci_exynos_priv_data *priv = host->priv;
c6d9deda SJ	178	unsigned int wanted = ios->clock;
	179	unsigned long actual;
	180	u8 div = priv->ciu_div + 1;
c3665006	181
cab3a802	182	if (ios->timing == MMC_TIMING_MMC_DDR52) {
89ad2be7 AK	183	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	184	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	185	mci_writel(host, CLKSEL64, priv->ddr_timing);
	186	else
	187	mci_writel(host, CLKSEL, priv->ddr_timing);
c6d9deda SJ	188	/* Should be double rate for DDR mode */
	189	if (ios->bus_width == MMC_BUS_WIDTH_8)
	190	wanted <<= 1;
	191	} else {
89ad2be7 AK	192	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	193	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	194	mci_writel(host, CLKSEL64, priv->sdr_timing);
	195	else
	196	mci_writel(host, CLKSEL, priv->sdr_timing);
c6d9deda SJ	197	}
c6d9deda SJ	198
a2a1fed8 SJ	199	/*
	200	* Don't care if wanted clock is zero or
	201	* ciu clock is unavailable
	202	*/
	203	if (!wanted \|\| IS_ERR(host->ciu_clk))
c6d9deda SJ	204	return;
	205
	206	/* Guaranteed minimum frequency for cclkin */
	207	if (wanted < EXYNOS_CCLKIN_MIN)
	208	wanted = EXYNOS_CCLKIN_MIN;
	209
	210	if (wanted != priv->cur_speed) {
	211	int ret = clk_set_rate(host->ciu_clk, wanted * div);
	212	if (ret)
	213	dev_warn(host->dev,
	214	"failed to set clk-rate %u error: %d\n",
	215	wanted * div, ret);
	216	actual = clk_get_rate(host->ciu_clk);
	217	host->bus_hz = actual / div;
	218	priv->cur_speed = wanted;
	219	host->current_speed = 0;
	220	}
c3665006 TA	221	}
	222
	223	static int dw_mci_exynos_parse_dt(struct dw_mci *host)
	224	{
e6c784ed	225	struct dw_mci_exynos_priv_data *priv;
c3665006 TA	226	struct device_node *np = host->dev->of_node;
	227	u32 timing[2];
	228	u32 div = 0;
e6c784ed	229	int idx;
c3665006 TA	230	int ret;
c3665006 TA	231
e6c784ed	232	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
bf3707ea	233	if (!priv)
e6c784ed	234	return -ENOMEM;
e6c784ed YK	235
	236	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
	237	if (of_device_is_compatible(np, exynos_compat[idx].compatible))
	238	priv->ctrl_type = exynos_compat[idx].ctrl_type;
	239	}
	240
c6d9deda SJ	241	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
	242	priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	243	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
	244	priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	245	else {
	246	of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
	247	priv->ciu_div = div;
	248	}
c3665006 TA	249
	250	ret = of_property_read_u32_array(np,
	251	"samsung,dw-mshc-sdr-timing", timing, 2);
	252	if (ret)
	253	return ret;
	254
2d9f0bd1 YK	255	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
2d9f0bd1 YK	256
c3665006 TA	257	ret = of_property_read_u32_array(np,
	258	"samsung,dw-mshc-ddr-timing", timing, 2);
	259	if (ret)
	260	return ret;
	261
	262	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
e6c784ed	263	host->priv = priv;
c3665006 TA	264	return 0;
	265	}
	266
c537a1c5 SJ	267	static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
c537a1c5 SJ	268	{
89ad2be7 AK	269	struct dw_mci_exynos_priv_data *priv = host->priv;
	270
	271	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	272	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	273	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
	274	else
	275	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
c537a1c5 SJ	276	}
	277
	278	static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
	279	{
	280	u32 clksel;
89ad2be7 AK	281	struct dw_mci_exynos_priv_data *priv = host->priv;
	282
	283	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	284	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	285	clksel = mci_readl(host, CLKSEL64);
	286	else
	287	clksel = mci_readl(host, CLKSEL);
c537a1c5	288	clksel = (clksel & ~0x7) \| SDMMC_CLKSEL_CCLK_SAMPLE(sample);
89ad2be7 AK	289	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	290	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	291	mci_writel(host, CLKSEL64, clksel);
	292	else
	293	mci_writel(host, CLKSEL, clksel);
c537a1c5 SJ	294	}
	295
	296	static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
	297	{
89ad2be7	298	struct dw_mci_exynos_priv_data *priv = host->priv;
c537a1c5 SJ	299	u32 clksel;
	300	u8 sample;
	301
89ad2be7 AK	302	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	303	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	304	clksel = mci_readl(host, CLKSEL64);
	305	else
	306	clksel = mci_readl(host, CLKSEL);
c537a1c5 SJ	307	sample = (clksel + 1) & 0x7;
c537a1c5 SJ	308	clksel = (clksel & ~0x7) \| sample;
89ad2be7 AK	309	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	310	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	311	mci_writel(host, CLKSEL64, clksel);
	312	else
	313	mci_writel(host, CLKSEL, clksel);
c537a1c5 SJ	314	return sample;
	315	}
	316
	317	static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
	318	{
	319	const u8 iter = 8;
	320	u8 __c;
	321	s8 i, loc = -1;
	322
	323	for (i = 0; i < iter; i++) {
	324	__c = ror8(candiates, i);
	325	if ((__c & 0xc7) == 0xc7) {
	326	loc = i;
	327	goto out;
	328	}
	329	}
	330
	331	for (i = 0; i < iter; i++) {
	332	__c = ror8(candiates, i);
	333	if ((__c & 0x83) == 0x83) {
	334	loc = i;
	335	goto out;
	336	}
	337	}
	338
	339	out:
	340	return loc;
	341	}
	342
6c2c6506	343	static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot)
c537a1c5 SJ	344	{
	345	struct dw_mci *host = slot->host;
	346	struct mmc_host *mmc = slot->mmc;
c537a1c5 SJ	347	u8 start_smpl, smpl, candiates = 0;
	348	s8 found = -1;
	349	int ret = 0;
	350
c537a1c5 SJ	351	start_smpl = dw_mci_exynos_get_clksmpl(host);
	352
	353	do {
c537a1c5 SJ	354	mci_writel(host, TMOUT, ~0);
	355	smpl = dw_mci_exynos_move_next_clksmpl(host);
	356
6c2c6506 UH	357	if (!mmc_send_tuning(mmc))
6c2c6506 UH	358	candiates \|= (1 << smpl);
c537a1c5	359
c537a1c5 SJ	360	} while (start_smpl != smpl);
	361
	362	found = dw_mci_exynos_get_best_clksmpl(candiates);
	363	if (found >= 0)
	364	dw_mci_exynos_set_clksmpl(host, found);
	365	else
	366	ret = -EIO;
	367
c537a1c5 SJ	368	return ret;
	369	}
	370
0f6e73d0 DK	371	/* Common capabilities of Exynos4/Exynos5 SoC */
0f6e73d0 DK	372	static unsigned long exynos_dwmmc_caps[4] = {
cab3a802	373	MMC_CAP_1_8V_DDR \| MMC_CAP_8_BIT_DATA \| MMC_CAP_CMD23,
c3665006 TA	374	MMC_CAP_CMD23,
	375	MMC_CAP_CMD23,
	376	MMC_CAP_CMD23,
	377	};
	378
0f6e73d0 DK	379	static const struct dw_mci_drv_data exynos_drv_data = {
0f6e73d0 DK	380	.caps = exynos_dwmmc_caps,
c3665006 TA	381	.init = dw_mci_exynos_priv_init,
	382	.setup_clock = dw_mci_exynos_setup_clock,
	383	.prepare_command = dw_mci_exynos_prepare_command,
	384	.set_ios = dw_mci_exynos_set_ios,
	385	.parse_dt = dw_mci_exynos_parse_dt,
c537a1c5	386	.execute_tuning = dw_mci_exynos_execute_tuning,
c3665006 TA	387	};
	388
	389	static const struct of_device_id dw_mci_exynos_match[] = {
0f6e73d0 DK	390	{ .compatible = "samsung,exynos4412-dw-mshc",
0f6e73d0 DK	391	.data = &exynos_drv_data, },
c3665006	392	{ .compatible = "samsung,exynos5250-dw-mshc",
0f6e73d0	393	.data = &exynos_drv_data, },
00fd041b YK	394	{ .compatible = "samsung,exynos5420-dw-mshc",
00fd041b YK	395	.data = &exynos_drv_data, },
6bce431c YK	396	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
6bce431c YK	397	.data = &exynos_drv_data, },
89ad2be7 AK	398	{ .compatible = "samsung,exynos7-dw-mshc",
	399	.data = &exynos_drv_data, },
	400	{ .compatible = "samsung,exynos7-dw-mshc-smu",
	401	.data = &exynos_drv_data, },
c3665006 TA	402	{},
c3665006 TA	403	};
517cb9f1	404	MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
c3665006	405
9665f7f2	406	static int dw_mci_exynos_probe(struct platform_device *pdev)
c3665006	407	{
8e2b36ea	408	const struct dw_mci_drv_data *drv_data;
c3665006 TA	409	const struct of_device_id *match;
	410
	411	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	412	drv_data = match->data;
	413	return dw_mci_pltfm_register(pdev, drv_data);
	414	}
	415
15a2e2ab	416	static const struct dev_pm_ops dw_mci_exynos_pmops = {
e2c63599 DA	417	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	418	.resume_noirq = dw_mci_exynos_resume_noirq,
	419	.thaw_noirq = dw_mci_exynos_resume_noirq,
	420	.restore_noirq = dw_mci_exynos_resume_noirq,
	421	};
	422
c3665006 TA	423	static struct platform_driver dw_mci_exynos_pltfm_driver = {
c3665006 TA	424	.probe = dw_mci_exynos_probe,
7d589edc	425	.remove = dw_mci_pltfm_remove,
c3665006 TA	426	.driver = {
c3665006 TA	427	.name = "dwmmc_exynos",
20183d50	428	.of_match_table = dw_mci_exynos_match,
e2c63599	429	.pm = &dw_mci_exynos_pmops,
c3665006 TA	430	},
	431	};
	432
	433	module_platform_driver(dw_mci_exynos_pltfm_driver);
	434
	435	MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
	436	MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
	437	MODULE_LICENSE("GPL v2");
	438	MODULE_ALIAS("platform:dwmmc-exynos");