projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4cdc2ec1 | 1 | /* |
| 2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License as published by | |
| 6 | * the Free Software Foundation; either version 2 of the License, or | |
| 7 | * (at your option) any later version. | |
| 8 | */ | |
| 9 | ||
| 10 | #include <linux/module.h> | |
| 11 | #include <linux/platform_device.h> | |
| 12 | #include <linux/clk.h> | |
| 13 | #include <linux/mmc/host.h> | |
| 14 | #include <linux/mmc/dw_mmc.h> | |
| 15 | #include <linux/of_address.h> | |
| 16 | ||
| 17 | #include "dw_mmc.h" | |
| 18 | #include "dw_mmc-pltfm.h" | |
| 19 | ||
| 20 | #define RK3288_CLKGEN_DIV 2 | |
| 21 | ||
| 22 | static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr) | |
| 23 | { | |
| 24 | *cmdr |= SDMMC_CMD_USE_HOLD_REG; | |
| 25 | } | |
| 26 | ||
| 27 | static int dw_mci_rk3288_setup_clock(struct dw_mci *host) | |
| 28 | { | |
| 29 | host->bus_hz /= RK3288_CLKGEN_DIV; | |
| 30 | ||
| 31 | return 0; | |
| 32 | } | |
| 33 | ||
| 34 | static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) | |
| 35 | { | |
| 36 | int ret; | |
| 37 | unsigned int cclkin; | |
| 38 | u32 bus_hz; | |
| 39 | ||
| e7791079 DA |
40 | if (ios->clock == 0) |
| 41 | return; | |
| 42 | ||
| 4cdc2ec1 | 43 | /* |
| 44 | * cclkin: source clock of mmc controller | |
| 45 | * bus_hz: card interface clock generated by CLKGEN | |
| 46 | * bus_hz = cclkin / RK3288_CLKGEN_DIV | |
| 47 | * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) | |
| 48 | * | |
| 49 | * Note: div can only be 0 or 1 | |
| 50 | * if DDR50 8bit mode(only emmc work in 8bit mode), | |
| 51 | * div must be set 1 | |
| 52 | */ | |
| 53 | if (ios->bus_width == MMC_BUS_WIDTH_8 && | |
| 54 | ios->timing == MMC_TIMING_MMC_DDR52) | |
| 55 | cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; | |
| 56 | else | |
| 57 | cclkin = ios->clock * RK3288_CLKGEN_DIV; | |
| 58 | ||
| 59 | ret = clk_set_rate(host->ciu_clk, cclkin); | |
| 60 | if (ret) | |
| 61 | dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); | |
| 62 | ||
| 63 | bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; | |
| 64 | if (bus_hz != host->bus_hz) { | |
| 65 | host->bus_hz = bus_hz; | |
| 66 | /* force dw_mci_setup_bus() */ | |
| 67 | host->current_speed = 0; | |
| 68 | } | |
| 69 | } | |
| 70 | ||
| 76756234 AK |
71 | static int dw_mci_rockchip_init(struct dw_mci *host) |
| 72 | { | |
| 73 | /* It is slot 8 on Rockchip SoCs */ | |
| 74 | host->sdio_id0 = 8; | |
| 75 | ||
| 57e10486 AK |
76 | /* It needs this quirk on all Rockchip SoCs */ |
| 77 | host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO; | |
| 78 | ||
| 76756234 AK |
79 | return 0; |
| 80 | } | |
| 81 | ||
| 6d53200b | 82 | /* Common capabilities of RK3288 SoC */ |
| 83 | static unsigned long dw_mci_rk3288_dwmmc_caps[4] = { | |
| 84 | MMC_CAP_RUNTIME_RESUME, /* emmc */ | |
| 85 | MMC_CAP_RUNTIME_RESUME, /* sdmmc */ | |
| 86 | MMC_CAP_RUNTIME_RESUME, /* sdio0 */ | |
| 87 | MMC_CAP_RUNTIME_RESUME, /* sdio1 */ | |
| 88 | }; | |
| 4cdc2ec1 | 89 | static const struct dw_mci_drv_data rk2928_drv_data = { |
| 90 | .prepare_command = dw_mci_rockchip_prepare_command, | |
| 76756234 | 91 | .init = dw_mci_rockchip_init, |
| 4cdc2ec1 | 92 | }; |
| 93 | ||
| 94 | static const struct dw_mci_drv_data rk3288_drv_data = { | |
| 6d53200b | 95 | .caps = dw_mci_rk3288_dwmmc_caps, |
| 4cdc2ec1 | 96 | .prepare_command = dw_mci_rockchip_prepare_command, |
| 97 | .set_ios = dw_mci_rk3288_set_ios, | |
| 98 | .setup_clock = dw_mci_rk3288_setup_clock, | |
| 76756234 | 99 | .init = dw_mci_rockchip_init, |
| 4cdc2ec1 | 100 | }; |
| 101 | ||
| 102 | static const struct of_device_id dw_mci_rockchip_match[] = { | |
| 103 | { .compatible = "rockchip,rk2928-dw-mshc", | |
| 104 | .data = &rk2928_drv_data }, | |
| 105 | { .compatible = "rockchip,rk3288-dw-mshc", | |
| 106 | .data = &rk3288_drv_data }, | |
| 107 | {}, | |
| 108 | }; | |
| 109 | MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); | |
| 110 | ||
| 111 | static int dw_mci_rockchip_probe(struct platform_device *pdev) | |
| 112 | { | |
| 113 | const struct dw_mci_drv_data *drv_data; | |
| 114 | const struct of_device_id *match; | |
| 115 | ||
| 116 | if (!pdev->dev.of_node) | |
| 117 | return -ENODEV; | |
| 118 | ||
| 119 | match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); | |
| 120 | drv_data = match->data; | |
| 121 | ||
| 122 | return dw_mci_pltfm_register(pdev, drv_data); | |
| 123 | } | |
| 124 | ||
| 125 | #ifdef CONFIG_PM_SLEEP | |
| 126 | static int dw_mci_rockchip_suspend(struct device *dev) | |
| 127 | { | |
| 128 | struct dw_mci *host = dev_get_drvdata(dev); | |
| 129 | ||
| 130 | return dw_mci_suspend(host); | |
| 131 | } | |
| 132 | ||
| 133 | static int dw_mci_rockchip_resume(struct device *dev) | |
| 134 | { | |
| 135 | struct dw_mci *host = dev_get_drvdata(dev); | |
| 136 | ||
| 137 | return dw_mci_resume(host); | |
| 138 | } | |
| 139 | #endif /* CONFIG_PM_SLEEP */ | |
| 140 | ||
| 141 | static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops, | |
| 142 | dw_mci_rockchip_suspend, | |
| 143 | dw_mci_rockchip_resume); | |
| 144 | ||
| 145 | static struct platform_driver dw_mci_rockchip_pltfm_driver = { | |
| 146 | .probe = dw_mci_rockchip_probe, | |
| 96083379 | 147 | .remove = dw_mci_pltfm_remove, |
| 4cdc2ec1 | 148 | .driver = { |
| 149 | .name = "dwmmc_rockchip", | |
| 150 | .of_match_table = dw_mci_rockchip_match, | |
| 151 | .pm = &dw_mci_rockchip_pmops, | |
| 152 | }, | |
| 153 | }; | |
| 154 | ||
| 155 | module_platform_driver(dw_mci_rockchip_pltfm_driver); | |
| 156 | ||
| 157 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); | |
| 158 | MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension"); | |
| a7ca2b16 | 159 | MODULE_ALIAS("platform:dwmmc_rockchip"); |
| 4cdc2ec1 | 160 | MODULE_LICENSE("GPL v2"); |