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mmc: sh_mmcif: remove unneeded clock connection ID
[deliverable/linux.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/dw_mmc.h>
33#include <linux/bitops.h>
c07946a3 34#include <linux/regulator/consumer.h>
1791b13e 35#include <linux/workqueue.h>
c91eab4b 36#include <linux/of.h>
f95f3850
WN		 37
38#include "dw_mmc.h"
39
40/* Common flag combinations */
41#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
42 SDMMC_INT_HTO | SDMMC_INT_SBE | \
43 SDMMC_INT_EBE)
44#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
45 SDMMC_INT_RESP_ERR)
46#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
47 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
48#define DW_MCI_SEND_STATUS 1
49#define DW_MCI_RECV_STATUS 2
50#define DW_MCI_DMA_THRESHOLD 16
51
52#ifdef CONFIG_MMC_DW_IDMAC
53struct idmac_desc {
54 u32 des0; /* Control Descriptor */
55#define IDMAC_DES0_DIC BIT(1)
56#define IDMAC_DES0_LD BIT(2)
57#define IDMAC_DES0_FD BIT(3)
58#define IDMAC_DES0_CH BIT(4)
59#define IDMAC_DES0_ER BIT(5)
60#define IDMAC_DES0_CES BIT(30)
61#define IDMAC_DES0_OWN BIT(31)
62
63 u32 des1; /* Buffer sizes */
64#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 65 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 66
67 u32 des2; /* buffer 1 physical address */
68
69 u32 des3; /* buffer 2 physical address */
70};
71#endif /* CONFIG_MMC_DW_IDMAC */
72
73/**
74 * struct dw_mci_slot - MMC slot state
75 * @mmc: The mmc_host representing this slot.
76 * @host: The MMC controller this slot is using.
77 * @ctype: Card type for this slot.
78 * @mrq: mmc_request currently being processed or waiting to be
79 * processed, or NULL when the slot is idle.
80 * @queue_node: List node for placing this node in the @queue list of
81 * &struct dw_mci.
82 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
83 * @flags: Random state bits associated with the slot.
84 * @id: Number of this slot.
85 * @last_detect_state: Most recently observed card detect state.
86 */
87struct dw_mci_slot {
88 struct mmc_host *mmc;
89 struct dw_mci *host;
90
91 u32 ctype;
92
93 struct mmc_request *mrq;
94 struct list_head queue_node;
95
96 unsigned int clock;
97 unsigned long flags;
98#define DW_MMC_CARD_PRESENT 0
99#define DW_MMC_CARD_NEED_INIT 1
100 int id;
101 int last_detect_state;
102};
103
104#if defined(CONFIG_DEBUG_FS)
105static int dw_mci_req_show(struct seq_file *s, void *v)
106{
107 struct dw_mci_slot *slot = s->private;
108 struct mmc_request *mrq;
109 struct mmc_command *cmd;
110 struct mmc_command *stop;
111 struct mmc_data *data;
112
113 /* Make sure we get a consistent snapshot */
114 spin_lock_bh(&slot->host->lock);
115 mrq = slot->mrq;
116
117 if (mrq) {
118 cmd = mrq->cmd;
119 data = mrq->data;
120 stop = mrq->stop;
121
122 if (cmd)
123 seq_printf(s,
124 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
125 cmd->opcode, cmd->arg, cmd->flags,
126 cmd->resp[0], cmd->resp[1], cmd->resp[2],
127 cmd->resp[2], cmd->error);
128 if (data)
129 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
130 data->bytes_xfered, data->blocks,
131 data->blksz, data->flags, data->error);
132 if (stop)
133 seq_printf(s,
134 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
135 stop->opcode, stop->arg, stop->flags,
136 stop->resp[0], stop->resp[1], stop->resp[2],
137 stop->resp[2], stop->error);
138 }
139
140 spin_unlock_bh(&slot->host->lock);
141
142 return 0;
143}
144
145static int dw_mci_req_open(struct inode *inode, struct file *file)
146{
147 return single_open(file, dw_mci_req_show, inode->i_private);
148}
149
150static const struct file_operations dw_mci_req_fops = {
151 .owner = THIS_MODULE,
152 .open = dw_mci_req_open,
153 .read = seq_read,
154 .llseek = seq_lseek,
155 .release = single_release,
156};
157
158static int dw_mci_regs_show(struct seq_file *s, void *v)
159{
160 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
161 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
162 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
163 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
164 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
165 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
166
167 return 0;
168}
169
170static int dw_mci_regs_open(struct inode *inode, struct file *file)
171{
172 return single_open(file, dw_mci_regs_show, inode->i_private);
173}
174
175static const struct file_operations dw_mci_regs_fops = {
176 .owner = THIS_MODULE,
177 .open = dw_mci_regs_open,
178 .read = seq_read,
179 .llseek = seq_lseek,
180 .release = single_release,
181};
182
183static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
184{
185 struct mmc_host *mmc = slot->mmc;
186 struct dw_mci *host = slot->host;
187 struct dentry *root;
188 struct dentry *node;
189
190 root = mmc->debugfs_root;
191 if (!root)
192 return;
193
194 node = debugfs_create_file("regs", S_IRUSR, root, host,
195 &dw_mci_regs_fops);
196 if (!node)
197 goto err;
198
199 node = debugfs_create_file("req", S_IRUSR, root, slot,
200 &dw_mci_req_fops);
201 if (!node)
202 goto err;
203
204 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
205 if (!node)
206 goto err;
207
208 node = debugfs_create_x32("pending_events", S_IRUSR, root,
209 (u32 *)&host->pending_events);
210 if (!node)
211 goto err;
212
213 node = debugfs_create_x32("completed_events", S_IRUSR, root,
214 (u32 *)&host->completed_events);
215 if (!node)
216 goto err;
217
218 return;
219
220err:
221 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
222}
223#endif /* defined(CONFIG_DEBUG_FS) */
224
225static void dw_mci_set_timeout(struct dw_mci *host)
226{
227 /* timeout (maximum) */
228 mci_writel(host, TMOUT, 0xffffffff);
229}
230
231static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
232{
233 struct mmc_data *data;
800d78bf 234 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 235 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
f95f3850
WN		 236 u32 cmdr;
237 cmd->error = -EINPROGRESS;
238
239 cmdr = cmd->opcode;
240
241 if (cmdr == MMC_STOP_TRANSMISSION)
242 cmdr |= SDMMC_CMD_STOP;
243 else
244 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
245
246 if (cmd->flags & MMC_RSP_PRESENT) {
247 /* We expect a response, so set this bit */
248 cmdr |= SDMMC_CMD_RESP_EXP;
249 if (cmd->flags & MMC_RSP_136)
250 cmdr |= SDMMC_CMD_RESP_LONG;
251 }
252
253 if (cmd->flags & MMC_RSP_CRC)
254 cmdr |= SDMMC_CMD_RESP_CRC;
255
256 data = cmd->data;
257 if (data) {
258 cmdr |= SDMMC_CMD_DAT_EXP;
259 if (data->flags & MMC_DATA_STREAM)
260 cmdr |= SDMMC_CMD_STRM_MODE;
261 if (data->flags & MMC_DATA_WRITE)
262 cmdr |= SDMMC_CMD_DAT_WR;
263 }
264
cb27a843
JH		 265 if (drv_data && drv_data->prepare_command)
266 drv_data->prepare_command(slot->host, &cmdr);
800d78bf 267
f95f3850
WN		 268 return cmdr;
269}
270
271static void dw_mci_start_command(struct dw_mci *host,
272 struct mmc_command *cmd, u32 cmd_flags)
273{
274 host->cmd = cmd;
4a90920c 275 dev_vdbg(host->dev,
f95f3850
WN		 276 "start command: ARGR=0x%08x CMDR=0x%08x\n",
277 cmd->arg, cmd_flags);
278
279 mci_writel(host, CMDARG, cmd->arg);
280 wmb();
281
282 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
283}
284
285static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
286{
287 dw_mci_start_command(host, data->stop, host->stop_cmdr);
288}
289
290/* DMA interface functions */
291static void dw_mci_stop_dma(struct dw_mci *host)
292{
03e8cb53 293 if (host->using_dma) {
f95f3850
WN		 294 host->dma_ops->stop(host);
295 host->dma_ops->cleanup(host);
296 } else {
297 /* Data transfer was stopped by the interrupt handler */
298 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
299 }
300}
301
9aa51408
SJ		 302static int dw_mci_get_dma_dir(struct mmc_data *data)
303{
304 if (data->flags & MMC_DATA_WRITE)
305 return DMA_TO_DEVICE;
306 else
307 return DMA_FROM_DEVICE;
308}
309
9beee912 310#ifdef CONFIG_MMC_DW_IDMAC
f95f3850
WN		 311static void dw_mci_dma_cleanup(struct dw_mci *host)
312{
313 struct mmc_data *data = host->data;
314
315 if (data)
9aa51408 316 if (!data->host_cookie)
4a90920c 317 dma_unmap_sg(host->dev,
9aa51408
SJ		 318 data->sg,
319 data->sg_len,
320 dw_mci_get_dma_dir(data));
f95f3850
WN		 321}
322
323static void dw_mci_idmac_stop_dma(struct dw_mci *host)
324{
325 u32 temp;
326
327 /* Disable and reset the IDMAC interface */
328 temp = mci_readl(host, CTRL);
329 temp &= ~SDMMC_CTRL_USE_IDMAC;
330 temp |= SDMMC_CTRL_DMA_RESET;
331 mci_writel(host, CTRL, temp);
332
333 /* Stop the IDMAC running */
334 temp = mci_readl(host, BMOD);
a5289a43 335 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 336 mci_writel(host, BMOD, temp);
337}
338
339static void dw_mci_idmac_complete_dma(struct dw_mci *host)
340{
341 struct mmc_data *data = host->data;
342
4a90920c 343 dev_vdbg(host->dev, "DMA complete\n");
f95f3850
WN		 344
345 host->dma_ops->cleanup(host);
346
347 /*
348 * If the card was removed, data will be NULL. No point in trying to
349 * send the stop command or waiting for NBUSY in this case.
350 */
351 if (data) {
352 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
353 tasklet_schedule(&host->tasklet);
354 }
355}
356
357static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
358 unsigned int sg_len)
359{
360 int i;
361 struct idmac_desc *desc = host->sg_cpu;
362
363 for (i = 0; i < sg_len; i++, desc++) {
364 unsigned int length = sg_dma_len(&data->sg[i]);
365 u32 mem_addr = sg_dma_address(&data->sg[i]);
366
367 /* Set the OWN bit and disable interrupts for this descriptor */
368 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
369
370 /* Buffer length */
371 IDMAC_SET_BUFFER1_SIZE(desc, length);
372
373 /* Physical address to DMA to/from */
374 desc->des2 = mem_addr;
375 }
376
377 /* Set first descriptor */
378 desc = host->sg_cpu;
379 desc->des0 |= IDMAC_DES0_FD;
380
381 /* Set last descriptor */
382 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
383 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
384 desc->des0 |= IDMAC_DES0_LD;
385
386 wmb();
387}
388
389static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
390{
391 u32 temp;
392
393 dw_mci_translate_sglist(host, host->data, sg_len);
394
395 /* Select IDMAC interface */
396 temp = mci_readl(host, CTRL);
397 temp |= SDMMC_CTRL_USE_IDMAC;
398 mci_writel(host, CTRL, temp);
399
400 wmb();
401
402 /* Enable the IDMAC */
403 temp = mci_readl(host, BMOD);
a5289a43 404 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 405 mci_writel(host, BMOD, temp);
406
407 /* Start it running */
408 mci_writel(host, PLDMND, 1);
409}
410
411static int dw_mci_idmac_init(struct dw_mci *host)
412{
413 struct idmac_desc *p;
897b69e7 414 int i;
f95f3850
WN		 415
416 /* Number of descriptors in the ring buffer */
417 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
418
419 /* Forward link the descriptor list */
420 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
421 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
422
423 /* Set the last descriptor as the end-of-ring descriptor */
424 p->des3 = host->sg_dma;
425 p->des0 = IDMAC_DES0_ER;
426
141a712a
SJ		 427 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
428
f95f3850
WN		 429 /* Mask out interrupts - get Tx & Rx complete only */
430 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
431 SDMMC_IDMAC_INT_TI);
432
433 /* Set the descriptor base address */
434 mci_writel(host, DBADDR, host->sg_dma);
435 return 0;
436}
437
8e2b36ea 438static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 439 .init = dw_mci_idmac_init,
440 .start = dw_mci_idmac_start_dma,
441 .stop = dw_mci_idmac_stop_dma,
442 .complete = dw_mci_idmac_complete_dma,
443 .cleanup = dw_mci_dma_cleanup,
444};
445#endif /* CONFIG_MMC_DW_IDMAC */
446
9aa51408
SJ		 447static int dw_mci_pre_dma_transfer(struct dw_mci *host,
448 struct mmc_data *data,
449 bool next)
f95f3850
WN		 450{
451 struct scatterlist *sg;
9aa51408 452 unsigned int i, sg_len;
03e8cb53 453
9aa51408
SJ		 454 if (!next && data->host_cookie)
455 return data->host_cookie;
f95f3850
WN		 456
457 /*
458 * We don't do DMA on "complex" transfers, i.e. with
459 * non-word-aligned buffers or lengths. Also, we don't bother
460 * with all the DMA setup overhead for short transfers.
461 */
462 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
463 return -EINVAL;
9aa51408 464
f95f3850
WN		 465 if (data->blksz & 3)
466 return -EINVAL;
467
468 for_each_sg(data->sg, sg, data->sg_len, i) {
469 if (sg->offset & 3 || sg->length & 3)
470 return -EINVAL;
471 }
472
4a90920c 473 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 474 data->sg,
475 data->sg_len,
476 dw_mci_get_dma_dir(data));
477 if (sg_len == 0)
478 return -EINVAL;
03e8cb53 479
9aa51408
SJ		 480 if (next)
481 data->host_cookie = sg_len;
f95f3850 482
9aa51408
SJ		 483 return sg_len;
484}
485
9aa51408
SJ		 486static void dw_mci_pre_req(struct mmc_host *mmc,
487 struct mmc_request *mrq,
488 bool is_first_req)
489{
490 struct dw_mci_slot *slot = mmc_priv(mmc);
491 struct mmc_data *data = mrq->data;
492
493 if (!slot->host->use_dma || !data)
494 return;
495
496 if (data->host_cookie) {
497 data->host_cookie = 0;
498 return;
499 }
500
501 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
502 data->host_cookie = 0;
503}
504
505static void dw_mci_post_req(struct mmc_host *mmc,
506 struct mmc_request *mrq,
507 int err)
508{
509 struct dw_mci_slot *slot = mmc_priv(mmc);
510 struct mmc_data *data = mrq->data;
511
512 if (!slot->host->use_dma || !data)
513 return;
514
515 if (data->host_cookie)
4a90920c 516 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 517 data->sg,
518 data->sg_len,
519 dw_mci_get_dma_dir(data));
520 data->host_cookie = 0;
521}
522
523static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
524{
525 int sg_len;
526 u32 temp;
527
528 host->using_dma = 0;
529
530 /* If we don't have a channel, we can't do DMA */
531 if (!host->use_dma)
532 return -ENODEV;
533
534 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 535 if (sg_len < 0) {
536 host->dma_ops->stop(host);
9aa51408 537 return sg_len;
a99aa9b9 538 }
9aa51408
SJ		 539
540 host->using_dma = 1;
f95f3850 541
4a90920c 542 dev_vdbg(host->dev,
f95f3850
WN		 543 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
544 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
545 sg_len);
546
547 /* Enable the DMA interface */
548 temp = mci_readl(host, CTRL);
549 temp |= SDMMC_CTRL_DMA_ENABLE;
550 mci_writel(host, CTRL, temp);
551
552 /* Disable RX/TX IRQs, let DMA handle it */
553 temp = mci_readl(host, INTMASK);
554 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
555 mci_writel(host, INTMASK, temp);
556
557 host->dma_ops->start(host, sg_len);
558
559 return 0;
560}
561
562static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
563{
564 u32 temp;
565
566 data->error = -EINPROGRESS;
567
568 WARN_ON(host->data);
569 host->sg = NULL;
570 host->data = data;
571
55c5efbc
JH		 572 if (data->flags & MMC_DATA_READ)
573 host->dir_status = DW_MCI_RECV_STATUS;
574 else
575 host->dir_status = DW_MCI_SEND_STATUS;
576
f95f3850 577 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 578 int flags = SG_MITER_ATOMIC;
579 if (host->data->flags & MMC_DATA_READ)
580 flags |= SG_MITER_TO_SG;
581 else
582 flags |= SG_MITER_FROM_SG;
583
584 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 585 host->sg = data->sg;
34b664a2
JH		 586 host->part_buf_start = 0;
587 host->part_buf_count = 0;
f95f3850 588
b40af3aa 589 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 590 temp = mci_readl(host, INTMASK);
591 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
592 mci_writel(host, INTMASK, temp);
593
594 temp = mci_readl(host, CTRL);
595 temp &= ~SDMMC_CTRL_DMA_ENABLE;
596 mci_writel(host, CTRL, temp);
597 }
598}
599
600static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
601{
602 struct dw_mci *host = slot->host;
603 unsigned long timeout = jiffies + msecs_to_jiffies(500);
604 unsigned int cmd_status = 0;
605
606 mci_writel(host, CMDARG, arg);
607 wmb();
608 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
609
610 while (time_before(jiffies, timeout)) {
611 cmd_status = mci_readl(host, CMD);
612 if (!(cmd_status & SDMMC_CMD_START))
613 return;
614 }
615 dev_err(&slot->mmc->class_dev,
616 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
617 cmd, arg, cmd_status);
618}
619
ab269128 620static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 621{
622 struct dw_mci *host = slot->host;
623 u32 div;
9623b5b9 624 u32 clk_en_a;
f95f3850 625
ab269128 626 if (slot->clock != host->current_speed || force_clkinit) {
e419990b
SJ		 627 div = host->bus_hz / slot->clock;
628 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
f95f3850
WN		 629 /*
630 * move the + 1 after the divide to prevent
631 * over-clocking the card.
632 */
e419990b
SJ		 633 div += 1;
634
635 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850
WN		 636
637 dev_info(&slot->mmc->class_dev,
638 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
639 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
640 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
641
642 /* disable clock */
643 mci_writel(host, CLKENA, 0);
644 mci_writel(host, CLKSRC, 0);
645
646 /* inform CIU */
647 mci_send_cmd(slot,
648 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
649
650 /* set clock to desired speed */
651 mci_writel(host, CLKDIV, div);
652
653 /* inform CIU */
654 mci_send_cmd(slot,
655 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
656
9623b5b9
DA		 657 /* enable clock; only low power if no SDIO */
658 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
659 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
660 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
661 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 662
663 /* inform CIU */
664 mci_send_cmd(slot,
665 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
666
667 host->current_speed = slot->clock;
668 }
669
670 /* Set the current slot bus width */
1d56c453 671 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 672}
673
053b3ce6
SJ		 674static void __dw_mci_start_request(struct dw_mci *host,
675 struct dw_mci_slot *slot,
676 struct mmc_command *cmd)
f95f3850
WN		 677{
678 struct mmc_request *mrq;
f95f3850
WN		 679 struct mmc_data *data;
680 u32 cmdflags;
681
682 mrq = slot->mrq;
683 if (host->pdata->select_slot)
684 host->pdata->select_slot(slot->id);
685
686 /* Slot specific timing and width adjustment */
ab269128 687 dw_mci_setup_bus(slot, false);
f95f3850
WN		 688
689 host->cur_slot = slot;
690 host->mrq = mrq;
691
692 host->pending_events = 0;
693 host->completed_events = 0;
694 host->data_status = 0;
695
053b3ce6 696 data = cmd->data;
f95f3850
WN		 697 if (data) {
698 dw_mci_set_timeout(host);
699 mci_writel(host, BYTCNT, data->blksz*data->blocks);
700 mci_writel(host, BLKSIZ, data->blksz);
701 }
702
f95f3850
WN		 703 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
704
705 /* this is the first command, send the initialization clock */
706 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
707 cmdflags |= SDMMC_CMD_INIT;
708
709 if (data) {
710 dw_mci_submit_data(host, data);
711 wmb();
712 }
713
714 dw_mci_start_command(host, cmd, cmdflags);
715
716 if (mrq->stop)
717 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
718}
719
053b3ce6
SJ		 720static void dw_mci_start_request(struct dw_mci *host,
721 struct dw_mci_slot *slot)
722{
723 struct mmc_request *mrq = slot->mrq;
724 struct mmc_command *cmd;
725
726 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
727 __dw_mci_start_request(host, slot, cmd);
728}
729
7456caae 730/* must be called with host->lock held */
f95f3850
WN		 731static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
732 struct mmc_request *mrq)
733{
734 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
735 host->state);
736
f95f3850
WN		 737 slot->mrq = mrq;
738
739 if (host->state == STATE_IDLE) {
740 host->state = STATE_SENDING_CMD;
741 dw_mci_start_request(host, slot);
742 } else {
743 list_add_tail(&slot->queue_node, &host->queue);
744 }
f95f3850
WN		 745}
746
747static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
748{
749 struct dw_mci_slot *slot = mmc_priv(mmc);
750 struct dw_mci *host = slot->host;
751
752 WARN_ON(slot->mrq);
753
7456caae
JH		 754 /*
755 * The check for card presence and queueing of the request must be
756 * atomic, otherwise the card could be removed in between and the
757 * request wouldn't fail until another card was inserted.
758 */
759 spin_lock_bh(&host->lock);
760
f95f3850 761 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 762 spin_unlock_bh(&host->lock);
f95f3850
WN		 763 mrq->cmd->error = -ENOMEDIUM;
764 mmc_request_done(mmc, mrq);
765 return;
766 }
767
f95f3850 768 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 769
770 spin_unlock_bh(&host->lock);
f95f3850
WN		 771}
772
773static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
774{
775 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 776 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 777 u32 regs;
f95f3850
WN		 778
779 /* set default 1 bit mode */
780 slot->ctype = SDMMC_CTYPE_1BIT;
781
782 switch (ios->bus_width) {
783 case MMC_BUS_WIDTH_1:
784 slot->ctype = SDMMC_CTYPE_1BIT;
785 break;
786 case MMC_BUS_WIDTH_4:
787 slot->ctype = SDMMC_CTYPE_4BIT;
788 break;
c9b2a06f
JC		 789 case MMC_BUS_WIDTH_8:
790 slot->ctype = SDMMC_CTYPE_8BIT;
791 break;
f95f3850
WN		 792 }
793
3f514291
SJ		 794 regs = mci_readl(slot->host, UHS_REG);
795
41babf75 796 /* DDR mode set */
3f514291 797 if (ios->timing == MMC_TIMING_UHS_DDR50)
41babf75 798 regs |= (0x1 << slot->id) << 16;
3f514291
SJ		 799 else
800 regs &= ~(0x1 << slot->id) << 16;
801
802 mci_writel(slot->host, UHS_REG, regs);
41babf75 803
f95f3850
WN		 804 if (ios->clock) {
805 /*
806 * Use mirror of ios->clock to prevent race with mmc
807 * core ios update when finding the minimum.
808 */
809 slot->clock = ios->clock;
810 }
811
cb27a843
JH		 812 if (drv_data && drv_data->set_ios)
813 drv_data->set_ios(slot->host, ios);
800d78bf 814
f95f3850
WN		 815 switch (ios->power_mode) {
816 case MMC_POWER_UP:
817 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
818 break;
819 default:
820 break;
821 }
822}
823
824static int dw_mci_get_ro(struct mmc_host *mmc)
825{
826 int read_only;
827 struct dw_mci_slot *slot = mmc_priv(mmc);
828 struct dw_mci_board *brd = slot->host->pdata;
829
830 /* Use platform get_ro function, else try on board write protect */
b4967aa5
TA		 831 if (brd->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)
832 read_only = 0;
833 else if (brd->get_ro)
f95f3850
WN		 834 read_only = brd->get_ro(slot->id);
835 else
836 read_only =
837 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
838
839 dev_dbg(&mmc->class_dev, "card is %s\n",
840 read_only ? "read-only" : "read-write");
841
842 return read_only;
843}
844
845static int dw_mci_get_cd(struct mmc_host *mmc)
846{
847 int present;
848 struct dw_mci_slot *slot = mmc_priv(mmc);
849 struct dw_mci_board *brd = slot->host->pdata;
850
851 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 852 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
853 present = 1;
854 else if (brd->get_cd)
f95f3850
WN		 855 present = !brd->get_cd(slot->id);
856 else
857 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
858 == 0 ? 1 : 0;
859
860 if (present)
861 dev_dbg(&mmc->class_dev, "card is present\n");
862 else
863 dev_dbg(&mmc->class_dev, "card is not present\n");
864
865 return present;
866}
867
9623b5b9
DA		 868/*
869 * Disable lower power mode.
870 *
871 * Low power mode will stop the card clock when idle. According to the
872 * description of the CLKENA register we should disable low power mode
873 * for SDIO cards if we need SDIO interrupts to work.
874 *
875 * This function is fast if low power mode is already disabled.
876 */
877static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
878{
879 struct dw_mci *host = slot->host;
880 u32 clk_en_a;
881 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
882
883 clk_en_a = mci_readl(host, CLKENA);
884
885 if (clk_en_a & clken_low_pwr) {
886 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
887 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
888 SDMMC_CMD_PRV_DAT_WAIT, 0);
889 }
890}
891
1a5c8e1f
SH		 892static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
893{
894 struct dw_mci_slot *slot = mmc_priv(mmc);
895 struct dw_mci *host = slot->host;
896 u32 int_mask;
897
898 /* Enable/disable Slot Specific SDIO interrupt */
899 int_mask = mci_readl(host, INTMASK);
900 if (enb) {
9623b5b9
DA		 901 /*
902 * Turn off low power mode if it was enabled. This is a bit of
903 * a heavy operation and we disable / enable IRQs a lot, so
904 * we'll leave low power mode disabled and it will get
905 * re-enabled again in dw_mci_setup_bus().
906 */
907 dw_mci_disable_low_power(slot);
908
1a5c8e1f 909 mci_writel(host, INTMASK,
705ad047 910 (int_mask | SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 911 } else {
912 mci_writel(host, INTMASK,
705ad047 913 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 914 }
915}
916
f95f3850 917static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 918 .request = dw_mci_request,
9aa51408
SJ		 919 .pre_req = dw_mci_pre_req,
920 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 921 .set_ios = dw_mci_set_ios,
922 .get_ro = dw_mci_get_ro,
923 .get_cd = dw_mci_get_cd,
924 .enable_sdio_irq = dw_mci_enable_sdio_irq,
f95f3850
WN		 925};
926
927static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
928 __releases(&host->lock)
929 __acquires(&host->lock)
930{
931 struct dw_mci_slot *slot;
932 struct mmc_host *prev_mmc = host->cur_slot->mmc;
933
934 WARN_ON(host->cmd || host->data);
935
936 host->cur_slot->mrq = NULL;
937 host->mrq = NULL;
938 if (!list_empty(&host->queue)) {
939 slot = list_entry(host->queue.next,
940 struct dw_mci_slot, queue_node);
941 list_del(&slot->queue_node);
4a90920c 942 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 943 mmc_hostname(slot->mmc));
944 host->state = STATE_SENDING_CMD;
945 dw_mci_start_request(host, slot);
946 } else {
4a90920c 947 dev_vdbg(host->dev, "list empty\n");
f95f3850
WN		 948 host->state = STATE_IDLE;
949 }
950
951 spin_unlock(&host->lock);
952 mmc_request_done(prev_mmc, mrq);
953 spin_lock(&host->lock);
954}
955
956static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
957{
958 u32 status = host->cmd_status;
959
960 host->cmd_status = 0;
961
962 /* Read the response from the card (up to 16 bytes) */
963 if (cmd->flags & MMC_RSP_PRESENT) {
964 if (cmd->flags & MMC_RSP_136) {
965 cmd->resp[3] = mci_readl(host, RESP0);
966 cmd->resp[2] = mci_readl(host, RESP1);
967 cmd->resp[1] = mci_readl(host, RESP2);
968 cmd->resp[0] = mci_readl(host, RESP3);
969 } else {
970 cmd->resp[0] = mci_readl(host, RESP0);
971 cmd->resp[1] = 0;
972 cmd->resp[2] = 0;
973 cmd->resp[3] = 0;
974 }
975 }
976
977 if (status & SDMMC_INT_RTO)
978 cmd->error = -ETIMEDOUT;
979 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
980 cmd->error = -EILSEQ;
981 else if (status & SDMMC_INT_RESP_ERR)
982 cmd->error = -EIO;
983 else
984 cmd->error = 0;
985
986 if (cmd->error) {
987 /* newer ip versions need a delay between retries */
988 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
989 mdelay(20);
990
991 if (cmd->data) {
f95f3850 992 dw_mci_stop_dma(host);
fda5f736 993 host->data = NULL;
f95f3850
WN		 994 }
995 }
996}
997
998static void dw_mci_tasklet_func(unsigned long priv)
999{
1000 struct dw_mci *host = (struct dw_mci *)priv;
1001 struct mmc_data *data;
1002 struct mmc_command *cmd;
1003 enum dw_mci_state state;
1004 enum dw_mci_state prev_state;
94dd5b33 1005 u32 status, ctrl;
f95f3850
WN		 1006
1007 spin_lock(&host->lock);
1008
1009 state = host->state;
1010 data = host->data;
1011
1012 do {
1013 prev_state = state;
1014
1015 switch (state) {
1016 case STATE_IDLE:
1017 break;
1018
1019 case STATE_SENDING_CMD:
1020 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1021 &host->pending_events))
1022 break;
1023
1024 cmd = host->cmd;
1025 host->cmd = NULL;
1026 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
053b3ce6
SJ		 1027 dw_mci_command_complete(host, cmd);
1028 if (cmd == host->mrq->sbc && !cmd->error) {
1029 prev_state = state = STATE_SENDING_CMD;
1030 __dw_mci_start_request(host, host->cur_slot,
1031 host->mrq->cmd);
1032 goto unlock;
1033 }
1034
f95f3850
WN		 1035 if (!host->mrq->data || cmd->error) {
1036 dw_mci_request_end(host, host->mrq);
1037 goto unlock;
1038 }
1039
1040 prev_state = state = STATE_SENDING_DATA;
1041 /* fall through */
1042
1043 case STATE_SENDING_DATA:
1044 if (test_and_clear_bit(EVENT_DATA_ERROR,
1045 &host->pending_events)) {
1046 dw_mci_stop_dma(host);
1047 if (data->stop)
1048 send_stop_cmd(host, data);
1049 state = STATE_DATA_ERROR;
1050 break;
1051 }
1052
1053 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1054 &host->pending_events))
1055 break;
1056
1057 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1058 prev_state = state = STATE_DATA_BUSY;
1059 /* fall through */
1060
1061 case STATE_DATA_BUSY:
1062 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1063 &host->pending_events))
1064 break;
1065
1066 host->data = NULL;
1067 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1068 status = host->data_status;
1069
1070 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1071 if (status & SDMMC_INT_DTO) {
f95f3850
WN		 1072 data->error = -ETIMEDOUT;
1073 } else if (status & SDMMC_INT_DCRC) {
f95f3850 1074 data->error = -EILSEQ;
55c5efbc
JH		 1075 } else if (status & SDMMC_INT_EBE &&
1076 host->dir_status ==
1077 DW_MCI_SEND_STATUS) {
1078 /*
1079 * No data CRC status was returned.
1080 * The number of bytes transferred will
1081 * be exaggerated in PIO mode.
1082 */
1083 data->bytes_xfered = 0;
1084 data->error = -ETIMEDOUT;
f95f3850 1085 } else {
4a90920c 1086 dev_err(host->dev,
f95f3850
WN		 1087 "data FIFO error "
1088 "(status=%08x)\n",
1089 status);
1090 data->error = -EIO;
1091 }
94dd5b33
JH		 1092 /*
1093 * After an error, there may be data lingering
1094 * in the FIFO, so reset it - doing so
1095 * generates a block interrupt, hence setting
1096 * the scatter-gather pointer to NULL.
1097 */
f9c2a0dc 1098 sg_miter_stop(&host->sg_miter);
94dd5b33
JH		 1099 host->sg = NULL;
1100 ctrl = mci_readl(host, CTRL);
1101 ctrl |= SDMMC_CTRL_FIFO_RESET;
1102 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 1103 } else {
1104 data->bytes_xfered = data->blocks * data->blksz;
1105 data->error = 0;
1106 }
1107
1108 if (!data->stop) {
1109 dw_mci_request_end(host, host->mrq);
1110 goto unlock;
1111 }
1112
053b3ce6
SJ		 1113 if (host->mrq->sbc && !data->error) {
1114 data->stop->error = 0;
1115 dw_mci_request_end(host, host->mrq);
1116 goto unlock;
1117 }
1118
f95f3850
WN		 1119 prev_state = state = STATE_SENDING_STOP;
1120 if (!data->error)
1121 send_stop_cmd(host, data);
1122 /* fall through */
1123
1124 case STATE_SENDING_STOP:
1125 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1126 &host->pending_events))
1127 break;
1128
1129 host->cmd = NULL;
1130 dw_mci_command_complete(host, host->mrq->stop);
1131 dw_mci_request_end(host, host->mrq);
1132 goto unlock;
1133
1134 case STATE_DATA_ERROR:
1135 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1136 &host->pending_events))
1137 break;
1138
1139 state = STATE_DATA_BUSY;
1140 break;
1141 }
1142 } while (state != prev_state);
1143
1144 host->state = state;
1145unlock:
1146 spin_unlock(&host->lock);
1147
1148}
1149
34b664a2
JH		 1150/* push final bytes to part_buf, only use during push */
1151static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1152{
34b664a2
JH		 1153 memcpy((void *)&host->part_buf, buf, cnt);
1154 host->part_buf_count = cnt;
1155}
f95f3850 1156
34b664a2
JH		 1157/* append bytes to part_buf, only use during push */
1158static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1159{
1160 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1161 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1162 host->part_buf_count += cnt;
1163 return cnt;
1164}
f95f3850 1165
34b664a2
JH		 1166/* pull first bytes from part_buf, only use during pull */
1167static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1168{
1169 cnt = min(cnt, (int)host->part_buf_count);
1170 if (cnt) {
1171 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1172 cnt);
1173 host->part_buf_count -= cnt;
1174 host->part_buf_start += cnt;
f95f3850 1175 }
34b664a2 1176 return cnt;
f95f3850
WN		 1177}
1178
34b664a2
JH		 1179/* pull final bytes from the part_buf, assuming it's just been filled */
1180static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1181{
34b664a2
JH		 1182 memcpy(buf, &host->part_buf, cnt);
1183 host->part_buf_start = cnt;
1184 host->part_buf_count = (1 << host->data_shift) - cnt;
1185}
f95f3850 1186
34b664a2
JH		 1187static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1188{
1189 /* try and push anything in the part_buf */
1190 if (unlikely(host->part_buf_count)) {
1191 int len = dw_mci_push_part_bytes(host, buf, cnt);
1192 buf += len;
1193 cnt -= len;
1194 if (!sg_next(host->sg) || host->part_buf_count == 2) {
4e0a5adf
JC		 1195 mci_writew(host, DATA(host->data_offset),
1196 host->part_buf16);
34b664a2
JH		 1197 host->part_buf_count = 0;
1198 }
1199 }
1200#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1201 if (unlikely((unsigned long)buf & 0x1)) {
1202 while (cnt >= 2) {
1203 u16 aligned_buf[64];
1204 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1205 int items = len >> 1;
1206 int i;
1207 /* memcpy from input buffer into aligned buffer */
1208 memcpy(aligned_buf, buf, len);
1209 buf += len;
1210 cnt -= len;
1211 /* push data from aligned buffer into fifo */
1212 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1213 mci_writew(host, DATA(host->data_offset),
1214 aligned_buf[i]);
34b664a2
JH		 1215 }
1216 } else
1217#endif
1218 {
1219 u16 *pdata = buf;
1220 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1221 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1222 buf = pdata;
1223 }
1224 /* put anything remaining in the part_buf */
1225 if (cnt) {
1226 dw_mci_set_part_bytes(host, buf, cnt);
1227 if (!sg_next(host->sg))
4e0a5adf
JC		 1228 mci_writew(host, DATA(host->data_offset),
1229 host->part_buf16);
34b664a2
JH		 1230 }
1231}
f95f3850 1232
34b664a2
JH		 1233static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1234{
1235#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1236 if (unlikely((unsigned long)buf & 0x1)) {
1237 while (cnt >= 2) {
1238 /* pull data from fifo into aligned buffer */
1239 u16 aligned_buf[64];
1240 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1241 int items = len >> 1;
1242 int i;
1243 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1244 aligned_buf[i] = mci_readw(host,
1245 DATA(host->data_offset));
34b664a2
JH		 1246 /* memcpy from aligned buffer into output buffer */
1247 memcpy(buf, aligned_buf, len);
1248 buf += len;
1249 cnt -= len;
1250 }
1251 } else
1252#endif
1253 {
1254 u16 *pdata = buf;
1255 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1256 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1257 buf = pdata;
1258 }
1259 if (cnt) {
4e0a5adf 1260 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1261 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1262 }
1263}
1264
1265static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1266{
34b664a2
JH		 1267 /* try and push anything in the part_buf */
1268 if (unlikely(host->part_buf_count)) {
1269 int len = dw_mci_push_part_bytes(host, buf, cnt);
1270 buf += len;
1271 cnt -= len;
1272 if (!sg_next(host->sg) || host->part_buf_count == 4) {
4e0a5adf
JC		 1273 mci_writel(host, DATA(host->data_offset),
1274 host->part_buf32);
34b664a2
JH		 1275 host->part_buf_count = 0;
1276 }
1277 }
1278#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1279 if (unlikely((unsigned long)buf & 0x3)) {
1280 while (cnt >= 4) {
1281 u32 aligned_buf[32];
1282 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1283 int items = len >> 2;
1284 int i;
1285 /* memcpy from input buffer into aligned buffer */
1286 memcpy(aligned_buf, buf, len);
1287 buf += len;
1288 cnt -= len;
1289 /* push data from aligned buffer into fifo */
1290 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1291 mci_writel(host, DATA(host->data_offset),
1292 aligned_buf[i]);
34b664a2
JH		 1293 }
1294 } else
1295#endif
1296 {
1297 u32 *pdata = buf;
1298 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1299 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1300 buf = pdata;
1301 }
1302 /* put anything remaining in the part_buf */
1303 if (cnt) {
1304 dw_mci_set_part_bytes(host, buf, cnt);
1305 if (!sg_next(host->sg))
4e0a5adf
JC		 1306 mci_writel(host, DATA(host->data_offset),
1307 host->part_buf32);
f95f3850
WN		 1308 }
1309}
1310
1311static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1312{
34b664a2
JH		 1313#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1314 if (unlikely((unsigned long)buf & 0x3)) {
1315 while (cnt >= 4) {
1316 /* pull data from fifo into aligned buffer */
1317 u32 aligned_buf[32];
1318 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1319 int items = len >> 2;
1320 int i;
1321 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1322 aligned_buf[i] = mci_readl(host,
1323 DATA(host->data_offset));
34b664a2
JH		 1324 /* memcpy from aligned buffer into output buffer */
1325 memcpy(buf, aligned_buf, len);
1326 buf += len;
1327 cnt -= len;
1328 }
1329 } else
1330#endif
1331 {
1332 u32 *pdata = buf;
1333 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1334 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1335 buf = pdata;
1336 }
1337 if (cnt) {
4e0a5adf 1338 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1339 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1340 }
1341}
1342
1343static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1344{
34b664a2
JH		 1345 /* try and push anything in the part_buf */
1346 if (unlikely(host->part_buf_count)) {
1347 int len = dw_mci_push_part_bytes(host, buf, cnt);
1348 buf += len;
1349 cnt -= len;
1350 if (!sg_next(host->sg) || host->part_buf_count == 8) {
4e0a5adf
JC		 1351 mci_writew(host, DATA(host->data_offset),
1352 host->part_buf);
34b664a2
JH		 1353 host->part_buf_count = 0;
1354 }
1355 }
1356#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1357 if (unlikely((unsigned long)buf & 0x7)) {
1358 while (cnt >= 8) {
1359 u64 aligned_buf[16];
1360 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1361 int items = len >> 3;
1362 int i;
1363 /* memcpy from input buffer into aligned buffer */
1364 memcpy(aligned_buf, buf, len);
1365 buf += len;
1366 cnt -= len;
1367 /* push data from aligned buffer into fifo */
1368 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1369 mci_writeq(host, DATA(host->data_offset),
1370 aligned_buf[i]);
34b664a2
JH		 1371 }
1372 } else
1373#endif
1374 {
1375 u64 *pdata = buf;
1376 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1377 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1378 buf = pdata;
1379 }
1380 /* put anything remaining in the part_buf */
1381 if (cnt) {
1382 dw_mci_set_part_bytes(host, buf, cnt);
1383 if (!sg_next(host->sg))
4e0a5adf
JC		 1384 mci_writeq(host, DATA(host->data_offset),
1385 host->part_buf);
f95f3850
WN		 1386 }
1387}
1388
1389static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1390{
34b664a2
JH		 1391#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1392 if (unlikely((unsigned long)buf & 0x7)) {
1393 while (cnt >= 8) {
1394 /* pull data from fifo into aligned buffer */
1395 u64 aligned_buf[16];
1396 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1397 int items = len >> 3;
1398 int i;
1399 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1400 aligned_buf[i] = mci_readq(host,
1401 DATA(host->data_offset));
34b664a2
JH		 1402 /* memcpy from aligned buffer into output buffer */
1403 memcpy(buf, aligned_buf, len);
1404 buf += len;
1405 cnt -= len;
1406 }
1407 } else
1408#endif
1409 {
1410 u64 *pdata = buf;
1411 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1412 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1413 buf = pdata;
1414 }
1415 if (cnt) {
4e0a5adf 1416 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1417 dw_mci_pull_final_bytes(host, buf, cnt);
1418 }
1419}
f95f3850 1420
34b664a2
JH		 1421static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1422{
1423 int len;
f95f3850 1424
34b664a2
JH		 1425 /* get remaining partial bytes */
1426 len = dw_mci_pull_part_bytes(host, buf, cnt);
1427 if (unlikely(len == cnt))
1428 return;
1429 buf += len;
1430 cnt -= len;
1431
1432 /* get the rest of the data */
1433 host->pull_data(host, buf, cnt);
f95f3850
WN		 1434}
1435
1436static void dw_mci_read_data_pio(struct dw_mci *host)
1437{
f9c2a0dc
SJ		 1438 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1439 void *buf;
1440 unsigned int offset;
f95f3850
WN		 1441 struct mmc_data *data = host->data;
1442 int shift = host->data_shift;
1443 u32 status;
ba6a902d 1444 unsigned int nbytes = 0, len;
f9c2a0dc 1445 unsigned int remain, fcnt;
f95f3850
WN		 1446
1447 do {
f9c2a0dc
SJ		 1448 if (!sg_miter_next(sg_miter))
1449 goto done;
1450
1451 host->sg = sg_miter->__sg;
1452 buf = sg_miter->addr;
1453 remain = sg_miter->length;
1454 offset = 0;
1455
1456 do {
1457 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1458 << shift) + host->part_buf_count;
1459 len = min(remain, fcnt);
1460 if (!len)
1461 break;
34b664a2 1462 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1463 offset += len;
1464 nbytes += len;
f9c2a0dc
SJ		 1465 remain -= len;
1466 } while (remain);
f95f3850 1467
e74f3a9c 1468 sg_miter->consumed = offset;
f95f3850
WN		 1469 status = mci_readl(host, MINTSTS);
1470 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
f95f3850 1471 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
f95f3850 1472 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1473
1474 if (!remain) {
1475 if (!sg_miter_next(sg_miter))
1476 goto done;
1477 sg_miter->consumed = 0;
1478 }
1479 sg_miter_stop(sg_miter);
f95f3850
WN		 1480 return;
1481
1482done:
1483 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1484 sg_miter_stop(sg_miter);
1485 host->sg = NULL;
f95f3850
WN		 1486 smp_wmb();
1487 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1488}
1489
1490static void dw_mci_write_data_pio(struct dw_mci *host)
1491{
f9c2a0dc
SJ		 1492 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1493 void *buf;
1494 unsigned int offset;
f95f3850
WN		 1495 struct mmc_data *data = host->data;
1496 int shift = host->data_shift;
1497 u32 status;
1498 unsigned int nbytes = 0, len;
f9c2a0dc
SJ		 1499 unsigned int fifo_depth = host->fifo_depth;
1500 unsigned int remain, fcnt;
f95f3850
WN		 1501
1502 do {
f9c2a0dc
SJ		 1503 if (!sg_miter_next(sg_miter))
1504 goto done;
1505
1506 host->sg = sg_miter->__sg;
1507 buf = sg_miter->addr;
1508 remain = sg_miter->length;
1509 offset = 0;
1510
1511 do {
1512 fcnt = ((fifo_depth -
1513 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1514 << shift) - host->part_buf_count;
1515 len = min(remain, fcnt);
1516 if (!len)
1517 break;
f95f3850 1518 host->push_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1519 offset += len;
1520 nbytes += len;
f9c2a0dc
SJ		 1521 remain -= len;
1522 } while (remain);
f95f3850 1523
e74f3a9c 1524 sg_miter->consumed = offset;
f95f3850
WN		 1525 status = mci_readl(host, MINTSTS);
1526 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 1527 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850 1528 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1529
1530 if (!remain) {
1531 if (!sg_miter_next(sg_miter))
1532 goto done;
1533 sg_miter->consumed = 0;
1534 }
1535 sg_miter_stop(sg_miter);
f95f3850
WN		 1536 return;
1537
1538done:
1539 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1540 sg_miter_stop(sg_miter);
1541 host->sg = NULL;
f95f3850
WN		 1542 smp_wmb();
1543 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1544}
1545
1546static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1547{
1548 if (!host->cmd_status)
1549 host->cmd_status = status;
1550
1551 smp_wmb();
1552
1553 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1554 tasklet_schedule(&host->tasklet);
1555}
1556
1557static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1558{
1559 struct dw_mci *host = dev_id;
182c9081 1560 u32 pending;
f95f3850 1561 unsigned int pass_count = 0;
1a5c8e1f 1562 int i;
f95f3850
WN		 1563
1564 do {
f95f3850
WN		 1565 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1566
1567 /*
1568 * DTO fix - version 2.10a and below, and only if internal DMA
1569 * is configured.
1570 */
1571 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1572 if (!pending &&
1573 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1574 pending |= SDMMC_INT_DATA_OVER;
1575 }
1576
1577 if (!pending)
1578 break;
1579
1580 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1581 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 1582 host->cmd_status = pending;
f95f3850
WN		 1583 smp_wmb();
1584 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1585 }
1586
1587 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1588 /* if there is an error report DATA_ERROR */
1589 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 1590 host->data_status = pending;
f95f3850
WN		 1591 smp_wmb();
1592 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 1593 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1594 }
1595
1596 if (pending & SDMMC_INT_DATA_OVER) {
1597 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1598 if (!host->data_status)
182c9081 1599 host->data_status = pending;
f95f3850
WN		 1600 smp_wmb();
1601 if (host->dir_status == DW_MCI_RECV_STATUS) {
1602 if (host->sg != NULL)
1603 dw_mci_read_data_pio(host);
1604 }
1605 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1606 tasklet_schedule(&host->tasklet);
1607 }
1608
1609 if (pending & SDMMC_INT_RXDR) {
1610 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1611 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1612 dw_mci_read_data_pio(host);
1613 }
1614
1615 if (pending & SDMMC_INT_TXDR) {
1616 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1617 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1618 dw_mci_write_data_pio(host);
1619 }
1620
1621 if (pending & SDMMC_INT_CMD_DONE) {
1622 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 1623 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 1624 }
1625
1626 if (pending & SDMMC_INT_CD) {
1627 mci_writel(host, RINTSTS, SDMMC_INT_CD);
95dcc2cb 1628 queue_work(host->card_workqueue, &host->card_work);
f95f3850
WN		 1629 }
1630
1a5c8e1f
SH		 1631 /* Handle SDIO Interrupts */
1632 for (i = 0; i < host->num_slots; i++) {
1633 struct dw_mci_slot *slot = host->slot[i];
1634 if (pending & SDMMC_INT_SDIO(i)) {
1635 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1636 mmc_signal_sdio_irq(slot->mmc);
1637 }
1638 }
1639
f95f3850
WN		 1640 } while (pass_count++ < 5);
1641
1642#ifdef CONFIG_MMC_DW_IDMAC
1643 /* Handle DMA interrupts */
1644 pending = mci_readl(host, IDSTS);
1645 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1646 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1647 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
f95f3850
WN		 1648 host->dma_ops->complete(host);
1649 }
1650#endif
1651
1652 return IRQ_HANDLED;
1653}
1654
1791b13e 1655static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1656{
1791b13e 1657 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1658 int i;
1659
1660 for (i = 0; i < host->num_slots; i++) {
1661 struct dw_mci_slot *slot = host->slot[i];
1662 struct mmc_host *mmc = slot->mmc;
1663 struct mmc_request *mrq;
1664 int present;
1665 u32 ctrl;
1666
1667 present = dw_mci_get_cd(mmc);
1668 while (present != slot->last_detect_state) {
f95f3850
WN		 1669 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1670 present ? "inserted" : "removed");
1671
1791b13e
JH		 1672 /* Power up slot (before spin_lock, may sleep) */
1673 if (present != 0 && host->pdata->setpower)
1674 host->pdata->setpower(slot->id, mmc->ocr_avail);
1675
1676 spin_lock_bh(&host->lock);
1677
f95f3850
WN		 1678 /* Card change detected */
1679 slot->last_detect_state = present;
1680
1791b13e
JH		 1681 /* Mark card as present if applicable */
1682 if (present != 0)
f95f3850 1683 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1684
1685 /* Clean up queue if present */
1686 mrq = slot->mrq;
1687 if (mrq) {
1688 if (mrq == host->mrq) {
1689 host->data = NULL;
1690 host->cmd = NULL;
1691
1692 switch (host->state) {
1693 case STATE_IDLE:
1694 break;
1695 case STATE_SENDING_CMD:
1696 mrq->cmd->error = -ENOMEDIUM;
1697 if (!mrq->data)
1698 break;
1699 /* fall through */
1700 case STATE_SENDING_DATA:
1701 mrq->data->error = -ENOMEDIUM;
1702 dw_mci_stop_dma(host);
1703 break;
1704 case STATE_DATA_BUSY:
1705 case STATE_DATA_ERROR:
1706 if (mrq->data->error == -EINPROGRESS)
1707 mrq->data->error = -ENOMEDIUM;
1708 if (!mrq->stop)
1709 break;
1710 /* fall through */
1711 case STATE_SENDING_STOP:
1712 mrq->stop->error = -ENOMEDIUM;
1713 break;
1714 }
1715
1716 dw_mci_request_end(host, mrq);
1717 } else {
1718 list_del(&slot->queue_node);
1719 mrq->cmd->error = -ENOMEDIUM;
1720 if (mrq->data)
1721 mrq->data->error = -ENOMEDIUM;
1722 if (mrq->stop)
1723 mrq->stop->error = -ENOMEDIUM;
1724
1725 spin_unlock(&host->lock);
1726 mmc_request_done(slot->mmc, mrq);
1727 spin_lock(&host->lock);
1728 }
1729 }
1730
1731 /* Power down slot */
1732 if (present == 0) {
f95f3850
WN		 1733 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1734
1735 /*
1736 * Clear down the FIFO - doing so generates a
1737 * block interrupt, hence setting the
1738 * scatter-gather pointer to NULL.
1739 */
f9c2a0dc 1740 sg_miter_stop(&host->sg_miter);
f95f3850
WN		 1741 host->sg = NULL;
1742
1743 ctrl = mci_readl(host, CTRL);
1744 ctrl |= SDMMC_CTRL_FIFO_RESET;
1745 mci_writel(host, CTRL, ctrl);
1746
1747#ifdef CONFIG_MMC_DW_IDMAC
1748 ctrl = mci_readl(host, BMOD);
141a712a
SJ		 1749 /* Software reset of DMA */
1750 ctrl |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 1751 mci_writel(host, BMOD, ctrl);
1752#endif
1753
1754 }
1755
1791b13e
JH		 1756 spin_unlock_bh(&host->lock);
1757
1758 /* Power down slot (after spin_unlock, may sleep) */
1759 if (present == 0 && host->pdata->setpower)
1760 host->pdata->setpower(slot->id, 0);
1761
f95f3850
WN		 1762 present = dw_mci_get_cd(mmc);
1763 }
1764
1765 mmc_detect_change(slot->mmc,
1766 msecs_to_jiffies(host->pdata->detect_delay_ms));
1767 }
1768}
1769
c91eab4b
TA		 1770#ifdef CONFIG_OF
1771/* given a slot id, find out the device node representing that slot */
1772static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1773{
1774 struct device_node *np;
1775 const __be32 *addr;
1776 int len;
1777
1778 if (!dev || !dev->of_node)
1779 return NULL;
1780
1781 for_each_child_of_node(dev->of_node, np) {
1782 addr = of_get_property(np, "reg", &len);
1783 if (!addr || (len < sizeof(int)))
1784 continue;
1785 if (be32_to_cpup(addr) == slot)
1786 return np;
1787 }
1788 return NULL;
1789}
1790
1791/* find out bus-width for a given slot */
1792static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1793{
1794 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1795 u32 bus_wd = 1;
1796
1797 if (!np)
1798 return 1;
1799
1800 if (of_property_read_u32(np, "bus-width", &bus_wd))
1801 dev_err(dev, "bus-width property not found, assuming width"
1802 " as 1\n");
1803 return bus_wd;
1804}
1805#else /* CONFIG_OF */
1806static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1807{
1808 return 1;
1809}
1810static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1811{
1812 return NULL;
1813}
1814#endif /* CONFIG_OF */
1815
36c179a9 1816static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 1817{
1818 struct mmc_host *mmc;
1819 struct dw_mci_slot *slot;
e95baf13 1820 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 1821 int ctrl_id, ret;
c91eab4b 1822 u8 bus_width;
f95f3850 1823
4a90920c 1824 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 1825 if (!mmc)
1826 return -ENOMEM;
1827
1828 slot = mmc_priv(mmc);
1829 slot->id = id;
1830 slot->mmc = mmc;
1831 slot->host = host;
c91eab4b 1832 host->slot[id] = slot;
f95f3850
WN		 1833
1834 mmc->ops = &dw_mci_ops;
1835 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1836 mmc->f_max = host->bus_hz;
1837
1838 if (host->pdata->get_ocr)
1839 mmc->ocr_avail = host->pdata->get_ocr(id);
1840 else
1841 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1842
1843 /*
1844 * Start with slot power disabled, it will be enabled when a card
1845 * is detected.
1846 */
1847 if (host->pdata->setpower)
1848 host->pdata->setpower(id, 0);
1849
fc3d7720
JC		 1850 if (host->pdata->caps)
1851 mmc->caps = host->pdata->caps;
fc3d7720 1852
ab269128
AK		 1853 if (host->pdata->pm_caps)
1854 mmc->pm_caps = host->pdata->pm_caps;
1855
800d78bf
TA		 1856 if (host->dev->of_node) {
1857 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
1858 if (ctrl_id < 0)
1859 ctrl_id = 0;
1860 } else {
1861 ctrl_id = to_platform_device(host->dev)->id;
1862 }
cb27a843
JH		 1863 if (drv_data && drv_data->caps)
1864 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 1865
4f408cc6
SJ		 1866 if (host->pdata->caps2)
1867 mmc->caps2 = host->pdata->caps2;
4f408cc6 1868
f95f3850 1869 if (host->pdata->get_bus_wd)
c91eab4b
TA		 1870 bus_width = host->pdata->get_bus_wd(slot->id);
1871 else if (host->dev->of_node)
1872 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
1873 else
1874 bus_width = 1;
1875
cb27a843 1876 if (drv_data && drv_data->setup_bus) {
800d78bf
TA		 1877 struct device_node *slot_np;
1878 slot_np = dw_mci_of_find_slot_node(host->dev, slot->id);
cb27a843 1879 ret = drv_data->setup_bus(host, slot_np, bus_width);
800d78bf
TA		 1880 if (ret)
1881 goto err_setup_bus;
1882 }
1883
c91eab4b
TA		 1884 switch (bus_width) {
1885 case 8:
1886 mmc->caps |= MMC_CAP_8_BIT_DATA;
1887 case 4:
1888 mmc->caps |= MMC_CAP_4_BIT_DATA;
1889 }
f95f3850
WN		 1890
1891 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
6daa7778 1892 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
f95f3850 1893
f95f3850
WN		 1894 if (host->pdata->blk_settings) {
1895 mmc->max_segs = host->pdata->blk_settings->max_segs;
1896 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1897 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1898 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1899 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1900 } else {
1901 /* Useful defaults if platform data is unset. */
a39e5746
JC		 1902#ifdef CONFIG_MMC_DW_IDMAC
1903 mmc->max_segs = host->ring_size;
1904 mmc->max_blk_size = 65536;
1905 mmc->max_blk_count = host->ring_size;
1906 mmc->max_seg_size = 0x1000;
1907 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1908#else
f95f3850
WN		 1909 mmc->max_segs = 64;
1910 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1911 mmc->max_blk_count = 512;
1912 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1913 mmc->max_seg_size = mmc->max_req_size;
f95f3850 1914#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 1915 }
f95f3850 1916
c07946a3
JC		 1917 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1918 if (IS_ERR(host->vmmc)) {
a3c76eb9 1919 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
c07946a3
JC		 1920 host->vmmc = NULL;
1921 } else
1922 regulator_enable(host->vmmc);
1923
f95f3850
WN		 1924 if (dw_mci_get_cd(mmc))
1925 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1926 else
1927 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1928
f95f3850
WN		 1929 mmc_add_host(mmc);
1930
1931#if defined(CONFIG_DEBUG_FS)
1932 dw_mci_init_debugfs(slot);
1933#endif
1934
1935 /* Card initially undetected */
1936 slot->last_detect_state = 0;
1937
dd6c4b98
WN		 1938 /*
1939 * Card may have been plugged in prior to boot so we
1940 * need to run the detect tasklet
1941 */
95dcc2cb 1942 queue_work(host->card_workqueue, &host->card_work);
dd6c4b98 1943
f95f3850 1944 return 0;
800d78bf
TA		 1945
1946err_setup_bus:
1947 mmc_free_host(mmc);
1948 return -EINVAL;
f95f3850
WN		 1949}
1950
1951static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1952{
1953 /* Shutdown detect IRQ */
1954 if (slot->host->pdata->exit)
1955 slot->host->pdata->exit(id);
1956
1957 /* Debugfs stuff is cleaned up by mmc core */
1958 mmc_remove_host(slot->mmc);
1959 slot->host->slot[id] = NULL;
1960 mmc_free_host(slot->mmc);
1961}
1962
1963static void dw_mci_init_dma(struct dw_mci *host)
1964{
1965 /* Alloc memory for sg translation */
4a90920c 1966 host->sg_cpu = dma_alloc_coherent(host->dev, PAGE_SIZE,
f95f3850
WN		 1967 &host->sg_dma, GFP_KERNEL);
1968 if (!host->sg_cpu) {
4a90920c 1969 dev_err(host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 1970 __func__);
1971 goto no_dma;
1972 }
1973
1974 /* Determine which DMA interface to use */
1975#ifdef CONFIG_MMC_DW_IDMAC
1976 host->dma_ops = &dw_mci_idmac_ops;
00956ea3 1977 dev_info(host->dev, "Using internal DMA controller.\n");
f95f3850
WN		 1978#endif
1979
1980 if (!host->dma_ops)
1981 goto no_dma;
1982
e1631f98
JC		 1983 if (host->dma_ops->init && host->dma_ops->start &&
1984 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 1985 if (host->dma_ops->init(host)) {
4a90920c 1986 dev_err(host->dev, "%s: Unable to initialize "
f95f3850
WN		 1987 "DMA Controller.\n", __func__);
1988 goto no_dma;
1989 }
1990 } else {
4a90920c 1991 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 1992 goto no_dma;
1993 }
1994
1995 host->use_dma = 1;
1996 return;
1997
1998no_dma:
4a90920c 1999 dev_info(host->dev, "Using PIO mode.\n");
f95f3850
WN		 2000 host->use_dma = 0;
2001 return;
2002}
2003
2004static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
2005{
2006 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2007 unsigned int ctrl;
2008
2009 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2010 SDMMC_CTRL_DMA_RESET));
2011
2012 /* wait till resets clear */
2013 do {
2014 ctrl = mci_readl(host, CTRL);
2015 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2016 SDMMC_CTRL_DMA_RESET)))
2017 return true;
2018 } while (time_before(jiffies, timeout));
2019
2020 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
2021
2022 return false;
2023}
2024
c91eab4b
TA		 2025#ifdef CONFIG_OF
2026static struct dw_mci_of_quirks {
2027 char *quirk;
2028 int id;
2029} of_quirks[] = {
2030 {
2031 .quirk = "supports-highspeed",
2032 .id = DW_MCI_QUIRK_HIGHSPEED,
2033 }, {
2034 .quirk = "broken-cd",
2035 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2036 },
2037};
2038
2039static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2040{
2041 struct dw_mci_board *pdata;
2042 struct device *dev = host->dev;
2043 struct device_node *np = dev->of_node;
e95baf13 2044 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2045 int idx, ret;
c91eab4b
TA		 2046
2047 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2048 if (!pdata) {
2049 dev_err(dev, "could not allocate memory for pdata\n");
2050 return ERR_PTR(-ENOMEM);
2051 }
2052
2053 /* find out number of slots supported */
2054 if (of_property_read_u32(dev->of_node, "num-slots",
2055 &pdata->num_slots)) {
2056 dev_info(dev, "num-slots property not found, "
2057 "assuming 1 slot is available\n");
2058 pdata->num_slots = 1;
2059 }
2060
2061 /* get quirks */
2062 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2063 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2064 pdata->quirks |= of_quirks[idx].id;
2065
2066 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2067 dev_info(dev, "fifo-depth property not found, using "
2068 "value of FIFOTH register as default\n");
2069
2070 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2071
cb27a843
JH		 2072 if (drv_data && drv_data->parse_dt) {
2073 ret = drv_data->parse_dt(host);
800d78bf
TA		 2074 if (ret)
2075 return ERR_PTR(ret);
2076 }
2077
ab269128
AK		 2078 if (of_find_property(np, "keep-power-in-suspend", NULL))
2079 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2080
2081 if (of_find_property(np, "enable-sdio-wakeup", NULL))
2082 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2083
c91eab4b
TA		 2084 return pdata;
2085}
2086
2087#else /* CONFIG_OF */
2088static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2089{
2090 return ERR_PTR(-EINVAL);
2091}
2092#endif /* CONFIG_OF */
2093
62ca8034 2094int dw_mci_probe(struct dw_mci *host)
f95f3850 2095{
e95baf13 2096 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2097 int width, i, ret = 0;
f95f3850 2098 u32 fifo_size;
1c2215b7 2099 int init_slots = 0;
f95f3850 2100
c91eab4b
TA		 2101 if (!host->pdata) {
2102 host->pdata = dw_mci_parse_dt(host);
2103 if (IS_ERR(host->pdata)) {
2104 dev_err(host->dev, "platform data not available\n");
2105 return -EINVAL;
2106 }
f95f3850
WN		 2107 }
2108
62ca8034 2109 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
4a90920c 2110 dev_err(host->dev,
f95f3850 2111 "Platform data must supply select_slot function\n");
62ca8034 2112 return -ENODEV;
f95f3850
WN		 2113 }
2114
f90a0612
TA		 2115 host->biu_clk = clk_get(host->dev, "biu");
2116 if (IS_ERR(host->biu_clk)) {
2117 dev_dbg(host->dev, "biu clock not available\n");
2118 } else {
2119 ret = clk_prepare_enable(host->biu_clk);
2120 if (ret) {
2121 dev_err(host->dev, "failed to enable biu clock\n");
2122 clk_put(host->biu_clk);
2123 return ret;
2124 }
2125 }
2126
2127 host->ciu_clk = clk_get(host->dev, "ciu");
2128 if (IS_ERR(host->ciu_clk)) {
2129 dev_dbg(host->dev, "ciu clock not available\n");
2130 } else {
2131 ret = clk_prepare_enable(host->ciu_clk);
2132 if (ret) {
2133 dev_err(host->dev, "failed to enable ciu clock\n");
2134 clk_put(host->ciu_clk);
2135 goto err_clk_biu;
2136 }
2137 }
2138
2139 if (IS_ERR(host->ciu_clk))
2140 host->bus_hz = host->pdata->bus_hz;
2141 else
2142 host->bus_hz = clk_get_rate(host->ciu_clk);
2143
cb27a843
JH		 2144 if (drv_data && drv_data->setup_clock) {
2145 ret = drv_data->setup_clock(host);
800d78bf
TA		 2146 if (ret) {
2147 dev_err(host->dev,
2148 "implementation specific clock setup failed\n");
2149 goto err_clk_ciu;
2150 }
2151 }
2152
f90a0612 2153 if (!host->bus_hz) {
4a90920c 2154 dev_err(host->dev,
f95f3850 2155 "Platform data must supply bus speed\n");
f90a0612
TA		 2156 ret = -ENODEV;
2157 goto err_clk_ciu;
f95f3850
WN		 2158 }
2159
62ca8034 2160 host->quirks = host->pdata->quirks;
f95f3850
WN		 2161
2162 spin_lock_init(&host->lock);
2163 INIT_LIST_HEAD(&host->queue);
2164
f95f3850
WN		 2165 /*
2166 * Get the host data width - this assumes that HCON has been set with
2167 * the correct values.
2168 */
2169 i = (mci_readl(host, HCON) >> 7) & 0x7;
2170 if (!i) {
2171 host->push_data = dw_mci_push_data16;
2172 host->pull_data = dw_mci_pull_data16;
2173 width = 16;
2174 host->data_shift = 1;
2175 } else if (i == 2) {
2176 host->push_data = dw_mci_push_data64;
2177 host->pull_data = dw_mci_pull_data64;
2178 width = 64;
2179 host->data_shift = 3;
2180 } else {
2181 /* Check for a reserved value, and warn if it is */
2182 WARN((i != 1),
2183 "HCON reports a reserved host data width!\n"
2184 "Defaulting to 32-bit access.\n");
2185 host->push_data = dw_mci_push_data32;
2186 host->pull_data = dw_mci_pull_data32;
2187 width = 32;
2188 host->data_shift = 2;
2189 }
2190
2191 /* Reset all blocks */
4a90920c 2192 if (!mci_wait_reset(host->dev, host))
141a712a
SJ		 2193 return -ENODEV;
2194
2195 host->dma_ops = host->pdata->dma_ops;
2196 dw_mci_init_dma(host);
f95f3850
WN		 2197
2198 /* Clear the interrupts for the host controller */
2199 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2200 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2201
2202 /* Put in max timeout */
2203 mci_writel(host, TMOUT, 0xFFFFFFFF);
2204
2205 /*
2206 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2207 * Tx Mark = fifo_size / 2 DMA Size = 8
2208 */
b86d8253
JH		 2209 if (!host->pdata->fifo_depth) {
2210 /*
2211 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2212 * have been overwritten by the bootloader, just like we're
2213 * about to do, so if you know the value for your hardware, you
2214 * should put it in the platform data.
2215 */
2216 fifo_size = mci_readl(host, FIFOTH);
8234e869 2217 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2218 } else {
2219 fifo_size = host->pdata->fifo_depth;
2220 }
2221 host->fifo_depth = fifo_size;
e61cf118
JC		 2222 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2223 ((fifo_size/2) << 0));
2224 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2225
2226 /* disable clock to CIU */
2227 mci_writel(host, CLKENA, 0);
2228 mci_writel(host, CLKSRC, 0);
2229
2230 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
95dcc2cb 2231 host->card_workqueue = alloc_workqueue("dw-mci-card",
1791b13e 2232 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
95dcc2cb 2233 if (!host->card_workqueue)
1791b13e
JH		 2234 goto err_dmaunmap;
2235 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
62ca8034 2236 ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
f95f3850 2237 if (ret)
1791b13e 2238 goto err_workqueue;
f95f3850 2239
f95f3850
WN		 2240 if (host->pdata->num_slots)
2241 host->num_slots = host->pdata->num_slots;
2242 else
2243 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2244
2da1d7f2
YC		 2245 /*
2246 * Enable interrupts for command done, data over, data empty, card det,
2247 * receive ready and error such as transmit, receive timeout, crc error
2248 */
2249 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2250 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2251 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2252 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2253 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2254
2255 dev_info(host->dev, "DW MMC controller at irq %d, "
2256 "%d bit host data width, "
2257 "%u deep fifo\n",
2258 host->irq, width, fifo_size);
2259
f95f3850
WN		 2260 /* We need at least one slot to succeed */
2261 for (i = 0; i < host->num_slots; i++) {
2262 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 2263 if (ret)
2264 dev_dbg(host->dev, "slot %d init failed\n", i);
2265 else
2266 init_slots++;
2267 }
2268
2269 if (init_slots) {
2270 dev_info(host->dev, "%d slots initialized\n", init_slots);
2271 } else {
2272 dev_dbg(host->dev, "attempted to initialize %d slots, "
2273 "but failed on all\n", host->num_slots);
2274 goto err_init_slot;
f95f3850
WN		 2275 }
2276
4e0a5adf
JC		 2277 /*
2278 * In 2.40a spec, Data offset is changed.
2279 * Need to check the version-id and set data-offset for DATA register.
2280 */
2281 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
4a90920c 2282 dev_info(host->dev, "Version ID is %04x\n", host->verid);
4e0a5adf
JC		 2283
2284 if (host->verid < DW_MMC_240A)
2285 host->data_offset = DATA_OFFSET;
2286 else
2287 host->data_offset = DATA_240A_OFFSET;
2288
f95f3850 2289 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4a90920c 2290 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2291
2292 return 0;
2293
2294err_init_slot:
62ca8034 2295 free_irq(host->irq, host);
f95f3850 2296
1791b13e 2297err_workqueue:
95dcc2cb 2298 destroy_workqueue(host->card_workqueue);
1791b13e 2299
f95f3850
WN		 2300err_dmaunmap:
2301 if (host->use_dma && host->dma_ops->exit)
2302 host->dma_ops->exit(host);
4a90920c 2303 dma_free_coherent(host->dev, PAGE_SIZE,
f95f3850 2304 host->sg_cpu, host->sg_dma);
f95f3850 2305
c07946a3
JC		 2306 if (host->vmmc) {
2307 regulator_disable(host->vmmc);
2308 regulator_put(host->vmmc);
2309 }
f90a0612
TA		 2310
2311err_clk_ciu:
2312 if (!IS_ERR(host->ciu_clk)) {
2313 clk_disable_unprepare(host->ciu_clk);
2314 clk_put(host->ciu_clk);
2315 }
2316err_clk_biu:
2317 if (!IS_ERR(host->biu_clk)) {
2318 clk_disable_unprepare(host->biu_clk);
2319 clk_put(host->biu_clk);
2320 }
f95f3850
WN		 2321 return ret;
2322}
62ca8034 2323EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2324
62ca8034 2325void dw_mci_remove(struct dw_mci *host)
f95f3850 2326{
f95f3850
WN		 2327 int i;
2328
2329 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2330 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2331
f95f3850 2332 for (i = 0; i < host->num_slots; i++) {
4a90920c 2333 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 2334 if (host->slot[i])
2335 dw_mci_cleanup_slot(host->slot[i], i);
2336 }
2337
2338 /* disable clock to CIU */
2339 mci_writel(host, CLKENA, 0);
2340 mci_writel(host, CLKSRC, 0);
2341
62ca8034 2342 free_irq(host->irq, host);
95dcc2cb 2343 destroy_workqueue(host->card_workqueue);
4a90920c 2344 dma_free_coherent(host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
f95f3850
WN		 2345
2346 if (host->use_dma && host->dma_ops->exit)
2347 host->dma_ops->exit(host);
2348
c07946a3
JC		 2349 if (host->vmmc) {
2350 regulator_disable(host->vmmc);
2351 regulator_put(host->vmmc);
2352 }
2353
f90a0612
TA		 2354 if (!IS_ERR(host->ciu_clk))
2355 clk_disable_unprepare(host->ciu_clk);
2356 if (!IS_ERR(host->biu_clk))
2357 clk_disable_unprepare(host->biu_clk);
2358 clk_put(host->ciu_clk);
2359 clk_put(host->biu_clk);
f95f3850 2360}
62ca8034
SH		 2361EXPORT_SYMBOL(dw_mci_remove);
2362
2363
f95f3850 2364
6fe8890d 2365#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2366/*
2367 * TODO: we should probably disable the clock to the card in the suspend path.
2368 */
62ca8034 2369int dw_mci_suspend(struct dw_mci *host)
f95f3850 2370{
62ca8034 2371 int i, ret = 0;
f95f3850
WN		 2372
2373 for (i = 0; i < host->num_slots; i++) {
2374 struct dw_mci_slot *slot = host->slot[i];
2375 if (!slot)
2376 continue;
2377 ret = mmc_suspend_host(slot->mmc);
2378 if (ret < 0) {
2379 while (--i >= 0) {
2380 slot = host->slot[i];
2381 if (slot)
2382 mmc_resume_host(host->slot[i]->mmc);
2383 }
2384 return ret;
2385 }
2386 }
2387
c07946a3
JC		 2388 if (host->vmmc)
2389 regulator_disable(host->vmmc);
2390
f95f3850
WN		 2391 return 0;
2392}
62ca8034 2393EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2394
62ca8034 2395int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2396{
2397 int i, ret;
f95f3850 2398
1d6c4e0a
JC		 2399 if (host->vmmc)
2400 regulator_enable(host->vmmc);
2401
4a90920c 2402 if (!mci_wait_reset(host->dev, host)) {
e61cf118
JC		 2403 ret = -ENODEV;
2404 return ret;
2405 }
2406
3bfe619d 2407 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 2408 host->dma_ops->init(host);
2409
e61cf118
JC		 2410 /* Restore the old value at FIFOTH register */
2411 mci_writel(host, FIFOTH, host->fifoth_val);
2412
2413 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2414 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2415 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2416 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2417 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2418
f95f3850
WN		 2419 for (i = 0; i < host->num_slots; i++) {
2420 struct dw_mci_slot *slot = host->slot[i];
2421 if (!slot)
2422 continue;
ab269128
AK		 2423 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2424 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2425 dw_mci_setup_bus(slot, true);
2426 }
2427
f95f3850
WN		 2428 ret = mmc_resume_host(host->slot[i]->mmc);
2429 if (ret < 0)
2430 return ret;
2431 }
f95f3850
WN		 2432 return 0;
2433}
62ca8034 2434EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2435#endif /* CONFIG_PM_SLEEP */
2436
f95f3850
WN		 2437static int __init dw_mci_init(void)
2438{
62ca8034
SH		 2439 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2440 return 0;
f95f3850
WN		 2441}
2442
2443static void __exit dw_mci_exit(void)
2444{
f95f3850
WN		 2445}
2446
2447module_init(dw_mci_init);
2448module_exit(dw_mci_exit);
2449
2450MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2451MODULE_AUTHOR("NXP Semiconductor VietNam");
2452MODULE_AUTHOR("Imagination Technologies Ltd");
2453MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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