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f95f3850 WN |
1 | /* |
2 | * Synopsys DesignWare Multimedia Card Interface driver | |
3 | * (Based on NXP driver for lpc 31xx) | |
4 | * | |
5 | * Copyright (C) 2009 NXP Semiconductors | |
6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/blkdev.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/debugfs.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
f95f3850 WN |
25 | #include <linux/seq_file.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/stat.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/mmc/host.h> | |
31 | #include <linux/mmc/mmc.h> | |
32 | #include <linux/mmc/dw_mmc.h> | |
33 | #include <linux/bitops.h> | |
c07946a3 | 34 | #include <linux/regulator/consumer.h> |
1791b13e | 35 | #include <linux/workqueue.h> |
c91eab4b | 36 | #include <linux/of.h> |
55a6ceb2 | 37 | #include <linux/of_gpio.h> |
f95f3850 WN |
38 | |
39 | #include "dw_mmc.h" | |
40 | ||
41 | /* Common flag combinations */ | |
3f7eec62 | 42 | #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ |
f95f3850 WN |
43 | SDMMC_INT_HTO | SDMMC_INT_SBE | \ |
44 | SDMMC_INT_EBE) | |
45 | #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ | |
46 | SDMMC_INT_RESP_ERR) | |
47 | #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ | |
48 | DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) | |
49 | #define DW_MCI_SEND_STATUS 1 | |
50 | #define DW_MCI_RECV_STATUS 2 | |
51 | #define DW_MCI_DMA_THRESHOLD 16 | |
52 | ||
53 | #ifdef CONFIG_MMC_DW_IDMAC | |
fc79a4d6 JS |
54 | #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ |
55 | SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ | |
56 | SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ | |
57 | SDMMC_IDMAC_INT_TI) | |
58 | ||
f95f3850 WN |
59 | struct idmac_desc { |
60 | u32 des0; /* Control Descriptor */ | |
61 | #define IDMAC_DES0_DIC BIT(1) | |
62 | #define IDMAC_DES0_LD BIT(2) | |
63 | #define IDMAC_DES0_FD BIT(3) | |
64 | #define IDMAC_DES0_CH BIT(4) | |
65 | #define IDMAC_DES0_ER BIT(5) | |
66 | #define IDMAC_DES0_CES BIT(30) | |
67 | #define IDMAC_DES0_OWN BIT(31) | |
68 | ||
69 | u32 des1; /* Buffer sizes */ | |
70 | #define IDMAC_SET_BUFFER1_SIZE(d, s) \ | |
9b7bbe10 | 71 | ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) |
f95f3850 WN |
72 | |
73 | u32 des2; /* buffer 1 physical address */ | |
74 | ||
75 | u32 des3; /* buffer 2 physical address */ | |
76 | }; | |
77 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
78 | ||
79 | /** | |
80 | * struct dw_mci_slot - MMC slot state | |
81 | * @mmc: The mmc_host representing this slot. | |
82 | * @host: The MMC controller this slot is using. | |
a70aaa64 | 83 | * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) |
55a6ceb2 | 84 | * @wp_gpio: If gpio_is_valid() we'll use this to read write protect. |
f95f3850 WN |
85 | * @ctype: Card type for this slot. |
86 | * @mrq: mmc_request currently being processed or waiting to be | |
87 | * processed, or NULL when the slot is idle. | |
88 | * @queue_node: List node for placing this node in the @queue list of | |
89 | * &struct dw_mci. | |
90 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
fdf492a1 DA |
91 | * @__clk_old: The last updated clock with reflecting clock divider. |
92 | * Keeping track of this helps us to avoid spamming the console | |
93 | * with CONFIG_MMC_CLKGATE. | |
f95f3850 WN |
94 | * @flags: Random state bits associated with the slot. |
95 | * @id: Number of this slot. | |
96 | * @last_detect_state: Most recently observed card detect state. | |
97 | */ | |
98 | struct dw_mci_slot { | |
99 | struct mmc_host *mmc; | |
100 | struct dw_mci *host; | |
101 | ||
a70aaa64 | 102 | int quirks; |
55a6ceb2 | 103 | int wp_gpio; |
a70aaa64 | 104 | |
f95f3850 WN |
105 | u32 ctype; |
106 | ||
107 | struct mmc_request *mrq; | |
108 | struct list_head queue_node; | |
109 | ||
110 | unsigned int clock; | |
fdf492a1 | 111 | unsigned int __clk_old; |
f95f3850 WN |
112 | unsigned long flags; |
113 | #define DW_MMC_CARD_PRESENT 0 | |
114 | #define DW_MMC_CARD_NEED_INIT 1 | |
115 | int id; | |
116 | int last_detect_state; | |
117 | }; | |
118 | ||
119 | #if defined(CONFIG_DEBUG_FS) | |
120 | static int dw_mci_req_show(struct seq_file *s, void *v) | |
121 | { | |
122 | struct dw_mci_slot *slot = s->private; | |
123 | struct mmc_request *mrq; | |
124 | struct mmc_command *cmd; | |
125 | struct mmc_command *stop; | |
126 | struct mmc_data *data; | |
127 | ||
128 | /* Make sure we get a consistent snapshot */ | |
129 | spin_lock_bh(&slot->host->lock); | |
130 | mrq = slot->mrq; | |
131 | ||
132 | if (mrq) { | |
133 | cmd = mrq->cmd; | |
134 | data = mrq->data; | |
135 | stop = mrq->stop; | |
136 | ||
137 | if (cmd) | |
138 | seq_printf(s, | |
139 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
140 | cmd->opcode, cmd->arg, cmd->flags, | |
141 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
142 | cmd->resp[2], cmd->error); | |
143 | if (data) | |
144 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
145 | data->bytes_xfered, data->blocks, | |
146 | data->blksz, data->flags, data->error); | |
147 | if (stop) | |
148 | seq_printf(s, | |
149 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
150 | stop->opcode, stop->arg, stop->flags, | |
151 | stop->resp[0], stop->resp[1], stop->resp[2], | |
152 | stop->resp[2], stop->error); | |
153 | } | |
154 | ||
155 | spin_unlock_bh(&slot->host->lock); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static int dw_mci_req_open(struct inode *inode, struct file *file) | |
161 | { | |
162 | return single_open(file, dw_mci_req_show, inode->i_private); | |
163 | } | |
164 | ||
165 | static const struct file_operations dw_mci_req_fops = { | |
166 | .owner = THIS_MODULE, | |
167 | .open = dw_mci_req_open, | |
168 | .read = seq_read, | |
169 | .llseek = seq_lseek, | |
170 | .release = single_release, | |
171 | }; | |
172 | ||
173 | static int dw_mci_regs_show(struct seq_file *s, void *v) | |
174 | { | |
175 | seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); | |
176 | seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); | |
177 | seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); | |
178 | seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); | |
179 | seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); | |
180 | seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static int dw_mci_regs_open(struct inode *inode, struct file *file) | |
186 | { | |
187 | return single_open(file, dw_mci_regs_show, inode->i_private); | |
188 | } | |
189 | ||
190 | static const struct file_operations dw_mci_regs_fops = { | |
191 | .owner = THIS_MODULE, | |
192 | .open = dw_mci_regs_open, | |
193 | .read = seq_read, | |
194 | .llseek = seq_lseek, | |
195 | .release = single_release, | |
196 | }; | |
197 | ||
198 | static void dw_mci_init_debugfs(struct dw_mci_slot *slot) | |
199 | { | |
200 | struct mmc_host *mmc = slot->mmc; | |
201 | struct dw_mci *host = slot->host; | |
202 | struct dentry *root; | |
203 | struct dentry *node; | |
204 | ||
205 | root = mmc->debugfs_root; | |
206 | if (!root) | |
207 | return; | |
208 | ||
209 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
210 | &dw_mci_regs_fops); | |
211 | if (!node) | |
212 | goto err; | |
213 | ||
214 | node = debugfs_create_file("req", S_IRUSR, root, slot, | |
215 | &dw_mci_req_fops); | |
216 | if (!node) | |
217 | goto err; | |
218 | ||
219 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); | |
220 | if (!node) | |
221 | goto err; | |
222 | ||
223 | node = debugfs_create_x32("pending_events", S_IRUSR, root, | |
224 | (u32 *)&host->pending_events); | |
225 | if (!node) | |
226 | goto err; | |
227 | ||
228 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
229 | (u32 *)&host->completed_events); | |
230 | if (!node) | |
231 | goto err; | |
232 | ||
233 | return; | |
234 | ||
235 | err: | |
236 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); | |
237 | } | |
238 | #endif /* defined(CONFIG_DEBUG_FS) */ | |
239 | ||
240 | static void dw_mci_set_timeout(struct dw_mci *host) | |
241 | { | |
242 | /* timeout (maximum) */ | |
243 | mci_writel(host, TMOUT, 0xffffffff); | |
244 | } | |
245 | ||
246 | static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) | |
247 | { | |
248 | struct mmc_data *data; | |
800d78bf | 249 | struct dw_mci_slot *slot = mmc_priv(mmc); |
e95baf13 | 250 | const struct dw_mci_drv_data *drv_data = slot->host->drv_data; |
f95f3850 WN |
251 | u32 cmdr; |
252 | cmd->error = -EINPROGRESS; | |
253 | ||
254 | cmdr = cmd->opcode; | |
255 | ||
256 | if (cmdr == MMC_STOP_TRANSMISSION) | |
257 | cmdr |= SDMMC_CMD_STOP; | |
258 | else | |
259 | cmdr |= SDMMC_CMD_PRV_DAT_WAIT; | |
260 | ||
261 | if (cmd->flags & MMC_RSP_PRESENT) { | |
262 | /* We expect a response, so set this bit */ | |
263 | cmdr |= SDMMC_CMD_RESP_EXP; | |
264 | if (cmd->flags & MMC_RSP_136) | |
265 | cmdr |= SDMMC_CMD_RESP_LONG; | |
266 | } | |
267 | ||
268 | if (cmd->flags & MMC_RSP_CRC) | |
269 | cmdr |= SDMMC_CMD_RESP_CRC; | |
270 | ||
271 | data = cmd->data; | |
272 | if (data) { | |
273 | cmdr |= SDMMC_CMD_DAT_EXP; | |
274 | if (data->flags & MMC_DATA_STREAM) | |
275 | cmdr |= SDMMC_CMD_STRM_MODE; | |
276 | if (data->flags & MMC_DATA_WRITE) | |
277 | cmdr |= SDMMC_CMD_DAT_WR; | |
278 | } | |
279 | ||
cb27a843 JH |
280 | if (drv_data && drv_data->prepare_command) |
281 | drv_data->prepare_command(slot->host, &cmdr); | |
800d78bf | 282 | |
f95f3850 WN |
283 | return cmdr; |
284 | } | |
285 | ||
286 | static void dw_mci_start_command(struct dw_mci *host, | |
287 | struct mmc_command *cmd, u32 cmd_flags) | |
288 | { | |
289 | host->cmd = cmd; | |
4a90920c | 290 | dev_vdbg(host->dev, |
f95f3850 WN |
291 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
292 | cmd->arg, cmd_flags); | |
293 | ||
294 | mci_writel(host, CMDARG, cmd->arg); | |
295 | wmb(); | |
296 | ||
297 | mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); | |
298 | } | |
299 | ||
300 | static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data) | |
301 | { | |
302 | dw_mci_start_command(host, data->stop, host->stop_cmdr); | |
303 | } | |
304 | ||
305 | /* DMA interface functions */ | |
306 | static void dw_mci_stop_dma(struct dw_mci *host) | |
307 | { | |
03e8cb53 | 308 | if (host->using_dma) { |
f95f3850 WN |
309 | host->dma_ops->stop(host); |
310 | host->dma_ops->cleanup(host); | |
311 | } else { | |
312 | /* Data transfer was stopped by the interrupt handler */ | |
313 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
314 | } | |
315 | } | |
316 | ||
9aa51408 SJ |
317 | static int dw_mci_get_dma_dir(struct mmc_data *data) |
318 | { | |
319 | if (data->flags & MMC_DATA_WRITE) | |
320 | return DMA_TO_DEVICE; | |
321 | else | |
322 | return DMA_FROM_DEVICE; | |
323 | } | |
324 | ||
9beee912 | 325 | #ifdef CONFIG_MMC_DW_IDMAC |
f95f3850 WN |
326 | static void dw_mci_dma_cleanup(struct dw_mci *host) |
327 | { | |
328 | struct mmc_data *data = host->data; | |
329 | ||
330 | if (data) | |
9aa51408 | 331 | if (!data->host_cookie) |
4a90920c | 332 | dma_unmap_sg(host->dev, |
9aa51408 SJ |
333 | data->sg, |
334 | data->sg_len, | |
335 | dw_mci_get_dma_dir(data)); | |
f95f3850 WN |
336 | } |
337 | ||
338 | static void dw_mci_idmac_stop_dma(struct dw_mci *host) | |
339 | { | |
340 | u32 temp; | |
341 | ||
342 | /* Disable and reset the IDMAC interface */ | |
343 | temp = mci_readl(host, CTRL); | |
344 | temp &= ~SDMMC_CTRL_USE_IDMAC; | |
345 | temp |= SDMMC_CTRL_DMA_RESET; | |
346 | mci_writel(host, CTRL, temp); | |
347 | ||
348 | /* Stop the IDMAC running */ | |
349 | temp = mci_readl(host, BMOD); | |
a5289a43 | 350 | temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); |
f95f3850 WN |
351 | mci_writel(host, BMOD, temp); |
352 | } | |
353 | ||
354 | static void dw_mci_idmac_complete_dma(struct dw_mci *host) | |
355 | { | |
356 | struct mmc_data *data = host->data; | |
357 | ||
4a90920c | 358 | dev_vdbg(host->dev, "DMA complete\n"); |
f95f3850 WN |
359 | |
360 | host->dma_ops->cleanup(host); | |
361 | ||
362 | /* | |
363 | * If the card was removed, data will be NULL. No point in trying to | |
364 | * send the stop command or waiting for NBUSY in this case. | |
365 | */ | |
366 | if (data) { | |
367 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
368 | tasklet_schedule(&host->tasklet); | |
369 | } | |
370 | } | |
371 | ||
372 | static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, | |
373 | unsigned int sg_len) | |
374 | { | |
375 | int i; | |
376 | struct idmac_desc *desc = host->sg_cpu; | |
377 | ||
378 | for (i = 0; i < sg_len; i++, desc++) { | |
379 | unsigned int length = sg_dma_len(&data->sg[i]); | |
380 | u32 mem_addr = sg_dma_address(&data->sg[i]); | |
381 | ||
382 | /* Set the OWN bit and disable interrupts for this descriptor */ | |
383 | desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; | |
384 | ||
385 | /* Buffer length */ | |
386 | IDMAC_SET_BUFFER1_SIZE(desc, length); | |
387 | ||
388 | /* Physical address to DMA to/from */ | |
389 | desc->des2 = mem_addr; | |
390 | } | |
391 | ||
392 | /* Set first descriptor */ | |
393 | desc = host->sg_cpu; | |
394 | desc->des0 |= IDMAC_DES0_FD; | |
395 | ||
396 | /* Set last descriptor */ | |
397 | desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); | |
398 | desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); | |
399 | desc->des0 |= IDMAC_DES0_LD; | |
400 | ||
401 | wmb(); | |
402 | } | |
403 | ||
404 | static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) | |
405 | { | |
406 | u32 temp; | |
407 | ||
408 | dw_mci_translate_sglist(host, host->data, sg_len); | |
409 | ||
410 | /* Select IDMAC interface */ | |
411 | temp = mci_readl(host, CTRL); | |
412 | temp |= SDMMC_CTRL_USE_IDMAC; | |
413 | mci_writel(host, CTRL, temp); | |
414 | ||
415 | wmb(); | |
416 | ||
417 | /* Enable the IDMAC */ | |
418 | temp = mci_readl(host, BMOD); | |
a5289a43 | 419 | temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; |
f95f3850 WN |
420 | mci_writel(host, BMOD, temp); |
421 | ||
422 | /* Start it running */ | |
423 | mci_writel(host, PLDMND, 1); | |
424 | } | |
425 | ||
426 | static int dw_mci_idmac_init(struct dw_mci *host) | |
427 | { | |
428 | struct idmac_desc *p; | |
897b69e7 | 429 | int i; |
f95f3850 WN |
430 | |
431 | /* Number of descriptors in the ring buffer */ | |
432 | host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); | |
433 | ||
434 | /* Forward link the descriptor list */ | |
435 | for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) | |
436 | p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1)); | |
437 | ||
438 | /* Set the last descriptor as the end-of-ring descriptor */ | |
439 | p->des3 = host->sg_dma; | |
440 | p->des0 = IDMAC_DES0_ER; | |
441 | ||
141a712a SJ |
442 | mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET); |
443 | ||
f95f3850 | 444 | /* Mask out interrupts - get Tx & Rx complete only */ |
fc79a4d6 | 445 | mci_writel(host, IDSTS, IDMAC_INT_CLR); |
f95f3850 WN |
446 | mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI | |
447 | SDMMC_IDMAC_INT_TI); | |
448 | ||
449 | /* Set the descriptor base address */ | |
450 | mci_writel(host, DBADDR, host->sg_dma); | |
451 | return 0; | |
452 | } | |
453 | ||
8e2b36ea | 454 | static const struct dw_mci_dma_ops dw_mci_idmac_ops = { |
885c3e80 SJ |
455 | .init = dw_mci_idmac_init, |
456 | .start = dw_mci_idmac_start_dma, | |
457 | .stop = dw_mci_idmac_stop_dma, | |
458 | .complete = dw_mci_idmac_complete_dma, | |
459 | .cleanup = dw_mci_dma_cleanup, | |
460 | }; | |
461 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
462 | ||
9aa51408 SJ |
463 | static int dw_mci_pre_dma_transfer(struct dw_mci *host, |
464 | struct mmc_data *data, | |
465 | bool next) | |
f95f3850 WN |
466 | { |
467 | struct scatterlist *sg; | |
9aa51408 | 468 | unsigned int i, sg_len; |
03e8cb53 | 469 | |
9aa51408 SJ |
470 | if (!next && data->host_cookie) |
471 | return data->host_cookie; | |
f95f3850 WN |
472 | |
473 | /* | |
474 | * We don't do DMA on "complex" transfers, i.e. with | |
475 | * non-word-aligned buffers or lengths. Also, we don't bother | |
476 | * with all the DMA setup overhead for short transfers. | |
477 | */ | |
478 | if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) | |
479 | return -EINVAL; | |
9aa51408 | 480 | |
f95f3850 WN |
481 | if (data->blksz & 3) |
482 | return -EINVAL; | |
483 | ||
484 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
485 | if (sg->offset & 3 || sg->length & 3) | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
4a90920c | 489 | sg_len = dma_map_sg(host->dev, |
9aa51408 SJ |
490 | data->sg, |
491 | data->sg_len, | |
492 | dw_mci_get_dma_dir(data)); | |
493 | if (sg_len == 0) | |
494 | return -EINVAL; | |
03e8cb53 | 495 | |
9aa51408 SJ |
496 | if (next) |
497 | data->host_cookie = sg_len; | |
f95f3850 | 498 | |
9aa51408 SJ |
499 | return sg_len; |
500 | } | |
501 | ||
9aa51408 SJ |
502 | static void dw_mci_pre_req(struct mmc_host *mmc, |
503 | struct mmc_request *mrq, | |
504 | bool is_first_req) | |
505 | { | |
506 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
507 | struct mmc_data *data = mrq->data; | |
508 | ||
509 | if (!slot->host->use_dma || !data) | |
510 | return; | |
511 | ||
512 | if (data->host_cookie) { | |
513 | data->host_cookie = 0; | |
514 | return; | |
515 | } | |
516 | ||
517 | if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) | |
518 | data->host_cookie = 0; | |
519 | } | |
520 | ||
521 | static void dw_mci_post_req(struct mmc_host *mmc, | |
522 | struct mmc_request *mrq, | |
523 | int err) | |
524 | { | |
525 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
526 | struct mmc_data *data = mrq->data; | |
527 | ||
528 | if (!slot->host->use_dma || !data) | |
529 | return; | |
530 | ||
531 | if (data->host_cookie) | |
4a90920c | 532 | dma_unmap_sg(slot->host->dev, |
9aa51408 SJ |
533 | data->sg, |
534 | data->sg_len, | |
535 | dw_mci_get_dma_dir(data)); | |
536 | data->host_cookie = 0; | |
537 | } | |
538 | ||
539 | static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) | |
540 | { | |
541 | int sg_len; | |
542 | u32 temp; | |
543 | ||
544 | host->using_dma = 0; | |
545 | ||
546 | /* If we don't have a channel, we can't do DMA */ | |
547 | if (!host->use_dma) | |
548 | return -ENODEV; | |
549 | ||
550 | sg_len = dw_mci_pre_dma_transfer(host, data, 0); | |
a99aa9b9 SJ |
551 | if (sg_len < 0) { |
552 | host->dma_ops->stop(host); | |
9aa51408 | 553 | return sg_len; |
a99aa9b9 | 554 | } |
9aa51408 SJ |
555 | |
556 | host->using_dma = 1; | |
f95f3850 | 557 | |
4a90920c | 558 | dev_vdbg(host->dev, |
f95f3850 WN |
559 | "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", |
560 | (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, | |
561 | sg_len); | |
562 | ||
563 | /* Enable the DMA interface */ | |
564 | temp = mci_readl(host, CTRL); | |
565 | temp |= SDMMC_CTRL_DMA_ENABLE; | |
566 | mci_writel(host, CTRL, temp); | |
567 | ||
568 | /* Disable RX/TX IRQs, let DMA handle it */ | |
569 | temp = mci_readl(host, INTMASK); | |
570 | temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); | |
571 | mci_writel(host, INTMASK, temp); | |
572 | ||
573 | host->dma_ops->start(host, sg_len); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) | |
579 | { | |
580 | u32 temp; | |
581 | ||
582 | data->error = -EINPROGRESS; | |
583 | ||
584 | WARN_ON(host->data); | |
585 | host->sg = NULL; | |
586 | host->data = data; | |
587 | ||
55c5efbc JH |
588 | if (data->flags & MMC_DATA_READ) |
589 | host->dir_status = DW_MCI_RECV_STATUS; | |
590 | else | |
591 | host->dir_status = DW_MCI_SEND_STATUS; | |
592 | ||
f95f3850 | 593 | if (dw_mci_submit_data_dma(host, data)) { |
f9c2a0dc SJ |
594 | int flags = SG_MITER_ATOMIC; |
595 | if (host->data->flags & MMC_DATA_READ) | |
596 | flags |= SG_MITER_TO_SG; | |
597 | else | |
598 | flags |= SG_MITER_FROM_SG; | |
599 | ||
600 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
f95f3850 | 601 | host->sg = data->sg; |
34b664a2 JH |
602 | host->part_buf_start = 0; |
603 | host->part_buf_count = 0; | |
f95f3850 | 604 | |
b40af3aa | 605 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); |
f95f3850 WN |
606 | temp = mci_readl(host, INTMASK); |
607 | temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; | |
608 | mci_writel(host, INTMASK, temp); | |
609 | ||
610 | temp = mci_readl(host, CTRL); | |
611 | temp &= ~SDMMC_CTRL_DMA_ENABLE; | |
612 | mci_writel(host, CTRL, temp); | |
613 | } | |
614 | } | |
615 | ||
616 | static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) | |
617 | { | |
618 | struct dw_mci *host = slot->host; | |
619 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
620 | unsigned int cmd_status = 0; | |
621 | ||
622 | mci_writel(host, CMDARG, arg); | |
623 | wmb(); | |
624 | mci_writel(host, CMD, SDMMC_CMD_START | cmd); | |
625 | ||
626 | while (time_before(jiffies, timeout)) { | |
627 | cmd_status = mci_readl(host, CMD); | |
628 | if (!(cmd_status & SDMMC_CMD_START)) | |
629 | return; | |
630 | } | |
631 | dev_err(&slot->mmc->class_dev, | |
632 | "Timeout sending command (cmd %#x arg %#x status %#x)\n", | |
633 | cmd, arg, cmd_status); | |
634 | } | |
635 | ||
ab269128 | 636 | static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) |
f95f3850 WN |
637 | { |
638 | struct dw_mci *host = slot->host; | |
fdf492a1 | 639 | unsigned int clock = slot->clock; |
f95f3850 | 640 | u32 div; |
9623b5b9 | 641 | u32 clk_en_a; |
f95f3850 | 642 | |
fdf492a1 DA |
643 | if (!clock) { |
644 | mci_writel(host, CLKENA, 0); | |
645 | mci_send_cmd(slot, | |
646 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
647 | } else if (clock != host->current_speed || force_clkinit) { | |
648 | div = host->bus_hz / clock; | |
649 | if (host->bus_hz % clock && host->bus_hz > clock) | |
f95f3850 WN |
650 | /* |
651 | * move the + 1 after the divide to prevent | |
652 | * over-clocking the card. | |
653 | */ | |
e419990b SJ |
654 | div += 1; |
655 | ||
fdf492a1 | 656 | div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; |
f95f3850 | 657 | |
fdf492a1 DA |
658 | if ((clock << div) != slot->__clk_old || force_clkinit) |
659 | dev_info(&slot->mmc->class_dev, | |
660 | "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", | |
661 | slot->id, host->bus_hz, clock, | |
662 | div ? ((host->bus_hz / div) >> 1) : | |
663 | host->bus_hz, div); | |
f95f3850 WN |
664 | |
665 | /* disable clock */ | |
666 | mci_writel(host, CLKENA, 0); | |
667 | mci_writel(host, CLKSRC, 0); | |
668 | ||
669 | /* inform CIU */ | |
670 | mci_send_cmd(slot, | |
671 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
672 | ||
673 | /* set clock to desired speed */ | |
674 | mci_writel(host, CLKDIV, div); | |
675 | ||
676 | /* inform CIU */ | |
677 | mci_send_cmd(slot, | |
678 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
679 | ||
9623b5b9 DA |
680 | /* enable clock; only low power if no SDIO */ |
681 | clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; | |
682 | if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id))) | |
683 | clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; | |
684 | mci_writel(host, CLKENA, clk_en_a); | |
f95f3850 WN |
685 | |
686 | /* inform CIU */ | |
687 | mci_send_cmd(slot, | |
688 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
689 | ||
fdf492a1 DA |
690 | /* keep the clock with reflecting clock dividor */ |
691 | slot->__clk_old = clock << div; | |
f95f3850 WN |
692 | } |
693 | ||
fdf492a1 DA |
694 | host->current_speed = clock; |
695 | ||
f95f3850 | 696 | /* Set the current slot bus width */ |
1d56c453 | 697 | mci_writel(host, CTYPE, (slot->ctype << slot->id)); |
f95f3850 WN |
698 | } |
699 | ||
053b3ce6 SJ |
700 | static void __dw_mci_start_request(struct dw_mci *host, |
701 | struct dw_mci_slot *slot, | |
702 | struct mmc_command *cmd) | |
f95f3850 WN |
703 | { |
704 | struct mmc_request *mrq; | |
f95f3850 WN |
705 | struct mmc_data *data; |
706 | u32 cmdflags; | |
707 | ||
708 | mrq = slot->mrq; | |
709 | if (host->pdata->select_slot) | |
710 | host->pdata->select_slot(slot->id); | |
711 | ||
f95f3850 WN |
712 | host->cur_slot = slot; |
713 | host->mrq = mrq; | |
714 | ||
715 | host->pending_events = 0; | |
716 | host->completed_events = 0; | |
717 | host->data_status = 0; | |
718 | ||
053b3ce6 | 719 | data = cmd->data; |
f95f3850 WN |
720 | if (data) { |
721 | dw_mci_set_timeout(host); | |
722 | mci_writel(host, BYTCNT, data->blksz*data->blocks); | |
723 | mci_writel(host, BLKSIZ, data->blksz); | |
724 | } | |
725 | ||
f95f3850 WN |
726 | cmdflags = dw_mci_prepare_command(slot->mmc, cmd); |
727 | ||
728 | /* this is the first command, send the initialization clock */ | |
729 | if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) | |
730 | cmdflags |= SDMMC_CMD_INIT; | |
731 | ||
732 | if (data) { | |
733 | dw_mci_submit_data(host, data); | |
734 | wmb(); | |
735 | } | |
736 | ||
737 | dw_mci_start_command(host, cmd, cmdflags); | |
738 | ||
739 | if (mrq->stop) | |
740 | host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); | |
741 | } | |
742 | ||
053b3ce6 SJ |
743 | static void dw_mci_start_request(struct dw_mci *host, |
744 | struct dw_mci_slot *slot) | |
745 | { | |
746 | struct mmc_request *mrq = slot->mrq; | |
747 | struct mmc_command *cmd; | |
748 | ||
749 | cmd = mrq->sbc ? mrq->sbc : mrq->cmd; | |
750 | __dw_mci_start_request(host, slot, cmd); | |
751 | } | |
752 | ||
7456caae | 753 | /* must be called with host->lock held */ |
f95f3850 WN |
754 | static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, |
755 | struct mmc_request *mrq) | |
756 | { | |
757 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
758 | host->state); | |
759 | ||
f95f3850 WN |
760 | slot->mrq = mrq; |
761 | ||
762 | if (host->state == STATE_IDLE) { | |
763 | host->state = STATE_SENDING_CMD; | |
764 | dw_mci_start_request(host, slot); | |
765 | } else { | |
766 | list_add_tail(&slot->queue_node, &host->queue); | |
767 | } | |
f95f3850 WN |
768 | } |
769 | ||
770 | static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
771 | { | |
772 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
773 | struct dw_mci *host = slot->host; | |
774 | ||
775 | WARN_ON(slot->mrq); | |
776 | ||
7456caae JH |
777 | /* |
778 | * The check for card presence and queueing of the request must be | |
779 | * atomic, otherwise the card could be removed in between and the | |
780 | * request wouldn't fail until another card was inserted. | |
781 | */ | |
782 | spin_lock_bh(&host->lock); | |
783 | ||
f95f3850 | 784 | if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { |
7456caae | 785 | spin_unlock_bh(&host->lock); |
f95f3850 WN |
786 | mrq->cmd->error = -ENOMEDIUM; |
787 | mmc_request_done(mmc, mrq); | |
788 | return; | |
789 | } | |
790 | ||
f95f3850 | 791 | dw_mci_queue_request(host, slot, mrq); |
7456caae JH |
792 | |
793 | spin_unlock_bh(&host->lock); | |
f95f3850 WN |
794 | } |
795 | ||
796 | static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
797 | { | |
798 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
e95baf13 | 799 | const struct dw_mci_drv_data *drv_data = slot->host->drv_data; |
41babf75 | 800 | u32 regs; |
f95f3850 | 801 | |
f95f3850 | 802 | switch (ios->bus_width) { |
f95f3850 WN |
803 | case MMC_BUS_WIDTH_4: |
804 | slot->ctype = SDMMC_CTYPE_4BIT; | |
805 | break; | |
c9b2a06f JC |
806 | case MMC_BUS_WIDTH_8: |
807 | slot->ctype = SDMMC_CTYPE_8BIT; | |
808 | break; | |
b2f7cb45 JC |
809 | default: |
810 | /* set default 1 bit mode */ | |
811 | slot->ctype = SDMMC_CTYPE_1BIT; | |
f95f3850 WN |
812 | } |
813 | ||
3f514291 SJ |
814 | regs = mci_readl(slot->host, UHS_REG); |
815 | ||
41babf75 | 816 | /* DDR mode set */ |
3f514291 | 817 | if (ios->timing == MMC_TIMING_UHS_DDR50) |
c69042a5 | 818 | regs |= ((0x1 << slot->id) << 16); |
3f514291 | 819 | else |
c69042a5 | 820 | regs &= ~((0x1 << slot->id) << 16); |
3f514291 SJ |
821 | |
822 | mci_writel(slot->host, UHS_REG, regs); | |
41babf75 | 823 | |
fdf492a1 DA |
824 | /* |
825 | * Use mirror of ios->clock to prevent race with mmc | |
826 | * core ios update when finding the minimum. | |
827 | */ | |
828 | slot->clock = ios->clock; | |
f95f3850 | 829 | |
cb27a843 JH |
830 | if (drv_data && drv_data->set_ios) |
831 | drv_data->set_ios(slot->host, ios); | |
800d78bf | 832 | |
bf7cb224 JC |
833 | /* Slot specific timing and width adjustment */ |
834 | dw_mci_setup_bus(slot, false); | |
835 | ||
f95f3850 WN |
836 | switch (ios->power_mode) { |
837 | case MMC_POWER_UP: | |
838 | set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); | |
e6f34e2f JH |
839 | /* Power up slot */ |
840 | if (slot->host->pdata->setpower) | |
841 | slot->host->pdata->setpower(slot->id, mmc->ocr_avail); | |
4366dcc5 JC |
842 | regs = mci_readl(slot->host, PWREN); |
843 | regs |= (1 << slot->id); | |
844 | mci_writel(slot->host, PWREN, regs); | |
e6f34e2f JH |
845 | break; |
846 | case MMC_POWER_OFF: | |
847 | /* Power down slot */ | |
848 | if (slot->host->pdata->setpower) | |
849 | slot->host->pdata->setpower(slot->id, 0); | |
4366dcc5 JC |
850 | regs = mci_readl(slot->host, PWREN); |
851 | regs &= ~(1 << slot->id); | |
852 | mci_writel(slot->host, PWREN, regs); | |
f95f3850 WN |
853 | break; |
854 | default: | |
855 | break; | |
856 | } | |
857 | } | |
858 | ||
859 | static int dw_mci_get_ro(struct mmc_host *mmc) | |
860 | { | |
861 | int read_only; | |
862 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
863 | struct dw_mci_board *brd = slot->host->pdata; | |
864 | ||
865 | /* Use platform get_ro function, else try on board write protect */ | |
9640639b | 866 | if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) |
b4967aa5 TA |
867 | read_only = 0; |
868 | else if (brd->get_ro) | |
f95f3850 | 869 | read_only = brd->get_ro(slot->id); |
55a6ceb2 DA |
870 | else if (gpio_is_valid(slot->wp_gpio)) |
871 | read_only = gpio_get_value(slot->wp_gpio); | |
f95f3850 WN |
872 | else |
873 | read_only = | |
874 | mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; | |
875 | ||
876 | dev_dbg(&mmc->class_dev, "card is %s\n", | |
877 | read_only ? "read-only" : "read-write"); | |
878 | ||
879 | return read_only; | |
880 | } | |
881 | ||
882 | static int dw_mci_get_cd(struct mmc_host *mmc) | |
883 | { | |
884 | int present; | |
885 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
886 | struct dw_mci_board *brd = slot->host->pdata; | |
887 | ||
888 | /* Use platform get_cd function, else try onboard card detect */ | |
fc3d7720 JC |
889 | if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) |
890 | present = 1; | |
891 | else if (brd->get_cd) | |
f95f3850 WN |
892 | present = !brd->get_cd(slot->id); |
893 | else | |
894 | present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) | |
895 | == 0 ? 1 : 0; | |
896 | ||
897 | if (present) | |
898 | dev_dbg(&mmc->class_dev, "card is present\n"); | |
899 | else | |
900 | dev_dbg(&mmc->class_dev, "card is not present\n"); | |
901 | ||
902 | return present; | |
903 | } | |
904 | ||
9623b5b9 DA |
905 | /* |
906 | * Disable lower power mode. | |
907 | * | |
908 | * Low power mode will stop the card clock when idle. According to the | |
909 | * description of the CLKENA register we should disable low power mode | |
910 | * for SDIO cards if we need SDIO interrupts to work. | |
911 | * | |
912 | * This function is fast if low power mode is already disabled. | |
913 | */ | |
914 | static void dw_mci_disable_low_power(struct dw_mci_slot *slot) | |
915 | { | |
916 | struct dw_mci *host = slot->host; | |
917 | u32 clk_en_a; | |
918 | const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; | |
919 | ||
920 | clk_en_a = mci_readl(host, CLKENA); | |
921 | ||
922 | if (clk_en_a & clken_low_pwr) { | |
923 | mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr); | |
924 | mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | | |
925 | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
926 | } | |
927 | } | |
928 | ||
1a5c8e1f SH |
929 | static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) |
930 | { | |
931 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
932 | struct dw_mci *host = slot->host; | |
933 | u32 int_mask; | |
934 | ||
935 | /* Enable/disable Slot Specific SDIO interrupt */ | |
936 | int_mask = mci_readl(host, INTMASK); | |
937 | if (enb) { | |
9623b5b9 DA |
938 | /* |
939 | * Turn off low power mode if it was enabled. This is a bit of | |
940 | * a heavy operation and we disable / enable IRQs a lot, so | |
941 | * we'll leave low power mode disabled and it will get | |
942 | * re-enabled again in dw_mci_setup_bus(). | |
943 | */ | |
944 | dw_mci_disable_low_power(slot); | |
945 | ||
1a5c8e1f | 946 | mci_writel(host, INTMASK, |
705ad047 | 947 | (int_mask | SDMMC_INT_SDIO(slot->id))); |
1a5c8e1f SH |
948 | } else { |
949 | mci_writel(host, INTMASK, | |
705ad047 | 950 | (int_mask & ~SDMMC_INT_SDIO(slot->id))); |
1a5c8e1f SH |
951 | } |
952 | } | |
953 | ||
f95f3850 | 954 | static const struct mmc_host_ops dw_mci_ops = { |
1a5c8e1f | 955 | .request = dw_mci_request, |
9aa51408 SJ |
956 | .pre_req = dw_mci_pre_req, |
957 | .post_req = dw_mci_post_req, | |
1a5c8e1f SH |
958 | .set_ios = dw_mci_set_ios, |
959 | .get_ro = dw_mci_get_ro, | |
960 | .get_cd = dw_mci_get_cd, | |
961 | .enable_sdio_irq = dw_mci_enable_sdio_irq, | |
f95f3850 WN |
962 | }; |
963 | ||
964 | static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) | |
965 | __releases(&host->lock) | |
966 | __acquires(&host->lock) | |
967 | { | |
968 | struct dw_mci_slot *slot; | |
969 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
970 | ||
971 | WARN_ON(host->cmd || host->data); | |
972 | ||
973 | host->cur_slot->mrq = NULL; | |
974 | host->mrq = NULL; | |
975 | if (!list_empty(&host->queue)) { | |
976 | slot = list_entry(host->queue.next, | |
977 | struct dw_mci_slot, queue_node); | |
978 | list_del(&slot->queue_node); | |
4a90920c | 979 | dev_vdbg(host->dev, "list not empty: %s is next\n", |
f95f3850 WN |
980 | mmc_hostname(slot->mmc)); |
981 | host->state = STATE_SENDING_CMD; | |
982 | dw_mci_start_request(host, slot); | |
983 | } else { | |
4a90920c | 984 | dev_vdbg(host->dev, "list empty\n"); |
f95f3850 WN |
985 | host->state = STATE_IDLE; |
986 | } | |
987 | ||
988 | spin_unlock(&host->lock); | |
989 | mmc_request_done(prev_mmc, mrq); | |
990 | spin_lock(&host->lock); | |
991 | } | |
992 | ||
993 | static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) | |
994 | { | |
995 | u32 status = host->cmd_status; | |
996 | ||
997 | host->cmd_status = 0; | |
998 | ||
999 | /* Read the response from the card (up to 16 bytes) */ | |
1000 | if (cmd->flags & MMC_RSP_PRESENT) { | |
1001 | if (cmd->flags & MMC_RSP_136) { | |
1002 | cmd->resp[3] = mci_readl(host, RESP0); | |
1003 | cmd->resp[2] = mci_readl(host, RESP1); | |
1004 | cmd->resp[1] = mci_readl(host, RESP2); | |
1005 | cmd->resp[0] = mci_readl(host, RESP3); | |
1006 | } else { | |
1007 | cmd->resp[0] = mci_readl(host, RESP0); | |
1008 | cmd->resp[1] = 0; | |
1009 | cmd->resp[2] = 0; | |
1010 | cmd->resp[3] = 0; | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | if (status & SDMMC_INT_RTO) | |
1015 | cmd->error = -ETIMEDOUT; | |
1016 | else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) | |
1017 | cmd->error = -EILSEQ; | |
1018 | else if (status & SDMMC_INT_RESP_ERR) | |
1019 | cmd->error = -EIO; | |
1020 | else | |
1021 | cmd->error = 0; | |
1022 | ||
1023 | if (cmd->error) { | |
1024 | /* newer ip versions need a delay between retries */ | |
1025 | if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) | |
1026 | mdelay(20); | |
1027 | ||
1028 | if (cmd->data) { | |
f95f3850 | 1029 | dw_mci_stop_dma(host); |
fda5f736 | 1030 | host->data = NULL; |
f95f3850 WN |
1031 | } |
1032 | } | |
1033 | } | |
1034 | ||
1035 | static void dw_mci_tasklet_func(unsigned long priv) | |
1036 | { | |
1037 | struct dw_mci *host = (struct dw_mci *)priv; | |
1038 | struct mmc_data *data; | |
1039 | struct mmc_command *cmd; | |
1040 | enum dw_mci_state state; | |
1041 | enum dw_mci_state prev_state; | |
94dd5b33 | 1042 | u32 status, ctrl; |
f95f3850 WN |
1043 | |
1044 | spin_lock(&host->lock); | |
1045 | ||
1046 | state = host->state; | |
1047 | data = host->data; | |
1048 | ||
1049 | do { | |
1050 | prev_state = state; | |
1051 | ||
1052 | switch (state) { | |
1053 | case STATE_IDLE: | |
1054 | break; | |
1055 | ||
1056 | case STATE_SENDING_CMD: | |
1057 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
1058 | &host->pending_events)) | |
1059 | break; | |
1060 | ||
1061 | cmd = host->cmd; | |
1062 | host->cmd = NULL; | |
1063 | set_bit(EVENT_CMD_COMPLETE, &host->completed_events); | |
053b3ce6 SJ |
1064 | dw_mci_command_complete(host, cmd); |
1065 | if (cmd == host->mrq->sbc && !cmd->error) { | |
1066 | prev_state = state = STATE_SENDING_CMD; | |
1067 | __dw_mci_start_request(host, host->cur_slot, | |
1068 | host->mrq->cmd); | |
1069 | goto unlock; | |
1070 | } | |
1071 | ||
f95f3850 WN |
1072 | if (!host->mrq->data || cmd->error) { |
1073 | dw_mci_request_end(host, host->mrq); | |
1074 | goto unlock; | |
1075 | } | |
1076 | ||
1077 | prev_state = state = STATE_SENDING_DATA; | |
1078 | /* fall through */ | |
1079 | ||
1080 | case STATE_SENDING_DATA: | |
1081 | if (test_and_clear_bit(EVENT_DATA_ERROR, | |
1082 | &host->pending_events)) { | |
1083 | dw_mci_stop_dma(host); | |
1084 | if (data->stop) | |
1085 | send_stop_cmd(host, data); | |
1086 | state = STATE_DATA_ERROR; | |
1087 | break; | |
1088 | } | |
1089 | ||
1090 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
1091 | &host->pending_events)) | |
1092 | break; | |
1093 | ||
1094 | set_bit(EVENT_XFER_COMPLETE, &host->completed_events); | |
1095 | prev_state = state = STATE_DATA_BUSY; | |
1096 | /* fall through */ | |
1097 | ||
1098 | case STATE_DATA_BUSY: | |
1099 | if (!test_and_clear_bit(EVENT_DATA_COMPLETE, | |
1100 | &host->pending_events)) | |
1101 | break; | |
1102 | ||
1103 | host->data = NULL; | |
1104 | set_bit(EVENT_DATA_COMPLETE, &host->completed_events); | |
1105 | status = host->data_status; | |
1106 | ||
1107 | if (status & DW_MCI_DATA_ERROR_FLAGS) { | |
3f7eec62 | 1108 | if (status & SDMMC_INT_DRTO) { |
f95f3850 WN |
1109 | data->error = -ETIMEDOUT; |
1110 | } else if (status & SDMMC_INT_DCRC) { | |
f95f3850 | 1111 | data->error = -EILSEQ; |
55c5efbc JH |
1112 | } else if (status & SDMMC_INT_EBE && |
1113 | host->dir_status == | |
1114 | DW_MCI_SEND_STATUS) { | |
1115 | /* | |
1116 | * No data CRC status was returned. | |
1117 | * The number of bytes transferred will | |
1118 | * be exaggerated in PIO mode. | |
1119 | */ | |
1120 | data->bytes_xfered = 0; | |
1121 | data->error = -ETIMEDOUT; | |
f95f3850 | 1122 | } else { |
4a90920c | 1123 | dev_err(host->dev, |
f95f3850 WN |
1124 | "data FIFO error " |
1125 | "(status=%08x)\n", | |
1126 | status); | |
1127 | data->error = -EIO; | |
1128 | } | |
94dd5b33 JH |
1129 | /* |
1130 | * After an error, there may be data lingering | |
1131 | * in the FIFO, so reset it - doing so | |
1132 | * generates a block interrupt, hence setting | |
1133 | * the scatter-gather pointer to NULL. | |
1134 | */ | |
f9c2a0dc | 1135 | sg_miter_stop(&host->sg_miter); |
94dd5b33 JH |
1136 | host->sg = NULL; |
1137 | ctrl = mci_readl(host, CTRL); | |
1138 | ctrl |= SDMMC_CTRL_FIFO_RESET; | |
1139 | mci_writel(host, CTRL, ctrl); | |
f95f3850 WN |
1140 | } else { |
1141 | data->bytes_xfered = data->blocks * data->blksz; | |
1142 | data->error = 0; | |
1143 | } | |
1144 | ||
1145 | if (!data->stop) { | |
1146 | dw_mci_request_end(host, host->mrq); | |
1147 | goto unlock; | |
1148 | } | |
1149 | ||
053b3ce6 SJ |
1150 | if (host->mrq->sbc && !data->error) { |
1151 | data->stop->error = 0; | |
1152 | dw_mci_request_end(host, host->mrq); | |
1153 | goto unlock; | |
1154 | } | |
1155 | ||
f95f3850 WN |
1156 | prev_state = state = STATE_SENDING_STOP; |
1157 | if (!data->error) | |
1158 | send_stop_cmd(host, data); | |
1159 | /* fall through */ | |
1160 | ||
1161 | case STATE_SENDING_STOP: | |
1162 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
1163 | &host->pending_events)) | |
1164 | break; | |
1165 | ||
1166 | host->cmd = NULL; | |
1167 | dw_mci_command_complete(host, host->mrq->stop); | |
1168 | dw_mci_request_end(host, host->mrq); | |
1169 | goto unlock; | |
1170 | ||
1171 | case STATE_DATA_ERROR: | |
1172 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
1173 | &host->pending_events)) | |
1174 | break; | |
1175 | ||
1176 | state = STATE_DATA_BUSY; | |
1177 | break; | |
1178 | } | |
1179 | } while (state != prev_state); | |
1180 | ||
1181 | host->state = state; | |
1182 | unlock: | |
1183 | spin_unlock(&host->lock); | |
1184 | ||
1185 | } | |
1186 | ||
34b664a2 JH |
1187 | /* push final bytes to part_buf, only use during push */ |
1188 | static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1189 | { |
34b664a2 JH |
1190 | memcpy((void *)&host->part_buf, buf, cnt); |
1191 | host->part_buf_count = cnt; | |
1192 | } | |
f95f3850 | 1193 | |
34b664a2 JH |
1194 | /* append bytes to part_buf, only use during push */ |
1195 | static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1196 | { | |
1197 | cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); | |
1198 | memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); | |
1199 | host->part_buf_count += cnt; | |
1200 | return cnt; | |
1201 | } | |
f95f3850 | 1202 | |
34b664a2 JH |
1203 | /* pull first bytes from part_buf, only use during pull */ |
1204 | static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1205 | { | |
1206 | cnt = min(cnt, (int)host->part_buf_count); | |
1207 | if (cnt) { | |
1208 | memcpy(buf, (void *)&host->part_buf + host->part_buf_start, | |
1209 | cnt); | |
1210 | host->part_buf_count -= cnt; | |
1211 | host->part_buf_start += cnt; | |
f95f3850 | 1212 | } |
34b664a2 | 1213 | return cnt; |
f95f3850 WN |
1214 | } |
1215 | ||
34b664a2 JH |
1216 | /* pull final bytes from the part_buf, assuming it's just been filled */ |
1217 | static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1218 | { |
34b664a2 JH |
1219 | memcpy(buf, &host->part_buf, cnt); |
1220 | host->part_buf_start = cnt; | |
1221 | host->part_buf_count = (1 << host->data_shift) - cnt; | |
1222 | } | |
f95f3850 | 1223 | |
34b664a2 JH |
1224 | static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) |
1225 | { | |
cfbeb59c MC |
1226 | struct mmc_data *data = host->data; |
1227 | int init_cnt = cnt; | |
1228 | ||
34b664a2 JH |
1229 | /* try and push anything in the part_buf */ |
1230 | if (unlikely(host->part_buf_count)) { | |
1231 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1232 | buf += len; | |
1233 | cnt -= len; | |
cfbeb59c | 1234 | if (host->part_buf_count == 2) { |
4e0a5adf JC |
1235 | mci_writew(host, DATA(host->data_offset), |
1236 | host->part_buf16); | |
34b664a2 JH |
1237 | host->part_buf_count = 0; |
1238 | } | |
1239 | } | |
1240 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1241 | if (unlikely((unsigned long)buf & 0x1)) { | |
1242 | while (cnt >= 2) { | |
1243 | u16 aligned_buf[64]; | |
1244 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1245 | int items = len >> 1; | |
1246 | int i; | |
1247 | /* memcpy from input buffer into aligned buffer */ | |
1248 | memcpy(aligned_buf, buf, len); | |
1249 | buf += len; | |
1250 | cnt -= len; | |
1251 | /* push data from aligned buffer into fifo */ | |
1252 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1253 | mci_writew(host, DATA(host->data_offset), |
1254 | aligned_buf[i]); | |
34b664a2 JH |
1255 | } |
1256 | } else | |
1257 | #endif | |
1258 | { | |
1259 | u16 *pdata = buf; | |
1260 | for (; cnt >= 2; cnt -= 2) | |
4e0a5adf | 1261 | mci_writew(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1262 | buf = pdata; |
1263 | } | |
1264 | /* put anything remaining in the part_buf */ | |
1265 | if (cnt) { | |
1266 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1267 | /* Push data if we have reached the expected data length */ |
1268 | if ((data->bytes_xfered + init_cnt) == | |
1269 | (data->blksz * data->blocks)) | |
4e0a5adf | 1270 | mci_writew(host, DATA(host->data_offset), |
cfbeb59c | 1271 | host->part_buf16); |
34b664a2 JH |
1272 | } |
1273 | } | |
f95f3850 | 1274 | |
34b664a2 JH |
1275 | static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) |
1276 | { | |
1277 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1278 | if (unlikely((unsigned long)buf & 0x1)) { | |
1279 | while (cnt >= 2) { | |
1280 | /* pull data from fifo into aligned buffer */ | |
1281 | u16 aligned_buf[64]; | |
1282 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1283 | int items = len >> 1; | |
1284 | int i; | |
1285 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1286 | aligned_buf[i] = mci_readw(host, |
1287 | DATA(host->data_offset)); | |
34b664a2 JH |
1288 | /* memcpy from aligned buffer into output buffer */ |
1289 | memcpy(buf, aligned_buf, len); | |
1290 | buf += len; | |
1291 | cnt -= len; | |
1292 | } | |
1293 | } else | |
1294 | #endif | |
1295 | { | |
1296 | u16 *pdata = buf; | |
1297 | for (; cnt >= 2; cnt -= 2) | |
4e0a5adf | 1298 | *pdata++ = mci_readw(host, DATA(host->data_offset)); |
34b664a2 JH |
1299 | buf = pdata; |
1300 | } | |
1301 | if (cnt) { | |
4e0a5adf | 1302 | host->part_buf16 = mci_readw(host, DATA(host->data_offset)); |
34b664a2 | 1303 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1304 | } |
1305 | } | |
1306 | ||
1307 | static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) | |
1308 | { | |
cfbeb59c MC |
1309 | struct mmc_data *data = host->data; |
1310 | int init_cnt = cnt; | |
1311 | ||
34b664a2 JH |
1312 | /* try and push anything in the part_buf */ |
1313 | if (unlikely(host->part_buf_count)) { | |
1314 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1315 | buf += len; | |
1316 | cnt -= len; | |
cfbeb59c | 1317 | if (host->part_buf_count == 4) { |
4e0a5adf JC |
1318 | mci_writel(host, DATA(host->data_offset), |
1319 | host->part_buf32); | |
34b664a2 JH |
1320 | host->part_buf_count = 0; |
1321 | } | |
1322 | } | |
1323 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1324 | if (unlikely((unsigned long)buf & 0x3)) { | |
1325 | while (cnt >= 4) { | |
1326 | u32 aligned_buf[32]; | |
1327 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1328 | int items = len >> 2; | |
1329 | int i; | |
1330 | /* memcpy from input buffer into aligned buffer */ | |
1331 | memcpy(aligned_buf, buf, len); | |
1332 | buf += len; | |
1333 | cnt -= len; | |
1334 | /* push data from aligned buffer into fifo */ | |
1335 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1336 | mci_writel(host, DATA(host->data_offset), |
1337 | aligned_buf[i]); | |
34b664a2 JH |
1338 | } |
1339 | } else | |
1340 | #endif | |
1341 | { | |
1342 | u32 *pdata = buf; | |
1343 | for (; cnt >= 4; cnt -= 4) | |
4e0a5adf | 1344 | mci_writel(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1345 | buf = pdata; |
1346 | } | |
1347 | /* put anything remaining in the part_buf */ | |
1348 | if (cnt) { | |
1349 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1350 | /* Push data if we have reached the expected data length */ |
1351 | if ((data->bytes_xfered + init_cnt) == | |
1352 | (data->blksz * data->blocks)) | |
4e0a5adf | 1353 | mci_writel(host, DATA(host->data_offset), |
cfbeb59c | 1354 | host->part_buf32); |
f95f3850 WN |
1355 | } |
1356 | } | |
1357 | ||
1358 | static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) | |
1359 | { | |
34b664a2 JH |
1360 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1361 | if (unlikely((unsigned long)buf & 0x3)) { | |
1362 | while (cnt >= 4) { | |
1363 | /* pull data from fifo into aligned buffer */ | |
1364 | u32 aligned_buf[32]; | |
1365 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1366 | int items = len >> 2; | |
1367 | int i; | |
1368 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1369 | aligned_buf[i] = mci_readl(host, |
1370 | DATA(host->data_offset)); | |
34b664a2 JH |
1371 | /* memcpy from aligned buffer into output buffer */ |
1372 | memcpy(buf, aligned_buf, len); | |
1373 | buf += len; | |
1374 | cnt -= len; | |
1375 | } | |
1376 | } else | |
1377 | #endif | |
1378 | { | |
1379 | u32 *pdata = buf; | |
1380 | for (; cnt >= 4; cnt -= 4) | |
4e0a5adf | 1381 | *pdata++ = mci_readl(host, DATA(host->data_offset)); |
34b664a2 JH |
1382 | buf = pdata; |
1383 | } | |
1384 | if (cnt) { | |
4e0a5adf | 1385 | host->part_buf32 = mci_readl(host, DATA(host->data_offset)); |
34b664a2 | 1386 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1387 | } |
1388 | } | |
1389 | ||
1390 | static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) | |
1391 | { | |
cfbeb59c MC |
1392 | struct mmc_data *data = host->data; |
1393 | int init_cnt = cnt; | |
1394 | ||
34b664a2 JH |
1395 | /* try and push anything in the part_buf */ |
1396 | if (unlikely(host->part_buf_count)) { | |
1397 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1398 | buf += len; | |
1399 | cnt -= len; | |
c09fbd74 | 1400 | |
cfbeb59c | 1401 | if (host->part_buf_count == 8) { |
c09fbd74 | 1402 | mci_writeq(host, DATA(host->data_offset), |
4e0a5adf | 1403 | host->part_buf); |
34b664a2 JH |
1404 | host->part_buf_count = 0; |
1405 | } | |
1406 | } | |
1407 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1408 | if (unlikely((unsigned long)buf & 0x7)) { | |
1409 | while (cnt >= 8) { | |
1410 | u64 aligned_buf[16]; | |
1411 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1412 | int items = len >> 3; | |
1413 | int i; | |
1414 | /* memcpy from input buffer into aligned buffer */ | |
1415 | memcpy(aligned_buf, buf, len); | |
1416 | buf += len; | |
1417 | cnt -= len; | |
1418 | /* push data from aligned buffer into fifo */ | |
1419 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1420 | mci_writeq(host, DATA(host->data_offset), |
1421 | aligned_buf[i]); | |
34b664a2 JH |
1422 | } |
1423 | } else | |
1424 | #endif | |
1425 | { | |
1426 | u64 *pdata = buf; | |
1427 | for (; cnt >= 8; cnt -= 8) | |
4e0a5adf | 1428 | mci_writeq(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1429 | buf = pdata; |
1430 | } | |
1431 | /* put anything remaining in the part_buf */ | |
1432 | if (cnt) { | |
1433 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1434 | /* Push data if we have reached the expected data length */ |
1435 | if ((data->bytes_xfered + init_cnt) == | |
1436 | (data->blksz * data->blocks)) | |
4e0a5adf | 1437 | mci_writeq(host, DATA(host->data_offset), |
cfbeb59c | 1438 | host->part_buf); |
f95f3850 WN |
1439 | } |
1440 | } | |
1441 | ||
1442 | static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) | |
1443 | { | |
34b664a2 JH |
1444 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1445 | if (unlikely((unsigned long)buf & 0x7)) { | |
1446 | while (cnt >= 8) { | |
1447 | /* pull data from fifo into aligned buffer */ | |
1448 | u64 aligned_buf[16]; | |
1449 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1450 | int items = len >> 3; | |
1451 | int i; | |
1452 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1453 | aligned_buf[i] = mci_readq(host, |
1454 | DATA(host->data_offset)); | |
34b664a2 JH |
1455 | /* memcpy from aligned buffer into output buffer */ |
1456 | memcpy(buf, aligned_buf, len); | |
1457 | buf += len; | |
1458 | cnt -= len; | |
1459 | } | |
1460 | } else | |
1461 | #endif | |
1462 | { | |
1463 | u64 *pdata = buf; | |
1464 | for (; cnt >= 8; cnt -= 8) | |
4e0a5adf | 1465 | *pdata++ = mci_readq(host, DATA(host->data_offset)); |
34b664a2 JH |
1466 | buf = pdata; |
1467 | } | |
1468 | if (cnt) { | |
4e0a5adf | 1469 | host->part_buf = mci_readq(host, DATA(host->data_offset)); |
34b664a2 JH |
1470 | dw_mci_pull_final_bytes(host, buf, cnt); |
1471 | } | |
1472 | } | |
f95f3850 | 1473 | |
34b664a2 JH |
1474 | static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) |
1475 | { | |
1476 | int len; | |
f95f3850 | 1477 | |
34b664a2 JH |
1478 | /* get remaining partial bytes */ |
1479 | len = dw_mci_pull_part_bytes(host, buf, cnt); | |
1480 | if (unlikely(len == cnt)) | |
1481 | return; | |
1482 | buf += len; | |
1483 | cnt -= len; | |
1484 | ||
1485 | /* get the rest of the data */ | |
1486 | host->pull_data(host, buf, cnt); | |
f95f3850 WN |
1487 | } |
1488 | ||
87a74d39 | 1489 | static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) |
f95f3850 | 1490 | { |
f9c2a0dc SJ |
1491 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
1492 | void *buf; | |
1493 | unsigned int offset; | |
f95f3850 WN |
1494 | struct mmc_data *data = host->data; |
1495 | int shift = host->data_shift; | |
1496 | u32 status; | |
3e4b0d8b | 1497 | unsigned int len; |
f9c2a0dc | 1498 | unsigned int remain, fcnt; |
f95f3850 WN |
1499 | |
1500 | do { | |
f9c2a0dc SJ |
1501 | if (!sg_miter_next(sg_miter)) |
1502 | goto done; | |
1503 | ||
4225fc85 | 1504 | host->sg = sg_miter->piter.sg; |
f9c2a0dc SJ |
1505 | buf = sg_miter->addr; |
1506 | remain = sg_miter->length; | |
1507 | offset = 0; | |
1508 | ||
1509 | do { | |
1510 | fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) | |
1511 | << shift) + host->part_buf_count; | |
1512 | len = min(remain, fcnt); | |
1513 | if (!len) | |
1514 | break; | |
34b664a2 | 1515 | dw_mci_pull_data(host, (void *)(buf + offset), len); |
3e4b0d8b | 1516 | data->bytes_xfered += len; |
f95f3850 | 1517 | offset += len; |
f9c2a0dc SJ |
1518 | remain -= len; |
1519 | } while (remain); | |
f95f3850 | 1520 | |
e74f3a9c | 1521 | sg_miter->consumed = offset; |
f95f3850 WN |
1522 | status = mci_readl(host, MINTSTS); |
1523 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
87a74d39 KK |
1524 | /* if the RXDR is ready read again */ |
1525 | } while ((status & SDMMC_INT_RXDR) || | |
1526 | (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); | |
f9c2a0dc SJ |
1527 | |
1528 | if (!remain) { | |
1529 | if (!sg_miter_next(sg_miter)) | |
1530 | goto done; | |
1531 | sg_miter->consumed = 0; | |
1532 | } | |
1533 | sg_miter_stop(sg_miter); | |
f95f3850 WN |
1534 | return; |
1535 | ||
1536 | done: | |
f9c2a0dc SJ |
1537 | sg_miter_stop(sg_miter); |
1538 | host->sg = NULL; | |
f95f3850 WN |
1539 | smp_wmb(); |
1540 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
1541 | } | |
1542 | ||
1543 | static void dw_mci_write_data_pio(struct dw_mci *host) | |
1544 | { | |
f9c2a0dc SJ |
1545 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
1546 | void *buf; | |
1547 | unsigned int offset; | |
f95f3850 WN |
1548 | struct mmc_data *data = host->data; |
1549 | int shift = host->data_shift; | |
1550 | u32 status; | |
3e4b0d8b | 1551 | unsigned int len; |
f9c2a0dc SJ |
1552 | unsigned int fifo_depth = host->fifo_depth; |
1553 | unsigned int remain, fcnt; | |
f95f3850 WN |
1554 | |
1555 | do { | |
f9c2a0dc SJ |
1556 | if (!sg_miter_next(sg_miter)) |
1557 | goto done; | |
1558 | ||
4225fc85 | 1559 | host->sg = sg_miter->piter.sg; |
f9c2a0dc SJ |
1560 | buf = sg_miter->addr; |
1561 | remain = sg_miter->length; | |
1562 | offset = 0; | |
1563 | ||
1564 | do { | |
1565 | fcnt = ((fifo_depth - | |
1566 | SDMMC_GET_FCNT(mci_readl(host, STATUS))) | |
1567 | << shift) - host->part_buf_count; | |
1568 | len = min(remain, fcnt); | |
1569 | if (!len) | |
1570 | break; | |
f95f3850 | 1571 | host->push_data(host, (void *)(buf + offset), len); |
3e4b0d8b | 1572 | data->bytes_xfered += len; |
f95f3850 | 1573 | offset += len; |
f9c2a0dc SJ |
1574 | remain -= len; |
1575 | } while (remain); | |
f95f3850 | 1576 | |
e74f3a9c | 1577 | sg_miter->consumed = offset; |
f95f3850 WN |
1578 | status = mci_readl(host, MINTSTS); |
1579 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
f95f3850 | 1580 | } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ |
f9c2a0dc SJ |
1581 | |
1582 | if (!remain) { | |
1583 | if (!sg_miter_next(sg_miter)) | |
1584 | goto done; | |
1585 | sg_miter->consumed = 0; | |
1586 | } | |
1587 | sg_miter_stop(sg_miter); | |
f95f3850 WN |
1588 | return; |
1589 | ||
1590 | done: | |
f9c2a0dc SJ |
1591 | sg_miter_stop(sg_miter); |
1592 | host->sg = NULL; | |
f95f3850 WN |
1593 | smp_wmb(); |
1594 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
1595 | } | |
1596 | ||
1597 | static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) | |
1598 | { | |
1599 | if (!host->cmd_status) | |
1600 | host->cmd_status = status; | |
1601 | ||
1602 | smp_wmb(); | |
1603 | ||
1604 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
1605 | tasklet_schedule(&host->tasklet); | |
1606 | } | |
1607 | ||
1608 | static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) | |
1609 | { | |
1610 | struct dw_mci *host = dev_id; | |
182c9081 | 1611 | u32 pending; |
1a5c8e1f | 1612 | int i; |
f95f3850 | 1613 | |
1fb5f68a MC |
1614 | pending = mci_readl(host, MINTSTS); /* read-only mask reg */ |
1615 | ||
476d79f1 DA |
1616 | /* |
1617 | * DTO fix - version 2.10a and below, and only if internal DMA | |
1618 | * is configured. | |
1619 | */ | |
1620 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { | |
1621 | if (!pending && | |
1622 | ((mci_readl(host, STATUS) >> 17) & 0x1fff)) | |
1623 | pending |= SDMMC_INT_DATA_OVER; | |
1624 | } | |
f95f3850 | 1625 | |
476d79f1 | 1626 | if (pending) { |
f95f3850 WN |
1627 | if (pending & DW_MCI_CMD_ERROR_FLAGS) { |
1628 | mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); | |
182c9081 | 1629 | host->cmd_status = pending; |
f95f3850 WN |
1630 | smp_wmb(); |
1631 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
f95f3850 WN |
1632 | } |
1633 | ||
1634 | if (pending & DW_MCI_DATA_ERROR_FLAGS) { | |
1635 | /* if there is an error report DATA_ERROR */ | |
1636 | mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); | |
182c9081 | 1637 | host->data_status = pending; |
f95f3850 WN |
1638 | smp_wmb(); |
1639 | set_bit(EVENT_DATA_ERROR, &host->pending_events); | |
9b2026a1 | 1640 | tasklet_schedule(&host->tasklet); |
f95f3850 WN |
1641 | } |
1642 | ||
1643 | if (pending & SDMMC_INT_DATA_OVER) { | |
1644 | mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); | |
1645 | if (!host->data_status) | |
182c9081 | 1646 | host->data_status = pending; |
f95f3850 WN |
1647 | smp_wmb(); |
1648 | if (host->dir_status == DW_MCI_RECV_STATUS) { | |
1649 | if (host->sg != NULL) | |
87a74d39 | 1650 | dw_mci_read_data_pio(host, true); |
f95f3850 WN |
1651 | } |
1652 | set_bit(EVENT_DATA_COMPLETE, &host->pending_events); | |
1653 | tasklet_schedule(&host->tasklet); | |
1654 | } | |
1655 | ||
1656 | if (pending & SDMMC_INT_RXDR) { | |
1657 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
b40af3aa | 1658 | if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) |
87a74d39 | 1659 | dw_mci_read_data_pio(host, false); |
f95f3850 WN |
1660 | } |
1661 | ||
1662 | if (pending & SDMMC_INT_TXDR) { | |
1663 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
b40af3aa | 1664 | if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) |
f95f3850 WN |
1665 | dw_mci_write_data_pio(host); |
1666 | } | |
1667 | ||
1668 | if (pending & SDMMC_INT_CMD_DONE) { | |
1669 | mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); | |
182c9081 | 1670 | dw_mci_cmd_interrupt(host, pending); |
f95f3850 WN |
1671 | } |
1672 | ||
1673 | if (pending & SDMMC_INT_CD) { | |
1674 | mci_writel(host, RINTSTS, SDMMC_INT_CD); | |
95dcc2cb | 1675 | queue_work(host->card_workqueue, &host->card_work); |
f95f3850 WN |
1676 | } |
1677 | ||
1a5c8e1f SH |
1678 | /* Handle SDIO Interrupts */ |
1679 | for (i = 0; i < host->num_slots; i++) { | |
1680 | struct dw_mci_slot *slot = host->slot[i]; | |
1681 | if (pending & SDMMC_INT_SDIO(i)) { | |
1682 | mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i)); | |
1683 | mmc_signal_sdio_irq(slot->mmc); | |
1684 | } | |
1685 | } | |
1686 | ||
1fb5f68a | 1687 | } |
f95f3850 WN |
1688 | |
1689 | #ifdef CONFIG_MMC_DW_IDMAC | |
1690 | /* Handle DMA interrupts */ | |
1691 | pending = mci_readl(host, IDSTS); | |
1692 | if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { | |
1693 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI); | |
1694 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); | |
f95f3850 WN |
1695 | host->dma_ops->complete(host); |
1696 | } | |
1697 | #endif | |
1698 | ||
1699 | return IRQ_HANDLED; | |
1700 | } | |
1701 | ||
1791b13e | 1702 | static void dw_mci_work_routine_card(struct work_struct *work) |
f95f3850 | 1703 | { |
1791b13e | 1704 | struct dw_mci *host = container_of(work, struct dw_mci, card_work); |
f95f3850 WN |
1705 | int i; |
1706 | ||
1707 | for (i = 0; i < host->num_slots; i++) { | |
1708 | struct dw_mci_slot *slot = host->slot[i]; | |
1709 | struct mmc_host *mmc = slot->mmc; | |
1710 | struct mmc_request *mrq; | |
1711 | int present; | |
1712 | u32 ctrl; | |
1713 | ||
1714 | present = dw_mci_get_cd(mmc); | |
1715 | while (present != slot->last_detect_state) { | |
f95f3850 WN |
1716 | dev_dbg(&slot->mmc->class_dev, "card %s\n", |
1717 | present ? "inserted" : "removed"); | |
1718 | ||
1791b13e JH |
1719 | spin_lock_bh(&host->lock); |
1720 | ||
f95f3850 WN |
1721 | /* Card change detected */ |
1722 | slot->last_detect_state = present; | |
1723 | ||
1791b13e JH |
1724 | /* Mark card as present if applicable */ |
1725 | if (present != 0) | |
f95f3850 | 1726 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); |
f95f3850 WN |
1727 | |
1728 | /* Clean up queue if present */ | |
1729 | mrq = slot->mrq; | |
1730 | if (mrq) { | |
1731 | if (mrq == host->mrq) { | |
1732 | host->data = NULL; | |
1733 | host->cmd = NULL; | |
1734 | ||
1735 | switch (host->state) { | |
1736 | case STATE_IDLE: | |
1737 | break; | |
1738 | case STATE_SENDING_CMD: | |
1739 | mrq->cmd->error = -ENOMEDIUM; | |
1740 | if (!mrq->data) | |
1741 | break; | |
1742 | /* fall through */ | |
1743 | case STATE_SENDING_DATA: | |
1744 | mrq->data->error = -ENOMEDIUM; | |
1745 | dw_mci_stop_dma(host); | |
1746 | break; | |
1747 | case STATE_DATA_BUSY: | |
1748 | case STATE_DATA_ERROR: | |
1749 | if (mrq->data->error == -EINPROGRESS) | |
1750 | mrq->data->error = -ENOMEDIUM; | |
1751 | if (!mrq->stop) | |
1752 | break; | |
1753 | /* fall through */ | |
1754 | case STATE_SENDING_STOP: | |
1755 | mrq->stop->error = -ENOMEDIUM; | |
1756 | break; | |
1757 | } | |
1758 | ||
1759 | dw_mci_request_end(host, mrq); | |
1760 | } else { | |
1761 | list_del(&slot->queue_node); | |
1762 | mrq->cmd->error = -ENOMEDIUM; | |
1763 | if (mrq->data) | |
1764 | mrq->data->error = -ENOMEDIUM; | |
1765 | if (mrq->stop) | |
1766 | mrq->stop->error = -ENOMEDIUM; | |
1767 | ||
1768 | spin_unlock(&host->lock); | |
1769 | mmc_request_done(slot->mmc, mrq); | |
1770 | spin_lock(&host->lock); | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | /* Power down slot */ | |
1775 | if (present == 0) { | |
f95f3850 WN |
1776 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); |
1777 | ||
1778 | /* | |
1779 | * Clear down the FIFO - doing so generates a | |
1780 | * block interrupt, hence setting the | |
1781 | * scatter-gather pointer to NULL. | |
1782 | */ | |
f9c2a0dc | 1783 | sg_miter_stop(&host->sg_miter); |
f95f3850 WN |
1784 | host->sg = NULL; |
1785 | ||
1786 | ctrl = mci_readl(host, CTRL); | |
1787 | ctrl |= SDMMC_CTRL_FIFO_RESET; | |
1788 | mci_writel(host, CTRL, ctrl); | |
1789 | ||
1790 | #ifdef CONFIG_MMC_DW_IDMAC | |
1791 | ctrl = mci_readl(host, BMOD); | |
141a712a SJ |
1792 | /* Software reset of DMA */ |
1793 | ctrl |= SDMMC_IDMAC_SWRESET; | |
f95f3850 WN |
1794 | mci_writel(host, BMOD, ctrl); |
1795 | #endif | |
1796 | ||
1797 | } | |
1798 | ||
1791b13e JH |
1799 | spin_unlock_bh(&host->lock); |
1800 | ||
f95f3850 WN |
1801 | present = dw_mci_get_cd(mmc); |
1802 | } | |
1803 | ||
1804 | mmc_detect_change(slot->mmc, | |
1805 | msecs_to_jiffies(host->pdata->detect_delay_ms)); | |
1806 | } | |
1807 | } | |
1808 | ||
c91eab4b TA |
1809 | #ifdef CONFIG_OF |
1810 | /* given a slot id, find out the device node representing that slot */ | |
1811 | static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) | |
1812 | { | |
1813 | struct device_node *np; | |
1814 | const __be32 *addr; | |
1815 | int len; | |
1816 | ||
1817 | if (!dev || !dev->of_node) | |
1818 | return NULL; | |
1819 | ||
1820 | for_each_child_of_node(dev->of_node, np) { | |
1821 | addr = of_get_property(np, "reg", &len); | |
1822 | if (!addr || (len < sizeof(int))) | |
1823 | continue; | |
1824 | if (be32_to_cpup(addr) == slot) | |
1825 | return np; | |
1826 | } | |
1827 | return NULL; | |
1828 | } | |
1829 | ||
a70aaa64 DA |
1830 | static struct dw_mci_of_slot_quirks { |
1831 | char *quirk; | |
1832 | int id; | |
1833 | } of_slot_quirks[] = { | |
1834 | { | |
1835 | .quirk = "disable-wp", | |
1836 | .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, | |
1837 | }, | |
1838 | }; | |
1839 | ||
1840 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) | |
1841 | { | |
1842 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | |
1843 | int quirks = 0; | |
1844 | int idx; | |
1845 | ||
1846 | /* get quirks */ | |
1847 | for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) | |
1848 | if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) | |
1849 | quirks |= of_slot_quirks[idx].id; | |
1850 | ||
1851 | return quirks; | |
1852 | } | |
1853 | ||
c91eab4b TA |
1854 | /* find out bus-width for a given slot */ |
1855 | static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) | |
1856 | { | |
1857 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | |
1858 | u32 bus_wd = 1; | |
1859 | ||
1860 | if (!np) | |
1861 | return 1; | |
1862 | ||
1863 | if (of_property_read_u32(np, "bus-width", &bus_wd)) | |
1864 | dev_err(dev, "bus-width property not found, assuming width" | |
1865 | " as 1\n"); | |
1866 | return bus_wd; | |
1867 | } | |
55a6ceb2 DA |
1868 | |
1869 | /* find the write protect gpio for a given slot; or -1 if none specified */ | |
1870 | static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) | |
1871 | { | |
1872 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | |
1873 | int gpio; | |
1874 | ||
1875 | if (!np) | |
1876 | return -EINVAL; | |
1877 | ||
1878 | gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
1879 | ||
1880 | /* Having a missing entry is valid; return silently */ | |
1881 | if (!gpio_is_valid(gpio)) | |
1882 | return -EINVAL; | |
1883 | ||
1884 | if (devm_gpio_request(dev, gpio, "dw-mci-wp")) { | |
1885 | dev_warn(dev, "gpio [%d] request failed\n", gpio); | |
1886 | return -EINVAL; | |
1887 | } | |
1888 | ||
1889 | return gpio; | |
1890 | } | |
c91eab4b | 1891 | #else /* CONFIG_OF */ |
a70aaa64 DA |
1892 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) |
1893 | { | |
1894 | return 0; | |
1895 | } | |
c91eab4b TA |
1896 | static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) |
1897 | { | |
1898 | return 1; | |
1899 | } | |
1900 | static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) | |
1901 | { | |
1902 | return NULL; | |
1903 | } | |
55a6ceb2 DA |
1904 | static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) |
1905 | { | |
1906 | return -EINVAL; | |
1907 | } | |
c91eab4b TA |
1908 | #endif /* CONFIG_OF */ |
1909 | ||
36c179a9 | 1910 | static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) |
f95f3850 WN |
1911 | { |
1912 | struct mmc_host *mmc; | |
1913 | struct dw_mci_slot *slot; | |
e95baf13 | 1914 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
800d78bf | 1915 | int ctrl_id, ret; |
c91eab4b | 1916 | u8 bus_width; |
f95f3850 | 1917 | |
4a90920c | 1918 | mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); |
f95f3850 WN |
1919 | if (!mmc) |
1920 | return -ENOMEM; | |
1921 | ||
1922 | slot = mmc_priv(mmc); | |
1923 | slot->id = id; | |
1924 | slot->mmc = mmc; | |
1925 | slot->host = host; | |
c91eab4b | 1926 | host->slot[id] = slot; |
f95f3850 | 1927 | |
a70aaa64 DA |
1928 | slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); |
1929 | ||
f95f3850 WN |
1930 | mmc->ops = &dw_mci_ops; |
1931 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); | |
1932 | mmc->f_max = host->bus_hz; | |
1933 | ||
1934 | if (host->pdata->get_ocr) | |
1935 | mmc->ocr_avail = host->pdata->get_ocr(id); | |
1936 | else | |
1937 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
1938 | ||
1939 | /* | |
1940 | * Start with slot power disabled, it will be enabled when a card | |
1941 | * is detected. | |
1942 | */ | |
1943 | if (host->pdata->setpower) | |
1944 | host->pdata->setpower(id, 0); | |
1945 | ||
fc3d7720 JC |
1946 | if (host->pdata->caps) |
1947 | mmc->caps = host->pdata->caps; | |
fc3d7720 | 1948 | |
ab269128 AK |
1949 | if (host->pdata->pm_caps) |
1950 | mmc->pm_caps = host->pdata->pm_caps; | |
1951 | ||
800d78bf TA |
1952 | if (host->dev->of_node) { |
1953 | ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); | |
1954 | if (ctrl_id < 0) | |
1955 | ctrl_id = 0; | |
1956 | } else { | |
1957 | ctrl_id = to_platform_device(host->dev)->id; | |
1958 | } | |
cb27a843 JH |
1959 | if (drv_data && drv_data->caps) |
1960 | mmc->caps |= drv_data->caps[ctrl_id]; | |
800d78bf | 1961 | |
4f408cc6 SJ |
1962 | if (host->pdata->caps2) |
1963 | mmc->caps2 = host->pdata->caps2; | |
4f408cc6 | 1964 | |
f95f3850 | 1965 | if (host->pdata->get_bus_wd) |
c91eab4b TA |
1966 | bus_width = host->pdata->get_bus_wd(slot->id); |
1967 | else if (host->dev->of_node) | |
1968 | bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id); | |
1969 | else | |
1970 | bus_width = 1; | |
1971 | ||
1972 | switch (bus_width) { | |
1973 | case 8: | |
1974 | mmc->caps |= MMC_CAP_8_BIT_DATA; | |
1975 | case 4: | |
1976 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1977 | } | |
f95f3850 WN |
1978 | |
1979 | if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) | |
6daa7778 | 1980 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
f95f3850 | 1981 | |
f95f3850 WN |
1982 | if (host->pdata->blk_settings) { |
1983 | mmc->max_segs = host->pdata->blk_settings->max_segs; | |
1984 | mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; | |
1985 | mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; | |
1986 | mmc->max_req_size = host->pdata->blk_settings->max_req_size; | |
1987 | mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; | |
1988 | } else { | |
1989 | /* Useful defaults if platform data is unset. */ | |
a39e5746 JC |
1990 | #ifdef CONFIG_MMC_DW_IDMAC |
1991 | mmc->max_segs = host->ring_size; | |
1992 | mmc->max_blk_size = 65536; | |
1993 | mmc->max_blk_count = host->ring_size; | |
1994 | mmc->max_seg_size = 0x1000; | |
1995 | mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; | |
1996 | #else | |
f95f3850 WN |
1997 | mmc->max_segs = 64; |
1998 | mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ | |
1999 | mmc->max_blk_count = 512; | |
2000 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
2001 | mmc->max_seg_size = mmc->max_req_size; | |
f95f3850 | 2002 | #endif /* CONFIG_MMC_DW_IDMAC */ |
a39e5746 | 2003 | } |
f95f3850 WN |
2004 | |
2005 | if (dw_mci_get_cd(mmc)) | |
2006 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
2007 | else | |
2008 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
2009 | ||
55a6ceb2 DA |
2010 | slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id); |
2011 | ||
0cea529d JC |
2012 | ret = mmc_add_host(mmc); |
2013 | if (ret) | |
2014 | goto err_setup_bus; | |
f95f3850 WN |
2015 | |
2016 | #if defined(CONFIG_DEBUG_FS) | |
2017 | dw_mci_init_debugfs(slot); | |
2018 | #endif | |
2019 | ||
2020 | /* Card initially undetected */ | |
2021 | slot->last_detect_state = 0; | |
2022 | ||
2023 | return 0; | |
800d78bf TA |
2024 | |
2025 | err_setup_bus: | |
2026 | mmc_free_host(mmc); | |
2027 | return -EINVAL; | |
f95f3850 WN |
2028 | } |
2029 | ||
2030 | static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) | |
2031 | { | |
2032 | /* Shutdown detect IRQ */ | |
2033 | if (slot->host->pdata->exit) | |
2034 | slot->host->pdata->exit(id); | |
2035 | ||
2036 | /* Debugfs stuff is cleaned up by mmc core */ | |
2037 | mmc_remove_host(slot->mmc); | |
2038 | slot->host->slot[id] = NULL; | |
2039 | mmc_free_host(slot->mmc); | |
2040 | } | |
2041 | ||
2042 | static void dw_mci_init_dma(struct dw_mci *host) | |
2043 | { | |
2044 | /* Alloc memory for sg translation */ | |
780f22af | 2045 | host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, |
f95f3850 WN |
2046 | &host->sg_dma, GFP_KERNEL); |
2047 | if (!host->sg_cpu) { | |
4a90920c | 2048 | dev_err(host->dev, "%s: could not alloc DMA memory\n", |
f95f3850 WN |
2049 | __func__); |
2050 | goto no_dma; | |
2051 | } | |
2052 | ||
2053 | /* Determine which DMA interface to use */ | |
2054 | #ifdef CONFIG_MMC_DW_IDMAC | |
2055 | host->dma_ops = &dw_mci_idmac_ops; | |
00956ea3 | 2056 | dev_info(host->dev, "Using internal DMA controller.\n"); |
f95f3850 WN |
2057 | #endif |
2058 | ||
2059 | if (!host->dma_ops) | |
2060 | goto no_dma; | |
2061 | ||
e1631f98 JC |
2062 | if (host->dma_ops->init && host->dma_ops->start && |
2063 | host->dma_ops->stop && host->dma_ops->cleanup) { | |
f95f3850 | 2064 | if (host->dma_ops->init(host)) { |
4a90920c | 2065 | dev_err(host->dev, "%s: Unable to initialize " |
f95f3850 WN |
2066 | "DMA Controller.\n", __func__); |
2067 | goto no_dma; | |
2068 | } | |
2069 | } else { | |
4a90920c | 2070 | dev_err(host->dev, "DMA initialization not found.\n"); |
f95f3850 WN |
2071 | goto no_dma; |
2072 | } | |
2073 | ||
2074 | host->use_dma = 1; | |
2075 | return; | |
2076 | ||
2077 | no_dma: | |
4a90920c | 2078 | dev_info(host->dev, "Using PIO mode.\n"); |
f95f3850 WN |
2079 | host->use_dma = 0; |
2080 | return; | |
2081 | } | |
2082 | ||
2083 | static bool mci_wait_reset(struct device *dev, struct dw_mci *host) | |
2084 | { | |
2085 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
2086 | unsigned int ctrl; | |
2087 | ||
2088 | mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | | |
2089 | SDMMC_CTRL_DMA_RESET)); | |
2090 | ||
2091 | /* wait till resets clear */ | |
2092 | do { | |
2093 | ctrl = mci_readl(host, CTRL); | |
2094 | if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | | |
2095 | SDMMC_CTRL_DMA_RESET))) | |
2096 | return true; | |
2097 | } while (time_before(jiffies, timeout)); | |
2098 | ||
2099 | dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl); | |
2100 | ||
2101 | return false; | |
2102 | } | |
2103 | ||
c91eab4b TA |
2104 | #ifdef CONFIG_OF |
2105 | static struct dw_mci_of_quirks { | |
2106 | char *quirk; | |
2107 | int id; | |
2108 | } of_quirks[] = { | |
2109 | { | |
2110 | .quirk = "supports-highspeed", | |
2111 | .id = DW_MCI_QUIRK_HIGHSPEED, | |
2112 | }, { | |
2113 | .quirk = "broken-cd", | |
2114 | .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, | |
2115 | }, | |
2116 | }; | |
2117 | ||
2118 | static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) | |
2119 | { | |
2120 | struct dw_mci_board *pdata; | |
2121 | struct device *dev = host->dev; | |
2122 | struct device_node *np = dev->of_node; | |
e95baf13 | 2123 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
800d78bf | 2124 | int idx, ret; |
3c6d89ea | 2125 | u32 clock_frequency; |
c91eab4b TA |
2126 | |
2127 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
2128 | if (!pdata) { | |
2129 | dev_err(dev, "could not allocate memory for pdata\n"); | |
2130 | return ERR_PTR(-ENOMEM); | |
2131 | } | |
2132 | ||
2133 | /* find out number of slots supported */ | |
2134 | if (of_property_read_u32(dev->of_node, "num-slots", | |
2135 | &pdata->num_slots)) { | |
2136 | dev_info(dev, "num-slots property not found, " | |
2137 | "assuming 1 slot is available\n"); | |
2138 | pdata->num_slots = 1; | |
2139 | } | |
2140 | ||
2141 | /* get quirks */ | |
2142 | for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) | |
2143 | if (of_get_property(np, of_quirks[idx].quirk, NULL)) | |
2144 | pdata->quirks |= of_quirks[idx].id; | |
2145 | ||
2146 | if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) | |
2147 | dev_info(dev, "fifo-depth property not found, using " | |
2148 | "value of FIFOTH register as default\n"); | |
2149 | ||
2150 | of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); | |
2151 | ||
3c6d89ea DA |
2152 | if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) |
2153 | pdata->bus_hz = clock_frequency; | |
2154 | ||
cb27a843 JH |
2155 | if (drv_data && drv_data->parse_dt) { |
2156 | ret = drv_data->parse_dt(host); | |
800d78bf TA |
2157 | if (ret) |
2158 | return ERR_PTR(ret); | |
2159 | } | |
2160 | ||
ab269128 AK |
2161 | if (of_find_property(np, "keep-power-in-suspend", NULL)) |
2162 | pdata->pm_caps |= MMC_PM_KEEP_POWER; | |
2163 | ||
2164 | if (of_find_property(np, "enable-sdio-wakeup", NULL)) | |
2165 | pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; | |
2166 | ||
c91eab4b TA |
2167 | return pdata; |
2168 | } | |
2169 | ||
2170 | #else /* CONFIG_OF */ | |
2171 | static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) | |
2172 | { | |
2173 | return ERR_PTR(-EINVAL); | |
2174 | } | |
2175 | #endif /* CONFIG_OF */ | |
2176 | ||
62ca8034 | 2177 | int dw_mci_probe(struct dw_mci *host) |
f95f3850 | 2178 | { |
e95baf13 | 2179 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
62ca8034 | 2180 | int width, i, ret = 0; |
f95f3850 | 2181 | u32 fifo_size; |
1c2215b7 | 2182 | int init_slots = 0; |
f95f3850 | 2183 | |
c91eab4b TA |
2184 | if (!host->pdata) { |
2185 | host->pdata = dw_mci_parse_dt(host); | |
2186 | if (IS_ERR(host->pdata)) { | |
2187 | dev_err(host->dev, "platform data not available\n"); | |
2188 | return -EINVAL; | |
2189 | } | |
f95f3850 WN |
2190 | } |
2191 | ||
62ca8034 | 2192 | if (!host->pdata->select_slot && host->pdata->num_slots > 1) { |
4a90920c | 2193 | dev_err(host->dev, |
f95f3850 | 2194 | "Platform data must supply select_slot function\n"); |
62ca8034 | 2195 | return -ENODEV; |
f95f3850 WN |
2196 | } |
2197 | ||
780f22af | 2198 | host->biu_clk = devm_clk_get(host->dev, "biu"); |
f90a0612 TA |
2199 | if (IS_ERR(host->biu_clk)) { |
2200 | dev_dbg(host->dev, "biu clock not available\n"); | |
2201 | } else { | |
2202 | ret = clk_prepare_enable(host->biu_clk); | |
2203 | if (ret) { | |
2204 | dev_err(host->dev, "failed to enable biu clock\n"); | |
f90a0612 TA |
2205 | return ret; |
2206 | } | |
2207 | } | |
2208 | ||
780f22af | 2209 | host->ciu_clk = devm_clk_get(host->dev, "ciu"); |
f90a0612 TA |
2210 | if (IS_ERR(host->ciu_clk)) { |
2211 | dev_dbg(host->dev, "ciu clock not available\n"); | |
3c6d89ea | 2212 | host->bus_hz = host->pdata->bus_hz; |
f90a0612 TA |
2213 | } else { |
2214 | ret = clk_prepare_enable(host->ciu_clk); | |
2215 | if (ret) { | |
2216 | dev_err(host->dev, "failed to enable ciu clock\n"); | |
f90a0612 TA |
2217 | goto err_clk_biu; |
2218 | } | |
f90a0612 | 2219 | |
3c6d89ea DA |
2220 | if (host->pdata->bus_hz) { |
2221 | ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); | |
2222 | if (ret) | |
2223 | dev_warn(host->dev, | |
2224 | "Unable to set bus rate to %ul\n", | |
2225 | host->pdata->bus_hz); | |
2226 | } | |
f90a0612 | 2227 | host->bus_hz = clk_get_rate(host->ciu_clk); |
3c6d89ea | 2228 | } |
f90a0612 | 2229 | |
cb27a843 JH |
2230 | if (drv_data && drv_data->setup_clock) { |
2231 | ret = drv_data->setup_clock(host); | |
800d78bf TA |
2232 | if (ret) { |
2233 | dev_err(host->dev, | |
2234 | "implementation specific clock setup failed\n"); | |
2235 | goto err_clk_ciu; | |
2236 | } | |
2237 | } | |
2238 | ||
a55d6ff0 | 2239 | host->vmmc = devm_regulator_get_optional(host->dev, "vmmc"); |
870556a3 DA |
2240 | if (IS_ERR(host->vmmc)) { |
2241 | ret = PTR_ERR(host->vmmc); | |
2242 | if (ret == -EPROBE_DEFER) | |
2243 | goto err_clk_ciu; | |
2244 | ||
2245 | dev_info(host->dev, "no vmmc regulator found: %d\n", ret); | |
2246 | host->vmmc = NULL; | |
2247 | } else { | |
2248 | ret = regulator_enable(host->vmmc); | |
2249 | if (ret) { | |
2250 | if (ret != -EPROBE_DEFER) | |
2251 | dev_err(host->dev, | |
2252 | "regulator_enable fail: %d\n", ret); | |
2253 | goto err_clk_ciu; | |
2254 | } | |
2255 | } | |
2256 | ||
f90a0612 | 2257 | if (!host->bus_hz) { |
4a90920c | 2258 | dev_err(host->dev, |
f95f3850 | 2259 | "Platform data must supply bus speed\n"); |
f90a0612 | 2260 | ret = -ENODEV; |
870556a3 | 2261 | goto err_regulator; |
f95f3850 WN |
2262 | } |
2263 | ||
62ca8034 | 2264 | host->quirks = host->pdata->quirks; |
f95f3850 WN |
2265 | |
2266 | spin_lock_init(&host->lock); | |
2267 | INIT_LIST_HEAD(&host->queue); | |
2268 | ||
f95f3850 WN |
2269 | /* |
2270 | * Get the host data width - this assumes that HCON has been set with | |
2271 | * the correct values. | |
2272 | */ | |
2273 | i = (mci_readl(host, HCON) >> 7) & 0x7; | |
2274 | if (!i) { | |
2275 | host->push_data = dw_mci_push_data16; | |
2276 | host->pull_data = dw_mci_pull_data16; | |
2277 | width = 16; | |
2278 | host->data_shift = 1; | |
2279 | } else if (i == 2) { | |
2280 | host->push_data = dw_mci_push_data64; | |
2281 | host->pull_data = dw_mci_pull_data64; | |
2282 | width = 64; | |
2283 | host->data_shift = 3; | |
2284 | } else { | |
2285 | /* Check for a reserved value, and warn if it is */ | |
2286 | WARN((i != 1), | |
2287 | "HCON reports a reserved host data width!\n" | |
2288 | "Defaulting to 32-bit access.\n"); | |
2289 | host->push_data = dw_mci_push_data32; | |
2290 | host->pull_data = dw_mci_pull_data32; | |
2291 | width = 32; | |
2292 | host->data_shift = 2; | |
2293 | } | |
2294 | ||
2295 | /* Reset all blocks */ | |
4a90920c | 2296 | if (!mci_wait_reset(host->dev, host)) |
141a712a SJ |
2297 | return -ENODEV; |
2298 | ||
2299 | host->dma_ops = host->pdata->dma_ops; | |
2300 | dw_mci_init_dma(host); | |
f95f3850 WN |
2301 | |
2302 | /* Clear the interrupts for the host controller */ | |
2303 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2304 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
2305 | ||
2306 | /* Put in max timeout */ | |
2307 | mci_writel(host, TMOUT, 0xFFFFFFFF); | |
2308 | ||
2309 | /* | |
2310 | * FIFO threshold settings RxMark = fifo_size / 2 - 1, | |
2311 | * Tx Mark = fifo_size / 2 DMA Size = 8 | |
2312 | */ | |
b86d8253 JH |
2313 | if (!host->pdata->fifo_depth) { |
2314 | /* | |
2315 | * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may | |
2316 | * have been overwritten by the bootloader, just like we're | |
2317 | * about to do, so if you know the value for your hardware, you | |
2318 | * should put it in the platform data. | |
2319 | */ | |
2320 | fifo_size = mci_readl(host, FIFOTH); | |
8234e869 | 2321 | fifo_size = 1 + ((fifo_size >> 16) & 0xfff); |
b86d8253 JH |
2322 | } else { |
2323 | fifo_size = host->pdata->fifo_depth; | |
2324 | } | |
2325 | host->fifo_depth = fifo_size; | |
e61cf118 JC |
2326 | host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | |
2327 | ((fifo_size/2) << 0)); | |
2328 | mci_writel(host, FIFOTH, host->fifoth_val); | |
f95f3850 WN |
2329 | |
2330 | /* disable clock to CIU */ | |
2331 | mci_writel(host, CLKENA, 0); | |
2332 | mci_writel(host, CLKSRC, 0); | |
2333 | ||
63008768 JH |
2334 | /* |
2335 | * In 2.40a spec, Data offset is changed. | |
2336 | * Need to check the version-id and set data-offset for DATA register. | |
2337 | */ | |
2338 | host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); | |
2339 | dev_info(host->dev, "Version ID is %04x\n", host->verid); | |
2340 | ||
2341 | if (host->verid < DW_MMC_240A) | |
2342 | host->data_offset = DATA_OFFSET; | |
2343 | else | |
2344 | host->data_offset = DATA_240A_OFFSET; | |
2345 | ||
f95f3850 | 2346 | tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); |
95dcc2cb | 2347 | host->card_workqueue = alloc_workqueue("dw-mci-card", |
1791b13e | 2348 | WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1); |
ef7aef9a WY |
2349 | if (!host->card_workqueue) { |
2350 | ret = -ENOMEM; | |
1791b13e | 2351 | goto err_dmaunmap; |
ef7aef9a | 2352 | } |
1791b13e | 2353 | INIT_WORK(&host->card_work, dw_mci_work_routine_card); |
780f22af SJ |
2354 | ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, |
2355 | host->irq_flags, "dw-mci", host); | |
f95f3850 | 2356 | if (ret) |
1791b13e | 2357 | goto err_workqueue; |
f95f3850 | 2358 | |
f95f3850 WN |
2359 | if (host->pdata->num_slots) |
2360 | host->num_slots = host->pdata->num_slots; | |
2361 | else | |
2362 | host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; | |
2363 | ||
2da1d7f2 YC |
2364 | /* |
2365 | * Enable interrupts for command done, data over, data empty, card det, | |
2366 | * receive ready and error such as transmit, receive timeout, crc error | |
2367 | */ | |
2368 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2369 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
2370 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
2371 | DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); | |
2372 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ | |
2373 | ||
2374 | dev_info(host->dev, "DW MMC controller at irq %d, " | |
2375 | "%d bit host data width, " | |
2376 | "%u deep fifo\n", | |
2377 | host->irq, width, fifo_size); | |
2378 | ||
f95f3850 WN |
2379 | /* We need at least one slot to succeed */ |
2380 | for (i = 0; i < host->num_slots; i++) { | |
2381 | ret = dw_mci_init_slot(host, i); | |
1c2215b7 TA |
2382 | if (ret) |
2383 | dev_dbg(host->dev, "slot %d init failed\n", i); | |
2384 | else | |
2385 | init_slots++; | |
2386 | } | |
2387 | ||
2388 | if (init_slots) { | |
2389 | dev_info(host->dev, "%d slots initialized\n", init_slots); | |
2390 | } else { | |
2391 | dev_dbg(host->dev, "attempted to initialize %d slots, " | |
2392 | "but failed on all\n", host->num_slots); | |
780f22af | 2393 | goto err_workqueue; |
f95f3850 WN |
2394 | } |
2395 | ||
f95f3850 | 2396 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) |
4a90920c | 2397 | dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); |
f95f3850 WN |
2398 | |
2399 | return 0; | |
2400 | ||
1791b13e | 2401 | err_workqueue: |
95dcc2cb | 2402 | destroy_workqueue(host->card_workqueue); |
1791b13e | 2403 | |
f95f3850 WN |
2404 | err_dmaunmap: |
2405 | if (host->use_dma && host->dma_ops->exit) | |
2406 | host->dma_ops->exit(host); | |
f95f3850 | 2407 | |
870556a3 | 2408 | err_regulator: |
780f22af | 2409 | if (host->vmmc) |
c07946a3 | 2410 | regulator_disable(host->vmmc); |
f90a0612 TA |
2411 | |
2412 | err_clk_ciu: | |
780f22af | 2413 | if (!IS_ERR(host->ciu_clk)) |
f90a0612 | 2414 | clk_disable_unprepare(host->ciu_clk); |
780f22af | 2415 | |
f90a0612 | 2416 | err_clk_biu: |
780f22af | 2417 | if (!IS_ERR(host->biu_clk)) |
f90a0612 | 2418 | clk_disable_unprepare(host->biu_clk); |
780f22af | 2419 | |
f95f3850 WN |
2420 | return ret; |
2421 | } | |
62ca8034 | 2422 | EXPORT_SYMBOL(dw_mci_probe); |
f95f3850 | 2423 | |
62ca8034 | 2424 | void dw_mci_remove(struct dw_mci *host) |
f95f3850 | 2425 | { |
f95f3850 WN |
2426 | int i; |
2427 | ||
2428 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2429 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
2430 | ||
f95f3850 | 2431 | for (i = 0; i < host->num_slots; i++) { |
4a90920c | 2432 | dev_dbg(host->dev, "remove slot %d\n", i); |
f95f3850 WN |
2433 | if (host->slot[i]) |
2434 | dw_mci_cleanup_slot(host->slot[i], i); | |
2435 | } | |
2436 | ||
2437 | /* disable clock to CIU */ | |
2438 | mci_writel(host, CLKENA, 0); | |
2439 | mci_writel(host, CLKSRC, 0); | |
2440 | ||
95dcc2cb | 2441 | destroy_workqueue(host->card_workqueue); |
f95f3850 WN |
2442 | |
2443 | if (host->use_dma && host->dma_ops->exit) | |
2444 | host->dma_ops->exit(host); | |
2445 | ||
780f22af | 2446 | if (host->vmmc) |
c07946a3 | 2447 | regulator_disable(host->vmmc); |
c07946a3 | 2448 | |
f90a0612 TA |
2449 | if (!IS_ERR(host->ciu_clk)) |
2450 | clk_disable_unprepare(host->ciu_clk); | |
780f22af | 2451 | |
f90a0612 TA |
2452 | if (!IS_ERR(host->biu_clk)) |
2453 | clk_disable_unprepare(host->biu_clk); | |
f95f3850 | 2454 | } |
62ca8034 SH |
2455 | EXPORT_SYMBOL(dw_mci_remove); |
2456 | ||
2457 | ||
f95f3850 | 2458 | |
6fe8890d | 2459 | #ifdef CONFIG_PM_SLEEP |
f95f3850 WN |
2460 | /* |
2461 | * TODO: we should probably disable the clock to the card in the suspend path. | |
2462 | */ | |
62ca8034 | 2463 | int dw_mci_suspend(struct dw_mci *host) |
f95f3850 | 2464 | { |
62ca8034 | 2465 | int i, ret = 0; |
f95f3850 WN |
2466 | |
2467 | for (i = 0; i < host->num_slots; i++) { | |
2468 | struct dw_mci_slot *slot = host->slot[i]; | |
2469 | if (!slot) | |
2470 | continue; | |
2471 | ret = mmc_suspend_host(slot->mmc); | |
2472 | if (ret < 0) { | |
2473 | while (--i >= 0) { | |
2474 | slot = host->slot[i]; | |
2475 | if (slot) | |
2476 | mmc_resume_host(host->slot[i]->mmc); | |
2477 | } | |
2478 | return ret; | |
2479 | } | |
2480 | } | |
2481 | ||
c07946a3 JC |
2482 | if (host->vmmc) |
2483 | regulator_disable(host->vmmc); | |
2484 | ||
f95f3850 WN |
2485 | return 0; |
2486 | } | |
62ca8034 | 2487 | EXPORT_SYMBOL(dw_mci_suspend); |
f95f3850 | 2488 | |
62ca8034 | 2489 | int dw_mci_resume(struct dw_mci *host) |
f95f3850 WN |
2490 | { |
2491 | int i, ret; | |
f95f3850 | 2492 | |
f2f942ce SK |
2493 | if (host->vmmc) { |
2494 | ret = regulator_enable(host->vmmc); | |
2495 | if (ret) { | |
2496 | dev_err(host->dev, | |
2497 | "failed to enable regulator: %d\n", ret); | |
2498 | return ret; | |
2499 | } | |
2500 | } | |
1d6c4e0a | 2501 | |
4a90920c | 2502 | if (!mci_wait_reset(host->dev, host)) { |
e61cf118 JC |
2503 | ret = -ENODEV; |
2504 | return ret; | |
2505 | } | |
2506 | ||
3bfe619d | 2507 | if (host->use_dma && host->dma_ops->init) |
141a712a SJ |
2508 | host->dma_ops->init(host); |
2509 | ||
e61cf118 JC |
2510 | /* Restore the old value at FIFOTH register */ |
2511 | mci_writel(host, FIFOTH, host->fifoth_val); | |
2512 | ||
2eb2944f DA |
2513 | /* Put in max timeout */ |
2514 | mci_writel(host, TMOUT, 0xFFFFFFFF); | |
2515 | ||
e61cf118 JC |
2516 | mci_writel(host, RINTSTS, 0xFFFFFFFF); |
2517 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
2518 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
2519 | DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); | |
2520 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); | |
2521 | ||
f95f3850 WN |
2522 | for (i = 0; i < host->num_slots; i++) { |
2523 | struct dw_mci_slot *slot = host->slot[i]; | |
2524 | if (!slot) | |
2525 | continue; | |
ab269128 AK |
2526 | if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { |
2527 | dw_mci_set_ios(slot->mmc, &slot->mmc->ios); | |
2528 | dw_mci_setup_bus(slot, true); | |
2529 | } | |
2530 | ||
f95f3850 WN |
2531 | ret = mmc_resume_host(host->slot[i]->mmc); |
2532 | if (ret < 0) | |
2533 | return ret; | |
2534 | } | |
f95f3850 WN |
2535 | return 0; |
2536 | } | |
62ca8034 | 2537 | EXPORT_SYMBOL(dw_mci_resume); |
6fe8890d JC |
2538 | #endif /* CONFIG_PM_SLEEP */ |
2539 | ||
f95f3850 WN |
2540 | static int __init dw_mci_init(void) |
2541 | { | |
8e1c4e4d | 2542 | pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); |
62ca8034 | 2543 | return 0; |
f95f3850 WN |
2544 | } |
2545 | ||
2546 | static void __exit dw_mci_exit(void) | |
2547 | { | |
f95f3850 WN |
2548 | } |
2549 | ||
2550 | module_init(dw_mci_init); | |
2551 | module_exit(dw_mci_exit); | |
2552 | ||
2553 | MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); | |
2554 | MODULE_AUTHOR("NXP Semiconductor VietNam"); | |
2555 | MODULE_AUTHOR("Imagination Technologies Ltd"); | |
2556 | MODULE_LICENSE("GPL v2"); |