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mmc: dw_mmc: empty FIFO after data transfer over interrupt in pio mode
[deliverable/linux.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/dw_mmc.h>
33#include <linux/bitops.h>
c07946a3 34#include <linux/regulator/consumer.h>
1791b13e 35#include <linux/workqueue.h>
c91eab4b 36#include <linux/of.h>
55a6ceb2 37#include <linux/of_gpio.h>
f95f3850
WN		 38
39#include "dw_mmc.h"
40
41/* Common flag combinations */
42#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
43 SDMMC_INT_HTO | SDMMC_INT_SBE | \
44 SDMMC_INT_EBE)
45#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
46 SDMMC_INT_RESP_ERR)
47#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
48 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
49#define DW_MCI_SEND_STATUS 1
50#define DW_MCI_RECV_STATUS 2
51#define DW_MCI_DMA_THRESHOLD 16
52
53#ifdef CONFIG_MMC_DW_IDMAC
54struct idmac_desc {
55 u32 des0; /* Control Descriptor */
56#define IDMAC_DES0_DIC BIT(1)
57#define IDMAC_DES0_LD BIT(2)
58#define IDMAC_DES0_FD BIT(3)
59#define IDMAC_DES0_CH BIT(4)
60#define IDMAC_DES0_ER BIT(5)
61#define IDMAC_DES0_CES BIT(30)
62#define IDMAC_DES0_OWN BIT(31)
63
64 u32 des1; /* Buffer sizes */
65#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 66 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 67
68 u32 des2; /* buffer 1 physical address */
69
70 u32 des3; /* buffer 2 physical address */
71};
72#endif /* CONFIG_MMC_DW_IDMAC */
73
74/**
75 * struct dw_mci_slot - MMC slot state
76 * @mmc: The mmc_host representing this slot.
77 * @host: The MMC controller this slot is using.
a70aaa64 78 * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
55a6ceb2 79 * @wp_gpio: If gpio_is_valid() we'll use this to read write protect.
f95f3850
WN		 80 * @ctype: Card type for this slot.
81 * @mrq: mmc_request currently being processed or waiting to be
82 * processed, or NULL when the slot is idle.
83 * @queue_node: List node for placing this node in the @queue list of
84 * &struct dw_mci.
85 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
86 * @flags: Random state bits associated with the slot.
87 * @id: Number of this slot.
88 * @last_detect_state: Most recently observed card detect state.
89 */
90struct dw_mci_slot {
91 struct mmc_host *mmc;
92 struct dw_mci *host;
93
a70aaa64 94 int quirks;
55a6ceb2 95 int wp_gpio;
a70aaa64 96
f95f3850
WN		 97 u32 ctype;
98
99 struct mmc_request *mrq;
100 struct list_head queue_node;
101
102 unsigned int clock;
103 unsigned long flags;
104#define DW_MMC_CARD_PRESENT 0
105#define DW_MMC_CARD_NEED_INIT 1
106 int id;
107 int last_detect_state;
108};
109
110#if defined(CONFIG_DEBUG_FS)
111static int dw_mci_req_show(struct seq_file *s, void *v)
112{
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149}
150
151static int dw_mci_req_open(struct inode *inode, struct file *file)
152{
153 return single_open(file, dw_mci_req_show, inode->i_private);
154}
155
156static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162};
163
164static int dw_mci_regs_show(struct seq_file *s, void *v)
165{
166 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
167 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
168 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
169 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
170 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
171 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
172
173 return 0;
174}
175
176static int dw_mci_regs_open(struct inode *inode, struct file *file)
177{
178 return single_open(file, dw_mci_regs_show, inode->i_private);
179}
180
181static const struct file_operations dw_mci_regs_fops = {
182 .owner = THIS_MODULE,
183 .open = dw_mci_regs_open,
184 .read = seq_read,
185 .llseek = seq_lseek,
186 .release = single_release,
187};
188
189static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
190{
191 struct mmc_host *mmc = slot->mmc;
192 struct dw_mci *host = slot->host;
193 struct dentry *root;
194 struct dentry *node;
195
196 root = mmc->debugfs_root;
197 if (!root)
198 return;
199
200 node = debugfs_create_file("regs", S_IRUSR, root, host,
201 &dw_mci_regs_fops);
202 if (!node)
203 goto err;
204
205 node = debugfs_create_file("req", S_IRUSR, root, slot,
206 &dw_mci_req_fops);
207 if (!node)
208 goto err;
209
210 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
211 if (!node)
212 goto err;
213
214 node = debugfs_create_x32("pending_events", S_IRUSR, root,
215 (u32 *)&host->pending_events);
216 if (!node)
217 goto err;
218
219 node = debugfs_create_x32("completed_events", S_IRUSR, root,
220 (u32 *)&host->completed_events);
221 if (!node)
222 goto err;
223
224 return;
225
226err:
227 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
228}
229#endif /* defined(CONFIG_DEBUG_FS) */
230
231static void dw_mci_set_timeout(struct dw_mci *host)
232{
233 /* timeout (maximum) */
234 mci_writel(host, TMOUT, 0xffffffff);
235}
236
237static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
238{
239 struct mmc_data *data;
800d78bf 240 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 241 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
f95f3850
WN		 242 u32 cmdr;
243 cmd->error = -EINPROGRESS;
244
245 cmdr = cmd->opcode;
246
247 if (cmdr == MMC_STOP_TRANSMISSION)
248 cmdr |= SDMMC_CMD_STOP;
249 else
250 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
251
252 if (cmd->flags & MMC_RSP_PRESENT) {
253 /* We expect a response, so set this bit */
254 cmdr |= SDMMC_CMD_RESP_EXP;
255 if (cmd->flags & MMC_RSP_136)
256 cmdr |= SDMMC_CMD_RESP_LONG;
257 }
258
259 if (cmd->flags & MMC_RSP_CRC)
260 cmdr |= SDMMC_CMD_RESP_CRC;
261
262 data = cmd->data;
263 if (data) {
264 cmdr |= SDMMC_CMD_DAT_EXP;
265 if (data->flags & MMC_DATA_STREAM)
266 cmdr |= SDMMC_CMD_STRM_MODE;
267 if (data->flags & MMC_DATA_WRITE)
268 cmdr |= SDMMC_CMD_DAT_WR;
269 }
270
cb27a843
JH		 271 if (drv_data && drv_data->prepare_command)
272 drv_data->prepare_command(slot->host, &cmdr);
800d78bf 273
f95f3850
WN		 274 return cmdr;
275}
276
277static void dw_mci_start_command(struct dw_mci *host,
278 struct mmc_command *cmd, u32 cmd_flags)
279{
280 host->cmd = cmd;
4a90920c 281 dev_vdbg(host->dev,
f95f3850
WN		 282 "start command: ARGR=0x%08x CMDR=0x%08x\n",
283 cmd->arg, cmd_flags);
284
285 mci_writel(host, CMDARG, cmd->arg);
286 wmb();
287
288 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
289}
290
291static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
292{
293 dw_mci_start_command(host, data->stop, host->stop_cmdr);
294}
295
296/* DMA interface functions */
297static void dw_mci_stop_dma(struct dw_mci *host)
298{
03e8cb53 299 if (host->using_dma) {
f95f3850
WN		 300 host->dma_ops->stop(host);
301 host->dma_ops->cleanup(host);
302 } else {
303 /* Data transfer was stopped by the interrupt handler */
304 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
305 }
306}
307
9aa51408
SJ		 308static int dw_mci_get_dma_dir(struct mmc_data *data)
309{
310 if (data->flags & MMC_DATA_WRITE)
311 return DMA_TO_DEVICE;
312 else
313 return DMA_FROM_DEVICE;
314}
315
9beee912 316#ifdef CONFIG_MMC_DW_IDMAC
f95f3850
WN		 317static void dw_mci_dma_cleanup(struct dw_mci *host)
318{
319 struct mmc_data *data = host->data;
320
321 if (data)
9aa51408 322 if (!data->host_cookie)
4a90920c 323 dma_unmap_sg(host->dev,
9aa51408
SJ		 324 data->sg,
325 data->sg_len,
326 dw_mci_get_dma_dir(data));
f95f3850
WN		 327}
328
329static void dw_mci_idmac_stop_dma(struct dw_mci *host)
330{
331 u32 temp;
332
333 /* Disable and reset the IDMAC interface */
334 temp = mci_readl(host, CTRL);
335 temp &= ~SDMMC_CTRL_USE_IDMAC;
336 temp |= SDMMC_CTRL_DMA_RESET;
337 mci_writel(host, CTRL, temp);
338
339 /* Stop the IDMAC running */
340 temp = mci_readl(host, BMOD);
a5289a43 341 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 342 mci_writel(host, BMOD, temp);
343}
344
345static void dw_mci_idmac_complete_dma(struct dw_mci *host)
346{
347 struct mmc_data *data = host->data;
348
4a90920c 349 dev_vdbg(host->dev, "DMA complete\n");
f95f3850
WN		 350
351 host->dma_ops->cleanup(host);
352
353 /*
354 * If the card was removed, data will be NULL. No point in trying to
355 * send the stop command or waiting for NBUSY in this case.
356 */
357 if (data) {
358 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
359 tasklet_schedule(&host->tasklet);
360 }
361}
362
363static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
364 unsigned int sg_len)
365{
366 int i;
367 struct idmac_desc *desc = host->sg_cpu;
368
369 for (i = 0; i < sg_len; i++, desc++) {
370 unsigned int length = sg_dma_len(&data->sg[i]);
371 u32 mem_addr = sg_dma_address(&data->sg[i]);
372
373 /* Set the OWN bit and disable interrupts for this descriptor */
374 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
375
376 /* Buffer length */
377 IDMAC_SET_BUFFER1_SIZE(desc, length);
378
379 /* Physical address to DMA to/from */
380 desc->des2 = mem_addr;
381 }
382
383 /* Set first descriptor */
384 desc = host->sg_cpu;
385 desc->des0 |= IDMAC_DES0_FD;
386
387 /* Set last descriptor */
388 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
389 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
390 desc->des0 |= IDMAC_DES0_LD;
391
392 wmb();
393}
394
395static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
396{
397 u32 temp;
398
399 dw_mci_translate_sglist(host, host->data, sg_len);
400
401 /* Select IDMAC interface */
402 temp = mci_readl(host, CTRL);
403 temp |= SDMMC_CTRL_USE_IDMAC;
404 mci_writel(host, CTRL, temp);
405
406 wmb();
407
408 /* Enable the IDMAC */
409 temp = mci_readl(host, BMOD);
a5289a43 410 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 411 mci_writel(host, BMOD, temp);
412
413 /* Start it running */
414 mci_writel(host, PLDMND, 1);
415}
416
417static int dw_mci_idmac_init(struct dw_mci *host)
418{
419 struct idmac_desc *p;
897b69e7 420 int i;
f95f3850
WN		 421
422 /* Number of descriptors in the ring buffer */
423 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
424
425 /* Forward link the descriptor list */
426 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
427 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
428
429 /* Set the last descriptor as the end-of-ring descriptor */
430 p->des3 = host->sg_dma;
431 p->des0 = IDMAC_DES0_ER;
432
141a712a
SJ		 433 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
434
f95f3850
WN		 435 /* Mask out interrupts - get Tx & Rx complete only */
436 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
437 SDMMC_IDMAC_INT_TI);
438
439 /* Set the descriptor base address */
440 mci_writel(host, DBADDR, host->sg_dma);
441 return 0;
442}
443
8e2b36ea 444static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 445 .init = dw_mci_idmac_init,
446 .start = dw_mci_idmac_start_dma,
447 .stop = dw_mci_idmac_stop_dma,
448 .complete = dw_mci_idmac_complete_dma,
449 .cleanup = dw_mci_dma_cleanup,
450};
451#endif /* CONFIG_MMC_DW_IDMAC */
452
9aa51408
SJ		 453static int dw_mci_pre_dma_transfer(struct dw_mci *host,
454 struct mmc_data *data,
455 bool next)
f95f3850
WN		 456{
457 struct scatterlist *sg;
9aa51408 458 unsigned int i, sg_len;
03e8cb53 459
9aa51408
SJ		 460 if (!next && data->host_cookie)
461 return data->host_cookie;
f95f3850
WN		 462
463 /*
464 * We don't do DMA on "complex" transfers, i.e. with
465 * non-word-aligned buffers or lengths. Also, we don't bother
466 * with all the DMA setup overhead for short transfers.
467 */
468 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
469 return -EINVAL;
9aa51408 470
f95f3850
WN		 471 if (data->blksz & 3)
472 return -EINVAL;
473
474 for_each_sg(data->sg, sg, data->sg_len, i) {
475 if (sg->offset & 3 || sg->length & 3)
476 return -EINVAL;
477 }
478
4a90920c 479 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 480 data->sg,
481 data->sg_len,
482 dw_mci_get_dma_dir(data));
483 if (sg_len == 0)
484 return -EINVAL;
03e8cb53 485
9aa51408
SJ		 486 if (next)
487 data->host_cookie = sg_len;
f95f3850 488
9aa51408
SJ		 489 return sg_len;
490}
491
9aa51408
SJ		 492static void dw_mci_pre_req(struct mmc_host *mmc,
493 struct mmc_request *mrq,
494 bool is_first_req)
495{
496 struct dw_mci_slot *slot = mmc_priv(mmc);
497 struct mmc_data *data = mrq->data;
498
499 if (!slot->host->use_dma || !data)
500 return;
501
502 if (data->host_cookie) {
503 data->host_cookie = 0;
504 return;
505 }
506
507 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
508 data->host_cookie = 0;
509}
510
511static void dw_mci_post_req(struct mmc_host *mmc,
512 struct mmc_request *mrq,
513 int err)
514{
515 struct dw_mci_slot *slot = mmc_priv(mmc);
516 struct mmc_data *data = mrq->data;
517
518 if (!slot->host->use_dma || !data)
519 return;
520
521 if (data->host_cookie)
4a90920c 522 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 523 data->sg,
524 data->sg_len,
525 dw_mci_get_dma_dir(data));
526 data->host_cookie = 0;
527}
528
529static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
530{
531 int sg_len;
532 u32 temp;
533
534 host->using_dma = 0;
535
536 /* If we don't have a channel, we can't do DMA */
537 if (!host->use_dma)
538 return -ENODEV;
539
540 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 541 if (sg_len < 0) {
542 host->dma_ops->stop(host);
9aa51408 543 return sg_len;
a99aa9b9 544 }
9aa51408
SJ		 545
546 host->using_dma = 1;
f95f3850 547
4a90920c 548 dev_vdbg(host->dev,
f95f3850
WN		 549 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
550 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
551 sg_len);
552
553 /* Enable the DMA interface */
554 temp = mci_readl(host, CTRL);
555 temp |= SDMMC_CTRL_DMA_ENABLE;
556 mci_writel(host, CTRL, temp);
557
558 /* Disable RX/TX IRQs, let DMA handle it */
559 temp = mci_readl(host, INTMASK);
560 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
561 mci_writel(host, INTMASK, temp);
562
563 host->dma_ops->start(host, sg_len);
564
565 return 0;
566}
567
568static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
569{
570 u32 temp;
571
572 data->error = -EINPROGRESS;
573
574 WARN_ON(host->data);
575 host->sg = NULL;
576 host->data = data;
577
55c5efbc
JH		 578 if (data->flags & MMC_DATA_READ)
579 host->dir_status = DW_MCI_RECV_STATUS;
580 else
581 host->dir_status = DW_MCI_SEND_STATUS;
582
f95f3850 583 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 584 int flags = SG_MITER_ATOMIC;
585 if (host->data->flags & MMC_DATA_READ)
586 flags |= SG_MITER_TO_SG;
587 else
588 flags |= SG_MITER_FROM_SG;
589
590 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 591 host->sg = data->sg;
34b664a2
JH		 592 host->part_buf_start = 0;
593 host->part_buf_count = 0;
f95f3850 594
b40af3aa 595 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 596 temp = mci_readl(host, INTMASK);
597 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
598 mci_writel(host, INTMASK, temp);
599
600 temp = mci_readl(host, CTRL);
601 temp &= ~SDMMC_CTRL_DMA_ENABLE;
602 mci_writel(host, CTRL, temp);
603 }
604}
605
606static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
607{
608 struct dw_mci *host = slot->host;
609 unsigned long timeout = jiffies + msecs_to_jiffies(500);
610 unsigned int cmd_status = 0;
611
612 mci_writel(host, CMDARG, arg);
613 wmb();
614 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
615
616 while (time_before(jiffies, timeout)) {
617 cmd_status = mci_readl(host, CMD);
618 if (!(cmd_status & SDMMC_CMD_START))
619 return;
620 }
621 dev_err(&slot->mmc->class_dev,
622 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
623 cmd, arg, cmd_status);
624}
625
ab269128 626static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 627{
628 struct dw_mci *host = slot->host;
629 u32 div;
9623b5b9 630 u32 clk_en_a;
f95f3850 631
ab269128 632 if (slot->clock != host->current_speed || force_clkinit) {
e419990b
SJ		 633 div = host->bus_hz / slot->clock;
634 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
f95f3850
WN		 635 /*
636 * move the + 1 after the divide to prevent
637 * over-clocking the card.
638 */
e419990b
SJ		 639 div += 1;
640
641 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850
WN		 642
643 dev_info(&slot->mmc->class_dev,
644 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
645 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
646 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
647
648 /* disable clock */
649 mci_writel(host, CLKENA, 0);
650 mci_writel(host, CLKSRC, 0);
651
652 /* inform CIU */
653 mci_send_cmd(slot,
654 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
655
656 /* set clock to desired speed */
657 mci_writel(host, CLKDIV, div);
658
659 /* inform CIU */
660 mci_send_cmd(slot,
661 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
662
9623b5b9
DA		 663 /* enable clock; only low power if no SDIO */
664 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
665 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
666 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
667 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 668
669 /* inform CIU */
670 mci_send_cmd(slot,
671 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
672
673 host->current_speed = slot->clock;
674 }
675
676 /* Set the current slot bus width */
1d56c453 677 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 678}
679
053b3ce6
SJ		 680static void __dw_mci_start_request(struct dw_mci *host,
681 struct dw_mci_slot *slot,
682 struct mmc_command *cmd)
f95f3850
WN		 683{
684 struct mmc_request *mrq;
f95f3850
WN		 685 struct mmc_data *data;
686 u32 cmdflags;
687
688 mrq = slot->mrq;
689 if (host->pdata->select_slot)
690 host->pdata->select_slot(slot->id);
691
f95f3850
WN		 692 host->cur_slot = slot;
693 host->mrq = mrq;
694
695 host->pending_events = 0;
696 host->completed_events = 0;
697 host->data_status = 0;
698
053b3ce6 699 data = cmd->data;
f95f3850
WN		 700 if (data) {
701 dw_mci_set_timeout(host);
702 mci_writel(host, BYTCNT, data->blksz*data->blocks);
703 mci_writel(host, BLKSIZ, data->blksz);
704 }
705
f95f3850
WN		 706 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
707
708 /* this is the first command, send the initialization clock */
709 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
710 cmdflags |= SDMMC_CMD_INIT;
711
712 if (data) {
713 dw_mci_submit_data(host, data);
714 wmb();
715 }
716
717 dw_mci_start_command(host, cmd, cmdflags);
718
719 if (mrq->stop)
720 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
721}
722
053b3ce6
SJ		 723static void dw_mci_start_request(struct dw_mci *host,
724 struct dw_mci_slot *slot)
725{
726 struct mmc_request *mrq = slot->mrq;
727 struct mmc_command *cmd;
728
729 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
730 __dw_mci_start_request(host, slot, cmd);
731}
732
7456caae 733/* must be called with host->lock held */
f95f3850
WN		 734static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
735 struct mmc_request *mrq)
736{
737 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
738 host->state);
739
f95f3850
WN		 740 slot->mrq = mrq;
741
742 if (host->state == STATE_IDLE) {
743 host->state = STATE_SENDING_CMD;
744 dw_mci_start_request(host, slot);
745 } else {
746 list_add_tail(&slot->queue_node, &host->queue);
747 }
f95f3850
WN		 748}
749
750static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
751{
752 struct dw_mci_slot *slot = mmc_priv(mmc);
753 struct dw_mci *host = slot->host;
754
755 WARN_ON(slot->mrq);
756
7456caae
JH		 757 /*
758 * The check for card presence and queueing of the request must be
759 * atomic, otherwise the card could be removed in between and the
760 * request wouldn't fail until another card was inserted.
761 */
762 spin_lock_bh(&host->lock);
763
f95f3850 764 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 765 spin_unlock_bh(&host->lock);
f95f3850
WN		 766 mrq->cmd->error = -ENOMEDIUM;
767 mmc_request_done(mmc, mrq);
768 return;
769 }
770
f95f3850 771 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 772
773 spin_unlock_bh(&host->lock);
f95f3850
WN		 774}
775
776static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
777{
778 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 779 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 780 u32 regs;
f95f3850 781
f95f3850 782 switch (ios->bus_width) {
f95f3850
WN		 783 case MMC_BUS_WIDTH_4:
784 slot->ctype = SDMMC_CTYPE_4BIT;
785 break;
c9b2a06f
JC		 786 case MMC_BUS_WIDTH_8:
787 slot->ctype = SDMMC_CTYPE_8BIT;
788 break;
b2f7cb45
JC		 789 default:
790 /* set default 1 bit mode */
791 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 792 }
793
3f514291
SJ		 794 regs = mci_readl(slot->host, UHS_REG);
795
41babf75 796 /* DDR mode set */
3f514291 797 if (ios->timing == MMC_TIMING_UHS_DDR50)
41babf75 798 regs |= (0x1 << slot->id) << 16;
3f514291
SJ		 799 else
800 regs &= ~(0x1 << slot->id) << 16;
801
802 mci_writel(slot->host, UHS_REG, regs);
41babf75 803
f95f3850
WN		 804 if (ios->clock) {
805 /*
806 * Use mirror of ios->clock to prevent race with mmc
807 * core ios update when finding the minimum.
808 */
809 slot->clock = ios->clock;
810 }
811
cb27a843
JH		 812 if (drv_data && drv_data->set_ios)
813 drv_data->set_ios(slot->host, ios);
800d78bf 814
bf7cb224
JC		 815 /* Slot specific timing and width adjustment */
816 dw_mci_setup_bus(slot, false);
817
f95f3850
WN		 818 switch (ios->power_mode) {
819 case MMC_POWER_UP:
820 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
821 break;
822 default:
823 break;
824 }
825}
826
827static int dw_mci_get_ro(struct mmc_host *mmc)
828{
829 int read_only;
830 struct dw_mci_slot *slot = mmc_priv(mmc);
831 struct dw_mci_board *brd = slot->host->pdata;
832
833 /* Use platform get_ro function, else try on board write protect */
9640639b 834 if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
b4967aa5
TA		 835 read_only = 0;
836 else if (brd->get_ro)
f95f3850 837 read_only = brd->get_ro(slot->id);
55a6ceb2
DA		 838 else if (gpio_is_valid(slot->wp_gpio))
839 read_only = gpio_get_value(slot->wp_gpio);
f95f3850
WN		 840 else
841 read_only =
842 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
843
844 dev_dbg(&mmc->class_dev, "card is %s\n",
845 read_only ? "read-only" : "read-write");
846
847 return read_only;
848}
849
850static int dw_mci_get_cd(struct mmc_host *mmc)
851{
852 int present;
853 struct dw_mci_slot *slot = mmc_priv(mmc);
854 struct dw_mci_board *brd = slot->host->pdata;
855
856 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 857 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
858 present = 1;
859 else if (brd->get_cd)
f95f3850
WN		 860 present = !brd->get_cd(slot->id);
861 else
862 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
863 == 0 ? 1 : 0;
864
865 if (present)
866 dev_dbg(&mmc->class_dev, "card is present\n");
867 else
868 dev_dbg(&mmc->class_dev, "card is not present\n");
869
870 return present;
871}
872
9623b5b9
DA		 873/*
874 * Disable lower power mode.
875 *
876 * Low power mode will stop the card clock when idle. According to the
877 * description of the CLKENA register we should disable low power mode
878 * for SDIO cards if we need SDIO interrupts to work.
879 *
880 * This function is fast if low power mode is already disabled.
881 */
882static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
883{
884 struct dw_mci *host = slot->host;
885 u32 clk_en_a;
886 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
887
888 clk_en_a = mci_readl(host, CLKENA);
889
890 if (clk_en_a & clken_low_pwr) {
891 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
892 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
893 SDMMC_CMD_PRV_DAT_WAIT, 0);
894 }
895}
896
1a5c8e1f
SH		 897static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
898{
899 struct dw_mci_slot *slot = mmc_priv(mmc);
900 struct dw_mci *host = slot->host;
901 u32 int_mask;
902
903 /* Enable/disable Slot Specific SDIO interrupt */
904 int_mask = mci_readl(host, INTMASK);
905 if (enb) {
9623b5b9
DA		 906 /*
907 * Turn off low power mode if it was enabled. This is a bit of
908 * a heavy operation and we disable / enable IRQs a lot, so
909 * we'll leave low power mode disabled and it will get
910 * re-enabled again in dw_mci_setup_bus().
911 */
912 dw_mci_disable_low_power(slot);
913
1a5c8e1f 914 mci_writel(host, INTMASK,
705ad047 915 (int_mask | SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 916 } else {
917 mci_writel(host, INTMASK,
705ad047 918 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 919 }
920}
921
f95f3850 922static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 923 .request = dw_mci_request,
9aa51408
SJ		 924 .pre_req = dw_mci_pre_req,
925 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 926 .set_ios = dw_mci_set_ios,
927 .get_ro = dw_mci_get_ro,
928 .get_cd = dw_mci_get_cd,
929 .enable_sdio_irq = dw_mci_enable_sdio_irq,
f95f3850
WN		 930};
931
932static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
933 __releases(&host->lock)
934 __acquires(&host->lock)
935{
936 struct dw_mci_slot *slot;
937 struct mmc_host *prev_mmc = host->cur_slot->mmc;
938
939 WARN_ON(host->cmd || host->data);
940
941 host->cur_slot->mrq = NULL;
942 host->mrq = NULL;
943 if (!list_empty(&host->queue)) {
944 slot = list_entry(host->queue.next,
945 struct dw_mci_slot, queue_node);
946 list_del(&slot->queue_node);
4a90920c 947 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 948 mmc_hostname(slot->mmc));
949 host->state = STATE_SENDING_CMD;
950 dw_mci_start_request(host, slot);
951 } else {
4a90920c 952 dev_vdbg(host->dev, "list empty\n");
f95f3850
WN		 953 host->state = STATE_IDLE;
954 }
955
956 spin_unlock(&host->lock);
957 mmc_request_done(prev_mmc, mrq);
958 spin_lock(&host->lock);
959}
960
961static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
962{
963 u32 status = host->cmd_status;
964
965 host->cmd_status = 0;
966
967 /* Read the response from the card (up to 16 bytes) */
968 if (cmd->flags & MMC_RSP_PRESENT) {
969 if (cmd->flags & MMC_RSP_136) {
970 cmd->resp[3] = mci_readl(host, RESP0);
971 cmd->resp[2] = mci_readl(host, RESP1);
972 cmd->resp[1] = mci_readl(host, RESP2);
973 cmd->resp[0] = mci_readl(host, RESP3);
974 } else {
975 cmd->resp[0] = mci_readl(host, RESP0);
976 cmd->resp[1] = 0;
977 cmd->resp[2] = 0;
978 cmd->resp[3] = 0;
979 }
980 }
981
982 if (status & SDMMC_INT_RTO)
983 cmd->error = -ETIMEDOUT;
984 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
985 cmd->error = -EILSEQ;
986 else if (status & SDMMC_INT_RESP_ERR)
987 cmd->error = -EIO;
988 else
989 cmd->error = 0;
990
991 if (cmd->error) {
992 /* newer ip versions need a delay between retries */
993 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
994 mdelay(20);
995
996 if (cmd->data) {
f95f3850 997 dw_mci_stop_dma(host);
fda5f736 998 host->data = NULL;
f95f3850
WN		 999 }
1000 }
1001}
1002
1003static void dw_mci_tasklet_func(unsigned long priv)
1004{
1005 struct dw_mci *host = (struct dw_mci *)priv;
1006 struct mmc_data *data;
1007 struct mmc_command *cmd;
1008 enum dw_mci_state state;
1009 enum dw_mci_state prev_state;
94dd5b33 1010 u32 status, ctrl;
f95f3850
WN		 1011
1012 spin_lock(&host->lock);
1013
1014 state = host->state;
1015 data = host->data;
1016
1017 do {
1018 prev_state = state;
1019
1020 switch (state) {
1021 case STATE_IDLE:
1022 break;
1023
1024 case STATE_SENDING_CMD:
1025 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1026 &host->pending_events))
1027 break;
1028
1029 cmd = host->cmd;
1030 host->cmd = NULL;
1031 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
053b3ce6
SJ		 1032 dw_mci_command_complete(host, cmd);
1033 if (cmd == host->mrq->sbc && !cmd->error) {
1034 prev_state = state = STATE_SENDING_CMD;
1035 __dw_mci_start_request(host, host->cur_slot,
1036 host->mrq->cmd);
1037 goto unlock;
1038 }
1039
f95f3850
WN		 1040 if (!host->mrq->data || cmd->error) {
1041 dw_mci_request_end(host, host->mrq);
1042 goto unlock;
1043 }
1044
1045 prev_state = state = STATE_SENDING_DATA;
1046 /* fall through */
1047
1048 case STATE_SENDING_DATA:
1049 if (test_and_clear_bit(EVENT_DATA_ERROR,
1050 &host->pending_events)) {
1051 dw_mci_stop_dma(host);
1052 if (data->stop)
1053 send_stop_cmd(host, data);
1054 state = STATE_DATA_ERROR;
1055 break;
1056 }
1057
1058 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1059 &host->pending_events))
1060 break;
1061
1062 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1063 prev_state = state = STATE_DATA_BUSY;
1064 /* fall through */
1065
1066 case STATE_DATA_BUSY:
1067 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1068 &host->pending_events))
1069 break;
1070
1071 host->data = NULL;
1072 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1073 status = host->data_status;
1074
1075 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1076 if (status & SDMMC_INT_DTO) {
f95f3850
WN		 1077 data->error = -ETIMEDOUT;
1078 } else if (status & SDMMC_INT_DCRC) {
f95f3850 1079 data->error = -EILSEQ;
55c5efbc
JH		 1080 } else if (status & SDMMC_INT_EBE &&
1081 host->dir_status ==
1082 DW_MCI_SEND_STATUS) {
1083 /*
1084 * No data CRC status was returned.
1085 * The number of bytes transferred will
1086 * be exaggerated in PIO mode.
1087 */
1088 data->bytes_xfered = 0;
1089 data->error = -ETIMEDOUT;
f95f3850 1090 } else {
4a90920c 1091 dev_err(host->dev,
f95f3850
WN		 1092 "data FIFO error "
1093 "(status=%08x)\n",
1094 status);
1095 data->error = -EIO;
1096 }
94dd5b33
JH		 1097 /*
1098 * After an error, there may be data lingering
1099 * in the FIFO, so reset it - doing so
1100 * generates a block interrupt, hence setting
1101 * the scatter-gather pointer to NULL.
1102 */
f9c2a0dc 1103 sg_miter_stop(&host->sg_miter);
94dd5b33
JH		 1104 host->sg = NULL;
1105 ctrl = mci_readl(host, CTRL);
1106 ctrl |= SDMMC_CTRL_FIFO_RESET;
1107 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 1108 } else {
1109 data->bytes_xfered = data->blocks * data->blksz;
1110 data->error = 0;
1111 }
1112
1113 if (!data->stop) {
1114 dw_mci_request_end(host, host->mrq);
1115 goto unlock;
1116 }
1117
053b3ce6
SJ		 1118 if (host->mrq->sbc && !data->error) {
1119 data->stop->error = 0;
1120 dw_mci_request_end(host, host->mrq);
1121 goto unlock;
1122 }
1123
f95f3850
WN		 1124 prev_state = state = STATE_SENDING_STOP;
1125 if (!data->error)
1126 send_stop_cmd(host, data);
1127 /* fall through */
1128
1129 case STATE_SENDING_STOP:
1130 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1131 &host->pending_events))
1132 break;
1133
1134 host->cmd = NULL;
1135 dw_mci_command_complete(host, host->mrq->stop);
1136 dw_mci_request_end(host, host->mrq);
1137 goto unlock;
1138
1139 case STATE_DATA_ERROR:
1140 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1141 &host->pending_events))
1142 break;
1143
1144 state = STATE_DATA_BUSY;
1145 break;
1146 }
1147 } while (state != prev_state);
1148
1149 host->state = state;
1150unlock:
1151 spin_unlock(&host->lock);
1152
1153}
1154
34b664a2
JH		 1155/* push final bytes to part_buf, only use during push */
1156static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1157{
34b664a2
JH		 1158 memcpy((void *)&host->part_buf, buf, cnt);
1159 host->part_buf_count = cnt;
1160}
f95f3850 1161
34b664a2
JH		 1162/* append bytes to part_buf, only use during push */
1163static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1164{
1165 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1166 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1167 host->part_buf_count += cnt;
1168 return cnt;
1169}
f95f3850 1170
34b664a2
JH		 1171/* pull first bytes from part_buf, only use during pull */
1172static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1173{
1174 cnt = min(cnt, (int)host->part_buf_count);
1175 if (cnt) {
1176 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1177 cnt);
1178 host->part_buf_count -= cnt;
1179 host->part_buf_start += cnt;
f95f3850 1180 }
34b664a2 1181 return cnt;
f95f3850
WN		 1182}
1183
34b664a2
JH		 1184/* pull final bytes from the part_buf, assuming it's just been filled */
1185static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1186{
34b664a2
JH		 1187 memcpy(buf, &host->part_buf, cnt);
1188 host->part_buf_start = cnt;
1189 host->part_buf_count = (1 << host->data_shift) - cnt;
1190}
f95f3850 1191
34b664a2
JH		 1192static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1193{
1194 /* try and push anything in the part_buf */
1195 if (unlikely(host->part_buf_count)) {
1196 int len = dw_mci_push_part_bytes(host, buf, cnt);
1197 buf += len;
1198 cnt -= len;
1199 if (!sg_next(host->sg) || host->part_buf_count == 2) {
4e0a5adf
JC		 1200 mci_writew(host, DATA(host->data_offset),
1201 host->part_buf16);
34b664a2
JH		 1202 host->part_buf_count = 0;
1203 }
1204 }
1205#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1206 if (unlikely((unsigned long)buf & 0x1)) {
1207 while (cnt >= 2) {
1208 u16 aligned_buf[64];
1209 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1210 int items = len >> 1;
1211 int i;
1212 /* memcpy from input buffer into aligned buffer */
1213 memcpy(aligned_buf, buf, len);
1214 buf += len;
1215 cnt -= len;
1216 /* push data from aligned buffer into fifo */
1217 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1218 mci_writew(host, DATA(host->data_offset),
1219 aligned_buf[i]);
34b664a2
JH		 1220 }
1221 } else
1222#endif
1223 {
1224 u16 *pdata = buf;
1225 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1226 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1227 buf = pdata;
1228 }
1229 /* put anything remaining in the part_buf */
1230 if (cnt) {
1231 dw_mci_set_part_bytes(host, buf, cnt);
1232 if (!sg_next(host->sg))
4e0a5adf
JC		 1233 mci_writew(host, DATA(host->data_offset),
1234 host->part_buf16);
34b664a2
JH		 1235 }
1236}
f95f3850 1237
34b664a2
JH		 1238static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1239{
1240#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1241 if (unlikely((unsigned long)buf & 0x1)) {
1242 while (cnt >= 2) {
1243 /* pull data from fifo into aligned buffer */
1244 u16 aligned_buf[64];
1245 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1246 int items = len >> 1;
1247 int i;
1248 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1249 aligned_buf[i] = mci_readw(host,
1250 DATA(host->data_offset));
34b664a2
JH		 1251 /* memcpy from aligned buffer into output buffer */
1252 memcpy(buf, aligned_buf, len);
1253 buf += len;
1254 cnt -= len;
1255 }
1256 } else
1257#endif
1258 {
1259 u16 *pdata = buf;
1260 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1261 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1262 buf = pdata;
1263 }
1264 if (cnt) {
4e0a5adf 1265 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1266 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1267 }
1268}
1269
1270static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1271{
34b664a2
JH		 1272 /* try and push anything in the part_buf */
1273 if (unlikely(host->part_buf_count)) {
1274 int len = dw_mci_push_part_bytes(host, buf, cnt);
1275 buf += len;
1276 cnt -= len;
1277 if (!sg_next(host->sg) || host->part_buf_count == 4) {
4e0a5adf
JC		 1278 mci_writel(host, DATA(host->data_offset),
1279 host->part_buf32);
34b664a2
JH		 1280 host->part_buf_count = 0;
1281 }
1282 }
1283#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1284 if (unlikely((unsigned long)buf & 0x3)) {
1285 while (cnt >= 4) {
1286 u32 aligned_buf[32];
1287 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1288 int items = len >> 2;
1289 int i;
1290 /* memcpy from input buffer into aligned buffer */
1291 memcpy(aligned_buf, buf, len);
1292 buf += len;
1293 cnt -= len;
1294 /* push data from aligned buffer into fifo */
1295 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1296 mci_writel(host, DATA(host->data_offset),
1297 aligned_buf[i]);
34b664a2
JH		 1298 }
1299 } else
1300#endif
1301 {
1302 u32 *pdata = buf;
1303 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1304 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1305 buf = pdata;
1306 }
1307 /* put anything remaining in the part_buf */
1308 if (cnt) {
1309 dw_mci_set_part_bytes(host, buf, cnt);
1310 if (!sg_next(host->sg))
4e0a5adf
JC		 1311 mci_writel(host, DATA(host->data_offset),
1312 host->part_buf32);
f95f3850
WN		 1313 }
1314}
1315
1316static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1317{
34b664a2
JH		 1318#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1319 if (unlikely((unsigned long)buf & 0x3)) {
1320 while (cnt >= 4) {
1321 /* pull data from fifo into aligned buffer */
1322 u32 aligned_buf[32];
1323 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1324 int items = len >> 2;
1325 int i;
1326 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1327 aligned_buf[i] = mci_readl(host,
1328 DATA(host->data_offset));
34b664a2
JH		 1329 /* memcpy from aligned buffer into output buffer */
1330 memcpy(buf, aligned_buf, len);
1331 buf += len;
1332 cnt -= len;
1333 }
1334 } else
1335#endif
1336 {
1337 u32 *pdata = buf;
1338 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1339 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1340 buf = pdata;
1341 }
1342 if (cnt) {
4e0a5adf 1343 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1344 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1345 }
1346}
1347
1348static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1349{
34b664a2
JH		 1350 /* try and push anything in the part_buf */
1351 if (unlikely(host->part_buf_count)) {
1352 int len = dw_mci_push_part_bytes(host, buf, cnt);
1353 buf += len;
1354 cnt -= len;
1355 if (!sg_next(host->sg) || host->part_buf_count == 8) {
4e0a5adf
JC		 1356 mci_writew(host, DATA(host->data_offset),
1357 host->part_buf);
34b664a2
JH		 1358 host->part_buf_count = 0;
1359 }
1360 }
1361#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1362 if (unlikely((unsigned long)buf & 0x7)) {
1363 while (cnt >= 8) {
1364 u64 aligned_buf[16];
1365 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1366 int items = len >> 3;
1367 int i;
1368 /* memcpy from input buffer into aligned buffer */
1369 memcpy(aligned_buf, buf, len);
1370 buf += len;
1371 cnt -= len;
1372 /* push data from aligned buffer into fifo */
1373 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1374 mci_writeq(host, DATA(host->data_offset),
1375 aligned_buf[i]);
34b664a2
JH		 1376 }
1377 } else
1378#endif
1379 {
1380 u64 *pdata = buf;
1381 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1382 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1383 buf = pdata;
1384 }
1385 /* put anything remaining in the part_buf */
1386 if (cnt) {
1387 dw_mci_set_part_bytes(host, buf, cnt);
1388 if (!sg_next(host->sg))
4e0a5adf
JC		 1389 mci_writeq(host, DATA(host->data_offset),
1390 host->part_buf);
f95f3850
WN		 1391 }
1392}
1393
1394static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1395{
34b664a2
JH		 1396#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1397 if (unlikely((unsigned long)buf & 0x7)) {
1398 while (cnt >= 8) {
1399 /* pull data from fifo into aligned buffer */
1400 u64 aligned_buf[16];
1401 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1402 int items = len >> 3;
1403 int i;
1404 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1405 aligned_buf[i] = mci_readq(host,
1406 DATA(host->data_offset));
34b664a2
JH		 1407 /* memcpy from aligned buffer into output buffer */
1408 memcpy(buf, aligned_buf, len);
1409 buf += len;
1410 cnt -= len;
1411 }
1412 } else
1413#endif
1414 {
1415 u64 *pdata = buf;
1416 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1417 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1418 buf = pdata;
1419 }
1420 if (cnt) {
4e0a5adf 1421 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1422 dw_mci_pull_final_bytes(host, buf, cnt);
1423 }
1424}
f95f3850 1425
34b664a2
JH		 1426static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1427{
1428 int len;
f95f3850 1429
34b664a2
JH		 1430 /* get remaining partial bytes */
1431 len = dw_mci_pull_part_bytes(host, buf, cnt);
1432 if (unlikely(len == cnt))
1433 return;
1434 buf += len;
1435 cnt -= len;
1436
1437 /* get the rest of the data */
1438 host->pull_data(host, buf, cnt);
f95f3850
WN		 1439}
1440
87a74d39 1441static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 1442{
f9c2a0dc
SJ		 1443 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1444 void *buf;
1445 unsigned int offset;
f95f3850
WN		 1446 struct mmc_data *data = host->data;
1447 int shift = host->data_shift;
1448 u32 status;
ba6a902d 1449 unsigned int nbytes = 0, len;
f9c2a0dc 1450 unsigned int remain, fcnt;
f95f3850
WN		 1451
1452 do {
f9c2a0dc
SJ		 1453 if (!sg_miter_next(sg_miter))
1454 goto done;
1455
4225fc85 1456 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 1457 buf = sg_miter->addr;
1458 remain = sg_miter->length;
1459 offset = 0;
1460
1461 do {
1462 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1463 << shift) + host->part_buf_count;
1464 len = min(remain, fcnt);
1465 if (!len)
1466 break;
34b664a2 1467 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1468 offset += len;
1469 nbytes += len;
f9c2a0dc
SJ		 1470 remain -= len;
1471 } while (remain);
f95f3850 1472
e74f3a9c 1473 sg_miter->consumed = offset;
f95f3850
WN		 1474 status = mci_readl(host, MINTSTS);
1475 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 1476 /* if the RXDR is ready read again */
1477 } while ((status & SDMMC_INT_RXDR) ||
1478 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f95f3850 1479 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1480
1481 if (!remain) {
1482 if (!sg_miter_next(sg_miter))
1483 goto done;
1484 sg_miter->consumed = 0;
1485 }
1486 sg_miter_stop(sg_miter);
f95f3850
WN		 1487 return;
1488
1489done:
1490 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1491 sg_miter_stop(sg_miter);
1492 host->sg = NULL;
f95f3850
WN		 1493 smp_wmb();
1494 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1495}
1496
1497static void dw_mci_write_data_pio(struct dw_mci *host)
1498{
f9c2a0dc
SJ		 1499 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1500 void *buf;
1501 unsigned int offset;
f95f3850
WN		 1502 struct mmc_data *data = host->data;
1503 int shift = host->data_shift;
1504 u32 status;
1505 unsigned int nbytes = 0, len;
f9c2a0dc
SJ		 1506 unsigned int fifo_depth = host->fifo_depth;
1507 unsigned int remain, fcnt;
f95f3850
WN		 1508
1509 do {
f9c2a0dc
SJ		 1510 if (!sg_miter_next(sg_miter))
1511 goto done;
1512
4225fc85 1513 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 1514 buf = sg_miter->addr;
1515 remain = sg_miter->length;
1516 offset = 0;
1517
1518 do {
1519 fcnt = ((fifo_depth -
1520 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1521 << shift) - host->part_buf_count;
1522 len = min(remain, fcnt);
1523 if (!len)
1524 break;
f95f3850 1525 host->push_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1526 offset += len;
1527 nbytes += len;
f9c2a0dc
SJ		 1528 remain -= len;
1529 } while (remain);
f95f3850 1530
e74f3a9c 1531 sg_miter->consumed = offset;
f95f3850
WN		 1532 status = mci_readl(host, MINTSTS);
1533 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 1534 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850 1535 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1536
1537 if (!remain) {
1538 if (!sg_miter_next(sg_miter))
1539 goto done;
1540 sg_miter->consumed = 0;
1541 }
1542 sg_miter_stop(sg_miter);
f95f3850
WN		 1543 return;
1544
1545done:
1546 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1547 sg_miter_stop(sg_miter);
1548 host->sg = NULL;
f95f3850
WN		 1549 smp_wmb();
1550 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1551}
1552
1553static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1554{
1555 if (!host->cmd_status)
1556 host->cmd_status = status;
1557
1558 smp_wmb();
1559
1560 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1561 tasklet_schedule(&host->tasklet);
1562}
1563
1564static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1565{
1566 struct dw_mci *host = dev_id;
182c9081 1567 u32 pending;
f95f3850 1568 unsigned int pass_count = 0;
1a5c8e1f 1569 int i;
f95f3850
WN		 1570
1571 do {
f95f3850
WN		 1572 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1573
1574 /*
1575 * DTO fix - version 2.10a and below, and only if internal DMA
1576 * is configured.
1577 */
1578 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1579 if (!pending &&
1580 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1581 pending |= SDMMC_INT_DATA_OVER;
1582 }
1583
1584 if (!pending)
1585 break;
1586
1587 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1588 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 1589 host->cmd_status = pending;
f95f3850
WN		 1590 smp_wmb();
1591 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1592 }
1593
1594 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1595 /* if there is an error report DATA_ERROR */
1596 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 1597 host->data_status = pending;
f95f3850
WN		 1598 smp_wmb();
1599 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 1600 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1601 }
1602
1603 if (pending & SDMMC_INT_DATA_OVER) {
1604 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1605 if (!host->data_status)
182c9081 1606 host->data_status = pending;
f95f3850
WN		 1607 smp_wmb();
1608 if (host->dir_status == DW_MCI_RECV_STATUS) {
1609 if (host->sg != NULL)
87a74d39 1610 dw_mci_read_data_pio(host, true);
f95f3850
WN		 1611 }
1612 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1613 tasklet_schedule(&host->tasklet);
1614 }
1615
1616 if (pending & SDMMC_INT_RXDR) {
1617 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1618 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 1619 dw_mci_read_data_pio(host, false);
f95f3850
WN		 1620 }
1621
1622 if (pending & SDMMC_INT_TXDR) {
1623 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1624 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1625 dw_mci_write_data_pio(host);
1626 }
1627
1628 if (pending & SDMMC_INT_CMD_DONE) {
1629 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 1630 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 1631 }
1632
1633 if (pending & SDMMC_INT_CD) {
1634 mci_writel(host, RINTSTS, SDMMC_INT_CD);
95dcc2cb 1635 queue_work(host->card_workqueue, &host->card_work);
f95f3850
WN		 1636 }
1637
1a5c8e1f
SH		 1638 /* Handle SDIO Interrupts */
1639 for (i = 0; i < host->num_slots; i++) {
1640 struct dw_mci_slot *slot = host->slot[i];
1641 if (pending & SDMMC_INT_SDIO(i)) {
1642 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1643 mmc_signal_sdio_irq(slot->mmc);
1644 }
1645 }
1646
f95f3850
WN		 1647 } while (pass_count++ < 5);
1648
1649#ifdef CONFIG_MMC_DW_IDMAC
1650 /* Handle DMA interrupts */
1651 pending = mci_readl(host, IDSTS);
1652 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1653 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1654 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
f95f3850
WN		 1655 host->dma_ops->complete(host);
1656 }
1657#endif
1658
1659 return IRQ_HANDLED;
1660}
1661
1791b13e 1662static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1663{
1791b13e 1664 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1665 int i;
1666
1667 for (i = 0; i < host->num_slots; i++) {
1668 struct dw_mci_slot *slot = host->slot[i];
1669 struct mmc_host *mmc = slot->mmc;
1670 struct mmc_request *mrq;
1671 int present;
1672 u32 ctrl;
1673
1674 present = dw_mci_get_cd(mmc);
1675 while (present != slot->last_detect_state) {
f95f3850
WN		 1676 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1677 present ? "inserted" : "removed");
1678
1791b13e
JH		 1679 /* Power up slot (before spin_lock, may sleep) */
1680 if (present != 0 && host->pdata->setpower)
1681 host->pdata->setpower(slot->id, mmc->ocr_avail);
1682
1683 spin_lock_bh(&host->lock);
1684
f95f3850
WN		 1685 /* Card change detected */
1686 slot->last_detect_state = present;
1687
1791b13e
JH		 1688 /* Mark card as present if applicable */
1689 if (present != 0)
f95f3850 1690 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1691
1692 /* Clean up queue if present */
1693 mrq = slot->mrq;
1694 if (mrq) {
1695 if (mrq == host->mrq) {
1696 host->data = NULL;
1697 host->cmd = NULL;
1698
1699 switch (host->state) {
1700 case STATE_IDLE:
1701 break;
1702 case STATE_SENDING_CMD:
1703 mrq->cmd->error = -ENOMEDIUM;
1704 if (!mrq->data)
1705 break;
1706 /* fall through */
1707 case STATE_SENDING_DATA:
1708 mrq->data->error = -ENOMEDIUM;
1709 dw_mci_stop_dma(host);
1710 break;
1711 case STATE_DATA_BUSY:
1712 case STATE_DATA_ERROR:
1713 if (mrq->data->error == -EINPROGRESS)
1714 mrq->data->error = -ENOMEDIUM;
1715 if (!mrq->stop)
1716 break;
1717 /* fall through */
1718 case STATE_SENDING_STOP:
1719 mrq->stop->error = -ENOMEDIUM;
1720 break;
1721 }
1722
1723 dw_mci_request_end(host, mrq);
1724 } else {
1725 list_del(&slot->queue_node);
1726 mrq->cmd->error = -ENOMEDIUM;
1727 if (mrq->data)
1728 mrq->data->error = -ENOMEDIUM;
1729 if (mrq->stop)
1730 mrq->stop->error = -ENOMEDIUM;
1731
1732 spin_unlock(&host->lock);
1733 mmc_request_done(slot->mmc, mrq);
1734 spin_lock(&host->lock);
1735 }
1736 }
1737
1738 /* Power down slot */
1739 if (present == 0) {
f95f3850
WN		 1740 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1741
1742 /*
1743 * Clear down the FIFO - doing so generates a
1744 * block interrupt, hence setting the
1745 * scatter-gather pointer to NULL.
1746 */
f9c2a0dc 1747 sg_miter_stop(&host->sg_miter);
f95f3850
WN		 1748 host->sg = NULL;
1749
1750 ctrl = mci_readl(host, CTRL);
1751 ctrl |= SDMMC_CTRL_FIFO_RESET;
1752 mci_writel(host, CTRL, ctrl);
1753
1754#ifdef CONFIG_MMC_DW_IDMAC
1755 ctrl = mci_readl(host, BMOD);
141a712a
SJ		 1756 /* Software reset of DMA */
1757 ctrl |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 1758 mci_writel(host, BMOD, ctrl);
1759#endif
1760
1761 }
1762
1791b13e
JH		 1763 spin_unlock_bh(&host->lock);
1764
1765 /* Power down slot (after spin_unlock, may sleep) */
1766 if (present == 0 && host->pdata->setpower)
1767 host->pdata->setpower(slot->id, 0);
1768
f95f3850
WN		 1769 present = dw_mci_get_cd(mmc);
1770 }
1771
1772 mmc_detect_change(slot->mmc,
1773 msecs_to_jiffies(host->pdata->detect_delay_ms));
1774 }
1775}
1776
c91eab4b
TA		 1777#ifdef CONFIG_OF
1778/* given a slot id, find out the device node representing that slot */
1779static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1780{
1781 struct device_node *np;
1782 const __be32 *addr;
1783 int len;
1784
1785 if (!dev || !dev->of_node)
1786 return NULL;
1787
1788 for_each_child_of_node(dev->of_node, np) {
1789 addr = of_get_property(np, "reg", &len);
1790 if (!addr || (len < sizeof(int)))
1791 continue;
1792 if (be32_to_cpup(addr) == slot)
1793 return np;
1794 }
1795 return NULL;
1796}
1797
a70aaa64
DA		 1798static struct dw_mci_of_slot_quirks {
1799 char *quirk;
1800 int id;
1801} of_slot_quirks[] = {
1802 {
1803 .quirk = "disable-wp",
1804 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
1805 },
1806};
1807
1808static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1809{
1810 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1811 int quirks = 0;
1812 int idx;
1813
1814 /* get quirks */
1815 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
1816 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
1817 quirks |= of_slot_quirks[idx].id;
1818
1819 return quirks;
1820}
1821
c91eab4b
TA		 1822/* find out bus-width for a given slot */
1823static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1824{
1825 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1826 u32 bus_wd = 1;
1827
1828 if (!np)
1829 return 1;
1830
1831 if (of_property_read_u32(np, "bus-width", &bus_wd))
1832 dev_err(dev, "bus-width property not found, assuming width"
1833 " as 1\n");
1834 return bus_wd;
1835}
55a6ceb2
DA		 1836
1837/* find the write protect gpio for a given slot; or -1 if none specified */
1838static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
1839{
1840 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1841 int gpio;
1842
1843 if (!np)
1844 return -EINVAL;
1845
1846 gpio = of_get_named_gpio(np, "wp-gpios", 0);
1847
1848 /* Having a missing entry is valid; return silently */
1849 if (!gpio_is_valid(gpio))
1850 return -EINVAL;
1851
1852 if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
1853 dev_warn(dev, "gpio [%d] request failed\n", gpio);
1854 return -EINVAL;
1855 }
1856
1857 return gpio;
1858}
c91eab4b 1859#else /* CONFIG_OF */
a70aaa64
DA		 1860static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1861{
1862 return 0;
1863}
c91eab4b
TA		 1864static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1865{
1866 return 1;
1867}
1868static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1869{
1870 return NULL;
1871}
55a6ceb2
DA		 1872static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
1873{
1874 return -EINVAL;
1875}
c91eab4b
TA		 1876#endif /* CONFIG_OF */
1877
36c179a9 1878static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 1879{
1880 struct mmc_host *mmc;
1881 struct dw_mci_slot *slot;
e95baf13 1882 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 1883 int ctrl_id, ret;
c91eab4b 1884 u8 bus_width;
f95f3850 1885
4a90920c 1886 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 1887 if (!mmc)
1888 return -ENOMEM;
1889
1890 slot = mmc_priv(mmc);
1891 slot->id = id;
1892 slot->mmc = mmc;
1893 slot->host = host;
c91eab4b 1894 host->slot[id] = slot;
f95f3850 1895
a70aaa64
DA		 1896 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
1897
f95f3850
WN		 1898 mmc->ops = &dw_mci_ops;
1899 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1900 mmc->f_max = host->bus_hz;
1901
1902 if (host->pdata->get_ocr)
1903 mmc->ocr_avail = host->pdata->get_ocr(id);
1904 else
1905 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1906
1907 /*
1908 * Start with slot power disabled, it will be enabled when a card
1909 * is detected.
1910 */
1911 if (host->pdata->setpower)
1912 host->pdata->setpower(id, 0);
1913
fc3d7720
JC		 1914 if (host->pdata->caps)
1915 mmc->caps = host->pdata->caps;
fc3d7720 1916
ab269128
AK		 1917 if (host->pdata->pm_caps)
1918 mmc->pm_caps = host->pdata->pm_caps;
1919
800d78bf
TA		 1920 if (host->dev->of_node) {
1921 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
1922 if (ctrl_id < 0)
1923 ctrl_id = 0;
1924 } else {
1925 ctrl_id = to_platform_device(host->dev)->id;
1926 }
cb27a843
JH		 1927 if (drv_data && drv_data->caps)
1928 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 1929
4f408cc6
SJ		 1930 if (host->pdata->caps2)
1931 mmc->caps2 = host->pdata->caps2;
4f408cc6 1932
f95f3850 1933 if (host->pdata->get_bus_wd)
c91eab4b
TA		 1934 bus_width = host->pdata->get_bus_wd(slot->id);
1935 else if (host->dev->of_node)
1936 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
1937 else
1938 bus_width = 1;
1939
cb27a843 1940 if (drv_data && drv_data->setup_bus) {
800d78bf
TA		 1941 struct device_node *slot_np;
1942 slot_np = dw_mci_of_find_slot_node(host->dev, slot->id);
cb27a843 1943 ret = drv_data->setup_bus(host, slot_np, bus_width);
800d78bf
TA		 1944 if (ret)
1945 goto err_setup_bus;
1946 }
1947
c91eab4b
TA		 1948 switch (bus_width) {
1949 case 8:
1950 mmc->caps |= MMC_CAP_8_BIT_DATA;
1951 case 4:
1952 mmc->caps |= MMC_CAP_4_BIT_DATA;
1953 }
f95f3850
WN		 1954
1955 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
6daa7778 1956 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
f95f3850 1957
f95f3850
WN		 1958 if (host->pdata->blk_settings) {
1959 mmc->max_segs = host->pdata->blk_settings->max_segs;
1960 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1961 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1962 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1963 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1964 } else {
1965 /* Useful defaults if platform data is unset. */
a39e5746
JC		 1966#ifdef CONFIG_MMC_DW_IDMAC
1967 mmc->max_segs = host->ring_size;
1968 mmc->max_blk_size = 65536;
1969 mmc->max_blk_count = host->ring_size;
1970 mmc->max_seg_size = 0x1000;
1971 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1972#else
f95f3850
WN		 1973 mmc->max_segs = 64;
1974 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1975 mmc->max_blk_count = 512;
1976 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1977 mmc->max_seg_size = mmc->max_req_size;
f95f3850 1978#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 1979 }
f95f3850 1980
780f22af 1981 host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
c07946a3 1982 if (IS_ERR(host->vmmc)) {
a3c76eb9 1983 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
c07946a3
JC		 1984 host->vmmc = NULL;
1985 } else
1986 regulator_enable(host->vmmc);
1987
f95f3850
WN		 1988 if (dw_mci_get_cd(mmc))
1989 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1990 else
1991 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1992
55a6ceb2
DA		 1993 slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
1994
0cea529d
JC		 1995 ret = mmc_add_host(mmc);
1996 if (ret)
1997 goto err_setup_bus;
f95f3850
WN		 1998
1999#if defined(CONFIG_DEBUG_FS)
2000 dw_mci_init_debugfs(slot);
2001#endif
2002
2003 /* Card initially undetected */
2004 slot->last_detect_state = 0;
2005
dd6c4b98
WN		 2006 /*
2007 * Card may have been plugged in prior to boot so we
2008 * need to run the detect tasklet
2009 */
95dcc2cb 2010 queue_work(host->card_workqueue, &host->card_work);
dd6c4b98 2011
f95f3850 2012 return 0;
800d78bf
TA		 2013
2014err_setup_bus:
2015 mmc_free_host(mmc);
2016 return -EINVAL;
f95f3850
WN		 2017}
2018
2019static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2020{
2021 /* Shutdown detect IRQ */
2022 if (slot->host->pdata->exit)
2023 slot->host->pdata->exit(id);
2024
2025 /* Debugfs stuff is cleaned up by mmc core */
2026 mmc_remove_host(slot->mmc);
2027 slot->host->slot[id] = NULL;
2028 mmc_free_host(slot->mmc);
2029}
2030
2031static void dw_mci_init_dma(struct dw_mci *host)
2032{
2033 /* Alloc memory for sg translation */
780f22af 2034 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
f95f3850
WN		 2035 &host->sg_dma, GFP_KERNEL);
2036 if (!host->sg_cpu) {
4a90920c 2037 dev_err(host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 2038 __func__);
2039 goto no_dma;
2040 }
2041
2042 /* Determine which DMA interface to use */
2043#ifdef CONFIG_MMC_DW_IDMAC
2044 host->dma_ops = &dw_mci_idmac_ops;
00956ea3 2045 dev_info(host->dev, "Using internal DMA controller.\n");
f95f3850
WN		 2046#endif
2047
2048 if (!host->dma_ops)
2049 goto no_dma;
2050
e1631f98
JC		 2051 if (host->dma_ops->init && host->dma_ops->start &&
2052 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2053 if (host->dma_ops->init(host)) {
4a90920c 2054 dev_err(host->dev, "%s: Unable to initialize "
f95f3850
WN		 2055 "DMA Controller.\n", __func__);
2056 goto no_dma;
2057 }
2058 } else {
4a90920c 2059 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2060 goto no_dma;
2061 }
2062
2063 host->use_dma = 1;
2064 return;
2065
2066no_dma:
4a90920c 2067 dev_info(host->dev, "Using PIO mode.\n");
f95f3850
WN		 2068 host->use_dma = 0;
2069 return;
2070}
2071
2072static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
2073{
2074 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2075 unsigned int ctrl;
2076
2077 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2078 SDMMC_CTRL_DMA_RESET));
2079
2080 /* wait till resets clear */
2081 do {
2082 ctrl = mci_readl(host, CTRL);
2083 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2084 SDMMC_CTRL_DMA_RESET)))
2085 return true;
2086 } while (time_before(jiffies, timeout));
2087
2088 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
2089
2090 return false;
2091}
2092
c91eab4b
TA		 2093#ifdef CONFIG_OF
2094static struct dw_mci_of_quirks {
2095 char *quirk;
2096 int id;
2097} of_quirks[] = {
2098 {
2099 .quirk = "supports-highspeed",
2100 .id = DW_MCI_QUIRK_HIGHSPEED,
2101 }, {
2102 .quirk = "broken-cd",
2103 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2104 },
2105};
2106
2107static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2108{
2109 struct dw_mci_board *pdata;
2110 struct device *dev = host->dev;
2111 struct device_node *np = dev->of_node;
e95baf13 2112 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2113 int idx, ret;
c91eab4b
TA		 2114
2115 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2116 if (!pdata) {
2117 dev_err(dev, "could not allocate memory for pdata\n");
2118 return ERR_PTR(-ENOMEM);
2119 }
2120
2121 /* find out number of slots supported */
2122 if (of_property_read_u32(dev->of_node, "num-slots",
2123 &pdata->num_slots)) {
2124 dev_info(dev, "num-slots property not found, "
2125 "assuming 1 slot is available\n");
2126 pdata->num_slots = 1;
2127 }
2128
2129 /* get quirks */
2130 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2131 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2132 pdata->quirks |= of_quirks[idx].id;
2133
2134 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2135 dev_info(dev, "fifo-depth property not found, using "
2136 "value of FIFOTH register as default\n");
2137
2138 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2139
cb27a843
JH		 2140 if (drv_data && drv_data->parse_dt) {
2141 ret = drv_data->parse_dt(host);
800d78bf
TA		 2142 if (ret)
2143 return ERR_PTR(ret);
2144 }
2145
ab269128
AK		 2146 if (of_find_property(np, "keep-power-in-suspend", NULL))
2147 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2148
2149 if (of_find_property(np, "enable-sdio-wakeup", NULL))
2150 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2151
c91eab4b
TA		 2152 return pdata;
2153}
2154
2155#else /* CONFIG_OF */
2156static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2157{
2158 return ERR_PTR(-EINVAL);
2159}
2160#endif /* CONFIG_OF */
2161
62ca8034 2162int dw_mci_probe(struct dw_mci *host)
f95f3850 2163{
e95baf13 2164 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2165 int width, i, ret = 0;
f95f3850 2166 u32 fifo_size;
1c2215b7 2167 int init_slots = 0;
f95f3850 2168
c91eab4b
TA		 2169 if (!host->pdata) {
2170 host->pdata = dw_mci_parse_dt(host);
2171 if (IS_ERR(host->pdata)) {
2172 dev_err(host->dev, "platform data not available\n");
2173 return -EINVAL;
2174 }
f95f3850
WN		 2175 }
2176
62ca8034 2177 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
4a90920c 2178 dev_err(host->dev,
f95f3850 2179 "Platform data must supply select_slot function\n");
62ca8034 2180 return -ENODEV;
f95f3850
WN		 2181 }
2182
780f22af 2183 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 2184 if (IS_ERR(host->biu_clk)) {
2185 dev_dbg(host->dev, "biu clock not available\n");
2186 } else {
2187 ret = clk_prepare_enable(host->biu_clk);
2188 if (ret) {
2189 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 2190 return ret;
2191 }
2192 }
2193
780f22af 2194 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 2195 if (IS_ERR(host->ciu_clk)) {
2196 dev_dbg(host->dev, "ciu clock not available\n");
2197 } else {
2198 ret = clk_prepare_enable(host->ciu_clk);
2199 if (ret) {
2200 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 2201 goto err_clk_biu;
2202 }
2203 }
2204
2205 if (IS_ERR(host->ciu_clk))
2206 host->bus_hz = host->pdata->bus_hz;
2207 else
2208 host->bus_hz = clk_get_rate(host->ciu_clk);
2209
cb27a843
JH		 2210 if (drv_data && drv_data->setup_clock) {
2211 ret = drv_data->setup_clock(host);
800d78bf
TA		 2212 if (ret) {
2213 dev_err(host->dev,
2214 "implementation specific clock setup failed\n");
2215 goto err_clk_ciu;
2216 }
2217 }
2218
f90a0612 2219 if (!host->bus_hz) {
4a90920c 2220 dev_err(host->dev,
f95f3850 2221 "Platform data must supply bus speed\n");
f90a0612
TA		 2222 ret = -ENODEV;
2223 goto err_clk_ciu;
f95f3850
WN		 2224 }
2225
62ca8034 2226 host->quirks = host->pdata->quirks;
f95f3850
WN		 2227
2228 spin_lock_init(&host->lock);
2229 INIT_LIST_HEAD(&host->queue);
2230
f95f3850
WN		 2231 /*
2232 * Get the host data width - this assumes that HCON has been set with
2233 * the correct values.
2234 */
2235 i = (mci_readl(host, HCON) >> 7) & 0x7;
2236 if (!i) {
2237 host->push_data = dw_mci_push_data16;
2238 host->pull_data = dw_mci_pull_data16;
2239 width = 16;
2240 host->data_shift = 1;
2241 } else if (i == 2) {
2242 host->push_data = dw_mci_push_data64;
2243 host->pull_data = dw_mci_pull_data64;
2244 width = 64;
2245 host->data_shift = 3;
2246 } else {
2247 /* Check for a reserved value, and warn if it is */
2248 WARN((i != 1),
2249 "HCON reports a reserved host data width!\n"
2250 "Defaulting to 32-bit access.\n");
2251 host->push_data = dw_mci_push_data32;
2252 host->pull_data = dw_mci_pull_data32;
2253 width = 32;
2254 host->data_shift = 2;
2255 }
2256
2257 /* Reset all blocks */
4a90920c 2258 if (!mci_wait_reset(host->dev, host))
141a712a
SJ		 2259 return -ENODEV;
2260
2261 host->dma_ops = host->pdata->dma_ops;
2262 dw_mci_init_dma(host);
f95f3850
WN		 2263
2264 /* Clear the interrupts for the host controller */
2265 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2266 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2267
2268 /* Put in max timeout */
2269 mci_writel(host, TMOUT, 0xFFFFFFFF);
2270
2271 /*
2272 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2273 * Tx Mark = fifo_size / 2 DMA Size = 8
2274 */
b86d8253
JH		 2275 if (!host->pdata->fifo_depth) {
2276 /*
2277 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2278 * have been overwritten by the bootloader, just like we're
2279 * about to do, so if you know the value for your hardware, you
2280 * should put it in the platform data.
2281 */
2282 fifo_size = mci_readl(host, FIFOTH);
8234e869 2283 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2284 } else {
2285 fifo_size = host->pdata->fifo_depth;
2286 }
2287 host->fifo_depth = fifo_size;
e61cf118
JC		 2288 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2289 ((fifo_size/2) << 0));
2290 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2291
2292 /* disable clock to CIU */
2293 mci_writel(host, CLKENA, 0);
2294 mci_writel(host, CLKSRC, 0);
2295
2296 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
95dcc2cb 2297 host->card_workqueue = alloc_workqueue("dw-mci-card",
1791b13e 2298 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
95dcc2cb 2299 if (!host->card_workqueue)
1791b13e
JH		 2300 goto err_dmaunmap;
2301 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
780f22af
SJ		 2302 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2303 host->irq_flags, "dw-mci", host);
f95f3850 2304 if (ret)
1791b13e 2305 goto err_workqueue;
f95f3850 2306
f95f3850
WN		 2307 if (host->pdata->num_slots)
2308 host->num_slots = host->pdata->num_slots;
2309 else
2310 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2311
2da1d7f2
YC		 2312 /*
2313 * Enable interrupts for command done, data over, data empty, card det,
2314 * receive ready and error such as transmit, receive timeout, crc error
2315 */
2316 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2317 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2318 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2319 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2320 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2321
2322 dev_info(host->dev, "DW MMC controller at irq %d, "
2323 "%d bit host data width, "
2324 "%u deep fifo\n",
2325 host->irq, width, fifo_size);
2326
f95f3850
WN		 2327 /* We need at least one slot to succeed */
2328 for (i = 0; i < host->num_slots; i++) {
2329 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 2330 if (ret)
2331 dev_dbg(host->dev, "slot %d init failed\n", i);
2332 else
2333 init_slots++;
2334 }
2335
2336 if (init_slots) {
2337 dev_info(host->dev, "%d slots initialized\n", init_slots);
2338 } else {
2339 dev_dbg(host->dev, "attempted to initialize %d slots, "
2340 "but failed on all\n", host->num_slots);
780f22af 2341 goto err_workqueue;
f95f3850
WN		 2342 }
2343
4e0a5adf
JC		 2344 /*
2345 * In 2.40a spec, Data offset is changed.
2346 * Need to check the version-id and set data-offset for DATA register.
2347 */
2348 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
4a90920c 2349 dev_info(host->dev, "Version ID is %04x\n", host->verid);
4e0a5adf
JC		 2350
2351 if (host->verid < DW_MMC_240A)
2352 host->data_offset = DATA_OFFSET;
2353 else
2354 host->data_offset = DATA_240A_OFFSET;
2355
f95f3850 2356 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4a90920c 2357 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2358
2359 return 0;
2360
1791b13e 2361err_workqueue:
95dcc2cb 2362 destroy_workqueue(host->card_workqueue);
1791b13e 2363
f95f3850
WN		 2364err_dmaunmap:
2365 if (host->use_dma && host->dma_ops->exit)
2366 host->dma_ops->exit(host);
f95f3850 2367
780f22af 2368 if (host->vmmc)
c07946a3 2369 regulator_disable(host->vmmc);
f90a0612
TA		 2370
2371err_clk_ciu:
780f22af 2372 if (!IS_ERR(host->ciu_clk))
f90a0612 2373 clk_disable_unprepare(host->ciu_clk);
780f22af 2374
f90a0612 2375err_clk_biu:
780f22af 2376 if (!IS_ERR(host->biu_clk))
f90a0612 2377 clk_disable_unprepare(host->biu_clk);
780f22af 2378
f95f3850
WN		 2379 return ret;
2380}
62ca8034 2381EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2382
62ca8034 2383void dw_mci_remove(struct dw_mci *host)
f95f3850 2384{
f95f3850
WN		 2385 int i;
2386
2387 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2388 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2389
f95f3850 2390 for (i = 0; i < host->num_slots; i++) {
4a90920c 2391 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 2392 if (host->slot[i])
2393 dw_mci_cleanup_slot(host->slot[i], i);
2394 }
2395
2396 /* disable clock to CIU */
2397 mci_writel(host, CLKENA, 0);
2398 mci_writel(host, CLKSRC, 0);
2399
95dcc2cb 2400 destroy_workqueue(host->card_workqueue);
f95f3850
WN		 2401
2402 if (host->use_dma && host->dma_ops->exit)
2403 host->dma_ops->exit(host);
2404
780f22af 2405 if (host->vmmc)
c07946a3 2406 regulator_disable(host->vmmc);
c07946a3 2407
f90a0612
TA		 2408 if (!IS_ERR(host->ciu_clk))
2409 clk_disable_unprepare(host->ciu_clk);
780f22af 2410
f90a0612
TA		 2411 if (!IS_ERR(host->biu_clk))
2412 clk_disable_unprepare(host->biu_clk);
f95f3850 2413}
62ca8034
SH		 2414EXPORT_SYMBOL(dw_mci_remove);
2415
2416
f95f3850 2417
6fe8890d 2418#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2419/*
2420 * TODO: we should probably disable the clock to the card in the suspend path.
2421 */
62ca8034 2422int dw_mci_suspend(struct dw_mci *host)
f95f3850 2423{
62ca8034 2424 int i, ret = 0;
f95f3850
WN		 2425
2426 for (i = 0; i < host->num_slots; i++) {
2427 struct dw_mci_slot *slot = host->slot[i];
2428 if (!slot)
2429 continue;
2430 ret = mmc_suspend_host(slot->mmc);
2431 if (ret < 0) {
2432 while (--i >= 0) {
2433 slot = host->slot[i];
2434 if (slot)
2435 mmc_resume_host(host->slot[i]->mmc);
2436 }
2437 return ret;
2438 }
2439 }
2440
c07946a3
JC		 2441 if (host->vmmc)
2442 regulator_disable(host->vmmc);
2443
f95f3850
WN		 2444 return 0;
2445}
62ca8034 2446EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2447
62ca8034 2448int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2449{
2450 int i, ret;
f95f3850 2451
1d6c4e0a
JC		 2452 if (host->vmmc)
2453 regulator_enable(host->vmmc);
2454
4a90920c 2455 if (!mci_wait_reset(host->dev, host)) {
e61cf118
JC		 2456 ret = -ENODEV;
2457 return ret;
2458 }
2459
3bfe619d 2460 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 2461 host->dma_ops->init(host);
2462
e61cf118
JC		 2463 /* Restore the old value at FIFOTH register */
2464 mci_writel(host, FIFOTH, host->fifoth_val);
2465
2466 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2467 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2468 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2469 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2470 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2471
f95f3850
WN		 2472 for (i = 0; i < host->num_slots; i++) {
2473 struct dw_mci_slot *slot = host->slot[i];
2474 if (!slot)
2475 continue;
ab269128
AK		 2476 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2477 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2478 dw_mci_setup_bus(slot, true);
2479 }
2480
f95f3850
WN		 2481 ret = mmc_resume_host(host->slot[i]->mmc);
2482 if (ret < 0)
2483 return ret;
2484 }
f95f3850
WN		 2485 return 0;
2486}
62ca8034 2487EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2488#endif /* CONFIG_PM_SLEEP */
2489
f95f3850
WN		 2490static int __init dw_mci_init(void)
2491{
62ca8034
SH		 2492 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2493 return 0;
f95f3850
WN		 2494}
2495
2496static void __exit dw_mci_exit(void)
2497{
f95f3850
WN		 2498}
2499
2500module_init(dw_mci_init);
2501module_exit(dw_mci_exit);
2502
2503MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2504MODULE_AUTHOR("NXP Semiconductor VietNam");
2505MODULE_AUTHOR("Imagination Technologies Ltd");
2506MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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