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f95f3850 WN |
1 | /* |
2 | * Synopsys DesignWare Multimedia Card Interface driver | |
3 | * (Based on NXP driver for lpc 31xx) | |
4 | * | |
5 | * Copyright (C) 2009 NXP Semiconductors | |
6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/blkdev.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/debugfs.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
f95f3850 WN |
25 | #include <linux/seq_file.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/stat.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/mmc/host.h> | |
31 | #include <linux/mmc/mmc.h> | |
32 | #include <linux/mmc/dw_mmc.h> | |
33 | #include <linux/bitops.h> | |
c07946a3 | 34 | #include <linux/regulator/consumer.h> |
1791b13e | 35 | #include <linux/workqueue.h> |
c91eab4b | 36 | #include <linux/of.h> |
55a6ceb2 | 37 | #include <linux/of_gpio.h> |
f95f3850 WN |
38 | |
39 | #include "dw_mmc.h" | |
40 | ||
41 | /* Common flag combinations */ | |
42 | #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \ | |
43 | SDMMC_INT_HTO | SDMMC_INT_SBE | \ | |
44 | SDMMC_INT_EBE) | |
45 | #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ | |
46 | SDMMC_INT_RESP_ERR) | |
47 | #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ | |
48 | DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) | |
49 | #define DW_MCI_SEND_STATUS 1 | |
50 | #define DW_MCI_RECV_STATUS 2 | |
51 | #define DW_MCI_DMA_THRESHOLD 16 | |
52 | ||
53 | #ifdef CONFIG_MMC_DW_IDMAC | |
54 | struct idmac_desc { | |
55 | u32 des0; /* Control Descriptor */ | |
56 | #define IDMAC_DES0_DIC BIT(1) | |
57 | #define IDMAC_DES0_LD BIT(2) | |
58 | #define IDMAC_DES0_FD BIT(3) | |
59 | #define IDMAC_DES0_CH BIT(4) | |
60 | #define IDMAC_DES0_ER BIT(5) | |
61 | #define IDMAC_DES0_CES BIT(30) | |
62 | #define IDMAC_DES0_OWN BIT(31) | |
63 | ||
64 | u32 des1; /* Buffer sizes */ | |
65 | #define IDMAC_SET_BUFFER1_SIZE(d, s) \ | |
9b7bbe10 | 66 | ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) |
f95f3850 WN |
67 | |
68 | u32 des2; /* buffer 1 physical address */ | |
69 | ||
70 | u32 des3; /* buffer 2 physical address */ | |
71 | }; | |
72 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
73 | ||
74 | /** | |
75 | * struct dw_mci_slot - MMC slot state | |
76 | * @mmc: The mmc_host representing this slot. | |
77 | * @host: The MMC controller this slot is using. | |
a70aaa64 | 78 | * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) |
55a6ceb2 | 79 | * @wp_gpio: If gpio_is_valid() we'll use this to read write protect. |
f95f3850 WN |
80 | * @ctype: Card type for this slot. |
81 | * @mrq: mmc_request currently being processed or waiting to be | |
82 | * processed, or NULL when the slot is idle. | |
83 | * @queue_node: List node for placing this node in the @queue list of | |
84 | * &struct dw_mci. | |
85 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
86 | * @flags: Random state bits associated with the slot. | |
87 | * @id: Number of this slot. | |
88 | * @last_detect_state: Most recently observed card detect state. | |
89 | */ | |
90 | struct dw_mci_slot { | |
91 | struct mmc_host *mmc; | |
92 | struct dw_mci *host; | |
93 | ||
a70aaa64 | 94 | int quirks; |
55a6ceb2 | 95 | int wp_gpio; |
a70aaa64 | 96 | |
f95f3850 WN |
97 | u32 ctype; |
98 | ||
99 | struct mmc_request *mrq; | |
100 | struct list_head queue_node; | |
101 | ||
102 | unsigned int clock; | |
103 | unsigned long flags; | |
104 | #define DW_MMC_CARD_PRESENT 0 | |
105 | #define DW_MMC_CARD_NEED_INIT 1 | |
106 | int id; | |
107 | int last_detect_state; | |
108 | }; | |
109 | ||
110 | #if defined(CONFIG_DEBUG_FS) | |
111 | static int dw_mci_req_show(struct seq_file *s, void *v) | |
112 | { | |
113 | struct dw_mci_slot *slot = s->private; | |
114 | struct mmc_request *mrq; | |
115 | struct mmc_command *cmd; | |
116 | struct mmc_command *stop; | |
117 | struct mmc_data *data; | |
118 | ||
119 | /* Make sure we get a consistent snapshot */ | |
120 | spin_lock_bh(&slot->host->lock); | |
121 | mrq = slot->mrq; | |
122 | ||
123 | if (mrq) { | |
124 | cmd = mrq->cmd; | |
125 | data = mrq->data; | |
126 | stop = mrq->stop; | |
127 | ||
128 | if (cmd) | |
129 | seq_printf(s, | |
130 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
131 | cmd->opcode, cmd->arg, cmd->flags, | |
132 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
133 | cmd->resp[2], cmd->error); | |
134 | if (data) | |
135 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
136 | data->bytes_xfered, data->blocks, | |
137 | data->blksz, data->flags, data->error); | |
138 | if (stop) | |
139 | seq_printf(s, | |
140 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
141 | stop->opcode, stop->arg, stop->flags, | |
142 | stop->resp[0], stop->resp[1], stop->resp[2], | |
143 | stop->resp[2], stop->error); | |
144 | } | |
145 | ||
146 | spin_unlock_bh(&slot->host->lock); | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static int dw_mci_req_open(struct inode *inode, struct file *file) | |
152 | { | |
153 | return single_open(file, dw_mci_req_show, inode->i_private); | |
154 | } | |
155 | ||
156 | static const struct file_operations dw_mci_req_fops = { | |
157 | .owner = THIS_MODULE, | |
158 | .open = dw_mci_req_open, | |
159 | .read = seq_read, | |
160 | .llseek = seq_lseek, | |
161 | .release = single_release, | |
162 | }; | |
163 | ||
164 | static int dw_mci_regs_show(struct seq_file *s, void *v) | |
165 | { | |
166 | seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); | |
167 | seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); | |
168 | seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); | |
169 | seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); | |
170 | seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); | |
171 | seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static int dw_mci_regs_open(struct inode *inode, struct file *file) | |
177 | { | |
178 | return single_open(file, dw_mci_regs_show, inode->i_private); | |
179 | } | |
180 | ||
181 | static const struct file_operations dw_mci_regs_fops = { | |
182 | .owner = THIS_MODULE, | |
183 | .open = dw_mci_regs_open, | |
184 | .read = seq_read, | |
185 | .llseek = seq_lseek, | |
186 | .release = single_release, | |
187 | }; | |
188 | ||
189 | static void dw_mci_init_debugfs(struct dw_mci_slot *slot) | |
190 | { | |
191 | struct mmc_host *mmc = slot->mmc; | |
192 | struct dw_mci *host = slot->host; | |
193 | struct dentry *root; | |
194 | struct dentry *node; | |
195 | ||
196 | root = mmc->debugfs_root; | |
197 | if (!root) | |
198 | return; | |
199 | ||
200 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
201 | &dw_mci_regs_fops); | |
202 | if (!node) | |
203 | goto err; | |
204 | ||
205 | node = debugfs_create_file("req", S_IRUSR, root, slot, | |
206 | &dw_mci_req_fops); | |
207 | if (!node) | |
208 | goto err; | |
209 | ||
210 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); | |
211 | if (!node) | |
212 | goto err; | |
213 | ||
214 | node = debugfs_create_x32("pending_events", S_IRUSR, root, | |
215 | (u32 *)&host->pending_events); | |
216 | if (!node) | |
217 | goto err; | |
218 | ||
219 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
220 | (u32 *)&host->completed_events); | |
221 | if (!node) | |
222 | goto err; | |
223 | ||
224 | return; | |
225 | ||
226 | err: | |
227 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); | |
228 | } | |
229 | #endif /* defined(CONFIG_DEBUG_FS) */ | |
230 | ||
231 | static void dw_mci_set_timeout(struct dw_mci *host) | |
232 | { | |
233 | /* timeout (maximum) */ | |
234 | mci_writel(host, TMOUT, 0xffffffff); | |
235 | } | |
236 | ||
237 | static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) | |
238 | { | |
239 | struct mmc_data *data; | |
800d78bf | 240 | struct dw_mci_slot *slot = mmc_priv(mmc); |
e95baf13 | 241 | const struct dw_mci_drv_data *drv_data = slot->host->drv_data; |
f95f3850 WN |
242 | u32 cmdr; |
243 | cmd->error = -EINPROGRESS; | |
244 | ||
245 | cmdr = cmd->opcode; | |
246 | ||
247 | if (cmdr == MMC_STOP_TRANSMISSION) | |
248 | cmdr |= SDMMC_CMD_STOP; | |
249 | else | |
250 | cmdr |= SDMMC_CMD_PRV_DAT_WAIT; | |
251 | ||
252 | if (cmd->flags & MMC_RSP_PRESENT) { | |
253 | /* We expect a response, so set this bit */ | |
254 | cmdr |= SDMMC_CMD_RESP_EXP; | |
255 | if (cmd->flags & MMC_RSP_136) | |
256 | cmdr |= SDMMC_CMD_RESP_LONG; | |
257 | } | |
258 | ||
259 | if (cmd->flags & MMC_RSP_CRC) | |
260 | cmdr |= SDMMC_CMD_RESP_CRC; | |
261 | ||
262 | data = cmd->data; | |
263 | if (data) { | |
264 | cmdr |= SDMMC_CMD_DAT_EXP; | |
265 | if (data->flags & MMC_DATA_STREAM) | |
266 | cmdr |= SDMMC_CMD_STRM_MODE; | |
267 | if (data->flags & MMC_DATA_WRITE) | |
268 | cmdr |= SDMMC_CMD_DAT_WR; | |
269 | } | |
270 | ||
cb27a843 JH |
271 | if (drv_data && drv_data->prepare_command) |
272 | drv_data->prepare_command(slot->host, &cmdr); | |
800d78bf | 273 | |
f95f3850 WN |
274 | return cmdr; |
275 | } | |
276 | ||
277 | static void dw_mci_start_command(struct dw_mci *host, | |
278 | struct mmc_command *cmd, u32 cmd_flags) | |
279 | { | |
280 | host->cmd = cmd; | |
4a90920c | 281 | dev_vdbg(host->dev, |
f95f3850 WN |
282 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
283 | cmd->arg, cmd_flags); | |
284 | ||
285 | mci_writel(host, CMDARG, cmd->arg); | |
286 | wmb(); | |
287 | ||
288 | mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); | |
289 | } | |
290 | ||
291 | static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data) | |
292 | { | |
293 | dw_mci_start_command(host, data->stop, host->stop_cmdr); | |
294 | } | |
295 | ||
296 | /* DMA interface functions */ | |
297 | static void dw_mci_stop_dma(struct dw_mci *host) | |
298 | { | |
03e8cb53 | 299 | if (host->using_dma) { |
f95f3850 WN |
300 | host->dma_ops->stop(host); |
301 | host->dma_ops->cleanup(host); | |
302 | } else { | |
303 | /* Data transfer was stopped by the interrupt handler */ | |
304 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
305 | } | |
306 | } | |
307 | ||
9aa51408 SJ |
308 | static int dw_mci_get_dma_dir(struct mmc_data *data) |
309 | { | |
310 | if (data->flags & MMC_DATA_WRITE) | |
311 | return DMA_TO_DEVICE; | |
312 | else | |
313 | return DMA_FROM_DEVICE; | |
314 | } | |
315 | ||
9beee912 | 316 | #ifdef CONFIG_MMC_DW_IDMAC |
f95f3850 WN |
317 | static void dw_mci_dma_cleanup(struct dw_mci *host) |
318 | { | |
319 | struct mmc_data *data = host->data; | |
320 | ||
321 | if (data) | |
9aa51408 | 322 | if (!data->host_cookie) |
4a90920c | 323 | dma_unmap_sg(host->dev, |
9aa51408 SJ |
324 | data->sg, |
325 | data->sg_len, | |
326 | dw_mci_get_dma_dir(data)); | |
f95f3850 WN |
327 | } |
328 | ||
329 | static void dw_mci_idmac_stop_dma(struct dw_mci *host) | |
330 | { | |
331 | u32 temp; | |
332 | ||
333 | /* Disable and reset the IDMAC interface */ | |
334 | temp = mci_readl(host, CTRL); | |
335 | temp &= ~SDMMC_CTRL_USE_IDMAC; | |
336 | temp |= SDMMC_CTRL_DMA_RESET; | |
337 | mci_writel(host, CTRL, temp); | |
338 | ||
339 | /* Stop the IDMAC running */ | |
340 | temp = mci_readl(host, BMOD); | |
a5289a43 | 341 | temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); |
f95f3850 WN |
342 | mci_writel(host, BMOD, temp); |
343 | } | |
344 | ||
345 | static void dw_mci_idmac_complete_dma(struct dw_mci *host) | |
346 | { | |
347 | struct mmc_data *data = host->data; | |
348 | ||
4a90920c | 349 | dev_vdbg(host->dev, "DMA complete\n"); |
f95f3850 WN |
350 | |
351 | host->dma_ops->cleanup(host); | |
352 | ||
353 | /* | |
354 | * If the card was removed, data will be NULL. No point in trying to | |
355 | * send the stop command or waiting for NBUSY in this case. | |
356 | */ | |
357 | if (data) { | |
358 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
359 | tasklet_schedule(&host->tasklet); | |
360 | } | |
361 | } | |
362 | ||
363 | static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, | |
364 | unsigned int sg_len) | |
365 | { | |
366 | int i; | |
367 | struct idmac_desc *desc = host->sg_cpu; | |
368 | ||
369 | for (i = 0; i < sg_len; i++, desc++) { | |
370 | unsigned int length = sg_dma_len(&data->sg[i]); | |
371 | u32 mem_addr = sg_dma_address(&data->sg[i]); | |
372 | ||
373 | /* Set the OWN bit and disable interrupts for this descriptor */ | |
374 | desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; | |
375 | ||
376 | /* Buffer length */ | |
377 | IDMAC_SET_BUFFER1_SIZE(desc, length); | |
378 | ||
379 | /* Physical address to DMA to/from */ | |
380 | desc->des2 = mem_addr; | |
381 | } | |
382 | ||
383 | /* Set first descriptor */ | |
384 | desc = host->sg_cpu; | |
385 | desc->des0 |= IDMAC_DES0_FD; | |
386 | ||
387 | /* Set last descriptor */ | |
388 | desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); | |
389 | desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); | |
390 | desc->des0 |= IDMAC_DES0_LD; | |
391 | ||
392 | wmb(); | |
393 | } | |
394 | ||
395 | static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) | |
396 | { | |
397 | u32 temp; | |
398 | ||
399 | dw_mci_translate_sglist(host, host->data, sg_len); | |
400 | ||
401 | /* Select IDMAC interface */ | |
402 | temp = mci_readl(host, CTRL); | |
403 | temp |= SDMMC_CTRL_USE_IDMAC; | |
404 | mci_writel(host, CTRL, temp); | |
405 | ||
406 | wmb(); | |
407 | ||
408 | /* Enable the IDMAC */ | |
409 | temp = mci_readl(host, BMOD); | |
a5289a43 | 410 | temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; |
f95f3850 WN |
411 | mci_writel(host, BMOD, temp); |
412 | ||
413 | /* Start it running */ | |
414 | mci_writel(host, PLDMND, 1); | |
415 | } | |
416 | ||
417 | static int dw_mci_idmac_init(struct dw_mci *host) | |
418 | { | |
419 | struct idmac_desc *p; | |
897b69e7 | 420 | int i; |
f95f3850 WN |
421 | |
422 | /* Number of descriptors in the ring buffer */ | |
423 | host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); | |
424 | ||
425 | /* Forward link the descriptor list */ | |
426 | for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) | |
427 | p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1)); | |
428 | ||
429 | /* Set the last descriptor as the end-of-ring descriptor */ | |
430 | p->des3 = host->sg_dma; | |
431 | p->des0 = IDMAC_DES0_ER; | |
432 | ||
141a712a SJ |
433 | mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET); |
434 | ||
f95f3850 WN |
435 | /* Mask out interrupts - get Tx & Rx complete only */ |
436 | mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI | | |
437 | SDMMC_IDMAC_INT_TI); | |
438 | ||
439 | /* Set the descriptor base address */ | |
440 | mci_writel(host, DBADDR, host->sg_dma); | |
441 | return 0; | |
442 | } | |
443 | ||
8e2b36ea | 444 | static const struct dw_mci_dma_ops dw_mci_idmac_ops = { |
885c3e80 SJ |
445 | .init = dw_mci_idmac_init, |
446 | .start = dw_mci_idmac_start_dma, | |
447 | .stop = dw_mci_idmac_stop_dma, | |
448 | .complete = dw_mci_idmac_complete_dma, | |
449 | .cleanup = dw_mci_dma_cleanup, | |
450 | }; | |
451 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
452 | ||
9aa51408 SJ |
453 | static int dw_mci_pre_dma_transfer(struct dw_mci *host, |
454 | struct mmc_data *data, | |
455 | bool next) | |
f95f3850 WN |
456 | { |
457 | struct scatterlist *sg; | |
9aa51408 | 458 | unsigned int i, sg_len; |
03e8cb53 | 459 | |
9aa51408 SJ |
460 | if (!next && data->host_cookie) |
461 | return data->host_cookie; | |
f95f3850 WN |
462 | |
463 | /* | |
464 | * We don't do DMA on "complex" transfers, i.e. with | |
465 | * non-word-aligned buffers or lengths. Also, we don't bother | |
466 | * with all the DMA setup overhead for short transfers. | |
467 | */ | |
468 | if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) | |
469 | return -EINVAL; | |
9aa51408 | 470 | |
f95f3850 WN |
471 | if (data->blksz & 3) |
472 | return -EINVAL; | |
473 | ||
474 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
475 | if (sg->offset & 3 || sg->length & 3) | |
476 | return -EINVAL; | |
477 | } | |
478 | ||
4a90920c | 479 | sg_len = dma_map_sg(host->dev, |
9aa51408 SJ |
480 | data->sg, |
481 | data->sg_len, | |
482 | dw_mci_get_dma_dir(data)); | |
483 | if (sg_len == 0) | |
484 | return -EINVAL; | |
03e8cb53 | 485 | |
9aa51408 SJ |
486 | if (next) |
487 | data->host_cookie = sg_len; | |
f95f3850 | 488 | |
9aa51408 SJ |
489 | return sg_len; |
490 | } | |
491 | ||
9aa51408 SJ |
492 | static void dw_mci_pre_req(struct mmc_host *mmc, |
493 | struct mmc_request *mrq, | |
494 | bool is_first_req) | |
495 | { | |
496 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
497 | struct mmc_data *data = mrq->data; | |
498 | ||
499 | if (!slot->host->use_dma || !data) | |
500 | return; | |
501 | ||
502 | if (data->host_cookie) { | |
503 | data->host_cookie = 0; | |
504 | return; | |
505 | } | |
506 | ||
507 | if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) | |
508 | data->host_cookie = 0; | |
509 | } | |
510 | ||
511 | static void dw_mci_post_req(struct mmc_host *mmc, | |
512 | struct mmc_request *mrq, | |
513 | int err) | |
514 | { | |
515 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
516 | struct mmc_data *data = mrq->data; | |
517 | ||
518 | if (!slot->host->use_dma || !data) | |
519 | return; | |
520 | ||
521 | if (data->host_cookie) | |
4a90920c | 522 | dma_unmap_sg(slot->host->dev, |
9aa51408 SJ |
523 | data->sg, |
524 | data->sg_len, | |
525 | dw_mci_get_dma_dir(data)); | |
526 | data->host_cookie = 0; | |
527 | } | |
528 | ||
529 | static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) | |
530 | { | |
531 | int sg_len; | |
532 | u32 temp; | |
533 | ||
534 | host->using_dma = 0; | |
535 | ||
536 | /* If we don't have a channel, we can't do DMA */ | |
537 | if (!host->use_dma) | |
538 | return -ENODEV; | |
539 | ||
540 | sg_len = dw_mci_pre_dma_transfer(host, data, 0); | |
a99aa9b9 SJ |
541 | if (sg_len < 0) { |
542 | host->dma_ops->stop(host); | |
9aa51408 | 543 | return sg_len; |
a99aa9b9 | 544 | } |
9aa51408 SJ |
545 | |
546 | host->using_dma = 1; | |
f95f3850 | 547 | |
4a90920c | 548 | dev_vdbg(host->dev, |
f95f3850 WN |
549 | "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", |
550 | (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, | |
551 | sg_len); | |
552 | ||
553 | /* Enable the DMA interface */ | |
554 | temp = mci_readl(host, CTRL); | |
555 | temp |= SDMMC_CTRL_DMA_ENABLE; | |
556 | mci_writel(host, CTRL, temp); | |
557 | ||
558 | /* Disable RX/TX IRQs, let DMA handle it */ | |
559 | temp = mci_readl(host, INTMASK); | |
560 | temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); | |
561 | mci_writel(host, INTMASK, temp); | |
562 | ||
563 | host->dma_ops->start(host, sg_len); | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
568 | static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) | |
569 | { | |
570 | u32 temp; | |
571 | ||
572 | data->error = -EINPROGRESS; | |
573 | ||
574 | WARN_ON(host->data); | |
575 | host->sg = NULL; | |
576 | host->data = data; | |
577 | ||
55c5efbc JH |
578 | if (data->flags & MMC_DATA_READ) |
579 | host->dir_status = DW_MCI_RECV_STATUS; | |
580 | else | |
581 | host->dir_status = DW_MCI_SEND_STATUS; | |
582 | ||
f95f3850 | 583 | if (dw_mci_submit_data_dma(host, data)) { |
f9c2a0dc SJ |
584 | int flags = SG_MITER_ATOMIC; |
585 | if (host->data->flags & MMC_DATA_READ) | |
586 | flags |= SG_MITER_TO_SG; | |
587 | else | |
588 | flags |= SG_MITER_FROM_SG; | |
589 | ||
590 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
f95f3850 | 591 | host->sg = data->sg; |
34b664a2 JH |
592 | host->part_buf_start = 0; |
593 | host->part_buf_count = 0; | |
f95f3850 | 594 | |
b40af3aa | 595 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); |
f95f3850 WN |
596 | temp = mci_readl(host, INTMASK); |
597 | temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; | |
598 | mci_writel(host, INTMASK, temp); | |
599 | ||
600 | temp = mci_readl(host, CTRL); | |
601 | temp &= ~SDMMC_CTRL_DMA_ENABLE; | |
602 | mci_writel(host, CTRL, temp); | |
603 | } | |
604 | } | |
605 | ||
606 | static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) | |
607 | { | |
608 | struct dw_mci *host = slot->host; | |
609 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
610 | unsigned int cmd_status = 0; | |
611 | ||
612 | mci_writel(host, CMDARG, arg); | |
613 | wmb(); | |
614 | mci_writel(host, CMD, SDMMC_CMD_START | cmd); | |
615 | ||
616 | while (time_before(jiffies, timeout)) { | |
617 | cmd_status = mci_readl(host, CMD); | |
618 | if (!(cmd_status & SDMMC_CMD_START)) | |
619 | return; | |
620 | } | |
621 | dev_err(&slot->mmc->class_dev, | |
622 | "Timeout sending command (cmd %#x arg %#x status %#x)\n", | |
623 | cmd, arg, cmd_status); | |
624 | } | |
625 | ||
ab269128 | 626 | static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) |
f95f3850 WN |
627 | { |
628 | struct dw_mci *host = slot->host; | |
629 | u32 div; | |
9623b5b9 | 630 | u32 clk_en_a; |
f95f3850 | 631 | |
ab269128 | 632 | if (slot->clock != host->current_speed || force_clkinit) { |
e419990b SJ |
633 | div = host->bus_hz / slot->clock; |
634 | if (host->bus_hz % slot->clock && host->bus_hz > slot->clock) | |
f95f3850 WN |
635 | /* |
636 | * move the + 1 after the divide to prevent | |
637 | * over-clocking the card. | |
638 | */ | |
e419990b SJ |
639 | div += 1; |
640 | ||
641 | div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0; | |
f95f3850 WN |
642 | |
643 | dev_info(&slot->mmc->class_dev, | |
644 | "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ" | |
645 | " div = %d)\n", slot->id, host->bus_hz, slot->clock, | |
646 | div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div); | |
647 | ||
648 | /* disable clock */ | |
649 | mci_writel(host, CLKENA, 0); | |
650 | mci_writel(host, CLKSRC, 0); | |
651 | ||
652 | /* inform CIU */ | |
653 | mci_send_cmd(slot, | |
654 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
655 | ||
656 | /* set clock to desired speed */ | |
657 | mci_writel(host, CLKDIV, div); | |
658 | ||
659 | /* inform CIU */ | |
660 | mci_send_cmd(slot, | |
661 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
662 | ||
9623b5b9 DA |
663 | /* enable clock; only low power if no SDIO */ |
664 | clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; | |
665 | if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id))) | |
666 | clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; | |
667 | mci_writel(host, CLKENA, clk_en_a); | |
f95f3850 WN |
668 | |
669 | /* inform CIU */ | |
670 | mci_send_cmd(slot, | |
671 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
672 | ||
673 | host->current_speed = slot->clock; | |
674 | } | |
675 | ||
676 | /* Set the current slot bus width */ | |
1d56c453 | 677 | mci_writel(host, CTYPE, (slot->ctype << slot->id)); |
f95f3850 WN |
678 | } |
679 | ||
053b3ce6 SJ |
680 | static void __dw_mci_start_request(struct dw_mci *host, |
681 | struct dw_mci_slot *slot, | |
682 | struct mmc_command *cmd) | |
f95f3850 WN |
683 | { |
684 | struct mmc_request *mrq; | |
f95f3850 WN |
685 | struct mmc_data *data; |
686 | u32 cmdflags; | |
687 | ||
688 | mrq = slot->mrq; | |
689 | if (host->pdata->select_slot) | |
690 | host->pdata->select_slot(slot->id); | |
691 | ||
f95f3850 WN |
692 | host->cur_slot = slot; |
693 | host->mrq = mrq; | |
694 | ||
695 | host->pending_events = 0; | |
696 | host->completed_events = 0; | |
697 | host->data_status = 0; | |
698 | ||
053b3ce6 | 699 | data = cmd->data; |
f95f3850 WN |
700 | if (data) { |
701 | dw_mci_set_timeout(host); | |
702 | mci_writel(host, BYTCNT, data->blksz*data->blocks); | |
703 | mci_writel(host, BLKSIZ, data->blksz); | |
704 | } | |
705 | ||
f95f3850 WN |
706 | cmdflags = dw_mci_prepare_command(slot->mmc, cmd); |
707 | ||
708 | /* this is the first command, send the initialization clock */ | |
709 | if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) | |
710 | cmdflags |= SDMMC_CMD_INIT; | |
711 | ||
712 | if (data) { | |
713 | dw_mci_submit_data(host, data); | |
714 | wmb(); | |
715 | } | |
716 | ||
717 | dw_mci_start_command(host, cmd, cmdflags); | |
718 | ||
719 | if (mrq->stop) | |
720 | host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); | |
721 | } | |
722 | ||
053b3ce6 SJ |
723 | static void dw_mci_start_request(struct dw_mci *host, |
724 | struct dw_mci_slot *slot) | |
725 | { | |
726 | struct mmc_request *mrq = slot->mrq; | |
727 | struct mmc_command *cmd; | |
728 | ||
729 | cmd = mrq->sbc ? mrq->sbc : mrq->cmd; | |
730 | __dw_mci_start_request(host, slot, cmd); | |
731 | } | |
732 | ||
7456caae | 733 | /* must be called with host->lock held */ |
f95f3850 WN |
734 | static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, |
735 | struct mmc_request *mrq) | |
736 | { | |
737 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
738 | host->state); | |
739 | ||
f95f3850 WN |
740 | slot->mrq = mrq; |
741 | ||
742 | if (host->state == STATE_IDLE) { | |
743 | host->state = STATE_SENDING_CMD; | |
744 | dw_mci_start_request(host, slot); | |
745 | } else { | |
746 | list_add_tail(&slot->queue_node, &host->queue); | |
747 | } | |
f95f3850 WN |
748 | } |
749 | ||
750 | static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
751 | { | |
752 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
753 | struct dw_mci *host = slot->host; | |
754 | ||
755 | WARN_ON(slot->mrq); | |
756 | ||
7456caae JH |
757 | /* |
758 | * The check for card presence and queueing of the request must be | |
759 | * atomic, otherwise the card could be removed in between and the | |
760 | * request wouldn't fail until another card was inserted. | |
761 | */ | |
762 | spin_lock_bh(&host->lock); | |
763 | ||
f95f3850 | 764 | if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { |
7456caae | 765 | spin_unlock_bh(&host->lock); |
f95f3850 WN |
766 | mrq->cmd->error = -ENOMEDIUM; |
767 | mmc_request_done(mmc, mrq); | |
768 | return; | |
769 | } | |
770 | ||
f95f3850 | 771 | dw_mci_queue_request(host, slot, mrq); |
7456caae JH |
772 | |
773 | spin_unlock_bh(&host->lock); | |
f95f3850 WN |
774 | } |
775 | ||
776 | static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
777 | { | |
778 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
e95baf13 | 779 | const struct dw_mci_drv_data *drv_data = slot->host->drv_data; |
41babf75 | 780 | u32 regs; |
f95f3850 | 781 | |
f95f3850 | 782 | switch (ios->bus_width) { |
f95f3850 WN |
783 | case MMC_BUS_WIDTH_4: |
784 | slot->ctype = SDMMC_CTYPE_4BIT; | |
785 | break; | |
c9b2a06f JC |
786 | case MMC_BUS_WIDTH_8: |
787 | slot->ctype = SDMMC_CTYPE_8BIT; | |
788 | break; | |
b2f7cb45 JC |
789 | default: |
790 | /* set default 1 bit mode */ | |
791 | slot->ctype = SDMMC_CTYPE_1BIT; | |
f95f3850 WN |
792 | } |
793 | ||
3f514291 SJ |
794 | regs = mci_readl(slot->host, UHS_REG); |
795 | ||
41babf75 | 796 | /* DDR mode set */ |
3f514291 | 797 | if (ios->timing == MMC_TIMING_UHS_DDR50) |
c69042a5 | 798 | regs |= ((0x1 << slot->id) << 16); |
3f514291 | 799 | else |
c69042a5 | 800 | regs &= ~((0x1 << slot->id) << 16); |
3f514291 SJ |
801 | |
802 | mci_writel(slot->host, UHS_REG, regs); | |
41babf75 | 803 | |
f95f3850 WN |
804 | if (ios->clock) { |
805 | /* | |
806 | * Use mirror of ios->clock to prevent race with mmc | |
807 | * core ios update when finding the minimum. | |
808 | */ | |
809 | slot->clock = ios->clock; | |
810 | } | |
811 | ||
cb27a843 JH |
812 | if (drv_data && drv_data->set_ios) |
813 | drv_data->set_ios(slot->host, ios); | |
800d78bf | 814 | |
bf7cb224 JC |
815 | /* Slot specific timing and width adjustment */ |
816 | dw_mci_setup_bus(slot, false); | |
817 | ||
f95f3850 WN |
818 | switch (ios->power_mode) { |
819 | case MMC_POWER_UP: | |
820 | set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); | |
e6f34e2f JH |
821 | /* Power up slot */ |
822 | if (slot->host->pdata->setpower) | |
823 | slot->host->pdata->setpower(slot->id, mmc->ocr_avail); | |
4366dcc5 JC |
824 | regs = mci_readl(slot->host, PWREN); |
825 | regs |= (1 << slot->id); | |
826 | mci_writel(slot->host, PWREN, regs); | |
e6f34e2f JH |
827 | break; |
828 | case MMC_POWER_OFF: | |
829 | /* Power down slot */ | |
830 | if (slot->host->pdata->setpower) | |
831 | slot->host->pdata->setpower(slot->id, 0); | |
4366dcc5 JC |
832 | regs = mci_readl(slot->host, PWREN); |
833 | regs &= ~(1 << slot->id); | |
834 | mci_writel(slot->host, PWREN, regs); | |
f95f3850 WN |
835 | break; |
836 | default: | |
837 | break; | |
838 | } | |
839 | } | |
840 | ||
841 | static int dw_mci_get_ro(struct mmc_host *mmc) | |
842 | { | |
843 | int read_only; | |
844 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
845 | struct dw_mci_board *brd = slot->host->pdata; | |
846 | ||
847 | /* Use platform get_ro function, else try on board write protect */ | |
9640639b | 848 | if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) |
b4967aa5 TA |
849 | read_only = 0; |
850 | else if (brd->get_ro) | |
f95f3850 | 851 | read_only = brd->get_ro(slot->id); |
55a6ceb2 DA |
852 | else if (gpio_is_valid(slot->wp_gpio)) |
853 | read_only = gpio_get_value(slot->wp_gpio); | |
f95f3850 WN |
854 | else |
855 | read_only = | |
856 | mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; | |
857 | ||
858 | dev_dbg(&mmc->class_dev, "card is %s\n", | |
859 | read_only ? "read-only" : "read-write"); | |
860 | ||
861 | return read_only; | |
862 | } | |
863 | ||
864 | static int dw_mci_get_cd(struct mmc_host *mmc) | |
865 | { | |
866 | int present; | |
867 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
868 | struct dw_mci_board *brd = slot->host->pdata; | |
869 | ||
870 | /* Use platform get_cd function, else try onboard card detect */ | |
fc3d7720 JC |
871 | if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) |
872 | present = 1; | |
873 | else if (brd->get_cd) | |
f95f3850 WN |
874 | present = !brd->get_cd(slot->id); |
875 | else | |
876 | present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) | |
877 | == 0 ? 1 : 0; | |
878 | ||
879 | if (present) | |
880 | dev_dbg(&mmc->class_dev, "card is present\n"); | |
881 | else | |
882 | dev_dbg(&mmc->class_dev, "card is not present\n"); | |
883 | ||
884 | return present; | |
885 | } | |
886 | ||
9623b5b9 DA |
887 | /* |
888 | * Disable lower power mode. | |
889 | * | |
890 | * Low power mode will stop the card clock when idle. According to the | |
891 | * description of the CLKENA register we should disable low power mode | |
892 | * for SDIO cards if we need SDIO interrupts to work. | |
893 | * | |
894 | * This function is fast if low power mode is already disabled. | |
895 | */ | |
896 | static void dw_mci_disable_low_power(struct dw_mci_slot *slot) | |
897 | { | |
898 | struct dw_mci *host = slot->host; | |
899 | u32 clk_en_a; | |
900 | const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; | |
901 | ||
902 | clk_en_a = mci_readl(host, CLKENA); | |
903 | ||
904 | if (clk_en_a & clken_low_pwr) { | |
905 | mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr); | |
906 | mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | | |
907 | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
908 | } | |
909 | } | |
910 | ||
1a5c8e1f SH |
911 | static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) |
912 | { | |
913 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
914 | struct dw_mci *host = slot->host; | |
915 | u32 int_mask; | |
916 | ||
917 | /* Enable/disable Slot Specific SDIO interrupt */ | |
918 | int_mask = mci_readl(host, INTMASK); | |
919 | if (enb) { | |
9623b5b9 DA |
920 | /* |
921 | * Turn off low power mode if it was enabled. This is a bit of | |
922 | * a heavy operation and we disable / enable IRQs a lot, so | |
923 | * we'll leave low power mode disabled and it will get | |
924 | * re-enabled again in dw_mci_setup_bus(). | |
925 | */ | |
926 | dw_mci_disable_low_power(slot); | |
927 | ||
1a5c8e1f | 928 | mci_writel(host, INTMASK, |
705ad047 | 929 | (int_mask | SDMMC_INT_SDIO(slot->id))); |
1a5c8e1f SH |
930 | } else { |
931 | mci_writel(host, INTMASK, | |
705ad047 | 932 | (int_mask & ~SDMMC_INT_SDIO(slot->id))); |
1a5c8e1f SH |
933 | } |
934 | } | |
935 | ||
f95f3850 | 936 | static const struct mmc_host_ops dw_mci_ops = { |
1a5c8e1f | 937 | .request = dw_mci_request, |
9aa51408 SJ |
938 | .pre_req = dw_mci_pre_req, |
939 | .post_req = dw_mci_post_req, | |
1a5c8e1f SH |
940 | .set_ios = dw_mci_set_ios, |
941 | .get_ro = dw_mci_get_ro, | |
942 | .get_cd = dw_mci_get_cd, | |
943 | .enable_sdio_irq = dw_mci_enable_sdio_irq, | |
f95f3850 WN |
944 | }; |
945 | ||
946 | static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) | |
947 | __releases(&host->lock) | |
948 | __acquires(&host->lock) | |
949 | { | |
950 | struct dw_mci_slot *slot; | |
951 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
952 | ||
953 | WARN_ON(host->cmd || host->data); | |
954 | ||
955 | host->cur_slot->mrq = NULL; | |
956 | host->mrq = NULL; | |
957 | if (!list_empty(&host->queue)) { | |
958 | slot = list_entry(host->queue.next, | |
959 | struct dw_mci_slot, queue_node); | |
960 | list_del(&slot->queue_node); | |
4a90920c | 961 | dev_vdbg(host->dev, "list not empty: %s is next\n", |
f95f3850 WN |
962 | mmc_hostname(slot->mmc)); |
963 | host->state = STATE_SENDING_CMD; | |
964 | dw_mci_start_request(host, slot); | |
965 | } else { | |
4a90920c | 966 | dev_vdbg(host->dev, "list empty\n"); |
f95f3850 WN |
967 | host->state = STATE_IDLE; |
968 | } | |
969 | ||
970 | spin_unlock(&host->lock); | |
971 | mmc_request_done(prev_mmc, mrq); | |
972 | spin_lock(&host->lock); | |
973 | } | |
974 | ||
975 | static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) | |
976 | { | |
977 | u32 status = host->cmd_status; | |
978 | ||
979 | host->cmd_status = 0; | |
980 | ||
981 | /* Read the response from the card (up to 16 bytes) */ | |
982 | if (cmd->flags & MMC_RSP_PRESENT) { | |
983 | if (cmd->flags & MMC_RSP_136) { | |
984 | cmd->resp[3] = mci_readl(host, RESP0); | |
985 | cmd->resp[2] = mci_readl(host, RESP1); | |
986 | cmd->resp[1] = mci_readl(host, RESP2); | |
987 | cmd->resp[0] = mci_readl(host, RESP3); | |
988 | } else { | |
989 | cmd->resp[0] = mci_readl(host, RESP0); | |
990 | cmd->resp[1] = 0; | |
991 | cmd->resp[2] = 0; | |
992 | cmd->resp[3] = 0; | |
993 | } | |
994 | } | |
995 | ||
996 | if (status & SDMMC_INT_RTO) | |
997 | cmd->error = -ETIMEDOUT; | |
998 | else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) | |
999 | cmd->error = -EILSEQ; | |
1000 | else if (status & SDMMC_INT_RESP_ERR) | |
1001 | cmd->error = -EIO; | |
1002 | else | |
1003 | cmd->error = 0; | |
1004 | ||
1005 | if (cmd->error) { | |
1006 | /* newer ip versions need a delay between retries */ | |
1007 | if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) | |
1008 | mdelay(20); | |
1009 | ||
1010 | if (cmd->data) { | |
f95f3850 | 1011 | dw_mci_stop_dma(host); |
fda5f736 | 1012 | host->data = NULL; |
f95f3850 WN |
1013 | } |
1014 | } | |
1015 | } | |
1016 | ||
1017 | static void dw_mci_tasklet_func(unsigned long priv) | |
1018 | { | |
1019 | struct dw_mci *host = (struct dw_mci *)priv; | |
1020 | struct mmc_data *data; | |
1021 | struct mmc_command *cmd; | |
1022 | enum dw_mci_state state; | |
1023 | enum dw_mci_state prev_state; | |
94dd5b33 | 1024 | u32 status, ctrl; |
f95f3850 WN |
1025 | |
1026 | spin_lock(&host->lock); | |
1027 | ||
1028 | state = host->state; | |
1029 | data = host->data; | |
1030 | ||
1031 | do { | |
1032 | prev_state = state; | |
1033 | ||
1034 | switch (state) { | |
1035 | case STATE_IDLE: | |
1036 | break; | |
1037 | ||
1038 | case STATE_SENDING_CMD: | |
1039 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
1040 | &host->pending_events)) | |
1041 | break; | |
1042 | ||
1043 | cmd = host->cmd; | |
1044 | host->cmd = NULL; | |
1045 | set_bit(EVENT_CMD_COMPLETE, &host->completed_events); | |
053b3ce6 SJ |
1046 | dw_mci_command_complete(host, cmd); |
1047 | if (cmd == host->mrq->sbc && !cmd->error) { | |
1048 | prev_state = state = STATE_SENDING_CMD; | |
1049 | __dw_mci_start_request(host, host->cur_slot, | |
1050 | host->mrq->cmd); | |
1051 | goto unlock; | |
1052 | } | |
1053 | ||
f95f3850 WN |
1054 | if (!host->mrq->data || cmd->error) { |
1055 | dw_mci_request_end(host, host->mrq); | |
1056 | goto unlock; | |
1057 | } | |
1058 | ||
1059 | prev_state = state = STATE_SENDING_DATA; | |
1060 | /* fall through */ | |
1061 | ||
1062 | case STATE_SENDING_DATA: | |
1063 | if (test_and_clear_bit(EVENT_DATA_ERROR, | |
1064 | &host->pending_events)) { | |
1065 | dw_mci_stop_dma(host); | |
1066 | if (data->stop) | |
1067 | send_stop_cmd(host, data); | |
1068 | state = STATE_DATA_ERROR; | |
1069 | break; | |
1070 | } | |
1071 | ||
1072 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
1073 | &host->pending_events)) | |
1074 | break; | |
1075 | ||
1076 | set_bit(EVENT_XFER_COMPLETE, &host->completed_events); | |
1077 | prev_state = state = STATE_DATA_BUSY; | |
1078 | /* fall through */ | |
1079 | ||
1080 | case STATE_DATA_BUSY: | |
1081 | if (!test_and_clear_bit(EVENT_DATA_COMPLETE, | |
1082 | &host->pending_events)) | |
1083 | break; | |
1084 | ||
1085 | host->data = NULL; | |
1086 | set_bit(EVENT_DATA_COMPLETE, &host->completed_events); | |
1087 | status = host->data_status; | |
1088 | ||
1089 | if (status & DW_MCI_DATA_ERROR_FLAGS) { | |
1090 | if (status & SDMMC_INT_DTO) { | |
f95f3850 WN |
1091 | data->error = -ETIMEDOUT; |
1092 | } else if (status & SDMMC_INT_DCRC) { | |
f95f3850 | 1093 | data->error = -EILSEQ; |
55c5efbc JH |
1094 | } else if (status & SDMMC_INT_EBE && |
1095 | host->dir_status == | |
1096 | DW_MCI_SEND_STATUS) { | |
1097 | /* | |
1098 | * No data CRC status was returned. | |
1099 | * The number of bytes transferred will | |
1100 | * be exaggerated in PIO mode. | |
1101 | */ | |
1102 | data->bytes_xfered = 0; | |
1103 | data->error = -ETIMEDOUT; | |
f95f3850 | 1104 | } else { |
4a90920c | 1105 | dev_err(host->dev, |
f95f3850 WN |
1106 | "data FIFO error " |
1107 | "(status=%08x)\n", | |
1108 | status); | |
1109 | data->error = -EIO; | |
1110 | } | |
94dd5b33 JH |
1111 | /* |
1112 | * After an error, there may be data lingering | |
1113 | * in the FIFO, so reset it - doing so | |
1114 | * generates a block interrupt, hence setting | |
1115 | * the scatter-gather pointer to NULL. | |
1116 | */ | |
f9c2a0dc | 1117 | sg_miter_stop(&host->sg_miter); |
94dd5b33 JH |
1118 | host->sg = NULL; |
1119 | ctrl = mci_readl(host, CTRL); | |
1120 | ctrl |= SDMMC_CTRL_FIFO_RESET; | |
1121 | mci_writel(host, CTRL, ctrl); | |
f95f3850 WN |
1122 | } else { |
1123 | data->bytes_xfered = data->blocks * data->blksz; | |
1124 | data->error = 0; | |
1125 | } | |
1126 | ||
1127 | if (!data->stop) { | |
1128 | dw_mci_request_end(host, host->mrq); | |
1129 | goto unlock; | |
1130 | } | |
1131 | ||
053b3ce6 SJ |
1132 | if (host->mrq->sbc && !data->error) { |
1133 | data->stop->error = 0; | |
1134 | dw_mci_request_end(host, host->mrq); | |
1135 | goto unlock; | |
1136 | } | |
1137 | ||
f95f3850 WN |
1138 | prev_state = state = STATE_SENDING_STOP; |
1139 | if (!data->error) | |
1140 | send_stop_cmd(host, data); | |
1141 | /* fall through */ | |
1142 | ||
1143 | case STATE_SENDING_STOP: | |
1144 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
1145 | &host->pending_events)) | |
1146 | break; | |
1147 | ||
1148 | host->cmd = NULL; | |
1149 | dw_mci_command_complete(host, host->mrq->stop); | |
1150 | dw_mci_request_end(host, host->mrq); | |
1151 | goto unlock; | |
1152 | ||
1153 | case STATE_DATA_ERROR: | |
1154 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
1155 | &host->pending_events)) | |
1156 | break; | |
1157 | ||
1158 | state = STATE_DATA_BUSY; | |
1159 | break; | |
1160 | } | |
1161 | } while (state != prev_state); | |
1162 | ||
1163 | host->state = state; | |
1164 | unlock: | |
1165 | spin_unlock(&host->lock); | |
1166 | ||
1167 | } | |
1168 | ||
34b664a2 JH |
1169 | /* push final bytes to part_buf, only use during push */ |
1170 | static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1171 | { |
34b664a2 JH |
1172 | memcpy((void *)&host->part_buf, buf, cnt); |
1173 | host->part_buf_count = cnt; | |
1174 | } | |
f95f3850 | 1175 | |
34b664a2 JH |
1176 | /* append bytes to part_buf, only use during push */ |
1177 | static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1178 | { | |
1179 | cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); | |
1180 | memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); | |
1181 | host->part_buf_count += cnt; | |
1182 | return cnt; | |
1183 | } | |
f95f3850 | 1184 | |
34b664a2 JH |
1185 | /* pull first bytes from part_buf, only use during pull */ |
1186 | static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1187 | { | |
1188 | cnt = min(cnt, (int)host->part_buf_count); | |
1189 | if (cnt) { | |
1190 | memcpy(buf, (void *)&host->part_buf + host->part_buf_start, | |
1191 | cnt); | |
1192 | host->part_buf_count -= cnt; | |
1193 | host->part_buf_start += cnt; | |
f95f3850 | 1194 | } |
34b664a2 | 1195 | return cnt; |
f95f3850 WN |
1196 | } |
1197 | ||
34b664a2 JH |
1198 | /* pull final bytes from the part_buf, assuming it's just been filled */ |
1199 | static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1200 | { |
34b664a2 JH |
1201 | memcpy(buf, &host->part_buf, cnt); |
1202 | host->part_buf_start = cnt; | |
1203 | host->part_buf_count = (1 << host->data_shift) - cnt; | |
1204 | } | |
f95f3850 | 1205 | |
34b664a2 JH |
1206 | static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) |
1207 | { | |
cfbeb59c MC |
1208 | struct mmc_data *data = host->data; |
1209 | int init_cnt = cnt; | |
1210 | ||
34b664a2 JH |
1211 | /* try and push anything in the part_buf */ |
1212 | if (unlikely(host->part_buf_count)) { | |
1213 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1214 | buf += len; | |
1215 | cnt -= len; | |
cfbeb59c | 1216 | if (host->part_buf_count == 2) { |
4e0a5adf JC |
1217 | mci_writew(host, DATA(host->data_offset), |
1218 | host->part_buf16); | |
34b664a2 JH |
1219 | host->part_buf_count = 0; |
1220 | } | |
1221 | } | |
1222 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1223 | if (unlikely((unsigned long)buf & 0x1)) { | |
1224 | while (cnt >= 2) { | |
1225 | u16 aligned_buf[64]; | |
1226 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1227 | int items = len >> 1; | |
1228 | int i; | |
1229 | /* memcpy from input buffer into aligned buffer */ | |
1230 | memcpy(aligned_buf, buf, len); | |
1231 | buf += len; | |
1232 | cnt -= len; | |
1233 | /* push data from aligned buffer into fifo */ | |
1234 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1235 | mci_writew(host, DATA(host->data_offset), |
1236 | aligned_buf[i]); | |
34b664a2 JH |
1237 | } |
1238 | } else | |
1239 | #endif | |
1240 | { | |
1241 | u16 *pdata = buf; | |
1242 | for (; cnt >= 2; cnt -= 2) | |
4e0a5adf | 1243 | mci_writew(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1244 | buf = pdata; |
1245 | } | |
1246 | /* put anything remaining in the part_buf */ | |
1247 | if (cnt) { | |
1248 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1249 | /* Push data if we have reached the expected data length */ |
1250 | if ((data->bytes_xfered + init_cnt) == | |
1251 | (data->blksz * data->blocks)) | |
4e0a5adf | 1252 | mci_writew(host, DATA(host->data_offset), |
cfbeb59c | 1253 | host->part_buf16); |
34b664a2 JH |
1254 | } |
1255 | } | |
f95f3850 | 1256 | |
34b664a2 JH |
1257 | static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) |
1258 | { | |
1259 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1260 | if (unlikely((unsigned long)buf & 0x1)) { | |
1261 | while (cnt >= 2) { | |
1262 | /* pull data from fifo into aligned buffer */ | |
1263 | u16 aligned_buf[64]; | |
1264 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1265 | int items = len >> 1; | |
1266 | int i; | |
1267 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1268 | aligned_buf[i] = mci_readw(host, |
1269 | DATA(host->data_offset)); | |
34b664a2 JH |
1270 | /* memcpy from aligned buffer into output buffer */ |
1271 | memcpy(buf, aligned_buf, len); | |
1272 | buf += len; | |
1273 | cnt -= len; | |
1274 | } | |
1275 | } else | |
1276 | #endif | |
1277 | { | |
1278 | u16 *pdata = buf; | |
1279 | for (; cnt >= 2; cnt -= 2) | |
4e0a5adf | 1280 | *pdata++ = mci_readw(host, DATA(host->data_offset)); |
34b664a2 JH |
1281 | buf = pdata; |
1282 | } | |
1283 | if (cnt) { | |
4e0a5adf | 1284 | host->part_buf16 = mci_readw(host, DATA(host->data_offset)); |
34b664a2 | 1285 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1286 | } |
1287 | } | |
1288 | ||
1289 | static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) | |
1290 | { | |
cfbeb59c MC |
1291 | struct mmc_data *data = host->data; |
1292 | int init_cnt = cnt; | |
1293 | ||
34b664a2 JH |
1294 | /* try and push anything in the part_buf */ |
1295 | if (unlikely(host->part_buf_count)) { | |
1296 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1297 | buf += len; | |
1298 | cnt -= len; | |
cfbeb59c | 1299 | if (host->part_buf_count == 4) { |
4e0a5adf JC |
1300 | mci_writel(host, DATA(host->data_offset), |
1301 | host->part_buf32); | |
34b664a2 JH |
1302 | host->part_buf_count = 0; |
1303 | } | |
1304 | } | |
1305 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1306 | if (unlikely((unsigned long)buf & 0x3)) { | |
1307 | while (cnt >= 4) { | |
1308 | u32 aligned_buf[32]; | |
1309 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1310 | int items = len >> 2; | |
1311 | int i; | |
1312 | /* memcpy from input buffer into aligned buffer */ | |
1313 | memcpy(aligned_buf, buf, len); | |
1314 | buf += len; | |
1315 | cnt -= len; | |
1316 | /* push data from aligned buffer into fifo */ | |
1317 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1318 | mci_writel(host, DATA(host->data_offset), |
1319 | aligned_buf[i]); | |
34b664a2 JH |
1320 | } |
1321 | } else | |
1322 | #endif | |
1323 | { | |
1324 | u32 *pdata = buf; | |
1325 | for (; cnt >= 4; cnt -= 4) | |
4e0a5adf | 1326 | mci_writel(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1327 | buf = pdata; |
1328 | } | |
1329 | /* put anything remaining in the part_buf */ | |
1330 | if (cnt) { | |
1331 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1332 | /* Push data if we have reached the expected data length */ |
1333 | if ((data->bytes_xfered + init_cnt) == | |
1334 | (data->blksz * data->blocks)) | |
4e0a5adf | 1335 | mci_writel(host, DATA(host->data_offset), |
cfbeb59c | 1336 | host->part_buf32); |
f95f3850 WN |
1337 | } |
1338 | } | |
1339 | ||
1340 | static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) | |
1341 | { | |
34b664a2 JH |
1342 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1343 | if (unlikely((unsigned long)buf & 0x3)) { | |
1344 | while (cnt >= 4) { | |
1345 | /* pull data from fifo into aligned buffer */ | |
1346 | u32 aligned_buf[32]; | |
1347 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1348 | int items = len >> 2; | |
1349 | int i; | |
1350 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1351 | aligned_buf[i] = mci_readl(host, |
1352 | DATA(host->data_offset)); | |
34b664a2 JH |
1353 | /* memcpy from aligned buffer into output buffer */ |
1354 | memcpy(buf, aligned_buf, len); | |
1355 | buf += len; | |
1356 | cnt -= len; | |
1357 | } | |
1358 | } else | |
1359 | #endif | |
1360 | { | |
1361 | u32 *pdata = buf; | |
1362 | for (; cnt >= 4; cnt -= 4) | |
4e0a5adf | 1363 | *pdata++ = mci_readl(host, DATA(host->data_offset)); |
34b664a2 JH |
1364 | buf = pdata; |
1365 | } | |
1366 | if (cnt) { | |
4e0a5adf | 1367 | host->part_buf32 = mci_readl(host, DATA(host->data_offset)); |
34b664a2 | 1368 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1369 | } |
1370 | } | |
1371 | ||
1372 | static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) | |
1373 | { | |
cfbeb59c MC |
1374 | struct mmc_data *data = host->data; |
1375 | int init_cnt = cnt; | |
1376 | ||
34b664a2 JH |
1377 | /* try and push anything in the part_buf */ |
1378 | if (unlikely(host->part_buf_count)) { | |
1379 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1380 | buf += len; | |
1381 | cnt -= len; | |
c09fbd74 | 1382 | |
cfbeb59c | 1383 | if (host->part_buf_count == 8) { |
c09fbd74 | 1384 | mci_writeq(host, DATA(host->data_offset), |
4e0a5adf | 1385 | host->part_buf); |
34b664a2 JH |
1386 | host->part_buf_count = 0; |
1387 | } | |
1388 | } | |
1389 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1390 | if (unlikely((unsigned long)buf & 0x7)) { | |
1391 | while (cnt >= 8) { | |
1392 | u64 aligned_buf[16]; | |
1393 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1394 | int items = len >> 3; | |
1395 | int i; | |
1396 | /* memcpy from input buffer into aligned buffer */ | |
1397 | memcpy(aligned_buf, buf, len); | |
1398 | buf += len; | |
1399 | cnt -= len; | |
1400 | /* push data from aligned buffer into fifo */ | |
1401 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1402 | mci_writeq(host, DATA(host->data_offset), |
1403 | aligned_buf[i]); | |
34b664a2 JH |
1404 | } |
1405 | } else | |
1406 | #endif | |
1407 | { | |
1408 | u64 *pdata = buf; | |
1409 | for (; cnt >= 8; cnt -= 8) | |
4e0a5adf | 1410 | mci_writeq(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1411 | buf = pdata; |
1412 | } | |
1413 | /* put anything remaining in the part_buf */ | |
1414 | if (cnt) { | |
1415 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1416 | /* Push data if we have reached the expected data length */ |
1417 | if ((data->bytes_xfered + init_cnt) == | |
1418 | (data->blksz * data->blocks)) | |
4e0a5adf | 1419 | mci_writeq(host, DATA(host->data_offset), |
cfbeb59c | 1420 | host->part_buf); |
f95f3850 WN |
1421 | } |
1422 | } | |
1423 | ||
1424 | static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) | |
1425 | { | |
34b664a2 JH |
1426 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1427 | if (unlikely((unsigned long)buf & 0x7)) { | |
1428 | while (cnt >= 8) { | |
1429 | /* pull data from fifo into aligned buffer */ | |
1430 | u64 aligned_buf[16]; | |
1431 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1432 | int items = len >> 3; | |
1433 | int i; | |
1434 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1435 | aligned_buf[i] = mci_readq(host, |
1436 | DATA(host->data_offset)); | |
34b664a2 JH |
1437 | /* memcpy from aligned buffer into output buffer */ |
1438 | memcpy(buf, aligned_buf, len); | |
1439 | buf += len; | |
1440 | cnt -= len; | |
1441 | } | |
1442 | } else | |
1443 | #endif | |
1444 | { | |
1445 | u64 *pdata = buf; | |
1446 | for (; cnt >= 8; cnt -= 8) | |
4e0a5adf | 1447 | *pdata++ = mci_readq(host, DATA(host->data_offset)); |
34b664a2 JH |
1448 | buf = pdata; |
1449 | } | |
1450 | if (cnt) { | |
4e0a5adf | 1451 | host->part_buf = mci_readq(host, DATA(host->data_offset)); |
34b664a2 JH |
1452 | dw_mci_pull_final_bytes(host, buf, cnt); |
1453 | } | |
1454 | } | |
f95f3850 | 1455 | |
34b664a2 JH |
1456 | static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) |
1457 | { | |
1458 | int len; | |
f95f3850 | 1459 | |
34b664a2 JH |
1460 | /* get remaining partial bytes */ |
1461 | len = dw_mci_pull_part_bytes(host, buf, cnt); | |
1462 | if (unlikely(len == cnt)) | |
1463 | return; | |
1464 | buf += len; | |
1465 | cnt -= len; | |
1466 | ||
1467 | /* get the rest of the data */ | |
1468 | host->pull_data(host, buf, cnt); | |
f95f3850 WN |
1469 | } |
1470 | ||
87a74d39 | 1471 | static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) |
f95f3850 | 1472 | { |
f9c2a0dc SJ |
1473 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
1474 | void *buf; | |
1475 | unsigned int offset; | |
f95f3850 WN |
1476 | struct mmc_data *data = host->data; |
1477 | int shift = host->data_shift; | |
1478 | u32 status; | |
3e4b0d8b | 1479 | unsigned int len; |
f9c2a0dc | 1480 | unsigned int remain, fcnt; |
f95f3850 WN |
1481 | |
1482 | do { | |
f9c2a0dc SJ |
1483 | if (!sg_miter_next(sg_miter)) |
1484 | goto done; | |
1485 | ||
4225fc85 | 1486 | host->sg = sg_miter->piter.sg; |
f9c2a0dc SJ |
1487 | buf = sg_miter->addr; |
1488 | remain = sg_miter->length; | |
1489 | offset = 0; | |
1490 | ||
1491 | do { | |
1492 | fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) | |
1493 | << shift) + host->part_buf_count; | |
1494 | len = min(remain, fcnt); | |
1495 | if (!len) | |
1496 | break; | |
34b664a2 | 1497 | dw_mci_pull_data(host, (void *)(buf + offset), len); |
3e4b0d8b | 1498 | data->bytes_xfered += len; |
f95f3850 | 1499 | offset += len; |
f9c2a0dc SJ |
1500 | remain -= len; |
1501 | } while (remain); | |
f95f3850 | 1502 | |
e74f3a9c | 1503 | sg_miter->consumed = offset; |
f95f3850 WN |
1504 | status = mci_readl(host, MINTSTS); |
1505 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
87a74d39 KK |
1506 | /* if the RXDR is ready read again */ |
1507 | } while ((status & SDMMC_INT_RXDR) || | |
1508 | (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); | |
f9c2a0dc SJ |
1509 | |
1510 | if (!remain) { | |
1511 | if (!sg_miter_next(sg_miter)) | |
1512 | goto done; | |
1513 | sg_miter->consumed = 0; | |
1514 | } | |
1515 | sg_miter_stop(sg_miter); | |
f95f3850 WN |
1516 | return; |
1517 | ||
1518 | done: | |
f9c2a0dc SJ |
1519 | sg_miter_stop(sg_miter); |
1520 | host->sg = NULL; | |
f95f3850 WN |
1521 | smp_wmb(); |
1522 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
1523 | } | |
1524 | ||
1525 | static void dw_mci_write_data_pio(struct dw_mci *host) | |
1526 | { | |
f9c2a0dc SJ |
1527 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
1528 | void *buf; | |
1529 | unsigned int offset; | |
f95f3850 WN |
1530 | struct mmc_data *data = host->data; |
1531 | int shift = host->data_shift; | |
1532 | u32 status; | |
3e4b0d8b | 1533 | unsigned int len; |
f9c2a0dc SJ |
1534 | unsigned int fifo_depth = host->fifo_depth; |
1535 | unsigned int remain, fcnt; | |
f95f3850 WN |
1536 | |
1537 | do { | |
f9c2a0dc SJ |
1538 | if (!sg_miter_next(sg_miter)) |
1539 | goto done; | |
1540 | ||
4225fc85 | 1541 | host->sg = sg_miter->piter.sg; |
f9c2a0dc SJ |
1542 | buf = sg_miter->addr; |
1543 | remain = sg_miter->length; | |
1544 | offset = 0; | |
1545 | ||
1546 | do { | |
1547 | fcnt = ((fifo_depth - | |
1548 | SDMMC_GET_FCNT(mci_readl(host, STATUS))) | |
1549 | << shift) - host->part_buf_count; | |
1550 | len = min(remain, fcnt); | |
1551 | if (!len) | |
1552 | break; | |
f95f3850 | 1553 | host->push_data(host, (void *)(buf + offset), len); |
3e4b0d8b | 1554 | data->bytes_xfered += len; |
f95f3850 | 1555 | offset += len; |
f9c2a0dc SJ |
1556 | remain -= len; |
1557 | } while (remain); | |
f95f3850 | 1558 | |
e74f3a9c | 1559 | sg_miter->consumed = offset; |
f95f3850 WN |
1560 | status = mci_readl(host, MINTSTS); |
1561 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
f95f3850 | 1562 | } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ |
f9c2a0dc SJ |
1563 | |
1564 | if (!remain) { | |
1565 | if (!sg_miter_next(sg_miter)) | |
1566 | goto done; | |
1567 | sg_miter->consumed = 0; | |
1568 | } | |
1569 | sg_miter_stop(sg_miter); | |
f95f3850 WN |
1570 | return; |
1571 | ||
1572 | done: | |
f9c2a0dc SJ |
1573 | sg_miter_stop(sg_miter); |
1574 | host->sg = NULL; | |
f95f3850 WN |
1575 | smp_wmb(); |
1576 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
1577 | } | |
1578 | ||
1579 | static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) | |
1580 | { | |
1581 | if (!host->cmd_status) | |
1582 | host->cmd_status = status; | |
1583 | ||
1584 | smp_wmb(); | |
1585 | ||
1586 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
1587 | tasklet_schedule(&host->tasklet); | |
1588 | } | |
1589 | ||
1590 | static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) | |
1591 | { | |
1592 | struct dw_mci *host = dev_id; | |
182c9081 | 1593 | u32 pending; |
1a5c8e1f | 1594 | int i; |
f95f3850 | 1595 | |
1fb5f68a MC |
1596 | pending = mci_readl(host, MINTSTS); /* read-only mask reg */ |
1597 | ||
1598 | if (pending) { | |
f95f3850 WN |
1599 | |
1600 | /* | |
1601 | * DTO fix - version 2.10a and below, and only if internal DMA | |
1602 | * is configured. | |
1603 | */ | |
1604 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { | |
1605 | if (!pending && | |
1606 | ((mci_readl(host, STATUS) >> 17) & 0x1fff)) | |
1607 | pending |= SDMMC_INT_DATA_OVER; | |
1608 | } | |
1609 | ||
f95f3850 WN |
1610 | if (pending & DW_MCI_CMD_ERROR_FLAGS) { |
1611 | mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); | |
182c9081 | 1612 | host->cmd_status = pending; |
f95f3850 WN |
1613 | smp_wmb(); |
1614 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
f95f3850 WN |
1615 | } |
1616 | ||
1617 | if (pending & DW_MCI_DATA_ERROR_FLAGS) { | |
1618 | /* if there is an error report DATA_ERROR */ | |
1619 | mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); | |
182c9081 | 1620 | host->data_status = pending; |
f95f3850 WN |
1621 | smp_wmb(); |
1622 | set_bit(EVENT_DATA_ERROR, &host->pending_events); | |
9b2026a1 | 1623 | tasklet_schedule(&host->tasklet); |
f95f3850 WN |
1624 | } |
1625 | ||
1626 | if (pending & SDMMC_INT_DATA_OVER) { | |
1627 | mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); | |
1628 | if (!host->data_status) | |
182c9081 | 1629 | host->data_status = pending; |
f95f3850 WN |
1630 | smp_wmb(); |
1631 | if (host->dir_status == DW_MCI_RECV_STATUS) { | |
1632 | if (host->sg != NULL) | |
87a74d39 | 1633 | dw_mci_read_data_pio(host, true); |
f95f3850 WN |
1634 | } |
1635 | set_bit(EVENT_DATA_COMPLETE, &host->pending_events); | |
1636 | tasklet_schedule(&host->tasklet); | |
1637 | } | |
1638 | ||
1639 | if (pending & SDMMC_INT_RXDR) { | |
1640 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
b40af3aa | 1641 | if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) |
87a74d39 | 1642 | dw_mci_read_data_pio(host, false); |
f95f3850 WN |
1643 | } |
1644 | ||
1645 | if (pending & SDMMC_INT_TXDR) { | |
1646 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
b40af3aa | 1647 | if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) |
f95f3850 WN |
1648 | dw_mci_write_data_pio(host); |
1649 | } | |
1650 | ||
1651 | if (pending & SDMMC_INT_CMD_DONE) { | |
1652 | mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); | |
182c9081 | 1653 | dw_mci_cmd_interrupt(host, pending); |
f95f3850 WN |
1654 | } |
1655 | ||
1656 | if (pending & SDMMC_INT_CD) { | |
1657 | mci_writel(host, RINTSTS, SDMMC_INT_CD); | |
95dcc2cb | 1658 | queue_work(host->card_workqueue, &host->card_work); |
f95f3850 WN |
1659 | } |
1660 | ||
1a5c8e1f SH |
1661 | /* Handle SDIO Interrupts */ |
1662 | for (i = 0; i < host->num_slots; i++) { | |
1663 | struct dw_mci_slot *slot = host->slot[i]; | |
1664 | if (pending & SDMMC_INT_SDIO(i)) { | |
1665 | mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i)); | |
1666 | mmc_signal_sdio_irq(slot->mmc); | |
1667 | } | |
1668 | } | |
1669 | ||
1fb5f68a | 1670 | } |
f95f3850 WN |
1671 | |
1672 | #ifdef CONFIG_MMC_DW_IDMAC | |
1673 | /* Handle DMA interrupts */ | |
1674 | pending = mci_readl(host, IDSTS); | |
1675 | if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { | |
1676 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI); | |
1677 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); | |
f95f3850 WN |
1678 | host->dma_ops->complete(host); |
1679 | } | |
1680 | #endif | |
1681 | ||
1682 | return IRQ_HANDLED; | |
1683 | } | |
1684 | ||
1791b13e | 1685 | static void dw_mci_work_routine_card(struct work_struct *work) |
f95f3850 | 1686 | { |
1791b13e | 1687 | struct dw_mci *host = container_of(work, struct dw_mci, card_work); |
f95f3850 WN |
1688 | int i; |
1689 | ||
1690 | for (i = 0; i < host->num_slots; i++) { | |
1691 | struct dw_mci_slot *slot = host->slot[i]; | |
1692 | struct mmc_host *mmc = slot->mmc; | |
1693 | struct mmc_request *mrq; | |
1694 | int present; | |
1695 | u32 ctrl; | |
1696 | ||
1697 | present = dw_mci_get_cd(mmc); | |
1698 | while (present != slot->last_detect_state) { | |
f95f3850 WN |
1699 | dev_dbg(&slot->mmc->class_dev, "card %s\n", |
1700 | present ? "inserted" : "removed"); | |
1701 | ||
1791b13e JH |
1702 | spin_lock_bh(&host->lock); |
1703 | ||
f95f3850 WN |
1704 | /* Card change detected */ |
1705 | slot->last_detect_state = present; | |
1706 | ||
1791b13e JH |
1707 | /* Mark card as present if applicable */ |
1708 | if (present != 0) | |
f95f3850 | 1709 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); |
f95f3850 WN |
1710 | |
1711 | /* Clean up queue if present */ | |
1712 | mrq = slot->mrq; | |
1713 | if (mrq) { | |
1714 | if (mrq == host->mrq) { | |
1715 | host->data = NULL; | |
1716 | host->cmd = NULL; | |
1717 | ||
1718 | switch (host->state) { | |
1719 | case STATE_IDLE: | |
1720 | break; | |
1721 | case STATE_SENDING_CMD: | |
1722 | mrq->cmd->error = -ENOMEDIUM; | |
1723 | if (!mrq->data) | |
1724 | break; | |
1725 | /* fall through */ | |
1726 | case STATE_SENDING_DATA: | |
1727 | mrq->data->error = -ENOMEDIUM; | |
1728 | dw_mci_stop_dma(host); | |
1729 | break; | |
1730 | case STATE_DATA_BUSY: | |
1731 | case STATE_DATA_ERROR: | |
1732 | if (mrq->data->error == -EINPROGRESS) | |
1733 | mrq->data->error = -ENOMEDIUM; | |
1734 | if (!mrq->stop) | |
1735 | break; | |
1736 | /* fall through */ | |
1737 | case STATE_SENDING_STOP: | |
1738 | mrq->stop->error = -ENOMEDIUM; | |
1739 | break; | |
1740 | } | |
1741 | ||
1742 | dw_mci_request_end(host, mrq); | |
1743 | } else { | |
1744 | list_del(&slot->queue_node); | |
1745 | mrq->cmd->error = -ENOMEDIUM; | |
1746 | if (mrq->data) | |
1747 | mrq->data->error = -ENOMEDIUM; | |
1748 | if (mrq->stop) | |
1749 | mrq->stop->error = -ENOMEDIUM; | |
1750 | ||
1751 | spin_unlock(&host->lock); | |
1752 | mmc_request_done(slot->mmc, mrq); | |
1753 | spin_lock(&host->lock); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | /* Power down slot */ | |
1758 | if (present == 0) { | |
f95f3850 WN |
1759 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); |
1760 | ||
1761 | /* | |
1762 | * Clear down the FIFO - doing so generates a | |
1763 | * block interrupt, hence setting the | |
1764 | * scatter-gather pointer to NULL. | |
1765 | */ | |
f9c2a0dc | 1766 | sg_miter_stop(&host->sg_miter); |
f95f3850 WN |
1767 | host->sg = NULL; |
1768 | ||
1769 | ctrl = mci_readl(host, CTRL); | |
1770 | ctrl |= SDMMC_CTRL_FIFO_RESET; | |
1771 | mci_writel(host, CTRL, ctrl); | |
1772 | ||
1773 | #ifdef CONFIG_MMC_DW_IDMAC | |
1774 | ctrl = mci_readl(host, BMOD); | |
141a712a SJ |
1775 | /* Software reset of DMA */ |
1776 | ctrl |= SDMMC_IDMAC_SWRESET; | |
f95f3850 WN |
1777 | mci_writel(host, BMOD, ctrl); |
1778 | #endif | |
1779 | ||
1780 | } | |
1781 | ||
1791b13e JH |
1782 | spin_unlock_bh(&host->lock); |
1783 | ||
f95f3850 WN |
1784 | present = dw_mci_get_cd(mmc); |
1785 | } | |
1786 | ||
1787 | mmc_detect_change(slot->mmc, | |
1788 | msecs_to_jiffies(host->pdata->detect_delay_ms)); | |
1789 | } | |
1790 | } | |
1791 | ||
c91eab4b TA |
1792 | #ifdef CONFIG_OF |
1793 | /* given a slot id, find out the device node representing that slot */ | |
1794 | static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) | |
1795 | { | |
1796 | struct device_node *np; | |
1797 | const __be32 *addr; | |
1798 | int len; | |
1799 | ||
1800 | if (!dev || !dev->of_node) | |
1801 | return NULL; | |
1802 | ||
1803 | for_each_child_of_node(dev->of_node, np) { | |
1804 | addr = of_get_property(np, "reg", &len); | |
1805 | if (!addr || (len < sizeof(int))) | |
1806 | continue; | |
1807 | if (be32_to_cpup(addr) == slot) | |
1808 | return np; | |
1809 | } | |
1810 | return NULL; | |
1811 | } | |
1812 | ||
a70aaa64 DA |
1813 | static struct dw_mci_of_slot_quirks { |
1814 | char *quirk; | |
1815 | int id; | |
1816 | } of_slot_quirks[] = { | |
1817 | { | |
1818 | .quirk = "disable-wp", | |
1819 | .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, | |
1820 | }, | |
1821 | }; | |
1822 | ||
1823 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) | |
1824 | { | |
1825 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | |
1826 | int quirks = 0; | |
1827 | int idx; | |
1828 | ||
1829 | /* get quirks */ | |
1830 | for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) | |
1831 | if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) | |
1832 | quirks |= of_slot_quirks[idx].id; | |
1833 | ||
1834 | return quirks; | |
1835 | } | |
1836 | ||
c91eab4b TA |
1837 | /* find out bus-width for a given slot */ |
1838 | static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) | |
1839 | { | |
1840 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | |
1841 | u32 bus_wd = 1; | |
1842 | ||
1843 | if (!np) | |
1844 | return 1; | |
1845 | ||
1846 | if (of_property_read_u32(np, "bus-width", &bus_wd)) | |
1847 | dev_err(dev, "bus-width property not found, assuming width" | |
1848 | " as 1\n"); | |
1849 | return bus_wd; | |
1850 | } | |
55a6ceb2 DA |
1851 | |
1852 | /* find the write protect gpio for a given slot; or -1 if none specified */ | |
1853 | static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) | |
1854 | { | |
1855 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | |
1856 | int gpio; | |
1857 | ||
1858 | if (!np) | |
1859 | return -EINVAL; | |
1860 | ||
1861 | gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
1862 | ||
1863 | /* Having a missing entry is valid; return silently */ | |
1864 | if (!gpio_is_valid(gpio)) | |
1865 | return -EINVAL; | |
1866 | ||
1867 | if (devm_gpio_request(dev, gpio, "dw-mci-wp")) { | |
1868 | dev_warn(dev, "gpio [%d] request failed\n", gpio); | |
1869 | return -EINVAL; | |
1870 | } | |
1871 | ||
1872 | return gpio; | |
1873 | } | |
c91eab4b | 1874 | #else /* CONFIG_OF */ |
a70aaa64 DA |
1875 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) |
1876 | { | |
1877 | return 0; | |
1878 | } | |
c91eab4b TA |
1879 | static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) |
1880 | { | |
1881 | return 1; | |
1882 | } | |
1883 | static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) | |
1884 | { | |
1885 | return NULL; | |
1886 | } | |
55a6ceb2 DA |
1887 | static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) |
1888 | { | |
1889 | return -EINVAL; | |
1890 | } | |
c91eab4b TA |
1891 | #endif /* CONFIG_OF */ |
1892 | ||
36c179a9 | 1893 | static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) |
f95f3850 WN |
1894 | { |
1895 | struct mmc_host *mmc; | |
1896 | struct dw_mci_slot *slot; | |
e95baf13 | 1897 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
800d78bf | 1898 | int ctrl_id, ret; |
c91eab4b | 1899 | u8 bus_width; |
f95f3850 | 1900 | |
4a90920c | 1901 | mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); |
f95f3850 WN |
1902 | if (!mmc) |
1903 | return -ENOMEM; | |
1904 | ||
1905 | slot = mmc_priv(mmc); | |
1906 | slot->id = id; | |
1907 | slot->mmc = mmc; | |
1908 | slot->host = host; | |
c91eab4b | 1909 | host->slot[id] = slot; |
f95f3850 | 1910 | |
a70aaa64 DA |
1911 | slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); |
1912 | ||
f95f3850 WN |
1913 | mmc->ops = &dw_mci_ops; |
1914 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); | |
1915 | mmc->f_max = host->bus_hz; | |
1916 | ||
1917 | if (host->pdata->get_ocr) | |
1918 | mmc->ocr_avail = host->pdata->get_ocr(id); | |
1919 | else | |
1920 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
1921 | ||
1922 | /* | |
1923 | * Start with slot power disabled, it will be enabled when a card | |
1924 | * is detected. | |
1925 | */ | |
1926 | if (host->pdata->setpower) | |
1927 | host->pdata->setpower(id, 0); | |
1928 | ||
fc3d7720 JC |
1929 | if (host->pdata->caps) |
1930 | mmc->caps = host->pdata->caps; | |
fc3d7720 | 1931 | |
ab269128 AK |
1932 | if (host->pdata->pm_caps) |
1933 | mmc->pm_caps = host->pdata->pm_caps; | |
1934 | ||
800d78bf TA |
1935 | if (host->dev->of_node) { |
1936 | ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); | |
1937 | if (ctrl_id < 0) | |
1938 | ctrl_id = 0; | |
1939 | } else { | |
1940 | ctrl_id = to_platform_device(host->dev)->id; | |
1941 | } | |
cb27a843 JH |
1942 | if (drv_data && drv_data->caps) |
1943 | mmc->caps |= drv_data->caps[ctrl_id]; | |
800d78bf | 1944 | |
4f408cc6 SJ |
1945 | if (host->pdata->caps2) |
1946 | mmc->caps2 = host->pdata->caps2; | |
4f408cc6 | 1947 | |
f95f3850 | 1948 | if (host->pdata->get_bus_wd) |
c91eab4b TA |
1949 | bus_width = host->pdata->get_bus_wd(slot->id); |
1950 | else if (host->dev->of_node) | |
1951 | bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id); | |
1952 | else | |
1953 | bus_width = 1; | |
1954 | ||
cb27a843 | 1955 | if (drv_data && drv_data->setup_bus) { |
800d78bf TA |
1956 | struct device_node *slot_np; |
1957 | slot_np = dw_mci_of_find_slot_node(host->dev, slot->id); | |
cb27a843 | 1958 | ret = drv_data->setup_bus(host, slot_np, bus_width); |
800d78bf TA |
1959 | if (ret) |
1960 | goto err_setup_bus; | |
1961 | } | |
1962 | ||
c91eab4b TA |
1963 | switch (bus_width) { |
1964 | case 8: | |
1965 | mmc->caps |= MMC_CAP_8_BIT_DATA; | |
1966 | case 4: | |
1967 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1968 | } | |
f95f3850 WN |
1969 | |
1970 | if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) | |
6daa7778 | 1971 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
f95f3850 | 1972 | |
f95f3850 WN |
1973 | if (host->pdata->blk_settings) { |
1974 | mmc->max_segs = host->pdata->blk_settings->max_segs; | |
1975 | mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; | |
1976 | mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; | |
1977 | mmc->max_req_size = host->pdata->blk_settings->max_req_size; | |
1978 | mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; | |
1979 | } else { | |
1980 | /* Useful defaults if platform data is unset. */ | |
a39e5746 JC |
1981 | #ifdef CONFIG_MMC_DW_IDMAC |
1982 | mmc->max_segs = host->ring_size; | |
1983 | mmc->max_blk_size = 65536; | |
1984 | mmc->max_blk_count = host->ring_size; | |
1985 | mmc->max_seg_size = 0x1000; | |
1986 | mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; | |
1987 | #else | |
f95f3850 WN |
1988 | mmc->max_segs = 64; |
1989 | mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ | |
1990 | mmc->max_blk_count = 512; | |
1991 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1992 | mmc->max_seg_size = mmc->max_req_size; | |
f95f3850 | 1993 | #endif /* CONFIG_MMC_DW_IDMAC */ |
a39e5746 | 1994 | } |
f95f3850 | 1995 | |
780f22af | 1996 | host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc"); |
c07946a3 | 1997 | if (IS_ERR(host->vmmc)) { |
a3c76eb9 | 1998 | pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc)); |
c07946a3 | 1999 | host->vmmc = NULL; |
f2f942ce SK |
2000 | } else { |
2001 | ret = regulator_enable(host->vmmc); | |
2002 | if (ret) { | |
2003 | dev_err(host->dev, | |
2004 | "failed to enable regulator: %d\n", ret); | |
2005 | goto err_setup_bus; | |
2006 | } | |
2007 | } | |
c07946a3 | 2008 | |
f95f3850 WN |
2009 | if (dw_mci_get_cd(mmc)) |
2010 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
2011 | else | |
2012 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
2013 | ||
55a6ceb2 DA |
2014 | slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id); |
2015 | ||
0cea529d JC |
2016 | ret = mmc_add_host(mmc); |
2017 | if (ret) | |
2018 | goto err_setup_bus; | |
f95f3850 WN |
2019 | |
2020 | #if defined(CONFIG_DEBUG_FS) | |
2021 | dw_mci_init_debugfs(slot); | |
2022 | #endif | |
2023 | ||
2024 | /* Card initially undetected */ | |
2025 | slot->last_detect_state = 0; | |
2026 | ||
dd6c4b98 WN |
2027 | /* |
2028 | * Card may have been plugged in prior to boot so we | |
2029 | * need to run the detect tasklet | |
2030 | */ | |
95dcc2cb | 2031 | queue_work(host->card_workqueue, &host->card_work); |
dd6c4b98 | 2032 | |
f95f3850 | 2033 | return 0; |
800d78bf TA |
2034 | |
2035 | err_setup_bus: | |
2036 | mmc_free_host(mmc); | |
2037 | return -EINVAL; | |
f95f3850 WN |
2038 | } |
2039 | ||
2040 | static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) | |
2041 | { | |
2042 | /* Shutdown detect IRQ */ | |
2043 | if (slot->host->pdata->exit) | |
2044 | slot->host->pdata->exit(id); | |
2045 | ||
2046 | /* Debugfs stuff is cleaned up by mmc core */ | |
2047 | mmc_remove_host(slot->mmc); | |
2048 | slot->host->slot[id] = NULL; | |
2049 | mmc_free_host(slot->mmc); | |
2050 | } | |
2051 | ||
2052 | static void dw_mci_init_dma(struct dw_mci *host) | |
2053 | { | |
2054 | /* Alloc memory for sg translation */ | |
780f22af | 2055 | host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, |
f95f3850 WN |
2056 | &host->sg_dma, GFP_KERNEL); |
2057 | if (!host->sg_cpu) { | |
4a90920c | 2058 | dev_err(host->dev, "%s: could not alloc DMA memory\n", |
f95f3850 WN |
2059 | __func__); |
2060 | goto no_dma; | |
2061 | } | |
2062 | ||
2063 | /* Determine which DMA interface to use */ | |
2064 | #ifdef CONFIG_MMC_DW_IDMAC | |
2065 | host->dma_ops = &dw_mci_idmac_ops; | |
00956ea3 | 2066 | dev_info(host->dev, "Using internal DMA controller.\n"); |
f95f3850 WN |
2067 | #endif |
2068 | ||
2069 | if (!host->dma_ops) | |
2070 | goto no_dma; | |
2071 | ||
e1631f98 JC |
2072 | if (host->dma_ops->init && host->dma_ops->start && |
2073 | host->dma_ops->stop && host->dma_ops->cleanup) { | |
f95f3850 | 2074 | if (host->dma_ops->init(host)) { |
4a90920c | 2075 | dev_err(host->dev, "%s: Unable to initialize " |
f95f3850 WN |
2076 | "DMA Controller.\n", __func__); |
2077 | goto no_dma; | |
2078 | } | |
2079 | } else { | |
4a90920c | 2080 | dev_err(host->dev, "DMA initialization not found.\n"); |
f95f3850 WN |
2081 | goto no_dma; |
2082 | } | |
2083 | ||
2084 | host->use_dma = 1; | |
2085 | return; | |
2086 | ||
2087 | no_dma: | |
4a90920c | 2088 | dev_info(host->dev, "Using PIO mode.\n"); |
f95f3850 WN |
2089 | host->use_dma = 0; |
2090 | return; | |
2091 | } | |
2092 | ||
2093 | static bool mci_wait_reset(struct device *dev, struct dw_mci *host) | |
2094 | { | |
2095 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
2096 | unsigned int ctrl; | |
2097 | ||
2098 | mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | | |
2099 | SDMMC_CTRL_DMA_RESET)); | |
2100 | ||
2101 | /* wait till resets clear */ | |
2102 | do { | |
2103 | ctrl = mci_readl(host, CTRL); | |
2104 | if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | | |
2105 | SDMMC_CTRL_DMA_RESET))) | |
2106 | return true; | |
2107 | } while (time_before(jiffies, timeout)); | |
2108 | ||
2109 | dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl); | |
2110 | ||
2111 | return false; | |
2112 | } | |
2113 | ||
c91eab4b TA |
2114 | #ifdef CONFIG_OF |
2115 | static struct dw_mci_of_quirks { | |
2116 | char *quirk; | |
2117 | int id; | |
2118 | } of_quirks[] = { | |
2119 | { | |
2120 | .quirk = "supports-highspeed", | |
2121 | .id = DW_MCI_QUIRK_HIGHSPEED, | |
2122 | }, { | |
2123 | .quirk = "broken-cd", | |
2124 | .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, | |
2125 | }, | |
2126 | }; | |
2127 | ||
2128 | static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) | |
2129 | { | |
2130 | struct dw_mci_board *pdata; | |
2131 | struct device *dev = host->dev; | |
2132 | struct device_node *np = dev->of_node; | |
e95baf13 | 2133 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
800d78bf | 2134 | int idx, ret; |
c91eab4b TA |
2135 | |
2136 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
2137 | if (!pdata) { | |
2138 | dev_err(dev, "could not allocate memory for pdata\n"); | |
2139 | return ERR_PTR(-ENOMEM); | |
2140 | } | |
2141 | ||
2142 | /* find out number of slots supported */ | |
2143 | if (of_property_read_u32(dev->of_node, "num-slots", | |
2144 | &pdata->num_slots)) { | |
2145 | dev_info(dev, "num-slots property not found, " | |
2146 | "assuming 1 slot is available\n"); | |
2147 | pdata->num_slots = 1; | |
2148 | } | |
2149 | ||
2150 | /* get quirks */ | |
2151 | for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) | |
2152 | if (of_get_property(np, of_quirks[idx].quirk, NULL)) | |
2153 | pdata->quirks |= of_quirks[idx].id; | |
2154 | ||
2155 | if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) | |
2156 | dev_info(dev, "fifo-depth property not found, using " | |
2157 | "value of FIFOTH register as default\n"); | |
2158 | ||
2159 | of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); | |
2160 | ||
cb27a843 JH |
2161 | if (drv_data && drv_data->parse_dt) { |
2162 | ret = drv_data->parse_dt(host); | |
800d78bf TA |
2163 | if (ret) |
2164 | return ERR_PTR(ret); | |
2165 | } | |
2166 | ||
ab269128 AK |
2167 | if (of_find_property(np, "keep-power-in-suspend", NULL)) |
2168 | pdata->pm_caps |= MMC_PM_KEEP_POWER; | |
2169 | ||
2170 | if (of_find_property(np, "enable-sdio-wakeup", NULL)) | |
2171 | pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; | |
2172 | ||
c91eab4b TA |
2173 | return pdata; |
2174 | } | |
2175 | ||
2176 | #else /* CONFIG_OF */ | |
2177 | static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) | |
2178 | { | |
2179 | return ERR_PTR(-EINVAL); | |
2180 | } | |
2181 | #endif /* CONFIG_OF */ | |
2182 | ||
62ca8034 | 2183 | int dw_mci_probe(struct dw_mci *host) |
f95f3850 | 2184 | { |
e95baf13 | 2185 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
62ca8034 | 2186 | int width, i, ret = 0; |
f95f3850 | 2187 | u32 fifo_size; |
1c2215b7 | 2188 | int init_slots = 0; |
f95f3850 | 2189 | |
c91eab4b TA |
2190 | if (!host->pdata) { |
2191 | host->pdata = dw_mci_parse_dt(host); | |
2192 | if (IS_ERR(host->pdata)) { | |
2193 | dev_err(host->dev, "platform data not available\n"); | |
2194 | return -EINVAL; | |
2195 | } | |
f95f3850 WN |
2196 | } |
2197 | ||
62ca8034 | 2198 | if (!host->pdata->select_slot && host->pdata->num_slots > 1) { |
4a90920c | 2199 | dev_err(host->dev, |
f95f3850 | 2200 | "Platform data must supply select_slot function\n"); |
62ca8034 | 2201 | return -ENODEV; |
f95f3850 WN |
2202 | } |
2203 | ||
780f22af | 2204 | host->biu_clk = devm_clk_get(host->dev, "biu"); |
f90a0612 TA |
2205 | if (IS_ERR(host->biu_clk)) { |
2206 | dev_dbg(host->dev, "biu clock not available\n"); | |
2207 | } else { | |
2208 | ret = clk_prepare_enable(host->biu_clk); | |
2209 | if (ret) { | |
2210 | dev_err(host->dev, "failed to enable biu clock\n"); | |
f90a0612 TA |
2211 | return ret; |
2212 | } | |
2213 | } | |
2214 | ||
780f22af | 2215 | host->ciu_clk = devm_clk_get(host->dev, "ciu"); |
f90a0612 TA |
2216 | if (IS_ERR(host->ciu_clk)) { |
2217 | dev_dbg(host->dev, "ciu clock not available\n"); | |
2218 | } else { | |
2219 | ret = clk_prepare_enable(host->ciu_clk); | |
2220 | if (ret) { | |
2221 | dev_err(host->dev, "failed to enable ciu clock\n"); | |
f90a0612 TA |
2222 | goto err_clk_biu; |
2223 | } | |
2224 | } | |
2225 | ||
2226 | if (IS_ERR(host->ciu_clk)) | |
2227 | host->bus_hz = host->pdata->bus_hz; | |
2228 | else | |
2229 | host->bus_hz = clk_get_rate(host->ciu_clk); | |
2230 | ||
cb27a843 JH |
2231 | if (drv_data && drv_data->setup_clock) { |
2232 | ret = drv_data->setup_clock(host); | |
800d78bf TA |
2233 | if (ret) { |
2234 | dev_err(host->dev, | |
2235 | "implementation specific clock setup failed\n"); | |
2236 | goto err_clk_ciu; | |
2237 | } | |
2238 | } | |
2239 | ||
f90a0612 | 2240 | if (!host->bus_hz) { |
4a90920c | 2241 | dev_err(host->dev, |
f95f3850 | 2242 | "Platform data must supply bus speed\n"); |
f90a0612 TA |
2243 | ret = -ENODEV; |
2244 | goto err_clk_ciu; | |
f95f3850 WN |
2245 | } |
2246 | ||
62ca8034 | 2247 | host->quirks = host->pdata->quirks; |
f95f3850 WN |
2248 | |
2249 | spin_lock_init(&host->lock); | |
2250 | INIT_LIST_HEAD(&host->queue); | |
2251 | ||
f95f3850 WN |
2252 | /* |
2253 | * Get the host data width - this assumes that HCON has been set with | |
2254 | * the correct values. | |
2255 | */ | |
2256 | i = (mci_readl(host, HCON) >> 7) & 0x7; | |
2257 | if (!i) { | |
2258 | host->push_data = dw_mci_push_data16; | |
2259 | host->pull_data = dw_mci_pull_data16; | |
2260 | width = 16; | |
2261 | host->data_shift = 1; | |
2262 | } else if (i == 2) { | |
2263 | host->push_data = dw_mci_push_data64; | |
2264 | host->pull_data = dw_mci_pull_data64; | |
2265 | width = 64; | |
2266 | host->data_shift = 3; | |
2267 | } else { | |
2268 | /* Check for a reserved value, and warn if it is */ | |
2269 | WARN((i != 1), | |
2270 | "HCON reports a reserved host data width!\n" | |
2271 | "Defaulting to 32-bit access.\n"); | |
2272 | host->push_data = dw_mci_push_data32; | |
2273 | host->pull_data = dw_mci_pull_data32; | |
2274 | width = 32; | |
2275 | host->data_shift = 2; | |
2276 | } | |
2277 | ||
2278 | /* Reset all blocks */ | |
4a90920c | 2279 | if (!mci_wait_reset(host->dev, host)) |
141a712a SJ |
2280 | return -ENODEV; |
2281 | ||
2282 | host->dma_ops = host->pdata->dma_ops; | |
2283 | dw_mci_init_dma(host); | |
f95f3850 WN |
2284 | |
2285 | /* Clear the interrupts for the host controller */ | |
2286 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2287 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
2288 | ||
2289 | /* Put in max timeout */ | |
2290 | mci_writel(host, TMOUT, 0xFFFFFFFF); | |
2291 | ||
2292 | /* | |
2293 | * FIFO threshold settings RxMark = fifo_size / 2 - 1, | |
2294 | * Tx Mark = fifo_size / 2 DMA Size = 8 | |
2295 | */ | |
b86d8253 JH |
2296 | if (!host->pdata->fifo_depth) { |
2297 | /* | |
2298 | * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may | |
2299 | * have been overwritten by the bootloader, just like we're | |
2300 | * about to do, so if you know the value for your hardware, you | |
2301 | * should put it in the platform data. | |
2302 | */ | |
2303 | fifo_size = mci_readl(host, FIFOTH); | |
8234e869 | 2304 | fifo_size = 1 + ((fifo_size >> 16) & 0xfff); |
b86d8253 JH |
2305 | } else { |
2306 | fifo_size = host->pdata->fifo_depth; | |
2307 | } | |
2308 | host->fifo_depth = fifo_size; | |
e61cf118 JC |
2309 | host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | |
2310 | ((fifo_size/2) << 0)); | |
2311 | mci_writel(host, FIFOTH, host->fifoth_val); | |
f95f3850 WN |
2312 | |
2313 | /* disable clock to CIU */ | |
2314 | mci_writel(host, CLKENA, 0); | |
2315 | mci_writel(host, CLKSRC, 0); | |
2316 | ||
63008768 JH |
2317 | /* |
2318 | * In 2.40a spec, Data offset is changed. | |
2319 | * Need to check the version-id and set data-offset for DATA register. | |
2320 | */ | |
2321 | host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); | |
2322 | dev_info(host->dev, "Version ID is %04x\n", host->verid); | |
2323 | ||
2324 | if (host->verid < DW_MMC_240A) | |
2325 | host->data_offset = DATA_OFFSET; | |
2326 | else | |
2327 | host->data_offset = DATA_240A_OFFSET; | |
2328 | ||
f95f3850 | 2329 | tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); |
95dcc2cb | 2330 | host->card_workqueue = alloc_workqueue("dw-mci-card", |
1791b13e | 2331 | WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1); |
95dcc2cb | 2332 | if (!host->card_workqueue) |
1791b13e JH |
2333 | goto err_dmaunmap; |
2334 | INIT_WORK(&host->card_work, dw_mci_work_routine_card); | |
780f22af SJ |
2335 | ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, |
2336 | host->irq_flags, "dw-mci", host); | |
f95f3850 | 2337 | if (ret) |
1791b13e | 2338 | goto err_workqueue; |
f95f3850 | 2339 | |
f95f3850 WN |
2340 | if (host->pdata->num_slots) |
2341 | host->num_slots = host->pdata->num_slots; | |
2342 | else | |
2343 | host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; | |
2344 | ||
2da1d7f2 YC |
2345 | /* |
2346 | * Enable interrupts for command done, data over, data empty, card det, | |
2347 | * receive ready and error such as transmit, receive timeout, crc error | |
2348 | */ | |
2349 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2350 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
2351 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
2352 | DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); | |
2353 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ | |
2354 | ||
2355 | dev_info(host->dev, "DW MMC controller at irq %d, " | |
2356 | "%d bit host data width, " | |
2357 | "%u deep fifo\n", | |
2358 | host->irq, width, fifo_size); | |
2359 | ||
f95f3850 WN |
2360 | /* We need at least one slot to succeed */ |
2361 | for (i = 0; i < host->num_slots; i++) { | |
2362 | ret = dw_mci_init_slot(host, i); | |
1c2215b7 TA |
2363 | if (ret) |
2364 | dev_dbg(host->dev, "slot %d init failed\n", i); | |
2365 | else | |
2366 | init_slots++; | |
2367 | } | |
2368 | ||
2369 | if (init_slots) { | |
2370 | dev_info(host->dev, "%d slots initialized\n", init_slots); | |
2371 | } else { | |
2372 | dev_dbg(host->dev, "attempted to initialize %d slots, " | |
2373 | "but failed on all\n", host->num_slots); | |
780f22af | 2374 | goto err_workqueue; |
f95f3850 WN |
2375 | } |
2376 | ||
f95f3850 | 2377 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) |
4a90920c | 2378 | dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); |
f95f3850 WN |
2379 | |
2380 | return 0; | |
2381 | ||
1791b13e | 2382 | err_workqueue: |
95dcc2cb | 2383 | destroy_workqueue(host->card_workqueue); |
1791b13e | 2384 | |
f95f3850 WN |
2385 | err_dmaunmap: |
2386 | if (host->use_dma && host->dma_ops->exit) | |
2387 | host->dma_ops->exit(host); | |
f95f3850 | 2388 | |
780f22af | 2389 | if (host->vmmc) |
c07946a3 | 2390 | regulator_disable(host->vmmc); |
f90a0612 TA |
2391 | |
2392 | err_clk_ciu: | |
780f22af | 2393 | if (!IS_ERR(host->ciu_clk)) |
f90a0612 | 2394 | clk_disable_unprepare(host->ciu_clk); |
780f22af | 2395 | |
f90a0612 | 2396 | err_clk_biu: |
780f22af | 2397 | if (!IS_ERR(host->biu_clk)) |
f90a0612 | 2398 | clk_disable_unprepare(host->biu_clk); |
780f22af | 2399 | |
f95f3850 WN |
2400 | return ret; |
2401 | } | |
62ca8034 | 2402 | EXPORT_SYMBOL(dw_mci_probe); |
f95f3850 | 2403 | |
62ca8034 | 2404 | void dw_mci_remove(struct dw_mci *host) |
f95f3850 | 2405 | { |
f95f3850 WN |
2406 | int i; |
2407 | ||
2408 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2409 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
2410 | ||
f95f3850 | 2411 | for (i = 0; i < host->num_slots; i++) { |
4a90920c | 2412 | dev_dbg(host->dev, "remove slot %d\n", i); |
f95f3850 WN |
2413 | if (host->slot[i]) |
2414 | dw_mci_cleanup_slot(host->slot[i], i); | |
2415 | } | |
2416 | ||
2417 | /* disable clock to CIU */ | |
2418 | mci_writel(host, CLKENA, 0); | |
2419 | mci_writel(host, CLKSRC, 0); | |
2420 | ||
95dcc2cb | 2421 | destroy_workqueue(host->card_workqueue); |
f95f3850 WN |
2422 | |
2423 | if (host->use_dma && host->dma_ops->exit) | |
2424 | host->dma_ops->exit(host); | |
2425 | ||
780f22af | 2426 | if (host->vmmc) |
c07946a3 | 2427 | regulator_disable(host->vmmc); |
c07946a3 | 2428 | |
f90a0612 TA |
2429 | if (!IS_ERR(host->ciu_clk)) |
2430 | clk_disable_unprepare(host->ciu_clk); | |
780f22af | 2431 | |
f90a0612 TA |
2432 | if (!IS_ERR(host->biu_clk)) |
2433 | clk_disable_unprepare(host->biu_clk); | |
f95f3850 | 2434 | } |
62ca8034 SH |
2435 | EXPORT_SYMBOL(dw_mci_remove); |
2436 | ||
2437 | ||
f95f3850 | 2438 | |
6fe8890d | 2439 | #ifdef CONFIG_PM_SLEEP |
f95f3850 WN |
2440 | /* |
2441 | * TODO: we should probably disable the clock to the card in the suspend path. | |
2442 | */ | |
62ca8034 | 2443 | int dw_mci_suspend(struct dw_mci *host) |
f95f3850 | 2444 | { |
62ca8034 | 2445 | int i, ret = 0; |
f95f3850 WN |
2446 | |
2447 | for (i = 0; i < host->num_slots; i++) { | |
2448 | struct dw_mci_slot *slot = host->slot[i]; | |
2449 | if (!slot) | |
2450 | continue; | |
2451 | ret = mmc_suspend_host(slot->mmc); | |
2452 | if (ret < 0) { | |
2453 | while (--i >= 0) { | |
2454 | slot = host->slot[i]; | |
2455 | if (slot) | |
2456 | mmc_resume_host(host->slot[i]->mmc); | |
2457 | } | |
2458 | return ret; | |
2459 | } | |
2460 | } | |
2461 | ||
c07946a3 JC |
2462 | if (host->vmmc) |
2463 | regulator_disable(host->vmmc); | |
2464 | ||
f95f3850 WN |
2465 | return 0; |
2466 | } | |
62ca8034 | 2467 | EXPORT_SYMBOL(dw_mci_suspend); |
f95f3850 | 2468 | |
62ca8034 | 2469 | int dw_mci_resume(struct dw_mci *host) |
f95f3850 WN |
2470 | { |
2471 | int i, ret; | |
f95f3850 | 2472 | |
f2f942ce SK |
2473 | if (host->vmmc) { |
2474 | ret = regulator_enable(host->vmmc); | |
2475 | if (ret) { | |
2476 | dev_err(host->dev, | |
2477 | "failed to enable regulator: %d\n", ret); | |
2478 | return ret; | |
2479 | } | |
2480 | } | |
1d6c4e0a | 2481 | |
4a90920c | 2482 | if (!mci_wait_reset(host->dev, host)) { |
e61cf118 JC |
2483 | ret = -ENODEV; |
2484 | return ret; | |
2485 | } | |
2486 | ||
3bfe619d | 2487 | if (host->use_dma && host->dma_ops->init) |
141a712a SJ |
2488 | host->dma_ops->init(host); |
2489 | ||
e61cf118 JC |
2490 | /* Restore the old value at FIFOTH register */ |
2491 | mci_writel(host, FIFOTH, host->fifoth_val); | |
2492 | ||
2493 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2494 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
2495 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
2496 | DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); | |
2497 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); | |
2498 | ||
f95f3850 WN |
2499 | for (i = 0; i < host->num_slots; i++) { |
2500 | struct dw_mci_slot *slot = host->slot[i]; | |
2501 | if (!slot) | |
2502 | continue; | |
ab269128 AK |
2503 | if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { |
2504 | dw_mci_set_ios(slot->mmc, &slot->mmc->ios); | |
2505 | dw_mci_setup_bus(slot, true); | |
2506 | } | |
2507 | ||
f95f3850 WN |
2508 | ret = mmc_resume_host(host->slot[i]->mmc); |
2509 | if (ret < 0) | |
2510 | return ret; | |
2511 | } | |
f95f3850 WN |
2512 | return 0; |
2513 | } | |
62ca8034 | 2514 | EXPORT_SYMBOL(dw_mci_resume); |
6fe8890d JC |
2515 | #endif /* CONFIG_PM_SLEEP */ |
2516 | ||
f95f3850 WN |
2517 | static int __init dw_mci_init(void) |
2518 | { | |
62ca8034 SH |
2519 | printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver"); |
2520 | return 0; | |
f95f3850 WN |
2521 | } |
2522 | ||
2523 | static void __exit dw_mci_exit(void) | |
2524 | { | |
f95f3850 WN |
2525 | } |
2526 | ||
2527 | module_init(dw_mci_init); | |
2528 | module_exit(dw_mci_exit); | |
2529 | ||
2530 | MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); | |
2531 | MODULE_AUTHOR("NXP Semiconductor VietNam"); | |
2532 | MODULE_AUTHOR("Imagination Technologies Ltd"); | |
2533 | MODULE_LICENSE("GPL v2"); |