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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...
[deliverable/linux.git] / drivers / mmc / host / omap.c
CommitLineData
730c9b7e 1/*
70f10482 2 * linux/drivers/mmc/host/omap.c
730c9b7e
CA		 3 *
4 * Copyright (C) 2004 Nokia Corporation
d36b6910 5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
730c9b7e
CA		 6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
730c9b7e
CA		 14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
3451c067 20#include <linux/dmaengine.h>
730c9b7e
CA		 21#include <linux/dma-mapping.h>
22#include <linux/delay.h>
23#include <linux/spinlock.h>
24#include <linux/timer.h>
9cb238c0 25#include <linux/of.h>
3451c067 26#include <linux/omap-dma.h>
730c9b7e 27#include <linux/mmc/host.h>
730c9b7e 28#include <linux/mmc/card.h>
b13d1f0f 29#include <linux/mmc/mmc.h>
730c9b7e 30#include <linux/clk.h>
45711f1a 31#include <linux/scatterlist.h>
5a0e3ad6 32#include <linux/slab.h>
68f39e74 33#include <linux/platform_data/mmc-omap.h>
730c9b7e 34
730c9b7e 35
0551f4df 36#define OMAP_MMC_REG_CMD 0x00
0e950fa6
MB		 37#define OMAP_MMC_REG_ARGL 0x01
38#define OMAP_MMC_REG_ARGH 0x02
39#define OMAP_MMC_REG_CON 0x03
40#define OMAP_MMC_REG_STAT 0x04
41#define OMAP_MMC_REG_IE 0x05
42#define OMAP_MMC_REG_CTO 0x06
43#define OMAP_MMC_REG_DTO 0x07
44#define OMAP_MMC_REG_DATA 0x08
45#define OMAP_MMC_REG_BLEN 0x09
46#define OMAP_MMC_REG_NBLK 0x0a
47#define OMAP_MMC_REG_BUF 0x0b
48#define OMAP_MMC_REG_SDIO 0x0d
49#define OMAP_MMC_REG_REV 0x0f
50#define OMAP_MMC_REG_RSP0 0x10
51#define OMAP_MMC_REG_RSP1 0x11
52#define OMAP_MMC_REG_RSP2 0x12
53#define OMAP_MMC_REG_RSP3 0x13
54#define OMAP_MMC_REG_RSP4 0x14
55#define OMAP_MMC_REG_RSP5 0x15
56#define OMAP_MMC_REG_RSP6 0x16
57#define OMAP_MMC_REG_RSP7 0x17
58#define OMAP_MMC_REG_IOSR 0x18
59#define OMAP_MMC_REG_SYSC 0x19
60#define OMAP_MMC_REG_SYSS 0x1a
0551f4df
JY		 61
62#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
63#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
64#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
65#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
66#define OMAP_MMC_STAT_A_FULL (1 << 10)
67#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
68#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
69#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
70#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
71#define OMAP_MMC_STAT_END_BUSY (1 << 4)
72#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
73#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
74#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
75
53db20d1
TL		 76#define mmc_omap7xx() (host->features & MMC_OMAP7XX)
77#define mmc_omap15xx() (host->features & MMC_OMAP15XX)
78#define mmc_omap16xx() (host->features & MMC_OMAP16XX)
79#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
80#define mmc_omap1() (host->features & MMC_OMAP1_MASK)
81#define mmc_omap2() (!mmc_omap1())
82
0e950fa6
MB		 83#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
84#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
85#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
0551f4df
JY		 86
87/*
88 * Command types
89 */
90#define OMAP_MMC_CMDTYPE_BC 0
91#define OMAP_MMC_CMDTYPE_BCR 1
92#define OMAP_MMC_CMDTYPE_AC 2
93#define OMAP_MMC_CMDTYPE_ADTC 3
94
730c9b7e 95#define DRIVER_NAME "mmci-omap"
730c9b7e
CA		 96
97/* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
7584d276 99#define OMAP_MMC_COVER_POLL_DELAY 500
730c9b7e 100
abfbe5f7
JY		 101struct mmc_omap_host;
102
103struct mmc_omap_slot {
104 int id;
105 unsigned int vdd;
106 u16 saved_con;
107 u16 bus_mode;
108 unsigned int fclk_freq;
abfbe5f7 109
7584d276
JL		 110 struct tasklet_struct cover_tasklet;
111 struct timer_list cover_timer;
5a0f3f1f
JY		 112 unsigned cover_open;
113
abfbe5f7
JY		 114 struct mmc_request *mrq;
115 struct mmc_omap_host *host;
116 struct mmc_host *mmc;
117 struct omap_mmc_slot_data *pdata;
118};
119
730c9b7e
CA		 120struct mmc_omap_host {
121 int initialized;
730c9b7e
CA		 122 struct mmc_request * mrq;
123 struct mmc_command * cmd;
124 struct mmc_data * data;
125 struct mmc_host * mmc;
126 struct device * dev;
127 unsigned char id; /* 16xx chips have 2 MMC blocks */
128 struct clk * iclk;
129 struct clk * fclk;
3451c067
RK		 130 struct dma_chan *dma_rx;
131 u32 dma_rx_burst;
132 struct dma_chan *dma_tx;
133 u32 dma_tx_burst;
89783b1e
JY		 134 void __iomem *virt_base;
135 unsigned int phys_base;
730c9b7e
CA		 136 int irq;
137 unsigned char bus_mode;
0e950fa6 138 unsigned int reg_shift;
730c9b7e 139
0fb4723d
JL		 140 struct work_struct cmd_abort_work;
141 unsigned abort:1;
142 struct timer_list cmd_abort_timer;
eb1860bc 143
0f602ec7
JL		 144 struct work_struct slot_release_work;
145 struct mmc_omap_slot *next_slot;
146 struct work_struct send_stop_work;
147 struct mmc_data *stop_data;
148
730c9b7e
CA		 149 unsigned int sg_len;
150 int sg_idx;
151 u16 * buffer;
152 u32 buffer_bytes_left;
153 u32 total_bytes_left;
154
53db20d1 155 unsigned features;
730c9b7e 156 unsigned brs_received:1, dma_done:1;
730c9b7e 157 unsigned dma_in_use:1;
3451c067 158 spinlock_t dma_lock;
730c9b7e 159
abfbe5f7
JY		 160 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
161 struct mmc_omap_slot *current_slot;
162 spinlock_t slot_lock;
163 wait_queue_head_t slot_wq;
164 int nr_slots;
165
0807a9b5
JL		 166 struct timer_list clk_timer;
167 spinlock_t clk_lock; /* for changing enabled state */
168 unsigned int fclk_enabled:1;
b01a4f1c 169 struct workqueue_struct *mmc_omap_wq;
0807a9b5 170
abfbe5f7 171 struct omap_mmc_platform_data *pdata;
730c9b7e
CA		 172};
173
0d9ee5b2 174
7c8ad982 175static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
0807a9b5
JL		 176{
177 unsigned long tick_ns;
178
179 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
03a16853 180 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
0807a9b5
JL		 181 ndelay(8 * tick_ns);
182 }
183}
184
7c8ad982 185static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
0807a9b5
JL		 186{
187 unsigned long flags;
188
189 spin_lock_irqsave(&host->clk_lock, flags);
190 if (host->fclk_enabled != enable) {
191 host->fclk_enabled = enable;
192 if (enable)
193 clk_enable(host->fclk);
194 else
195 clk_disable(host->fclk);
196 }
197 spin_unlock_irqrestore(&host->clk_lock, flags);
198}
199
abfbe5f7
JY		 200static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
201{
202 struct mmc_omap_host *host = slot->host;
203 unsigned long flags;
204
205 if (claimed)
206 goto no_claim;
207 spin_lock_irqsave(&host->slot_lock, flags);
208 while (host->mmc != NULL) {
209 spin_unlock_irqrestore(&host->slot_lock, flags);
210 wait_event(host->slot_wq, host->mmc == NULL);
211 spin_lock_irqsave(&host->slot_lock, flags);
212 }
213 host->mmc = slot->mmc;
214 spin_unlock_irqrestore(&host->slot_lock, flags);
215no_claim:
0807a9b5
JL		 216 del_timer(&host->clk_timer);
217 if (host->current_slot != slot || !claimed)
218 mmc_omap_fclk_offdelay(host->current_slot);
219
abfbe5f7 220 if (host->current_slot != slot) {
0807a9b5 221 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
abfbe5f7
JY		 222 if (host->pdata->switch_slot != NULL)
223 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
224 host->current_slot = slot;
225 }
226
0807a9b5
JL		 227 if (claimed) {
228 mmc_omap_fclk_enable(host, 1);
229
230 /* Doing the dummy read here seems to work around some bug
231 * at least in OMAP24xx silicon where the command would not
232 * start after writing the CMD register. Sigh. */
233 OMAP_MMC_READ(host, CON);
abfbe5f7 234
0807a9b5
JL		 235 OMAP_MMC_WRITE(host, CON, slot->saved_con);
236 } else
237 mmc_omap_fclk_enable(host, 0);
abfbe5f7
JY		 238}
239
240static void mmc_omap_start_request(struct mmc_omap_host *host,
241 struct mmc_request *req);
242
0f602ec7
JL		 243static void mmc_omap_slot_release_work(struct work_struct *work)
244{
245 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
246 slot_release_work);
247 struct mmc_omap_slot *next_slot = host->next_slot;
248 struct mmc_request *rq;
249
250 host->next_slot = NULL;
251 mmc_omap_select_slot(next_slot, 1);
252
253 rq = next_slot->mrq;
254 next_slot->mrq = NULL;
255 mmc_omap_start_request(host, rq);
256}
257
0807a9b5 258static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
abfbe5f7
JY		 259{
260 struct mmc_omap_host *host = slot->host;
261 unsigned long flags;
262 int i;
263
264 BUG_ON(slot == NULL || host->mmc == NULL);
0807a9b5
JL		 265
266 if (clk_enabled)
267 /* Keeps clock running for at least 8 cycles on valid freq */
268 mod_timer(&host->clk_timer, jiffies + HZ/10);
269 else {
270 del_timer(&host->clk_timer);
271 mmc_omap_fclk_offdelay(slot);
272 mmc_omap_fclk_enable(host, 0);
273 }
abfbe5f7
JY		 274
275 spin_lock_irqsave(&host->slot_lock, flags);
276 /* Check for any pending requests */
277 for (i = 0; i < host->nr_slots; i++) {
278 struct mmc_omap_slot *new_slot;
abfbe5f7
JY		 279
280 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
281 continue;
282
0f602ec7 283 BUG_ON(host->next_slot != NULL);
abfbe5f7
JY		 284 new_slot = host->slots[i];
285 /* The current slot should not have a request in queue */
286 BUG_ON(new_slot == host->current_slot);
287
0f602ec7 288 host->next_slot = new_slot;
abfbe5f7
JY		 289 host->mmc = new_slot->mmc;
290 spin_unlock_irqrestore(&host->slot_lock, flags);
b01a4f1c 291 queue_work(host->mmc_omap_wq, &host->slot_release_work);
abfbe5f7
JY		 292 return;
293 }
294
295 host->mmc = NULL;
296 wake_up(&host->slot_wq);
297 spin_unlock_irqrestore(&host->slot_lock, flags);
298}
299
5a0f3f1f
JY		 300static inline
301int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
302{
8348f002
KP		 303 if (slot->pdata->get_cover_state)
304 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
305 slot->id);
306 return 0;
5a0f3f1f
JY		 307}
308
309static ssize_t
310mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
311 char *buf)
312{
313 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
314 struct mmc_omap_slot *slot = mmc_priv(mmc);
315
316 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
317 "closed");
318}
319
320static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
321
abfbe5f7
JY		 322static ssize_t
323mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
324 char *buf)
325{
326 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
327 struct mmc_omap_slot *slot = mmc_priv(mmc);
328
329 return sprintf(buf, "%s\n", slot->pdata->name);
330}
331
332static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
333
730c9b7e
CA		 334static void
335mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
336{
337 u32 cmdreg;
338 u32 resptype;
339 u32 cmdtype;
b13d1f0f 340 u16 irq_mask;
730c9b7e
CA		 341
342 host->cmd = cmd;
343
344 resptype = 0;
345 cmdtype = 0;
346
347 /* Our hardware needs to know exact type */
1b3b2631
CEA		 348 switch (mmc_resp_type(cmd)) {
349 case MMC_RSP_NONE:
350 break;
351 case MMC_RSP_R1:
352 case MMC_RSP_R1B:
6f949909 353 /* resp 1, 1b, 6, 7 */
730c9b7e
CA		 354 resptype = 1;
355 break;
1b3b2631 356 case MMC_RSP_R2:
730c9b7e
CA		 357 resptype = 2;
358 break;
1b3b2631 359 case MMC_RSP_R3:
730c9b7e
CA		 360 resptype = 3;
361 break;
362 default:
1b3b2631 363 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
730c9b7e
CA		 364 break;
365 }
366
367 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
368 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
369 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
370 cmdtype = OMAP_MMC_CMDTYPE_BC;
371 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
372 cmdtype = OMAP_MMC_CMDTYPE_BCR;
373 } else {
374 cmdtype = OMAP_MMC_CMDTYPE_AC;
375 }
376
377 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
378
abfbe5f7 379 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
730c9b7e
CA		 380 cmdreg |= 1 << 6;
381
382 if (cmd->flags & MMC_RSP_BUSY)
383 cmdreg |= 1 << 11;
384
385 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
386 cmdreg |= 1 << 15;
387
0fb4723d 388 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
eb1860bc 389
3342ee8b
JY		 390 OMAP_MMC_WRITE(host, CTO, 200);
391 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
392 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
b13d1f0f
JN		 393 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
394 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
395 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
396 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
397 OMAP_MMC_STAT_END_OF_DATA;
398 if (cmd->opcode == MMC_ERASE)
399 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
400 OMAP_MMC_WRITE(host, IE, irq_mask);
3342ee8b 401 OMAP_MMC_WRITE(host, CMD, cmdreg);
730c9b7e
CA		 402}
403
a914ded2
JY		 404static void
405mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
406 int abort)
407{
408 enum dma_data_direction dma_data_dir;
3451c067
RK		 409 struct device *dev = mmc_dev(host->mmc);
410 struct dma_chan *c;
a914ded2 411
3451c067 412 if (data->flags & MMC_DATA_WRITE) {
a914ded2 413 dma_data_dir = DMA_TO_DEVICE;
3451c067
RK		 414 c = host->dma_tx;
415 } else {
a914ded2 416 dma_data_dir = DMA_FROM_DEVICE;
3451c067
RK		 417 c = host->dma_rx;
418 }
419 if (c) {
420 if (data->error) {
421 dmaengine_terminate_all(c);
422 /* Claim nothing transferred on error... */
423 data->bytes_xfered = 0;
424 }
425 dev = c->device->dev;
426 }
427 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
a914ded2
JY		 428}
429
0f602ec7
JL		 430static void mmc_omap_send_stop_work(struct work_struct *work)
431{
432 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
433 send_stop_work);
434 struct mmc_omap_slot *slot = host->current_slot;
435 struct mmc_data *data = host->stop_data;
436 unsigned long tick_ns;
437
03a16853 438 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
0f602ec7
JL		 439 ndelay(8*tick_ns);
440
441 mmc_omap_start_command(host, data->stop);
442}
443
730c9b7e
CA		 444static void
445mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
446{
a914ded2
JY		 447 if (host->dma_in_use)
448 mmc_omap_release_dma(host, data, data->error);
449
730c9b7e
CA		 450 host->data = NULL;
451 host->sg_len = 0;
730c9b7e
CA		 452
453 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
454 * dozens of requests until the card finishes writing data.
455 * It'd be cheaper to just wait till an EOFB interrupt arrives...
456 */
457
458 if (!data->stop) {
a914ded2
JY		 459 struct mmc_host *mmc;
460
730c9b7e 461 host->mrq = NULL;
a914ded2 462 mmc = host->mmc;
0807a9b5 463 mmc_omap_release_slot(host->current_slot, 1);
a914ded2 464 mmc_request_done(mmc, data->mrq);
730c9b7e
CA		 465 return;
466 }
467
0f602ec7 468 host->stop_data = data;
b01a4f1c 469 queue_work(host->mmc_omap_wq, &host->send_stop_work);
730c9b7e
CA		 470}
471
eb1860bc 472static void
0fb4723d 473mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
eb1860bc
JL		 474{
475 struct mmc_omap_slot *slot = host->current_slot;
476 unsigned int restarts, passes, timeout;
477 u16 stat = 0;
478
479 /* Sending abort takes 80 clocks. Have some extra and round up */
03a16853 480 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
eb1860bc 481 restarts = 0;
0fb4723d 482 while (restarts < maxloops) {
eb1860bc
JL		 483 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
484 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
485
486 passes = 0;
487 while (passes < timeout) {
488 stat = OMAP_MMC_READ(host, STAT);
489 if (stat & OMAP_MMC_STAT_END_OF_CMD)
490 goto out;
491 udelay(1);
492 passes++;
493 }
494
495 restarts++;
496 }
497out:
498 OMAP_MMC_WRITE(host, STAT, stat);
499}
500
a914ded2
JY		 501static void
502mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
503{
a914ded2
JY		 504 if (host->dma_in_use)
505 mmc_omap_release_dma(host, data, 1);
506
507 host->data = NULL;
508 host->sg_len = 0;
509
0fb4723d 510 mmc_omap_send_abort(host, 10000);
a914ded2
JY		 511}
512
730c9b7e
CA		 513static void
514mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
515{
516 unsigned long flags;
517 int done;
518
519 if (!host->dma_in_use) {
520 mmc_omap_xfer_done(host, data);
521 return;
522 }
523 done = 0;
524 spin_lock_irqsave(&host->dma_lock, flags);
525 if (host->dma_done)
526 done = 1;
527 else
528 host->brs_received = 1;
529 spin_unlock_irqrestore(&host->dma_lock, flags);
530 if (done)
531 mmc_omap_xfer_done(host, data);
532}
533
730c9b7e
CA		 534static void
535mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
536{
537 unsigned long flags;
538 int done;
539
540 done = 0;
541 spin_lock_irqsave(&host->dma_lock, flags);
542 if (host->brs_received)
543 done = 1;
544 else
545 host->dma_done = 1;
546 spin_unlock_irqrestore(&host->dma_lock, flags);
547 if (done)
548 mmc_omap_xfer_done(host, data);
549}
550
551static void
552mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
553{
554 host->cmd = NULL;
555
0fb4723d 556 del_timer(&host->cmd_abort_timer);
eb1860bc 557
730c9b7e
CA		 558 if (cmd->flags & MMC_RSP_PRESENT) {
559 if (cmd->flags & MMC_RSP_136) {
560 /* response type 2 */
561 cmd->resp[3] =
3342ee8b
JY		 562 OMAP_MMC_READ(host, RSP0) |
563 (OMAP_MMC_READ(host, RSP1) << 16);
730c9b7e 564 cmd->resp[2] =
3342ee8b
JY		 565 OMAP_MMC_READ(host, RSP2) |
566 (OMAP_MMC_READ(host, RSP3) << 16);
730c9b7e 567 cmd->resp[1] =
3342ee8b
JY		 568 OMAP_MMC_READ(host, RSP4) |
569 (OMAP_MMC_READ(host, RSP5) << 16);
730c9b7e 570 cmd->resp[0] =
3342ee8b
JY		 571 OMAP_MMC_READ(host, RSP6) |
572 (OMAP_MMC_READ(host, RSP7) << 16);
730c9b7e
CA		 573 } else {
574 /* response types 1, 1b, 3, 4, 5, 6 */
575 cmd->resp[0] =
3342ee8b
JY		 576 OMAP_MMC_READ(host, RSP6) |
577 (OMAP_MMC_READ(host, RSP7) << 16);
730c9b7e
CA		 578 }
579 }
580
17b0429d 581 if (host->data == NULL || cmd->error) {
a914ded2
JY		 582 struct mmc_host *mmc;
583
584 if (host->data != NULL)
585 mmc_omap_abort_xfer(host, host->data);
730c9b7e 586 host->mrq = NULL;
a914ded2 587 mmc = host->mmc;
0807a9b5 588 mmc_omap_release_slot(host->current_slot, 1);
a914ded2 589 mmc_request_done(mmc, cmd->mrq);
730c9b7e
CA		 590 }
591}
592
eb1860bc
JL		 593/*
594 * Abort stuck command. Can occur when card is removed while it is being
595 * read.
596 */
597static void mmc_omap_abort_command(struct work_struct *work)
598{
599 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
0fb4723d
JL		 600 cmd_abort_work);
601 BUG_ON(!host->cmd);
eb1860bc
JL		 602
603 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
604 host->cmd->opcode);
605
0fb4723d
JL		 606 if (host->cmd->error == 0)
607 host->cmd->error = -ETIMEDOUT;
eb1860bc 608
0fb4723d
JL		 609 if (host->data == NULL) {
610 struct mmc_command *cmd;
611 struct mmc_host *mmc;
612
613 cmd = host->cmd;
614 host->cmd = NULL;
615 mmc_omap_send_abort(host, 10000);
616
617 host->mrq = NULL;
618 mmc = host->mmc;
0807a9b5 619 mmc_omap_release_slot(host->current_slot, 1);
0fb4723d
JL		 620 mmc_request_done(mmc, cmd->mrq);
621 } else
622 mmc_omap_cmd_done(host, host->cmd);
eb1860bc 623
0fb4723d
JL		 624 host->abort = 0;
625 enable_irq(host->irq);
eb1860bc
JL		 626}
627
628static void
629mmc_omap_cmd_timer(unsigned long data)
630{
631 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
0fb4723d 632 unsigned long flags;
eb1860bc 633
0fb4723d
JL		 634 spin_lock_irqsave(&host->slot_lock, flags);
635 if (host->cmd != NULL && !host->abort) {
636 OMAP_MMC_WRITE(host, IE, 0);
637 disable_irq(host->irq);
638 host->abort = 1;
b01a4f1c 639 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0fb4723d
JL		 640 }
641 spin_unlock_irqrestore(&host->slot_lock, flags);
eb1860bc
JL		 642}
643
730c9b7e
CA		 644/* PIO only */
645static void
646mmc_omap_sg_to_buf(struct mmc_omap_host *host)
647{
648 struct scatterlist *sg;
649
650 sg = host->data->sg + host->sg_idx;
651 host->buffer_bytes_left = sg->length;
45711f1a 652 host->buffer = sg_virt(sg);
730c9b7e
CA		 653 if (host->buffer_bytes_left > host->total_bytes_left)
654 host->buffer_bytes_left = host->total_bytes_left;
655}
656
0807a9b5
JL		 657static void
658mmc_omap_clk_timer(unsigned long data)
659{
660 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
661
662 mmc_omap_fclk_enable(host, 0);
663}
664
730c9b7e
CA		 665/* PIO only */
666static void
667mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
668{
75b53aee 669 int n, nwords;
730c9b7e
CA		 670
671 if (host->buffer_bytes_left == 0) {
672 host->sg_idx++;
673 BUG_ON(host->sg_idx == host->sg_len);
674 mmc_omap_sg_to_buf(host);
675 }
676 n = 64;
677 if (n > host->buffer_bytes_left)
678 n = host->buffer_bytes_left;
75b53aee 679
03a16853
AL		 680 /* Round up to handle odd number of bytes to transfer */
681 nwords = DIV_ROUND_UP(n, 2);
75b53aee 682
730c9b7e
CA		 683 host->buffer_bytes_left -= n;
684 host->total_bytes_left -= n;
685 host->data->bytes_xfered += n;
686
687 if (write) {
75b53aee
PW		 688 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
689 host->buffer, nwords);
730c9b7e 690 } else {
75b53aee
PW		 691 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
692 host->buffer, nwords);
730c9b7e 693 }
75b53aee
PW		 694
695 host->buffer += nwords;
730c9b7e
CA		 696}
697
75d569d3
V		 698#ifdef CONFIG_MMC_DEBUG
699static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
730c9b7e
CA		 700{
701 static const char *mmc_omap_status_bits[] = {
702 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
703 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
704 };
75d569d3
V		 705 int i;
706 char res[64], *buf = res;
707
708 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
730c9b7e
CA		 709
710 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
75d569d3
V		 711 if (status & (1 << i))
712 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
713 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
714}
715#else
716static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
717{
730c9b7e 718}
75d569d3
V		 719#endif
720
730c9b7e 721
7d12e780 722static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
730c9b7e
CA		 723{
724 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
725 u16 status;
726 int end_command;
727 int end_transfer;
2a50b888 728 int transfer_error, cmd_error;
730c9b7e
CA		 729
730 if (host->cmd == NULL && host->data == NULL) {
3342ee8b 731 status = OMAP_MMC_READ(host, STAT);
2a50b888
JY		 732 dev_info(mmc_dev(host->slots[0]->mmc),
733 "Spurious IRQ 0x%04x\n", status);
730c9b7e 734 if (status != 0) {
3342ee8b
JY		 735 OMAP_MMC_WRITE(host, STAT, status);
736 OMAP_MMC_WRITE(host, IE, 0);
730c9b7e
CA		 737 }
738 return IRQ_HANDLED;
739 }
740
741 end_command = 0;
742 end_transfer = 0;
743 transfer_error = 0;
2a50b888 744 cmd_error = 0;
730c9b7e 745
3342ee8b 746 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
2a50b888
JY		 747 int cmd;
748
3342ee8b 749 OMAP_MMC_WRITE(host, STAT, status);
2a50b888
JY		 750 if (host->cmd != NULL)
751 cmd = host->cmd->opcode;
752 else
753 cmd = -1;
730c9b7e 754 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
2a50b888 755 status, cmd);
75d569d3
V		 756 mmc_omap_report_irq(host, status);
757
730c9b7e
CA		 758 if (host->total_bytes_left) {
759 if ((status & OMAP_MMC_STAT_A_FULL) ||
760 (status & OMAP_MMC_STAT_END_OF_DATA))
761 mmc_omap_xfer_data(host, 0);
762 if (status & OMAP_MMC_STAT_A_EMPTY)
763 mmc_omap_xfer_data(host, 1);
764 }
765
2a50b888 766 if (status & OMAP_MMC_STAT_END_OF_DATA)
730c9b7e 767 end_transfer = 1;
730c9b7e
CA		 768
769 if (status & OMAP_MMC_STAT_DATA_TOUT) {
2a50b888
JY		 770 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
771 cmd);
730c9b7e 772 if (host->data) {
17b0429d 773 host->data->error = -ETIMEDOUT;
730c9b7e
CA		 774 transfer_error = 1;
775 }
776 }
777
778 if (status & OMAP_MMC_STAT_DATA_CRC) {
779 if (host->data) {
17b0429d 780 host->data->error = -EILSEQ;
730c9b7e
CA		 781 dev_dbg(mmc_dev(host->mmc),
782 "data CRC error, bytes left %d\n",
783 host->total_bytes_left);
784 transfer_error = 1;
785 } else {
786 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
787 }
788 }
789
790 if (status & OMAP_MMC_STAT_CMD_TOUT) {
791 /* Timeouts are routine with some commands */
792 if (host->cmd) {
abfbe5f7
JY		 793 struct mmc_omap_slot *slot =
794 host->current_slot;
2a50b888
JY		 795 if (slot == NULL ||
796 !mmc_omap_cover_is_open(slot))
5a0f3f1f 797 dev_err(mmc_dev(host->mmc),
2a50b888
JY		 798 "command timeout (CMD%d)\n",
799 cmd);
17b0429d 800 host->cmd->error = -ETIMEDOUT;
730c9b7e 801 end_command = 1;
2a50b888 802 cmd_error = 1;
730c9b7e
CA		 803 }
804 }
805
806 if (status & OMAP_MMC_STAT_CMD_CRC) {
807 if (host->cmd) {
808 dev_err(mmc_dev(host->mmc),
809 "command CRC error (CMD%d, arg 0x%08x)\n",
2a50b888 810 cmd, host->cmd->arg);
17b0429d 811 host->cmd->error = -EILSEQ;
730c9b7e 812 end_command = 1;
2a50b888 813 cmd_error = 1;
730c9b7e
CA		 814 } else
815 dev_err(mmc_dev(host->mmc),
816 "command CRC error without cmd?\n");
817 }
818
819 if (status & OMAP_MMC_STAT_CARD_ERR) {
0107a4b3
RM		 820 dev_dbg(mmc_dev(host->mmc),
821 "ignoring card status error (CMD%d)\n",
2a50b888 822 cmd);
0107a4b3 823 end_command = 1;
730c9b7e
CA		 824 }
825
826 /*
827 * NOTE: On 1610 the END_OF_CMD may come too early when
2a50b888 828 * starting a write
730c9b7e
CA		 829 */
830 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
831 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
832 end_command = 1;
833 }
834 }
835
0fb4723d
JL		 836 if (cmd_error && host->data) {
837 del_timer(&host->cmd_abort_timer);
838 host->abort = 1;
839 OMAP_MMC_WRITE(host, IE, 0);
e749c6f2 840 disable_irq_nosync(host->irq);
b01a4f1c 841 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0fb4723d
JL		 842 return IRQ_HANDLED;
843 }
844
f6947514 845 if (end_command && host->cmd)
730c9b7e 846 mmc_omap_cmd_done(host, host->cmd);
2a50b888
JY		 847 if (host->data != NULL) {
848 if (transfer_error)
849 mmc_omap_xfer_done(host, host->data);
850 else if (end_transfer)
851 mmc_omap_end_of_data(host, host->data);
730c9b7e 852 }
730c9b7e
CA		 853
854 return IRQ_HANDLED;
855}
856
7584d276 857void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
5a0f3f1f 858{
7584d276 859 int cover_open;
5a0f3f1f 860 struct mmc_omap_host *host = dev_get_drvdata(dev);
7584d276 861 struct mmc_omap_slot *slot = host->slots[num];
5a0f3f1f 862
7584d276 863 BUG_ON(num >= host->nr_slots);
5a0f3f1f
JY		 864
865 /* Other subsystems can call in here before we're initialised. */
7584d276 866 if (host->nr_slots == 0 || !host->slots[num])
5a0f3f1f
JY		 867 return;
868
7584d276
JL		 869 cover_open = mmc_omap_cover_is_open(slot);
870 if (cover_open != slot->cover_open) {
871 slot->cover_open = cover_open;
872 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
873 }
874
875 tasklet_hi_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 876}
877
7584d276 878static void mmc_omap_cover_timer(unsigned long arg)
5a0f3f1f
JY		 879{
880 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
7584d276 881 tasklet_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 882}
883
7584d276 884static void mmc_omap_cover_handler(unsigned long param)
5a0f3f1f 885{
7584d276
JL		 886 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
887 int cover_open = mmc_omap_cover_is_open(slot);
5a0f3f1f 888
7584d276
JL		 889 mmc_detect_change(slot->mmc, 0);
890 if (!cover_open)
891 return;
892
893 /*
894 * If no card is inserted, we postpone polling until
895 * the cover has been closed.
896 */
897 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
898 return;
899
900 mod_timer(&slot->cover_timer,
901 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
5a0f3f1f
JY		 902}
903
3451c067
RK		 904static void mmc_omap_dma_callback(void *priv)
905{
906 struct mmc_omap_host *host = priv;
907 struct mmc_data *data = host->data;
908
909 /* If we got to the end of DMA, assume everything went well */
910 data->bytes_xfered += data->blocks * data->blksz;
911
912 mmc_omap_dma_done(host, data);
913}
914
730c9b7e
CA		 915static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
916{
917 u16 reg;
918
3342ee8b 919 reg = OMAP_MMC_READ(host, SDIO);
730c9b7e 920 reg &= ~(1 << 5);
3342ee8b 921 OMAP_MMC_WRITE(host, SDIO, reg);
730c9b7e 922 /* Set maximum timeout */
3342ee8b 923 OMAP_MMC_WRITE(host, CTO, 0xff);
730c9b7e
CA		 924}
925
926static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
927{
b8f9f0e9 928 unsigned int timeout, cycle_ns;
730c9b7e
CA		 929 u16 reg;
930
b8f9f0e9
JY		 931 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
932 timeout = req->data->timeout_ns / cycle_ns;
933 timeout += req->data->timeout_clks;
730c9b7e
CA		 934
935 /* Check if we need to use timeout multiplier register */
3342ee8b 936 reg = OMAP_MMC_READ(host, SDIO);
730c9b7e
CA		 937 if (timeout > 0xffff) {
938 reg |= (1 << 5);
939 timeout /= 1024;
940 } else
941 reg &= ~(1 << 5);
3342ee8b
JY		 942 OMAP_MMC_WRITE(host, SDIO, reg);
943 OMAP_MMC_WRITE(host, DTO, timeout);
730c9b7e
CA		 944}
945
946static void
947mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
948{
949 struct mmc_data *data = req->data;
a6c668fb 950 int i, use_dma = 1, block_size;
730c9b7e
CA		 951 unsigned sg_len;
952
953 host->data = data;
954 if (data == NULL) {
3342ee8b
JY		 955 OMAP_MMC_WRITE(host, BLEN, 0);
956 OMAP_MMC_WRITE(host, NBLK, 0);
957 OMAP_MMC_WRITE(host, BUF, 0);
730c9b7e
CA		 958 host->dma_in_use = 0;
959 set_cmd_timeout(host, req);
960 return;
961 }
962
a3fd4a1b 963 block_size = data->blksz;
730c9b7e 964
3342ee8b
JY		 965 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
966 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
730c9b7e
CA		 967 set_data_timeout(host, req);
968
969 /* cope with calling layer confusion; it issues "single
970 * block" writes using multi-block scatterlists.
971 */
972 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
973
974 /* Only do DMA for entire blocks */
a6c668fb
JN		 975 for (i = 0; i < sg_len; i++) {
976 if ((data->sg[i].length % block_size) != 0) {
977 use_dma = 0;
978 break;
730c9b7e
CA		 979 }
980 }
981
982 host->sg_idx = 0;
3451c067
RK		 983 if (use_dma) {
984 enum dma_data_direction dma_data_dir;
985 struct dma_async_tx_descriptor *tx;
986 struct dma_chan *c;
987 u32 burst, *bp;
988 u16 buf;
989
990 /*
991 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
992 * and 24xx. Use 16 or 32 word frames when the
993 * blocksize is at least that large. Blocksize is
994 * usually 512 bytes; but not for some SD reads.
995 */
53db20d1 996 burst = mmc_omap15xx() ? 32 : 64;
3451c067
RK		 997 if (burst > data->blksz)
998 burst = data->blksz;
999
1000 burst >>= 1;
1001
1002 if (data->flags & MMC_DATA_WRITE) {
1003 c = host->dma_tx;
1004 bp = &host->dma_tx_burst;
1005 buf = 0x0f80 | (burst - 1) << 0;
1006 dma_data_dir = DMA_TO_DEVICE;
1007 } else {
1008 c = host->dma_rx;
1009 bp = &host->dma_rx_burst;
1010 buf = 0x800f | (burst - 1) << 8;
1011 dma_data_dir = DMA_FROM_DEVICE;
1012 }
1013
1014 if (!c)
1015 goto use_pio;
1016
1017 /* Only reconfigure if we have a different burst size */
1018 if (*bp != burst) {
1019 struct dma_slave_config cfg;
1020
1021 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1022 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1023 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1024 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1025 cfg.src_maxburst = burst;
1026 cfg.dst_maxburst = burst;
1027
1028 if (dmaengine_slave_config(c, &cfg))
1029 goto use_pio;
1030
1031 *bp = burst;
1032 }
1033
1034 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035 dma_data_dir);
1036 if (host->sg_len == 0)
1037 goto use_pio;
1038
1039 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!tx)
1043 goto use_pio;
1044
1045 OMAP_MMC_WRITE(host, BUF, buf);
1046
1047 tx->callback = mmc_omap_dma_callback;
1048 tx->callback_param = host;
1049 dmaengine_submit(tx);
1050 host->brs_received = 0;
1051 host->dma_done = 0;
1052 host->dma_in_use = 1;
1053 return;
1054 }
1055 use_pio:
730c9b7e
CA		 1056
1057 /* Revert to PIO? */
4e078fbd
RK		 1058 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059 host->total_bytes_left = data->blocks * block_size;
1060 host->sg_len = sg_len;
1061 mmc_omap_sg_to_buf(host);
1062 host->dma_in_use = 0;
730c9b7e
CA		 1063}
1064
abfbe5f7
JY		 1065static void mmc_omap_start_request(struct mmc_omap_host *host,
1066 struct mmc_request *req)
730c9b7e 1067{
abfbe5f7 1068 BUG_ON(host->mrq != NULL);
730c9b7e
CA		 1069
1070 host->mrq = req;
1071
1072 /* only touch fifo AFTER the controller readies it */
1073 mmc_omap_prepare_data(host, req);
1074 mmc_omap_start_command(host, req->cmd);
3451c067
RK		 1075 if (host->dma_in_use) {
1076 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077 host->dma_tx : host->dma_rx;
1078
4e078fbd 1079 dma_async_issue_pending(c);
3451c067 1080 }
abfbe5f7
JY		 1081}
1082
1083static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084{
1085 struct mmc_omap_slot *slot = mmc_priv(mmc);
1086 struct mmc_omap_host *host = slot->host;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&host->slot_lock, flags);
1090 if (host->mmc != NULL) {
1091 BUG_ON(slot->mrq != NULL);
1092 slot->mrq = req;
1093 spin_unlock_irqrestore(&host->slot_lock, flags);
1094 return;
1095 } else
1096 host->mmc = mmc;
1097 spin_unlock_irqrestore(&host->slot_lock, flags);
1098 mmc_omap_select_slot(slot, 1);
1099 mmc_omap_start_request(host, req);
730c9b7e
CA		 1100}
1101
65b5b6e5
JY		 1102static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103 int vdd)
730c9b7e 1104{
65b5b6e5 1105 struct mmc_omap_host *host;
730c9b7e 1106
65b5b6e5
JY		 1107 host = slot->host;
1108
1109 if (slot->pdata->set_power != NULL)
1110 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111 vdd);
53db20d1 1112 if (mmc_omap2()) {
65b5b6e5
JY		 1113 u16 w;
1114
1115 if (power_on) {
1116 w = OMAP_MMC_READ(host, CON);
1117 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118 } else {
1119 w = OMAP_MMC_READ(host, CON);
1120 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121 }
730c9b7e
CA		 1122 }
1123}
1124
d3af5abe 1125static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
730c9b7e 1126{
abfbe5f7
JY		 1127 struct mmc_omap_slot *slot = mmc_priv(mmc);
1128 struct mmc_omap_host *host = slot->host;
d3af5abe 1129 int func_clk_rate = clk_get_rate(host->fclk);
730c9b7e 1130 int dsor;
730c9b7e
CA		 1131
1132 if (ios->clock == 0)
d3af5abe 1133 return 0;
730c9b7e 1134
d3af5abe
TL		 1135 dsor = func_clk_rate / ios->clock;
1136 if (dsor < 1)
1137 dsor = 1;
730c9b7e 1138
d3af5abe 1139 if (func_clk_rate / dsor > ios->clock)
730c9b7e
CA		 1140 dsor++;
1141
d3af5abe
TL		 1142 if (dsor > 250)
1143 dsor = 250;
d3af5abe 1144
abfbe5f7
JY		 1145 slot->fclk_freq = func_clk_rate / dsor;
1146
d3af5abe
TL		 1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 dsor |= 1 << 15;
1149
1150 return dsor;
1151}
1152
1153static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154{
abfbe5f7
JY		 1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int i, dsor;
0807a9b5 1158 int clk_enabled;
65b5b6e5
JY		 1159
1160 mmc_omap_select_slot(slot, 0);
1161
0807a9b5
JL		 1162 dsor = mmc_omap_calc_divisor(mmc, ios);
1163
65b5b6e5
JY		 1164 if (ios->vdd != slot->vdd)
1165 slot->vdd = ios->vdd;
730c9b7e 1166
0807a9b5 1167 clk_enabled = 0;
730c9b7e
CA		 1168 switch (ios->power_mode) {
1169 case MMC_POWER_OFF:
65b5b6e5 1170 mmc_omap_set_power(slot, 0, ios->vdd);
730c9b7e
CA		 1171 break;
1172 case MMC_POWER_UP:
46a6730e 1173 /* Cannot touch dsor yet, just power up MMC */
65b5b6e5
JY		 1174 mmc_omap_set_power(slot, 1, ios->vdd);
1175 goto exit;
46a6730e 1176 case MMC_POWER_ON:
0807a9b5
JL		 1177 mmc_omap_fclk_enable(host, 1);
1178 clk_enabled = 1;
c5cb431d 1179 dsor |= 1 << 11;
730c9b7e
CA		 1180 break;
1181 }
1182
65b5b6e5
JY		 1183 if (slot->bus_mode != ios->bus_mode) {
1184 if (slot->pdata->set_bus_mode != NULL)
1185 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1186 ios->bus_mode);
1187 slot->bus_mode = ios->bus_mode;
1188 }
730c9b7e
CA		 1189
1190 /* On insanely high arm_per frequencies something sometimes
1191 * goes somehow out of sync, and the POW bit is not being set,
1192 * which results in the while loop below getting stuck.
1193 * Writing to the CON register twice seems to do the trick. */
1194 for (i = 0; i < 2; i++)
3342ee8b 1195 OMAP_MMC_WRITE(host, CON, dsor);
65b5b6e5 1196 slot->saved_con = dsor;
46a6730e 1197 if (ios->power_mode == MMC_POWER_ON) {
9d7c6eee
JL		 1198 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1199 int usecs = 250;
1200
730c9b7e 1201 /* Send clock cycles, poll completion */
3342ee8b
JY		 1202 OMAP_MMC_WRITE(host, IE, 0);
1203 OMAP_MMC_WRITE(host, STAT, 0xffff);
c5cb431d 1204 OMAP_MMC_WRITE(host, CMD, 1 << 7);
9d7c6eee
JL		 1205 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1206 udelay(1);
1207 usecs--;
1208 }
3342ee8b 1209 OMAP_MMC_WRITE(host, STAT, 1);
730c9b7e 1210 }
65b5b6e5
JY		 1211
1212exit:
0807a9b5 1213 mmc_omap_release_slot(slot, clk_enabled);
730c9b7e
CA		 1214}
1215
ab7aefd0 1216static const struct mmc_host_ops mmc_omap_ops = {
730c9b7e
CA		 1217 .request = mmc_omap_request,
1218 .set_ios = mmc_omap_set_ios,
730c9b7e
CA		 1219};
1220
c3be1efd 1221static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
730c9b7e 1222{
abfbe5f7 1223 struct mmc_omap_slot *slot = NULL;
730c9b7e 1224 struct mmc_host *mmc;
abfbe5f7
JY		 1225 int r;
1226
1227 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1228 if (mmc == NULL)
1229 return -ENOMEM;
1230
1231 slot = mmc_priv(mmc);
1232 slot->host = host;
1233 slot->mmc = mmc;
1234 slot->id = id;
1235 slot->pdata = &host->pdata->slots[id];
1236
1237 host->slots[id] = slot;
1238
23af6039 1239 mmc->caps = 0;
90c62bf0 1240 if (host->pdata->slots[id].wires >= 4)
b13d1f0f 1241 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE;
abfbe5f7
JY		 1242
1243 mmc->ops = &mmc_omap_ops;
1244 mmc->f_min = 400000;
1245
53db20d1 1246 if (mmc_omap2())
abfbe5f7
JY		 1247 mmc->f_max = 48000000;
1248 else
1249 mmc->f_max = 24000000;
1250 if (host->pdata->max_freq)
1251 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1252 mmc->ocr_avail = slot->pdata->ocr_mask;
1253
1254 /* Use scatterlist DMA to reduce per-transfer costs.
1255 * NOTE max_seg_size assumption that small blocks aren't
1256 * normally used (except e.g. for reading SD registers).
1257 */
a36274e0 1258 mmc->max_segs = 32;
abfbe5f7
JY		 1259 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1260 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1261 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1262 mmc->max_seg_size = mmc->max_req_size;
1263
0e5c93e0
JN		 1264 if (slot->pdata->get_cover_state != NULL) {
1265 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1266 (unsigned long)slot);
1267 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1268 (unsigned long)slot);
1269 }
1270
abfbe5f7
JY		 1271 r = mmc_add_host(mmc);
1272 if (r < 0)
1273 goto err_remove_host;
1274
1275 if (slot->pdata->name != NULL) {
1276 r = device_create_file(&mmc->class_dev,
1277 &dev_attr_slot_name);
1278 if (r < 0)
1279 goto err_remove_host;
1280 }
1281
5a0f3f1f
JY		 1282 if (slot->pdata->get_cover_state != NULL) {
1283 r = device_create_file(&mmc->class_dev,
1284 &dev_attr_cover_switch);
1285 if (r < 0)
1286 goto err_remove_slot_name;
7584d276 1287 tasklet_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 1288 }
1289
abfbe5f7
JY		 1290 return 0;
1291
5a0f3f1f
JY		 1292err_remove_slot_name:
1293 if (slot->pdata->name != NULL)
1294 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
abfbe5f7
JY		 1295err_remove_host:
1296 mmc_remove_host(mmc);
1297 mmc_free_host(mmc);
1298 return r;
1299}
1300
1301static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1302{
1303 struct mmc_host *mmc = slot->mmc;
1304
1305 if (slot->pdata->name != NULL)
1306 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
5a0f3f1f
JY		 1307 if (slot->pdata->get_cover_state != NULL)
1308 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1309
7584d276
JL		 1310 tasklet_kill(&slot->cover_tasklet);
1311 del_timer_sync(&slot->cover_timer);
b01a4f1c 1312 flush_workqueue(slot->host->mmc_omap_wq);
abfbe5f7
JY		 1313
1314 mmc_remove_host(mmc);
1315 mmc_free_host(mmc);
1316}
1317
c3be1efd 1318static int mmc_omap_probe(struct platform_device *pdev)
abfbe5f7
JY		 1319{
1320 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
730c9b7e 1321 struct mmc_omap_host *host = NULL;
81ca7034 1322 struct resource *res;
3451c067 1323 dma_cap_mask_t mask;
31ee9181 1324 unsigned sig = 0;
abfbe5f7 1325 int i, ret = 0;
ce9c1a83 1326 int irq;
81ca7034 1327
abfbe5f7 1328 if (pdata == NULL) {
81ca7034
JY		 1329 dev_err(&pdev->dev, "platform data missing\n");
1330 return -ENXIO;
1331 }
abfbe5f7
JY		 1332 if (pdata->nr_slots == 0) {
1333 dev_err(&pdev->dev, "no slots\n");
9cb238c0 1334 return -EPROBE_DEFER;
abfbe5f7 1335 }
81ca7034 1336
64ac16ec
JN		 1337 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1338 GFP_KERNEL);
1339 if (host == NULL)
1340 return -ENOMEM;
1341
ce9c1a83 1342 irq = platform_get_irq(pdev, 0);
64ac16ec 1343 if (irq < 0)
ce9c1a83 1344 return -ENXIO;
730c9b7e 1345
64ac16ec
JN		 1346 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1347 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1348 if (IS_ERR(host->virt_base))
1349 return PTR_ERR(host->virt_base);
730c9b7e 1350
0f602ec7
JL		 1351 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1352 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1353
0fb4723d
JL		 1354 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1355 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1356 (unsigned long) host);
eb1860bc 1357
0807a9b5
JL		 1358 spin_lock_init(&host->clk_lock);
1359 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1360
730c9b7e 1361 spin_lock_init(&host->dma_lock);
abfbe5f7
JY		 1362 spin_lock_init(&host->slot_lock);
1363 init_waitqueue_head(&host->slot_wq);
1364
abfbe5f7 1365 host->pdata = pdata;
53db20d1 1366 host->features = host->pdata->slots[0].features;
abfbe5f7
JY		 1367 host->dev = &pdev->dev;
1368 platform_set_drvdata(pdev, host);
1369
730c9b7e 1370 host->id = pdev->id;
ce9c1a83 1371 host->irq = irq;
2ca5dc6f 1372 host->phys_base = res->start;
d4a36645 1373 host->iclk = clk_get(&pdev->dev, "ick");
64ac16ec
JN		 1374 if (IS_ERR(host->iclk))
1375 return PTR_ERR(host->iclk);
d4a36645 1376 clk_enable(host->iclk);
730c9b7e 1377
5c9e02b1 1378 host->fclk = clk_get(&pdev->dev, "fck");
730c9b7e
CA		 1379 if (IS_ERR(host->fclk)) {
1380 ret = PTR_ERR(host->fclk);
81ca7034 1381 goto err_free_iclk;
730c9b7e
CA		 1382 }
1383
3451c067
RK		 1384 dma_cap_zero(mask);
1385 dma_cap_set(DMA_SLAVE, mask);
1386
1387 host->dma_tx_burst = -1;
1388 host->dma_rx_burst = -1;
1389
31ee9181
TL		 1390 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1391 if (res)
1392 sig = res->start;
1393 host->dma_tx = dma_request_slave_channel_compat(mask,
1394 omap_dma_filter_fn, &sig, &pdev->dev, "tx");
3451c067
RK		 1395 if (!host->dma_tx)
1396 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1397 sig);
31ee9181
TL		 1398
1399 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1400 if (res)
1401 sig = res->start;
1402 host->dma_rx = dma_request_slave_channel_compat(mask,
1403 omap_dma_filter_fn, &sig, &pdev->dev, "rx");
3451c067
RK		 1404 if (!host->dma_rx)
1405 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1406 sig);
3451c067 1407
abfbe5f7
JY		 1408 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1409 if (ret)
3451c067 1410 goto err_free_dma;
42431acb 1411
abfbe5f7
JY		 1412 if (pdata->init != NULL) {
1413 ret = pdata->init(&pdev->dev);
1414 if (ret < 0)
1415 goto err_free_irq;
1416 }
730c9b7e 1417
abfbe5f7 1418 host->nr_slots = pdata->nr_slots;
53db20d1 1419 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
3caf4140
TL		 1420
1421 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1422 if (!host->mmc_omap_wq)
1423 goto err_plat_cleanup;
1424
abfbe5f7
JY		 1425 for (i = 0; i < pdata->nr_slots; i++) {
1426 ret = mmc_omap_new_slot(host, i);
1427 if (ret < 0) {
1428 while (--i >= 0)
1429 mmc_omap_remove_slot(host->slots[i]);
730c9b7e 1430
3caf4140 1431 goto err_destroy_wq;
730c9b7e 1432 }
730c9b7e
CA		 1433 }
1434
730c9b7e
CA		 1435 return 0;
1436
3caf4140
TL		 1437err_destroy_wq:
1438 destroy_workqueue(host->mmc_omap_wq);
abfbe5f7
JY		 1439err_plat_cleanup:
1440 if (pdata->cleanup)
1441 pdata->cleanup(&pdev->dev);
1442err_free_irq:
1443 free_irq(host->irq, host);
3451c067
RK		 1444err_free_dma:
1445 if (host->dma_tx)
1446 dma_release_channel(host->dma_tx);
1447 if (host->dma_rx)
1448 dma_release_channel(host->dma_rx);
81ca7034
JY		 1449 clk_put(host->fclk);
1450err_free_iclk:
e799acb2
LM		 1451 clk_disable(host->iclk);
1452 clk_put(host->iclk);
730c9b7e
CA		 1453 return ret;
1454}
1455
6e0ee714 1456static int mmc_omap_remove(struct platform_device *pdev)
730c9b7e
CA		 1457{
1458 struct mmc_omap_host *host = platform_get_drvdata(pdev);
abfbe5f7 1459 int i;
730c9b7e 1460
81ca7034
JY		 1461 BUG_ON(host == NULL);
1462
abfbe5f7
JY		 1463 for (i = 0; i < host->nr_slots; i++)
1464 mmc_omap_remove_slot(host->slots[i]);
1465
1466 if (host->pdata->cleanup)
1467 host->pdata->cleanup(&pdev->dev);
81ca7034 1468
d4a36645 1469 mmc_omap_fclk_enable(host, 0);
49c1d9da 1470 free_irq(host->irq, host);
d4a36645
RK		 1471 clk_put(host->fclk);
1472 clk_disable(host->iclk);
1473 clk_put(host->iclk);
730c9b7e 1474
3451c067
RK		 1475 if (host->dma_tx)
1476 dma_release_channel(host->dma_tx);
1477 if (host->dma_rx)
1478 dma_release_channel(host->dma_rx);
1479
b01a4f1c 1480 destroy_workqueue(host->mmc_omap_wq);
81ca7034 1481
730c9b7e
CA		 1482 return 0;
1483}
1484
9cb238c0
TL		 1485#if IS_BUILTIN(CONFIG_OF)
1486static const struct of_device_id mmc_omap_match[] = {
1487 { .compatible = "ti,omap2420-mmc", },
1488 { },
1489};
1490#endif
1491
730c9b7e 1492static struct platform_driver mmc_omap_driver = {
b6e0703b 1493 .probe = mmc_omap_probe,
0433c143 1494 .remove = mmc_omap_remove,
730c9b7e
CA		 1495 .driver = {
1496 .name = DRIVER_NAME,
bc65c724 1497 .owner = THIS_MODULE,
9cb238c0 1498 .of_match_table = of_match_ptr(mmc_omap_match),
730c9b7e
CA		 1499 },
1500};
1501
680f1b5b 1502module_platform_driver(mmc_omap_driver);
730c9b7e
CA		 1503MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1504MODULE_LICENSE("GPL");
bc65c724 1505MODULE_ALIAS("platform:" DRIVER_NAME);
d36b6910 1506MODULE_AUTHOR("Juha Yrjölä");
Linux kernel - Deliverables
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