projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: sdhci-s3c: Add clk_(enable/disable) in runtime suspend/resume
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
a45c6cb8
MC		 24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
a45c6cb8
MC		 28#include <linux/timer.h>
29#include <linux/clk.h>
46856a68
RN		 30#include <linux/of.h>
31#include <linux/of_gpio.h>
32#include <linux/of_device.h>
3451c067 33#include <linux/omap-dma.h>
a45c6cb8 34#include <linux/mmc/host.h>
13189e78 35#include <linux/mmc/core.h>
93caf8e6 36#include <linux/mmc/mmc.h>
a45c6cb8 37#include <linux/io.h>
db0fefc5
AH		 38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
fa4aa2d4 40#include <linux/pm_runtime.h>
a45c6cb8 41#include <mach/hardware.h>
ce491cf8
TL		 42#include <plat/board.h>
43#include <plat/mmc.h>
44#include <plat/cpu.h>
a45c6cb8
MC		 45
46/* OMAP HSMMC Host Controller Registers */
11dd62a7 47#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 48#define OMAP_HSMMC_CON 0x002C
49#define OMAP_HSMMC_BLK 0x0104
50#define OMAP_HSMMC_ARG 0x0108
51#define OMAP_HSMMC_CMD 0x010C
52#define OMAP_HSMMC_RSP10 0x0110
53#define OMAP_HSMMC_RSP32 0x0114
54#define OMAP_HSMMC_RSP54 0x0118
55#define OMAP_HSMMC_RSP76 0x011C
56#define OMAP_HSMMC_DATA 0x0120
57#define OMAP_HSMMC_HCTL 0x0128
58#define OMAP_HSMMC_SYSCTL 0x012C
59#define OMAP_HSMMC_STAT 0x0130
60#define OMAP_HSMMC_IE 0x0134
61#define OMAP_HSMMC_ISE 0x0138
62#define OMAP_HSMMC_CAPA 0x0140
63
64#define VS18 (1 << 26)
65#define VS30 (1 << 25)
66#define SDVS18 (0x5 << 9)
67#define SDVS30 (0x6 << 9)
eb250826 68#define SDVS33 (0x7 << 9)
1b331e69 69#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 70#define SDVSCLR 0xFFFFF1FF
71#define SDVSDET 0x00000400
72#define AUTOIDLE 0x1
73#define SDBP (1 << 8)
74#define DTO 0xe
75#define ICE 0x1
76#define ICS 0x2
77#define CEN (1 << 2)
78#define CLKD_MASK 0x0000FFC0
79#define CLKD_SHIFT 6
80#define DTO_MASK 0x000F0000
81#define DTO_SHIFT 16
82#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 83#define BWR_ENABLE (1 << 4)
84#define BRR_ENABLE (1 << 5)
93caf8e6 85#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 86#define INIT_STREAM (1 << 1)
87#define DP_SELECT (1 << 21)
88#define DDIR (1 << 4)
89#define DMA_EN 0x1
90#define MSBS (1 << 5)
91#define BCE (1 << 1)
92#define FOUR_BIT (1 << 1)
03b5d924 93#define DDR (1 << 19)
73153010 94#define DW8 (1 << 5)
a45c6cb8
MC		 95#define CC 0x1
96#define TC 0x02
97#define OD 0x1
98#define ERR (1 << 15)
99#define CMD_TIMEOUT (1 << 16)
100#define DATA_TIMEOUT (1 << 20)
101#define CMD_CRC (1 << 17)
102#define DATA_CRC (1 << 21)
103#define CARD_ERR (1 << 28)
104#define STAT_CLEAR 0xFFFFFFFF
105#define INIT_STREAM_CMD 0x00000000
106#define DUAL_VOLT_OCR_BIT 7
107#define SRC (1 << 25)
108#define SRD (1 << 26)
11dd62a7
DK		 109#define SOFTRESET (1 << 1)
110#define RESETDONE (1 << 0)
a45c6cb8 111
fa4aa2d4 112#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 113#define MMC_TIMEOUT_MS 20
6b206efe
AS		 114#define OMAP_MMC_MIN_CLOCK 400000
115#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 116#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 117
118/*
119 * One controller can have multiple slots, like on some omap boards using
120 * omap.c controller driver. Luckily this is not currently done on any known
121 * omap_hsmmc.c device.
122 */
123#define mmc_slot(host) (host->pdata->slots[host->slot_id])
124
125/*
126 * MMC Host controller read/write API's
127 */
128#define OMAP_HSMMC_READ(base, reg) \
129 __raw_readl((base) + OMAP_HSMMC_##reg)
130
131#define OMAP_HSMMC_WRITE(base, reg, val) \
132 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
133
9782aff8
PF		 134struct omap_hsmmc_next {
135 unsigned int dma_len;
136 s32 cookie;
137};
138
70a3341a 139struct omap_hsmmc_host {
a45c6cb8
MC		 140 struct device *dev;
141 struct mmc_host *mmc;
142 struct mmc_request *mrq;
143 struct mmc_command *cmd;
144 struct mmc_data *data;
145 struct clk *fclk;
a45c6cb8 146 struct clk *dbclk;
db0fefc5
AH		 147 /*
148 * vcc == configured supply
149 * vcc_aux == optional
150 * - MMC1, supply for DAT4..DAT7
151 * - MMC2/MMC2, external level shifter voltage supply, for
152 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
153 */
154 struct regulator *vcc;
155 struct regulator *vcc_aux;
a45c6cb8
MC		 156 void __iomem *base;
157 resource_size_t mapbase;
4dffd7a2 158 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 159 unsigned int dma_len;
0ccd76d4 160 unsigned int dma_sg_idx;
a45c6cb8 161 unsigned char bus_mode;
a3621465 162 unsigned char power_mode;
a45c6cb8
MC		 163 int suspended;
164 int irq;
a45c6cb8 165 int use_dma, dma_ch;
c5c98927
RK		 166 struct dma_chan *tx_chan;
167 struct dma_chan *rx_chan;
a45c6cb8 168 int slot_id;
4a694dc9 169 int response_busy;
11dd62a7 170 int context_loss;
b62f6228
AH		 171 int protect_card;
172 int reqs_blocked;
db0fefc5 173 int use_reg;
b417577d 174 int req_in_progress;
9782aff8 175 struct omap_hsmmc_next next_data;
11dd62a7 176
a45c6cb8
MC		 177 struct omap_mmc_platform_data *pdata;
178};
179
db0fefc5
AH		 180static int omap_hsmmc_card_detect(struct device *dev, int slot)
181{
182 struct omap_mmc_platform_data *mmc = dev->platform_data;
183
184 /* NOTE: assumes card detect signal is active-low */
185 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
186}
187
188static int omap_hsmmc_get_wp(struct device *dev, int slot)
189{
190 struct omap_mmc_platform_data *mmc = dev->platform_data;
191
192 /* NOTE: assumes write protect signal is active-high */
193 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
194}
195
196static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
197{
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
199
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202}
203
204#ifdef CONFIG_PM
205
206static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
207{
208 struct omap_mmc_platform_data *mmc = dev->platform_data;
209
210 disable_irq(mmc->slots[0].card_detect_irq);
211 return 0;
212}
213
214static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
215{
216 struct omap_mmc_platform_data *mmc = dev->platform_data;
217
218 enable_irq(mmc->slots[0].card_detect_irq);
219 return 0;
220}
221
222#else
223
224#define omap_hsmmc_suspend_cdirq NULL
225#define omap_hsmmc_resume_cdirq NULL
226
227#endif
228
b702b106
AH		 229#ifdef CONFIG_REGULATOR
230
69b07ece 231static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 232 int vdd)
233{
234 struct omap_hsmmc_host *host =
235 platform_get_drvdata(to_platform_device(dev));
236 int ret = 0;
237
238 /*
239 * If we don't see a Vcc regulator, assume it's a fixed
240 * voltage always-on regulator.
241 */
242 if (!host->vcc)
243 return 0;
1f84b71b
RN		 244 /*
245 * With DT, never turn OFF the regulator. This is because
246 * the pbias cell programming support is still missing when
247 * booting with Device tree
248 */
4d048f91 249 if (dev->of_node && !vdd)
1f84b71b 250 return 0;
db0fefc5
AH		 251
252 if (mmc_slot(host).before_set_reg)
253 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
254
255 /*
256 * Assume Vcc regulator is used only to power the card ... OMAP
257 * VDDS is used to power the pins, optionally with a transceiver to
258 * support cards using voltages other than VDDS (1.8V nominal). When a
259 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
260 *
261 * In some cases this regulator won't support enable/disable;
262 * e.g. it's a fixed rail for a WLAN chip.
263 *
264 * In other cases vcc_aux switches interface power. Example, for
265 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
266 * chips/cards need an interface voltage rail too.
267 */
268 if (power_on) {
99fc5131 269 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 270 /* Enable interface voltage rail, if needed */
271 if (ret == 0 && host->vcc_aux) {
272 ret = regulator_enable(host->vcc_aux);
273 if (ret < 0)
99fc5131
LW		 274 ret = mmc_regulator_set_ocr(host->mmc,
275 host->vcc, 0);
db0fefc5
AH		 276 }
277 } else {
99fc5131 278 /* Shut down the rail */
6da20c89
AH		 279 if (host->vcc_aux)
280 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 281 if (!ret) {
282 /* Then proceed to shut down the local regulator */
283 ret = mmc_regulator_set_ocr(host->mmc,
284 host->vcc, 0);
285 }
db0fefc5
AH		 286 }
287
288 if (mmc_slot(host).after_set_reg)
289 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
290
291 return ret;
292}
293
db0fefc5
AH		 294static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
295{
296 struct regulator *reg;
64be9782 297 int ocr_value = 0;
db0fefc5 298
db0fefc5
AH		 299 reg = regulator_get(host->dev, "vmmc");
300 if (IS_ERR(reg)) {
301 dev_dbg(host->dev, "vmmc regulator missing\n");
1fdc90fb 302 return PTR_ERR(reg);
db0fefc5 303 } else {
1fdc90fb 304 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5 305 host->vcc = reg;
64be9782 306 ocr_value = mmc_regulator_get_ocrmask(reg);
307 if (!mmc_slot(host).ocr_mask) {
308 mmc_slot(host).ocr_mask = ocr_value;
309 } else {
310 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 311 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 312 mmc_slot(host).ocr_mask);
64be9782 313 mmc_slot(host).ocr_mask = 0;
314 return -EINVAL;
315 }
316 }
db0fefc5
AH		 317
318 /* Allow an aux regulator */
319 reg = regulator_get(host->dev, "vmmc_aux");
320 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
321
b1c1df7a
B		 322 /* For eMMC do not power off when not in sleep state */
323 if (mmc_slot(host).no_regulator_off_init)
324 return 0;
db0fefc5
AH		 325 /*
326 * UGLY HACK: workaround regulator framework bugs.
327 * When the bootloader leaves a supply active, it's
328 * initialized with zero usecount ... and we can't
329 * disable it without first enabling it. Until the
330 * framework is fixed, we need a workaround like this
331 * (which is safe for MMC, but not in general).
332 */
e840ce13
AH		 333 if (regulator_is_enabled(host->vcc) > 0 ||
334 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
335 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
336
337 mmc_slot(host).set_power(host->dev, host->slot_id,
338 1, vdd);
339 mmc_slot(host).set_power(host->dev, host->slot_id,
340 0, 0);
db0fefc5
AH		 341 }
342 }
343
344 return 0;
db0fefc5
AH		 345}
346
347static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
348{
349 regulator_put(host->vcc);
350 regulator_put(host->vcc_aux);
351 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 352}
353
b702b106
AH		 354static inline int omap_hsmmc_have_reg(void)
355{
356 return 1;
357}
358
359#else
360
361static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
362{
363 return -EINVAL;
364}
365
366static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
367{
368}
369
370static inline int omap_hsmmc_have_reg(void)
371{
372 return 0;
373}
374
375#endif
376
377static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
378{
379 int ret;
380
381 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 382 if (pdata->slots[0].cover)
383 pdata->slots[0].get_cover_state =
384 omap_hsmmc_get_cover_state;
385 else
386 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
387 pdata->slots[0].card_detect_irq =
388 gpio_to_irq(pdata->slots[0].switch_pin);
389 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
390 if (ret)
391 return ret;
392 ret = gpio_direction_input(pdata->slots[0].switch_pin);
393 if (ret)
394 goto err_free_sp;
395 } else
396 pdata->slots[0].switch_pin = -EINVAL;
397
398 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
399 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
400 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
401 if (ret)
402 goto err_free_cd;
403 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
404 if (ret)
405 goto err_free_wp;
406 } else
407 pdata->slots[0].gpio_wp = -EINVAL;
408
409 return 0;
410
411err_free_wp:
412 gpio_free(pdata->slots[0].gpio_wp);
413err_free_cd:
414 if (gpio_is_valid(pdata->slots[0].switch_pin))
415err_free_sp:
416 gpio_free(pdata->slots[0].switch_pin);
417 return ret;
418}
419
420static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
421{
422 if (gpio_is_valid(pdata->slots[0].gpio_wp))
423 gpio_free(pdata->slots[0].gpio_wp);
424 if (gpio_is_valid(pdata->slots[0].switch_pin))
425 gpio_free(pdata->slots[0].switch_pin);
426}
427
e0c7f99b
AS		 428/*
429 * Start clock to the card
430 */
431static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
432{
433 OMAP_HSMMC_WRITE(host->base, SYSCTL,
434 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
435}
436
a45c6cb8
MC		 437/*
438 * Stop clock to the card
439 */
70a3341a 440static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 441{
442 OMAP_HSMMC_WRITE(host->base, SYSCTL,
443 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
444 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
445 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
446}
447
93caf8e6
AH		 448static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
449 struct mmc_command *cmd)
b417577d
AH		 450{
451 unsigned int irq_mask;
452
453 if (host->use_dma)
454 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
455 else
456 irq_mask = INT_EN_MASK;
457
93caf8e6
AH		 458 /* Disable timeout for erases */
459 if (cmd->opcode == MMC_ERASE)
460 irq_mask &= ~DTO_ENABLE;
461
b417577d
AH		 462 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
463 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
464 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
465}
466
467static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
468{
469 OMAP_HSMMC_WRITE(host->base, ISE, 0);
470 OMAP_HSMMC_WRITE(host->base, IE, 0);
471 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
472}
473
ac330f44 474/* Calculate divisor for the given clock frequency */
d83b6e03 475static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 476{
477 u16 dsor = 0;
478
479 if (ios->clock) {
d83b6e03 480 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 481 if (dsor > 250)
482 dsor = 250;
483 }
484
485 return dsor;
486}
487
5934df2f
AS		 488static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
489{
490 struct mmc_ios *ios = &host->mmc->ios;
491 unsigned long regval;
492 unsigned long timeout;
493
8986d31b 494 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 495
496 omap_hsmmc_stop_clock(host);
497
498 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
499 regval = regval & ~(CLKD_MASK | DTO_MASK);
d83b6e03 500 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
5934df2f
AS		 501 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
502 OMAP_HSMMC_WRITE(host->base, SYSCTL,
503 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
504
505 /* Wait till the ICS bit is set */
506 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
507 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
508 && time_before(jiffies, timeout))
509 cpu_relax();
510
511 omap_hsmmc_start_clock(host);
512}
513
3796fb8a
AS		 514static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
515{
516 struct mmc_ios *ios = &host->mmc->ios;
517 u32 con;
518
519 con = OMAP_HSMMC_READ(host->base, CON);
03b5d924
B		 520 if (ios->timing == MMC_TIMING_UHS_DDR50)
521 con |= DDR; /* configure in DDR mode */
522 else
523 con &= ~DDR;
3796fb8a
AS		 524 switch (ios->bus_width) {
525 case MMC_BUS_WIDTH_8:
526 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
527 break;
528 case MMC_BUS_WIDTH_4:
529 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
530 OMAP_HSMMC_WRITE(host->base, HCTL,
531 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
532 break;
533 case MMC_BUS_WIDTH_1:
534 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
535 OMAP_HSMMC_WRITE(host->base, HCTL,
536 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
537 break;
538 }
539}
540
541static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
542{
543 struct mmc_ios *ios = &host->mmc->ios;
544 u32 con;
545
546 con = OMAP_HSMMC_READ(host->base, CON);
547 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
548 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
549 else
550 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
551}
552
11dd62a7
DK		 553#ifdef CONFIG_PM
554
555/*
556 * Restore the MMC host context, if it was lost as result of a
557 * power state change.
558 */
70a3341a 559static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 560{
561 struct mmc_ios *ios = &host->mmc->ios;
562 struct omap_mmc_platform_data *pdata = host->pdata;
563 int context_loss = 0;
3796fb8a 564 u32 hctl, capa;
11dd62a7
DK		 565 unsigned long timeout;
566
567 if (pdata->get_context_loss_count) {
568 context_loss = pdata->get_context_loss_count(host->dev);
569 if (context_loss < 0)
570 return 1;
571 }
572
573 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
574 context_loss == host->context_loss ? "not " : "");
575 if (host->context_loss == context_loss)
576 return 1;
577
6c31b215
V		 578 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
579 return 1;
11dd62a7 580
c2200efb 581 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 582 if (host->power_mode != MMC_POWER_OFF &&
583 (1 << ios->vdd) <= MMC_VDD_23_24)
584 hctl = SDVS18;
585 else
586 hctl = SDVS30;
587 capa = VS30 | VS18;
588 } else {
589 hctl = SDVS18;
590 capa = VS18;
591 }
592
593 OMAP_HSMMC_WRITE(host->base, HCTL,
594 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
595
596 OMAP_HSMMC_WRITE(host->base, CAPA,
597 OMAP_HSMMC_READ(host->base, CAPA) | capa);
598
599 OMAP_HSMMC_WRITE(host->base, HCTL,
600 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
601
602 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
603 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
604 && time_before(jiffies, timeout))
605 ;
606
b417577d 607 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 608
609 /* Do not initialize card-specific things if the power is off */
610 if (host->power_mode == MMC_POWER_OFF)
611 goto out;
612
3796fb8a 613 omap_hsmmc_set_bus_width(host);
11dd62a7 614
5934df2f 615 omap_hsmmc_set_clock(host);
11dd62a7 616
3796fb8a
AS		 617 omap_hsmmc_set_bus_mode(host);
618
11dd62a7
DK		 619out:
620 host->context_loss = context_loss;
621
622 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
623 return 0;
624}
625
626/*
627 * Save the MMC host context (store the number of power state changes so far).
628 */
70a3341a 629static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 630{
631 struct omap_mmc_platform_data *pdata = host->pdata;
632 int context_loss;
633
634 if (pdata->get_context_loss_count) {
635 context_loss = pdata->get_context_loss_count(host->dev);
636 if (context_loss < 0)
637 return;
638 host->context_loss = context_loss;
639 }
640}
641
642#else
643
70a3341a 644static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 645{
646 return 0;
647}
648
70a3341a 649static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 650{
651}
652
653#endif
654
a45c6cb8
MC		 655/*
656 * Send init stream sequence to card
657 * before sending IDLE command
658 */
70a3341a 659static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 660{
661 int reg = 0;
662 unsigned long timeout;
663
b62f6228
AH		 664 if (host->protect_card)
665 return;
666
a45c6cb8 667 disable_irq(host->irq);
b417577d
AH		 668
669 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 670 OMAP_HSMMC_WRITE(host->base, CON,
671 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
672 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
673
674 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
675 while ((reg != CC) && time_before(jiffies, timeout))
676 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
677
678 OMAP_HSMMC_WRITE(host->base, CON,
679 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 680
681 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
682 OMAP_HSMMC_READ(host->base, STAT);
683
a45c6cb8
MC		 684 enable_irq(host->irq);
685}
686
687static inline
70a3341a 688int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 689{
690 int r = 1;
691
191d1f1d
DK		 692 if (mmc_slot(host).get_cover_state)
693 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 694 return r;
695}
696
697static ssize_t
70a3341a 698omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 699 char *buf)
700{
701 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 702 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 703
70a3341a
DK		 704 return sprintf(buf, "%s\n",
705 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 706}
707
70a3341a 708static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 709
710static ssize_t
70a3341a 711omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 712 char *buf)
713{
714 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 715 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 716
191d1f1d 717 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 718}
719
70a3341a 720static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 721
722/*
723 * Configure the response type and send the cmd.
724 */
725static void
70a3341a 726omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 727 struct mmc_data *data)
728{
729 int cmdreg = 0, resptype = 0, cmdtype = 0;
730
8986d31b 731 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 732 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
733 host->cmd = cmd;
734
93caf8e6 735 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 736
4a694dc9 737 host->response_busy = 0;
a45c6cb8
MC		 738 if (cmd->flags & MMC_RSP_PRESENT) {
739 if (cmd->flags & MMC_RSP_136)
740 resptype = 1;
4a694dc9
AH		 741 else if (cmd->flags & MMC_RSP_BUSY) {
742 resptype = 3;
743 host->response_busy = 1;
744 } else
a45c6cb8
MC		 745 resptype = 2;
746 }
747
748 /*
749 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
750 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
751 * a val of 0x3, rest 0x0.
752 */
753 if (cmd == host->mrq->stop)
754 cmdtype = 0x3;
755
756 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
757
758 if (data) {
759 cmdreg |= DP_SELECT | MSBS | BCE;
760 if (data->flags & MMC_DATA_READ)
761 cmdreg |= DDIR;
762 else
763 cmdreg &= ~(DDIR);
764 }
765
766 if (host->use_dma)
767 cmdreg |= DMA_EN;
768
b417577d 769 host->req_in_progress = 1;
4dffd7a2 770
a45c6cb8
MC		 771 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
772 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
773}
774
0ccd76d4 775static int
70a3341a 776omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 777{
778 if (data->flags & MMC_DATA_WRITE)
779 return DMA_TO_DEVICE;
780 else
781 return DMA_FROM_DEVICE;
782}
783
c5c98927
RK		 784static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
785 struct mmc_data *data)
786{
787 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
788}
789
b417577d
AH		 790static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
791{
792 int dma_ch;
31463b14 793 unsigned long flags;
b417577d 794
31463b14 795 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 796 host->req_in_progress = 0;
797 dma_ch = host->dma_ch;
31463b14 798 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 799
800 omap_hsmmc_disable_irq(host);
801 /* Do not complete the request if DMA is still in progress */
802 if (mrq->data && host->use_dma && dma_ch != -1)
803 return;
804 host->mrq = NULL;
805 mmc_request_done(host->mmc, mrq);
806}
807
a45c6cb8
MC		 808/*
809 * Notify the transfer complete to MMC core
810 */
811static void
70a3341a 812omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 813{
4a694dc9
AH		 814 if (!data) {
815 struct mmc_request *mrq = host->mrq;
816
23050103
AH		 817 /* TC before CC from CMD6 - don't know why, but it happens */
818 if (host->cmd && host->cmd->opcode == 6 &&
819 host->response_busy) {
820 host->response_busy = 0;
821 return;
822 }
823
b417577d 824 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 825 return;
826 }
827
a45c6cb8
MC		 828 host->data = NULL;
829
a45c6cb8
MC		 830 if (!data->error)
831 data->bytes_xfered += data->blocks * (data->blksz);
832 else
833 data->bytes_xfered = 0;
834
fe852273 835 if (!data->stop) {
b417577d 836 omap_hsmmc_request_done(host, data->mrq);
fe852273 837 return;
a45c6cb8 838 }
fe852273 839 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 840}
841
842/*
843 * Notify the core about command completion
844 */
845static void
70a3341a 846omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 847{
848 host->cmd = NULL;
849
850 if (cmd->flags & MMC_RSP_PRESENT) {
851 if (cmd->flags & MMC_RSP_136) {
852 /* response type 2 */
853 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
854 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
855 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
856 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
857 } else {
858 /* response types 1, 1b, 3, 4, 5, 6 */
859 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
860 }
861 }
b417577d
AH		 862 if ((host->data == NULL && !host->response_busy) || cmd->error)
863 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 864}
865
866/*
867 * DMA clean up for command errors
868 */
70a3341a 869static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 870{
b417577d 871 int dma_ch;
31463b14 872 unsigned long flags;
b417577d 873
82788ff5 874 host->data->error = errno;
a45c6cb8 875
31463b14 876 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 877 dma_ch = host->dma_ch;
878 host->dma_ch = -1;
31463b14 879 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 880
881 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 882 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
883
884 dmaengine_terminate_all(chan);
885 dma_unmap_sg(chan->device->dev,
886 host->data->sg, host->data->sg_len,
70a3341a 887 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 888
053bf34f 889 host->data->host_cookie = 0;
a45c6cb8
MC		 890 }
891 host->data = NULL;
a45c6cb8
MC		 892}
893
894/*
895 * Readable error output
896 */
897#ifdef CONFIG_MMC_DEBUG
699b958b 898static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 899{
900 /* --- means reserved bit without definition at documentation */
70a3341a 901 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 902 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
903 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
904 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
905 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 906 };
907 char res[256];
908 char *buf = res;
909 int len, i;
910
911 len = sprintf(buf, "MMC IRQ 0x%x :", status);
912 buf += len;
913
70a3341a 914 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 915 if (status & (1 << i)) {
70a3341a 916 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 917 buf += len;
918 }
919
8986d31b 920 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 921}
699b958b
AH		 922#else
923static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
924 u32 status)
925{
926}
a45c6cb8
MC		 927#endif /* CONFIG_MMC_DEBUG */
928
3ebf74b1
JP		 929/*
930 * MMC controller internal state machines reset
931 *
932 * Used to reset command or data internal state machines, using respectively
933 * SRC or SRD bit of SYSCTL register
934 * Can be called from interrupt context
935 */
70a3341a
DK		 936static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
937 unsigned long bit)
3ebf74b1
JP		 938{
939 unsigned long i = 0;
940 unsigned long limit = (loops_per_jiffy *
941 msecs_to_jiffies(MMC_TIMEOUT_MS));
942
943 OMAP_HSMMC_WRITE(host->base, SYSCTL,
944 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
945
07ad64b6
MC		 946 /*
947 * OMAP4 ES2 and greater has an updated reset logic.
948 * Monitor a 0->1 transition first
949 */
950 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 951 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 952 && (i++ < limit))
953 cpu_relax();
954 }
955 i = 0;
956
3ebf74b1
JP		 957 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
958 (i++ < limit))
959 cpu_relax();
960
961 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
962 dev_err(mmc_dev(host->mmc),
963 "Timeout waiting on controller reset in %s\n",
964 __func__);
965}
a45c6cb8 966
ae4bf788
V		 967static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, int err)
968{
969 omap_hsmmc_reset_controller_fsm(host, SRC);
970 host->cmd->error = err;
971
972 if (host->data) {
973 omap_hsmmc_reset_controller_fsm(host, SRD);
974 omap_hsmmc_dma_cleanup(host, err);
975 }
976
977}
978
b417577d 979static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 980{
a45c6cb8 981 struct mmc_data *data;
b417577d
AH		 982 int end_cmd = 0, end_trans = 0;
983
a45c6cb8 984 data = host->data;
8986d31b 985 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8
MC		 986
987 if (status & ERR) {
699b958b 988 omap_hsmmc_dbg_report_irq(host, status);
ae4bf788
V		 989 if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
990 hsmmc_command_incomplete(host, -ETIMEDOUT);
991 else if (status & (CMD_CRC | DATA_CRC))
992 hsmmc_command_incomplete(host, -EILSEQ);
993
994 end_cmd = 1;
995 if (host->data || host->response_busy) {
996 end_trans = 1;
997 host->response_busy = 0;
a45c6cb8
MC		 998 }
999 }
1000
a8fe29d8 1001 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1002 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1003 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1004 omap_hsmmc_xfer_done(host, data);
b417577d 1005}
a45c6cb8 1006
b417577d
AH		 1007/*
1008 * MMC controller IRQ handler
1009 */
1010static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1011{
1012 struct omap_hsmmc_host *host = dev_id;
1013 int status;
1014
1015 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1016 while (status & INT_EN_MASK && host->req_in_progress) {
b417577d 1017 omap_hsmmc_do_irq(host, status);
1f6b9fa4 1018
b417577d 1019 /* Flush posted write */
1f6b9fa4 1020 OMAP_HSMMC_WRITE(host->base, STAT, status);
b417577d 1021 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1022 }
4dffd7a2 1023
a45c6cb8
MC		 1024 return IRQ_HANDLED;
1025}
1026
70a3341a 1027static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1028{
1029 unsigned long i;
1030
1031 OMAP_HSMMC_WRITE(host->base, HCTL,
1032 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1033 for (i = 0; i < loops_per_jiffy; i++) {
1034 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1035 break;
1036 cpu_relax();
1037 }
1038}
1039
a45c6cb8 1040/*
eb250826
DB		 1041 * Switch MMC interface voltage ... only relevant for MMC1.
1042 *
1043 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1044 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1045 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1046 */
70a3341a 1047static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1048{
1049 u32 reg_val = 0;
1050 int ret;
1051
1052 /* Disable the clocks */
fa4aa2d4 1053 pm_runtime_put_sync(host->dev);
cd03d9a8 1054 if (host->dbclk)
94c18149 1055 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1056
1057 /* Turn the power off */
1058 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1059
1060 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1061 if (!ret)
1062 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1063 vdd);
fa4aa2d4 1064 pm_runtime_get_sync(host->dev);
cd03d9a8 1065 if (host->dbclk)
94c18149 1066 clk_prepare_enable(host->dbclk);
2bec0893 1067
a45c6cb8
MC		 1068 if (ret != 0)
1069 goto err;
1070
a45c6cb8
MC		 1071 OMAP_HSMMC_WRITE(host->base, HCTL,
1072 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1073 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1074
a45c6cb8
MC		 1075 /*
1076 * If a MMC dual voltage card is detected, the set_ios fn calls
1077 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1078 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1079 *
eb250826
DB		 1080 * Cope with a bit of slop in the range ... per data sheets:
1081 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1082 * but recommended values are 1.71V to 1.89V
1083 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1084 * but recommended values are 2.7V to 3.3V
1085 *
1086 * Board setup code shouldn't permit anything very out-of-range.
1087 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1088 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1089 */
eb250826 1090 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1091 reg_val |= SDVS18;
eb250826
DB		 1092 else
1093 reg_val |= SDVS30;
a45c6cb8
MC		 1094
1095 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1096 set_sd_bus_power(host);
a45c6cb8
MC		 1097
1098 return 0;
1099err:
1100 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1101 return ret;
1102}
1103
b62f6228
AH		 1104/* Protect the card while the cover is open */
1105static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1106{
1107 if (!mmc_slot(host).get_cover_state)
1108 return;
1109
1110 host->reqs_blocked = 0;
1111 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1112 if (host->protect_card) {
2cecdf00 1113 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1114 "card is now accessible\n",
1115 mmc_hostname(host->mmc));
1116 host->protect_card = 0;
1117 }
1118 } else {
1119 if (!host->protect_card) {
2cecdf00 1120 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1121 "card is now inaccessible\n",
1122 mmc_hostname(host->mmc));
1123 host->protect_card = 1;
1124 }
1125 }
1126}
1127
a45c6cb8 1128/*
7efab4f3 1129 * irq handler to notify the core about card insertion/removal
a45c6cb8 1130 */
7efab4f3 1131static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1132{
7efab4f3 1133 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1134 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1135 int carddetect;
1136
1137 if (host->suspended)
7efab4f3 1138 return IRQ_HANDLED;
a6b2240d
AH		 1139
1140 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1141
191d1f1d 1142 if (slot->card_detect)
db0fefc5 1143 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1144 else {
1145 omap_hsmmc_protect_card(host);
a6b2240d 1146 carddetect = -ENOSYS;
b62f6228 1147 }
a45c6cb8 1148
cdeebadd 1149 if (carddetect)
a45c6cb8 1150 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1151 else
a45c6cb8 1152 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1153 return IRQ_HANDLED;
1154}
1155
c5c98927 1156static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1157{
c5c98927
RK		 1158 struct omap_hsmmc_host *host = param;
1159 struct dma_chan *chan;
770d7432 1160 struct mmc_data *data;
c5c98927 1161 int req_in_progress;
a45c6cb8 1162
c5c98927 1163 spin_lock_irq(&host->irq_lock);
b417577d 1164 if (host->dma_ch < 0) {
c5c98927 1165 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1166 return;
b417577d 1167 }
a45c6cb8 1168
770d7432 1169 data = host->mrq->data;
c5c98927 1170 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1171 if (!data->host_cookie)
c5c98927
RK		 1172 dma_unmap_sg(chan->device->dev,
1173 data->sg, data->sg_len,
9782aff8 1174 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1175
1176 req_in_progress = host->req_in_progress;
a45c6cb8 1177 host->dma_ch = -1;
c5c98927 1178 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1179
1180 /* If DMA has finished after TC, complete the request */
1181 if (!req_in_progress) {
1182 struct mmc_request *mrq = host->mrq;
1183
1184 host->mrq = NULL;
1185 mmc_request_done(host->mmc, mrq);
1186 }
a45c6cb8
MC		 1187}
1188
9782aff8
PF		 1189static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1190 struct mmc_data *data,
c5c98927 1191 struct omap_hsmmc_next *next,
26b88520 1192 struct dma_chan *chan)
9782aff8
PF		 1193{
1194 int dma_len;
1195
1196 if (!next && data->host_cookie &&
1197 data->host_cookie != host->next_data.cookie) {
2cecdf00 1198 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1199 " host->next_data.cookie %d\n",
1200 __func__, data->host_cookie, host->next_data.cookie);
1201 data->host_cookie = 0;
1202 }
1203
1204 /* Check if next job is already prepared */
1205 if (next ||
1206 (!next && data->host_cookie != host->next_data.cookie)) {
26b88520 1207 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1208 omap_hsmmc_get_dma_dir(host, data));
1209
1210 } else {
1211 dma_len = host->next_data.dma_len;
1212 host->next_data.dma_len = 0;
1213 }
1214
1215
1216 if (dma_len == 0)
1217 return -EINVAL;
1218
1219 if (next) {
1220 next->dma_len = dma_len;
1221 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1222 } else
1223 host->dma_len = dma_len;
1224
1225 return 0;
1226}
1227
a45c6cb8
MC		 1228/*
1229 * Routine to configure and start DMA for the MMC card
1230 */
70a3341a
DK		 1231static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1232 struct mmc_request *req)
a45c6cb8 1233{
26b88520
RK		 1234 struct dma_slave_config cfg;
1235 struct dma_async_tx_descriptor *tx;
1236 int ret = 0, i;
a45c6cb8 1237 struct mmc_data *data = req->data;
c5c98927 1238 struct dma_chan *chan;
a45c6cb8 1239
0ccd76d4 1240 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1241 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1242 struct scatterlist *sgl;
1243
1244 sgl = data->sg + i;
1245 if (sgl->length % data->blksz)
1246 return -EINVAL;
1247 }
1248 if ((data->blksz % 4) != 0)
1249 /* REVISIT: The MMC buffer increments only when MSB is written.
1250 * Return error for blksz which is non multiple of four.
1251 */
1252 return -EINVAL;
1253
b417577d 1254 BUG_ON(host->dma_ch != -1);
a45c6cb8 1255
c5c98927 1256 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1257
26b88520
RK		 1258 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1259 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1260 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1261 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1262 cfg.src_maxburst = data->blksz / 4;
1263 cfg.dst_maxburst = data->blksz / 4;
c5c98927 1264
26b88520
RK		 1265 ret = dmaengine_slave_config(chan, &cfg);
1266 if (ret)
a45c6cb8 1267 return ret;
c5c98927 1268
26b88520 1269 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1270 if (ret)
1271 return ret;
a45c6cb8 1272
26b88520
RK		 1273 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1274 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1275 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1276 if (!tx) {
1277 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1278 /* FIXME: cleanup */
1279 return -1;
1280 }
a45c6cb8 1281
26b88520
RK		 1282 tx->callback = omap_hsmmc_dma_callback;
1283 tx->callback_param = host;
a45c6cb8 1284
26b88520
RK		 1285 /* Does not fail */
1286 dmaengine_submit(tx);
c5c98927 1287
26b88520 1288 host->dma_ch = 1;
c5c98927 1289
26b88520 1290 dma_async_issue_pending(chan);
a45c6cb8 1291
a45c6cb8
MC		 1292 return 0;
1293}
1294
70a3341a 1295static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1296 unsigned int timeout_ns,
1297 unsigned int timeout_clks)
a45c6cb8
MC		 1298{
1299 unsigned int timeout, cycle_ns;
1300 uint32_t reg, clkd, dto = 0;
1301
1302 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1303 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1304 if (clkd == 0)
1305 clkd = 1;
1306
1307 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1308 timeout = timeout_ns / cycle_ns;
1309 timeout += timeout_clks;
a45c6cb8
MC		 1310 if (timeout) {
1311 while ((timeout & 0x80000000) == 0) {
1312 dto += 1;
1313 timeout <<= 1;
1314 }
1315 dto = 31 - dto;
1316 timeout <<= 1;
1317 if (timeout && dto)
1318 dto += 1;
1319 if (dto >= 13)
1320 dto -= 13;
1321 else
1322 dto = 0;
1323 if (dto > 14)
1324 dto = 14;
1325 }
1326
1327 reg &= ~DTO_MASK;
1328 reg |= dto << DTO_SHIFT;
1329 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1330}
1331
1332/*
1333 * Configure block length for MMC/SD cards and initiate the transfer.
1334 */
1335static int
70a3341a 1336omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1337{
1338 int ret;
1339 host->data = req->data;
1340
1341 if (req->data == NULL) {
a45c6cb8 1342 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1343 /*
1344 * Set an arbitrary 100ms data timeout for commands with
1345 * busy signal.
1346 */
1347 if (req->cmd->flags & MMC_RSP_BUSY)
1348 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1349 return 0;
1350 }
1351
1352 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1353 | (req->data->blocks << 16));
e2bf08d6 1354 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1355
a45c6cb8 1356 if (host->use_dma) {
70a3341a 1357 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1358 if (ret != 0) {
1359 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1360 return ret;
1361 }
1362 }
1363 return 0;
1364}
1365
9782aff8
PF		 1366static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1367 int err)
1368{
1369 struct omap_hsmmc_host *host = mmc_priv(mmc);
1370 struct mmc_data *data = mrq->data;
1371
26b88520 1372 if (host->use_dma && data->host_cookie) {
c5c98927 1373 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1374
26b88520
RK		 1375 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1376 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1377 data->host_cookie = 0;
1378 }
1379}
1380
1381static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1382 bool is_first_req)
1383{
1384 struct omap_hsmmc_host *host = mmc_priv(mmc);
1385
1386 if (mrq->data->host_cookie) {
1387 mrq->data->host_cookie = 0;
1388 return ;
1389 }
1390
c5c98927
RK		 1391 if (host->use_dma) {
1392 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1393
9782aff8 1394 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1395 &host->next_data, c))
9782aff8 1396 mrq->data->host_cookie = 0;
c5c98927 1397 }
9782aff8
PF		 1398}
1399
a45c6cb8
MC		 1400/*
1401 * Request function. for read/write operation
1402 */
70a3341a 1403static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1404{
70a3341a 1405 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1406 int err;
a45c6cb8 1407
b417577d
AH		 1408 BUG_ON(host->req_in_progress);
1409 BUG_ON(host->dma_ch != -1);
1410 if (host->protect_card) {
1411 if (host->reqs_blocked < 3) {
1412 /*
1413 * Ensure the controller is left in a consistent
1414 * state by resetting the command and data state
1415 * machines.
1416 */
1417 omap_hsmmc_reset_controller_fsm(host, SRD);
1418 omap_hsmmc_reset_controller_fsm(host, SRC);
1419 host->reqs_blocked += 1;
1420 }
1421 req->cmd->error = -EBADF;
1422 if (req->data)
1423 req->data->error = -EBADF;
1424 req->cmd->retries = 0;
1425 mmc_request_done(mmc, req);
1426 return;
1427 } else if (host->reqs_blocked)
1428 host->reqs_blocked = 0;
a45c6cb8
MC		 1429 WARN_ON(host->mrq != NULL);
1430 host->mrq = req;
70a3341a 1431 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1432 if (err) {
1433 req->cmd->error = err;
1434 if (req->data)
1435 req->data->error = err;
1436 host->mrq = NULL;
1437 mmc_request_done(mmc, req);
1438 return;
1439 }
1440
70a3341a 1441 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1442}
1443
a45c6cb8 1444/* Routine to configure clock values. Exposed API to core */
70a3341a 1445static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1446{
70a3341a 1447 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1448 int do_send_init_stream = 0;
a45c6cb8 1449
fa4aa2d4 1450 pm_runtime_get_sync(host->dev);
5e2ea617 1451
a3621465
AH		 1452 if (ios->power_mode != host->power_mode) {
1453 switch (ios->power_mode) {
1454 case MMC_POWER_OFF:
1455 mmc_slot(host).set_power(host->dev, host->slot_id,
1456 0, 0);
1457 break;
1458 case MMC_POWER_UP:
1459 mmc_slot(host).set_power(host->dev, host->slot_id,
1460 1, ios->vdd);
1461 break;
1462 case MMC_POWER_ON:
1463 do_send_init_stream = 1;
1464 break;
1465 }
1466 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1467 }
1468
dd498eff
DK		 1469 /* FIXME: set registers based only on changes to ios */
1470
3796fb8a 1471 omap_hsmmc_set_bus_width(host);
a45c6cb8 1472
4621d5f8 1473 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1474 /* Only MMC1 can interface at 3V without some flavor
1475 * of external transceiver; but they all handle 1.8V.
1476 */
a45c6cb8 1477 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1f84b71b
RN		 1478 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1479 /*
1480 * With pbias cell programming missing, this
1481 * can't be allowed when booting with device
1482 * tree.
1483 */
4d048f91 1484 !host->dev->of_node) {
a45c6cb8
MC		 1485 /*
1486 * The mmc_select_voltage fn of the core does
1487 * not seem to set the power_mode to
1488 * MMC_POWER_UP upon recalculating the voltage.
1489 * vdd 1.8v.
1490 */
70a3341a
DK		 1491 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1492 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1493 "Switch operation failed\n");
1494 }
1495 }
1496
5934df2f 1497 omap_hsmmc_set_clock(host);
a45c6cb8 1498
a3621465 1499 if (do_send_init_stream)
a45c6cb8
MC		 1500 send_init_stream(host);
1501
3796fb8a 1502 omap_hsmmc_set_bus_mode(host);
5e2ea617 1503
fa4aa2d4 1504 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1505}
1506
1507static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1508{
70a3341a 1509 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1510
191d1f1d 1511 if (!mmc_slot(host).card_detect)
a45c6cb8 1512 return -ENOSYS;
db0fefc5 1513 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1514}
1515
1516static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1517{
70a3341a 1518 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1519
191d1f1d 1520 if (!mmc_slot(host).get_ro)
a45c6cb8 1521 return -ENOSYS;
191d1f1d 1522 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1523}
1524
4816858c
GI		 1525static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1526{
1527 struct omap_hsmmc_host *host = mmc_priv(mmc);
1528
1529 if (mmc_slot(host).init_card)
1530 mmc_slot(host).init_card(card);
1531}
1532
70a3341a 1533static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1534{
1535 u32 hctl, capa, value;
1536
1537 /* Only MMC1 supports 3.0V */
4621d5f8 1538 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1539 hctl = SDVS30;
1540 capa = VS30 | VS18;
1541 } else {
1542 hctl = SDVS18;
1543 capa = VS18;
1544 }
1545
1546 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1547 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1548
1549 value = OMAP_HSMMC_READ(host->base, CAPA);
1550 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1551
1b331e69 1552 /* Set SD bus power bit */
e13bb300 1553 set_sd_bus_power(host);
1b331e69
KK		 1554}
1555
70a3341a 1556static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1557{
70a3341a 1558 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1559
fa4aa2d4
B		 1560 pm_runtime_get_sync(host->dev);
1561
dd498eff
DK		 1562 return 0;
1563}
1564
907d2e7c 1565static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1566{
70a3341a 1567 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1568
fa4aa2d4
B		 1569 pm_runtime_mark_last_busy(host->dev);
1570 pm_runtime_put_autosuspend(host->dev);
1571
dd498eff
DK		 1572 return 0;
1573}
1574
70a3341a
DK		 1575static const struct mmc_host_ops omap_hsmmc_ops = {
1576 .enable = omap_hsmmc_enable_fclk,
1577 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1578 .post_req = omap_hsmmc_post_req,
1579 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1580 .request = omap_hsmmc_request,
1581 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1582 .get_cd = omap_hsmmc_get_cd,
1583 .get_ro = omap_hsmmc_get_ro,
4816858c 1584 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1585 /* NYET -- enable_sdio_irq */
1586};
1587
d900f712
DK		 1588#ifdef CONFIG_DEBUG_FS
1589
70a3341a 1590static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1591{
1592 struct mmc_host *mmc = s->private;
70a3341a 1593 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1594 int context_loss = 0;
1595
70a3341a
DK		 1596 if (host->pdata->get_context_loss_count)
1597 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1598
907d2e7c
AH		 1599 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1600 mmc->index, host->context_loss, context_loss);
5e2ea617 1601
7a8c2cef 1602 if (host->suspended) {
dd498eff
DK		 1603 seq_printf(s, "host suspended, can't read registers\n");
1604 return 0;
1605 }
1606
fa4aa2d4 1607 pm_runtime_get_sync(host->dev);
d900f712 1608
d900f712
DK		 1609 seq_printf(s, "CON:\t\t0x%08x\n",
1610 OMAP_HSMMC_READ(host->base, CON));
1611 seq_printf(s, "HCTL:\t\t0x%08x\n",
1612 OMAP_HSMMC_READ(host->base, HCTL));
1613 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1614 OMAP_HSMMC_READ(host->base, SYSCTL));
1615 seq_printf(s, "IE:\t\t0x%08x\n",
1616 OMAP_HSMMC_READ(host->base, IE));
1617 seq_printf(s, "ISE:\t\t0x%08x\n",
1618 OMAP_HSMMC_READ(host->base, ISE));
1619 seq_printf(s, "CAPA:\t\t0x%08x\n",
1620 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1621
fa4aa2d4
B		 1622 pm_runtime_mark_last_busy(host->dev);
1623 pm_runtime_put_autosuspend(host->dev);
dd498eff 1624
d900f712
DK		 1625 return 0;
1626}
1627
70a3341a 1628static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1629{
70a3341a 1630 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1631}
1632
1633static const struct file_operations mmc_regs_fops = {
70a3341a 1634 .open = omap_hsmmc_regs_open,
d900f712
DK		 1635 .read = seq_read,
1636 .llseek = seq_lseek,
1637 .release = single_release,
1638};
1639
70a3341a 1640static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1641{
1642 if (mmc->debugfs_root)
1643 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1644 mmc, &mmc_regs_fops);
1645}
1646
1647#else
1648
70a3341a 1649static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1650{
1651}
1652
1653#endif
1654
46856a68
RN		 1655#ifdef CONFIG_OF
1656static u16 omap4_reg_offset = 0x100;
1657
1658static const struct of_device_id omap_mmc_of_match[] = {
1659 {
1660 .compatible = "ti,omap2-hsmmc",
1661 },
1662 {
1663 .compatible = "ti,omap3-hsmmc",
1664 },
1665 {
1666 .compatible = "ti,omap4-hsmmc",
1667 .data = &omap4_reg_offset,
1668 },
1669 {},
b6d085f6 1670};
46856a68
RN		 1671MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1672
1673static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1674{
1675 struct omap_mmc_platform_data *pdata;
1676 struct device_node *np = dev->of_node;
1677 u32 bus_width;
1678
1679 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1680 if (!pdata)
1681 return NULL; /* out of memory */
1682
1683 if (of_find_property(np, "ti,dual-volt", NULL))
1684 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1685
1686 /* This driver only supports 1 slot */
1687 pdata->nr_slots = 1;
1688 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1689 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1690
1691 if (of_find_property(np, "ti,non-removable", NULL)) {
1692 pdata->slots[0].nonremovable = true;
1693 pdata->slots[0].no_regulator_off_init = true;
1694 }
7f217794 1695 of_property_read_u32(np, "bus-width", &bus_width);
46856a68
RN		 1696 if (bus_width == 4)
1697 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1698 else if (bus_width == 8)
1699 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1700
1701 if (of_find_property(np, "ti,needs-special-reset", NULL))
1702 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1703
1704 return pdata;
1705}
1706#else
1707static inline struct omap_mmc_platform_data
1708 *of_get_hsmmc_pdata(struct device *dev)
1709{
1710 return NULL;
1711}
1712#endif
1713
efa25fd3 1714static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1715{
1716 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1717 struct mmc_host *mmc;
70a3341a 1718 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1719 struct resource *res;
db0fefc5 1720 int ret, irq;
46856a68 1721 const struct of_device_id *match;
26b88520
RK		 1722 dma_cap_mask_t mask;
1723 unsigned tx_req, rx_req;
46856a68
RN		 1724
1725 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1726 if (match) {
1727 pdata = of_get_hsmmc_pdata(&pdev->dev);
1728 if (match->data) {
1729 u16 *offsetp = match->data;
1730 pdata->reg_offset = *offsetp;
1731 }
1732 }
a45c6cb8
MC		 1733
1734 if (pdata == NULL) {
1735 dev_err(&pdev->dev, "Platform Data is missing\n");
1736 return -ENXIO;
1737 }
1738
1739 if (pdata->nr_slots == 0) {
1740 dev_err(&pdev->dev, "No Slots\n");
1741 return -ENXIO;
1742 }
1743
1744 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1745 irq = platform_get_irq(pdev, 0);
1746 if (res == NULL || irq < 0)
1747 return -ENXIO;
1748
984b203a 1749 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1750 if (res == NULL)
1751 return -EBUSY;
1752
db0fefc5
AH		 1753 ret = omap_hsmmc_gpio_init(pdata);
1754 if (ret)
1755 goto err;
1756
70a3341a 1757 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1758 if (!mmc) {
1759 ret = -ENOMEM;
db0fefc5 1760 goto err_alloc;
a45c6cb8
MC		 1761 }
1762
1763 host = mmc_priv(mmc);
1764 host->mmc = mmc;
1765 host->pdata = pdata;
1766 host->dev = &pdev->dev;
1767 host->use_dma = 1;
a45c6cb8
MC		 1768 host->dma_ch = -1;
1769 host->irq = irq;
a45c6cb8 1770 host->slot_id = 0;
fc307df8 1771 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1772 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1773 host->power_mode = MMC_POWER_OFF;
9782aff8 1774 host->next_data.cookie = 1;
a45c6cb8
MC		 1775
1776 platform_set_drvdata(pdev, host);
a45c6cb8 1777
7a8c2cef 1778 mmc->ops = &omap_hsmmc_ops;
dd498eff 1779
e0eb2424
AH		 1780 /*
1781 * If regulator_disable can only put vcc_aux to sleep then there is
1782 * no off state.
1783 */
1784 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1785 mmc_slot(host).no_off = 1;
1786
d418ed87
DM		 1787 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1788
1789 if (pdata->max_freq > 0)
1790 mmc->f_max = pdata->max_freq;
1791 else
1792 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1793
4dffd7a2 1794 spin_lock_init(&host->irq_lock);
a45c6cb8 1795
6f7607cc 1796 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1797 if (IS_ERR(host->fclk)) {
1798 ret = PTR_ERR(host->fclk);
1799 host->fclk = NULL;
a45c6cb8
MC		 1800 goto err1;
1801 }
1802
9b68256c
PW		 1803 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1804 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1805 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1806 }
dd498eff 1807
fa4aa2d4
B		 1808 pm_runtime_enable(host->dev);
1809 pm_runtime_get_sync(host->dev);
1810 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1811 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1812
92a3aebf
B		 1813 omap_hsmmc_context_save(host);
1814
cd03d9a8
RN		 1815 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1816 /*
1817 * MMC can still work without debounce clock.
1818 */
1819 if (IS_ERR(host->dbclk)) {
1820 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1821 host->dbclk = NULL;
94c18149 1822 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8
RN		 1823 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1824 clk_put(host->dbclk);
1825 host->dbclk = NULL;
2bec0893 1826 }
a45c6cb8 1827
0ccd76d4
JY		 1828 /* Since we do only SG emulation, we can have as many segs
1829 * as we want. */
a36274e0 1830 mmc->max_segs = 1024;
0ccd76d4 1831
a45c6cb8
MC		 1832 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1833 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1834 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1835 mmc->max_seg_size = mmc->max_req_size;
1836
13189e78 1837 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1838 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1839
3a63833e
SG		 1840 mmc->caps |= mmc_slot(host).caps;
1841 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1842 mmc->caps |= MMC_CAP_4_BIT_DATA;
1843
191d1f1d 1844 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1845 mmc->caps |= MMC_CAP_NONREMOVABLE;
1846
6fdc75de
EP		 1847 mmc->pm_caps = mmc_slot(host).pm_caps;
1848
70a3341a 1849 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1850
b7bf773b
B		 1851 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1852 if (!res) {
1853 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
9c17d08c 1854 ret = -ENXIO;
b7bf773b
B		 1855 goto err_irq;
1856 }
26b88520 1857 tx_req = res->start;
b7bf773b
B		 1858
1859 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1860 if (!res) {
1861 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
9c17d08c 1862 ret = -ENXIO;
f3e2f1dd
GI		 1863 goto err_irq;
1864 }
26b88520 1865 rx_req = res->start;
a45c6cb8 1866
26b88520
RK		 1867 dma_cap_zero(mask);
1868 dma_cap_set(DMA_SLAVE, mask);
1869
1870 host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1871 if (!host->rx_chan) {
1872 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
04e8c7bc 1873 ret = -ENXIO;
26b88520
RK		 1874 goto err_irq;
1875 }
1876
1877 host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1878 if (!host->tx_chan) {
1879 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
04e8c7bc 1880 ret = -ENXIO;
26b88520 1881 goto err_irq;
c5c98927 1882 }
a45c6cb8
MC		 1883
1884 /* Request IRQ for MMC operations */
d9618e9f 1885 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1886 mmc_hostname(mmc), host);
1887 if (ret) {
1888 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1889 goto err_irq;
1890 }
1891
1892 if (pdata->init != NULL) {
1893 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 1894 dev_dbg(mmc_dev(host->mmc),
1895 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1896 goto err_irq_cd_init;
1897 }
1898 }
db0fefc5 1899
b702b106 1900 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1901 ret = omap_hsmmc_reg_get(host);
1902 if (ret)
1903 goto err_reg;
1904 host->use_reg = 1;
1905 }
1906
b583f26d 1907 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1908
1909 /* Request IRQ for card detect */
e1a55f5e 1910 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1911 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1912 NULL,
1913 omap_hsmmc_detect,
db35f83e 1914 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
7efab4f3 1915 mmc_hostname(mmc), host);
a45c6cb8
MC		 1916 if (ret) {
1917 dev_dbg(mmc_dev(host->mmc),
1918 "Unable to grab MMC CD IRQ\n");
1919 goto err_irq_cd;
1920 }
72f2e2c7 1921 pdata->suspend = omap_hsmmc_suspend_cdirq;
1922 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1923 }
1924
b417577d 1925 omap_hsmmc_disable_irq(host);
a45c6cb8 1926
b62f6228
AH		 1927 omap_hsmmc_protect_card(host);
1928
a45c6cb8
MC		 1929 mmc_add_host(mmc);
1930
191d1f1d 1931 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1932 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1933 if (ret < 0)
1934 goto err_slot_name;
1935 }
191d1f1d 1936 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1937 ret = device_create_file(&mmc->class_dev,
1938 &dev_attr_cover_switch);
1939 if (ret < 0)
db0fefc5 1940 goto err_slot_name;
a45c6cb8
MC		 1941 }
1942
70a3341a 1943 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 1944 pm_runtime_mark_last_busy(host->dev);
1945 pm_runtime_put_autosuspend(host->dev);
d900f712 1946
a45c6cb8
MC		 1947 return 0;
1948
a45c6cb8
MC		 1949err_slot_name:
1950 mmc_remove_host(mmc);
a45c6cb8 1951 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 1952err_irq_cd:
1953 if (host->use_reg)
1954 omap_hsmmc_reg_put(host);
1955err_reg:
1956 if (host->pdata->cleanup)
1957 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 1958err_irq_cd_init:
1959 free_irq(host->irq, host);
1960err_irq:
c5c98927
RK		 1961 if (host->tx_chan)
1962 dma_release_channel(host->tx_chan);
1963 if (host->rx_chan)
1964 dma_release_channel(host->rx_chan);
d59d77ed 1965 pm_runtime_put_sync(host->dev);
37f6190d 1966 pm_runtime_disable(host->dev);
a45c6cb8 1967 clk_put(host->fclk);
cd03d9a8 1968 if (host->dbclk) {
94c18149 1969 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1970 clk_put(host->dbclk);
1971 }
a45c6cb8
MC		 1972err1:
1973 iounmap(host->base);
db0fefc5
AH		 1974 platform_set_drvdata(pdev, NULL);
1975 mmc_free_host(mmc);
1976err_alloc:
1977 omap_hsmmc_gpio_free(pdata);
a45c6cb8 1978err:
48b332f9
RK		 1979 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1980 if (res)
1981 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 1982 return ret;
1983}
1984
efa25fd3 1985static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 1986{
70a3341a 1987 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 1988 struct resource *res;
1989
927ce944
FB		 1990 pm_runtime_get_sync(host->dev);
1991 mmc_remove_host(host->mmc);
1992 if (host->use_reg)
1993 omap_hsmmc_reg_put(host);
1994 if (host->pdata->cleanup)
1995 host->pdata->cleanup(&pdev->dev);
1996 free_irq(host->irq, host);
1997 if (mmc_slot(host).card_detect_irq)
1998 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 1999
c5c98927
RK		 2000 if (host->tx_chan)
2001 dma_release_channel(host->tx_chan);
2002 if (host->rx_chan)
2003 dma_release_channel(host->rx_chan);
2004
927ce944
FB		 2005 pm_runtime_put_sync(host->dev);
2006 pm_runtime_disable(host->dev);
2007 clk_put(host->fclk);
cd03d9a8 2008 if (host->dbclk) {
94c18149 2009 clk_disable_unprepare(host->dbclk);
927ce944 2010 clk_put(host->dbclk);
a45c6cb8
MC		 2011 }
2012
927ce944
FB		 2013 mmc_free_host(host->mmc);
2014 iounmap(host->base);
2015 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2016
a45c6cb8
MC		 2017 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2018 if (res)
984b203a 2019 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2020 platform_set_drvdata(pdev, NULL);
2021
2022 return 0;
2023}
2024
2025#ifdef CONFIG_PM
a791daa1 2026static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2027{
2028 int ret = 0;
927ce944 2029 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2030
927ce944 2031 if (!host)
a45c6cb8
MC		 2032 return 0;
2033
927ce944
FB		 2034 if (host && host->suspended)
2035 return 0;
fa4aa2d4 2036
927ce944
FB		 2037 pm_runtime_get_sync(host->dev);
2038 host->suspended = 1;
2039 if (host->pdata->suspend) {
2040 ret = host->pdata->suspend(dev, host->slot_id);
31f9d463 2041 if (ret) {
927ce944
FB		 2042 dev_dbg(dev, "Unable to handle MMC board"
2043 " level suspend\n");
a6b2240d 2044 host->suspended = 0;
927ce944 2045 return ret;
a6b2240d 2046 }
927ce944
FB		 2047 }
2048 ret = mmc_suspend_host(host->mmc);
31f9d463 2049
927ce944
FB		 2050 if (ret) {
2051 host->suspended = 0;
2052 if (host->pdata->resume) {
c4c8eeb4 2053 if (host->pdata->resume(dev, host->slot_id))
927ce944 2054 dev_dbg(dev, "Unmask interrupt failed\n");
31f9d463 2055 }
927ce944
FB		 2056 goto err;
2057 }
31f9d463 2058
927ce944
FB		 2059 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2060 omap_hsmmc_disable_irq(host);
2061 OMAP_HSMMC_WRITE(host->base, HCTL,
2062 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2063 }
927ce944 2064
cd03d9a8 2065 if (host->dbclk)
94c18149 2066 clk_disable_unprepare(host->dbclk);
31f9d463
EP		 2067err:
2068 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2069 return ret;
2070}
2071
2072/* Routine to resume the MMC device */
a791daa1 2073static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2074{
2075 int ret = 0;
927ce944
FB		 2076 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2077
2078 if (!host)
2079 return 0;
a45c6cb8
MC		 2080
2081 if (host && !host->suspended)
2082 return 0;
2083
927ce944 2084 pm_runtime_get_sync(host->dev);
11dd62a7 2085
cd03d9a8 2086 if (host->dbclk)
94c18149 2087 clk_prepare_enable(host->dbclk);
2bec0893 2088
927ce944
FB		 2089 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2090 omap_hsmmc_conf_bus_power(host);
1b331e69 2091
927ce944
FB		 2092 if (host->pdata->resume) {
2093 ret = host->pdata->resume(dev, host->slot_id);
2094 if (ret)
2095 dev_dbg(dev, "Unmask interrupt failed\n");
2096 }
a45c6cb8 2097
927ce944 2098 omap_hsmmc_protect_card(host);
b62f6228 2099
927ce944
FB		 2100 /* Notify the core to resume the host */
2101 ret = mmc_resume_host(host->mmc);
2102 if (ret == 0)
2103 host->suspended = 0;
fa4aa2d4 2104
927ce944
FB		 2105 pm_runtime_mark_last_busy(host->dev);
2106 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2107
2108 return ret;
2109
a45c6cb8
MC		 2110}
2111
2112#else
70a3341a
DK		 2113#define omap_hsmmc_suspend NULL
2114#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2115#endif
2116
fa4aa2d4
B		 2117static int omap_hsmmc_runtime_suspend(struct device *dev)
2118{
2119 struct omap_hsmmc_host *host;
2120
2121 host = platform_get_drvdata(to_platform_device(dev));
2122 omap_hsmmc_context_save(host);
927ce944 2123 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2124
2125 return 0;
2126}
2127
2128static int omap_hsmmc_runtime_resume(struct device *dev)
2129{
2130 struct omap_hsmmc_host *host;
2131
2132 host = platform_get_drvdata(to_platform_device(dev));
2133 omap_hsmmc_context_restore(host);
927ce944 2134 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2135
2136 return 0;
2137}
2138
a791daa1 2139static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2140 .suspend = omap_hsmmc_suspend,
2141 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2142 .runtime_suspend = omap_hsmmc_runtime_suspend,
2143 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2144};
2145
2146static struct platform_driver omap_hsmmc_driver = {
efa25fd3
FB		 2147 .probe = omap_hsmmc_probe,
2148 .remove = __devexit_p(omap_hsmmc_remove),
a45c6cb8
MC		 2149 .driver = {
2150 .name = DRIVER_NAME,
2151 .owner = THIS_MODULE,
a791daa1 2152 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2153 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2154 },
2155};
2156
b796450b 2157module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2158MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2159MODULE_LICENSE("GPL");
2160MODULE_ALIAS("platform:" DRIVER_NAME);
2161MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
This page took 0.469003 seconds and 5 git commands to generate.