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Merge tag 'for-linus-3.11-merge-window-part-2' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
CommitLineData
ff984e57
WW		 1/* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
433e075c 24#include <linux/slab.h>
ff984e57
WW		 25#include <linux/highmem.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/sd.h>
31#include <linux/mmc/card.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35/* SD Tuning Data Structure
36 * Record continuous timing phase path
37 */
38struct timing_phase_path {
39 int start;
40 int end;
41 int mid;
42 int len;
43};
44
45struct realtek_pci_sdmmc {
46 struct platform_device *pdev;
47 struct rtsx_pcr *pcr;
48 struct mmc_host *mmc;
49 struct mmc_request *mrq;
50
51 struct mutex host_mutex;
52
53 u8 ssc_depth;
54 unsigned int clock;
55 bool vpclk;
56 bool double_clk;
57 bool eject;
58 bool initial_mode;
59 bool ddr_mode;
d88691be
WW		 60 int power_state;
61#define SDMMC_POWER_ON 1
62#define SDMMC_POWER_OFF 0
ff984e57
WW		 63};
64
65static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
66{
67 return &(host->pdev->dev);
68}
69
70static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
71{
72 rtsx_pci_write_register(host->pcr, CARD_STOP,
73 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
74}
75
76#ifdef DEBUG
77static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
78{
79 struct rtsx_pcr *pcr = host->pcr;
80 u16 i;
81 u8 *ptr;
82
83 /* Print SD host internal registers */
84 rtsx_pci_init_cmd(pcr);
85 for (i = 0xFDA0; i <= 0xFDAE; i++)
86 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
87 for (i = 0xFD52; i <= 0xFD69; i++)
88 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
89 rtsx_pci_send_cmd(pcr, 100);
90
91 ptr = rtsx_pci_get_cmd_data(pcr);
92 for (i = 0xFDA0; i <= 0xFDAE; i++)
93 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
94 for (i = 0xFD52; i <= 0xFD69; i++)
95 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
96}
97#else
98#define sd_print_debug_regs(host)
99#endif /* DEBUG */
100
101static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
102 u8 *buf, int buf_len, int timeout)
103{
104 struct rtsx_pcr *pcr = host->pcr;
105 int err, i;
106 u8 trans_mode;
107
108 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
109
110 if (!buf)
111 buf_len = 0;
112
113 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
114 trans_mode = SD_TM_AUTO_TUNING;
115 else
116 trans_mode = SD_TM_NORMAL_READ;
117
118 rtsx_pci_init_cmd(pcr);
119
120 for (i = 0; i < 5; i++)
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
122
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
125 0xFF, (u8)(byte_cnt >> 8));
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
128
129 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
130 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
131 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
132 if (trans_mode != SD_TM_AUTO_TUNING)
133 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
134 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
135
136 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
137 0xFF, trans_mode | SD_TRANSFER_START);
138 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
139 SD_TRANSFER_END, SD_TRANSFER_END);
140
141 err = rtsx_pci_send_cmd(pcr, timeout);
142 if (err < 0) {
143 sd_print_debug_regs(host);
144 dev_dbg(sdmmc_dev(host),
145 "rtsx_pci_send_cmd fail (err = %d)\n", err);
146 return err;
147 }
148
149 if (buf && buf_len) {
150 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
151 if (err < 0) {
152 dev_dbg(sdmmc_dev(host),
153 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
154 return err;
155 }
156 }
157
158 return 0;
159}
160
161static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
162 u8 *buf, int buf_len, int timeout)
163{
164 struct rtsx_pcr *pcr = host->pcr;
165 int err, i;
166 u8 trans_mode;
167
168 if (!buf)
169 buf_len = 0;
170
171 if (buf && buf_len) {
172 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
173 if (err < 0) {
174 dev_dbg(sdmmc_dev(host),
175 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
176 return err;
177 }
178 }
179
180 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
181 rtsx_pci_init_cmd(pcr);
182
183 if (cmd) {
184 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
185 cmd[0] - 0x40);
186
187 for (i = 0; i < 5; i++)
188 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
189 SD_CMD0 + i, 0xFF, cmd[i]);
190 }
191
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
194 0xFF, (u8)(byte_cnt >> 8));
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
196 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
197
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
199 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
200 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
201
202 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
203 trans_mode | SD_TRANSFER_START);
204 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
205 SD_TRANSFER_END, SD_TRANSFER_END);
206
207 err = rtsx_pci_send_cmd(pcr, timeout);
208 if (err < 0) {
209 sd_print_debug_regs(host);
210 dev_dbg(sdmmc_dev(host),
211 "rtsx_pci_send_cmd fail (err = %d)\n", err);
212 return err;
213 }
214
215 return 0;
216}
217
218static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
219 struct mmc_command *cmd)
220{
221 struct rtsx_pcr *pcr = host->pcr;
222 u8 cmd_idx = (u8)cmd->opcode;
223 u32 arg = cmd->arg;
224 int err = 0;
225 int timeout = 100;
226 int i;
227 u8 *ptr;
228 int stat_idx = 0;
229 u8 rsp_type;
230 int rsp_len = 5;
231
232 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
233 __func__, cmd_idx, arg);
234
235 /* Response type:
236 * R0
237 * R1, R5, R6, R7
238 * R1b
239 * R2
240 * R3, R4
241 */
242 switch (mmc_resp_type(cmd)) {
243 case MMC_RSP_NONE:
244 rsp_type = SD_RSP_TYPE_R0;
245 rsp_len = 0;
246 break;
247 case MMC_RSP_R1:
248 rsp_type = SD_RSP_TYPE_R1;
249 break;
250 case MMC_RSP_R1B:
251 rsp_type = SD_RSP_TYPE_R1b;
252 break;
253 case MMC_RSP_R2:
254 rsp_type = SD_RSP_TYPE_R2;
255 rsp_len = 16;
256 break;
257 case MMC_RSP_R3:
258 rsp_type = SD_RSP_TYPE_R3;
259 break;
260 default:
261 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
262 err = -EINVAL;
263 goto out;
264 }
265
266 if (rsp_type == SD_RSP_TYPE_R1b)
267 timeout = 3000;
268
269 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
270 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
271 0xFF, SD_CLK_TOGGLE_EN);
272 if (err < 0)
273 goto out;
274 }
275
276 rtsx_pci_init_cmd(pcr);
277
278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
279 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
280 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
282 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
283
284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
285 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
286 0x01, PINGPONG_BUFFER);
287 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
288 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
289 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
290 SD_TRANSFER_END | SD_STAT_IDLE,
291 SD_TRANSFER_END | SD_STAT_IDLE);
292
293 if (rsp_type == SD_RSP_TYPE_R2) {
294 /* Read data from ping-pong buffer */
295 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
296 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
297 stat_idx = 16;
298 } else if (rsp_type != SD_RSP_TYPE_R0) {
299 /* Read data from SD_CMDx registers */
300 for (i = SD_CMD0; i <= SD_CMD4; i++)
301 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
302 stat_idx = 5;
303 }
304
305 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
306
307 err = rtsx_pci_send_cmd(pcr, timeout);
308 if (err < 0) {
309 sd_print_debug_regs(host);
310 sd_clear_error(host);
311 dev_dbg(sdmmc_dev(host),
312 "rtsx_pci_send_cmd error (err = %d)\n", err);
313 goto out;
314 }
315
316 if (rsp_type == SD_RSP_TYPE_R0) {
317 err = 0;
318 goto out;
319 }
320
321 /* Eliminate returned value of CHECK_REG_CMD */
322 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
323
324 /* Check (Start,Transmission) bit of Response */
325 if ((ptr[0] & 0xC0) != 0) {
326 err = -EILSEQ;
327 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
328 goto out;
329 }
330
331 /* Check CRC7 */
332 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
333 if (ptr[stat_idx] & SD_CRC7_ERR) {
334 err = -EILSEQ;
335 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
336 goto out;
337 }
338 }
339
340 if (rsp_type == SD_RSP_TYPE_R2) {
341 for (i = 0; i < 4; i++) {
342 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
343 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
344 i, cmd->resp[i]);
345 }
346 } else {
347 cmd->resp[0] = get_unaligned_be32(ptr + 1);
348 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
349 cmd->resp[0]);
350 }
351
352out:
353 cmd->error = err;
354}
355
356static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
357{
358 struct rtsx_pcr *pcr = host->pcr;
359 struct mmc_host *mmc = host->mmc;
360 struct mmc_card *card = mmc->card;
361 struct mmc_data *data = mrq->data;
362 int uhs = mmc_sd_card_uhs(card);
363 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
364 u8 cfg2, trans_mode;
365 int err;
366 size_t data_len = data->blksz * data->blocks;
367
368 if (read) {
369 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
370 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
371 trans_mode = SD_TM_AUTO_READ_3;
372 } else {
373 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
374 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
375 trans_mode = SD_TM_AUTO_WRITE_3;
376 }
377
378 if (!uhs)
379 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
380
381 rtsx_pci_init_cmd(pcr);
382
383 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
384 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
385 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
386 0xFF, (u8)data->blocks);
387 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
388 0xFF, (u8)(data->blocks >> 8));
ff984e57
WW		 389
390 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
391 DMA_DONE_INT, DMA_DONE_INT);
392 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
393 0xFF, (u8)(data_len >> 24));
394 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
395 0xFF, (u8)(data_len >> 16));
396 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
397 0xFF, (u8)(data_len >> 8));
398 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
399 if (read) {
400 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
401 0x03 | DMA_PACK_SIZE_MASK,
402 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
403 } else {
404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
405 0x03 | DMA_PACK_SIZE_MASK,
406 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
407 }
408
409 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
410 0x01, RING_BUFFER);
411
38d324df 412 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
ff984e57
WW		 413 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
414 trans_mode | SD_TRANSFER_START);
415 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
416 SD_TRANSFER_END, SD_TRANSFER_END);
417
418 rtsx_pci_send_cmd_no_wait(pcr);
419
420 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
421 if (err < 0) {
422 sd_clear_error(host);
423 return err;
424 }
425
426 return 0;
427}
428
429static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
430{
431 rtsx_pci_write_register(host->pcr, SD_CFG1,
432 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
433}
434
435static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
436{
437 rtsx_pci_write_register(host->pcr, SD_CFG1,
438 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
439}
440
441static void sd_normal_rw(struct realtek_pci_sdmmc *host,
442 struct mmc_request *mrq)
443{
444 struct mmc_command *cmd = mrq->cmd;
445 struct mmc_data *data = mrq->data;
446 u8 _cmd[5], *buf;
447
448 _cmd[0] = 0x40 | (u8)cmd->opcode;
449 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
450
451 buf = kzalloc(data->blksz, GFP_NOIO);
452 if (!buf) {
453 cmd->error = -ENOMEM;
454 return;
455 }
456
457 if (data->flags & MMC_DATA_READ) {
458 if (host->initial_mode)
459 sd_disable_initial_mode(host);
460
461 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
462 data->blksz, 200);
463
464 if (host->initial_mode)
465 sd_enable_initial_mode(host);
466
467 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
468 } else {
469 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
470
471 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
472 data->blksz, 200);
473 }
474
475 kfree(buf);
476}
477
478static int sd_change_phase(struct realtek_pci_sdmmc *host, u8 sample_point)
479{
480 struct rtsx_pcr *pcr = host->pcr;
481 int err;
482
483 dev_dbg(sdmmc_dev(host), "%s: sample_point = %d\n",
484 __func__, sample_point);
485
486 rtsx_pci_init_cmd(pcr);
487
488 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
489 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPRX_CTL, 0x1F, sample_point);
490 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
491 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
492 PHASE_NOT_RESET, PHASE_NOT_RESET);
493 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
494 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
495
496 err = rtsx_pci_send_cmd(pcr, 100);
497 if (err < 0)
498 return err;
499
500 return 0;
501}
502
503static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
504{
505 struct timing_phase_path path[MAX_PHASE + 1];
506 int i, j, cont_path_cnt;
507 int new_block, max_len, final_path_idx;
508 u8 final_phase = 0xFF;
509
510 /* Parse phase_map, take it as a bit-ring */
511 cont_path_cnt = 0;
512 new_block = 1;
513 j = 0;
514 for (i = 0; i < MAX_PHASE + 1; i++) {
515 if (phase_map & (1 << i)) {
516 if (new_block) {
517 new_block = 0;
518 j = cont_path_cnt++;
519 path[j].start = i;
520 path[j].end = i;
521 } else {
522 path[j].end = i;
523 }
524 } else {
525 new_block = 1;
526 if (cont_path_cnt) {
527 /* Calculate path length and middle point */
528 int idx = cont_path_cnt - 1;
529 path[idx].len =
530 path[idx].end - path[idx].start + 1;
531 path[idx].mid =
532 path[idx].start + path[idx].len / 2;
533 }
534 }
535 }
536
537 if (cont_path_cnt == 0) {
538 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
539 goto finish;
540 } else {
541 /* Calculate last continuous path length and middle point */
542 int idx = cont_path_cnt - 1;
543 path[idx].len = path[idx].end - path[idx].start + 1;
544 path[idx].mid = path[idx].start + path[idx].len / 2;
545 }
546
547 /* Connect the first and last continuous paths if they are adjacent */
548 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
549 /* Using negative index */
550 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
551 path[0].len += path[cont_path_cnt - 1].len;
552 path[0].mid = path[0].start + path[0].len / 2;
553 /* Convert negative middle point index to positive one */
554 if (path[0].mid < 0)
555 path[0].mid += MAX_PHASE + 1;
556 cont_path_cnt--;
557 }
558
559 /* Choose the longest continuous phase path */
560 max_len = 0;
561 final_phase = 0;
562 final_path_idx = 0;
563 for (i = 0; i < cont_path_cnt; i++) {
564 if (path[i].len > max_len) {
565 max_len = path[i].len;
566 final_phase = (u8)path[i].mid;
567 final_path_idx = i;
568 }
569
570 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
571 i, path[i].start);
572 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
573 i, path[i].end);
574 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
575 i, path[i].len);
576 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
577 i, path[i].mid);
578 }
579
580finish:
581 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
582 return final_phase;
583}
584
585static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
586{
587 int err, i;
588 u8 val = 0;
589
590 for (i = 0; i < 100; i++) {
591 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
592 if (val & SD_DATA_IDLE)
593 return;
594
595 udelay(100);
596 }
597}
598
599static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
600 u8 opcode, u8 sample_point)
601{
602 int err;
603 u8 cmd[5] = {0};
604
605 err = sd_change_phase(host, sample_point);
606 if (err < 0)
607 return err;
608
609 cmd[0] = 0x40 | opcode;
610 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
611 if (err < 0) {
612 /* Wait till SD DATA IDLE */
613 sd_wait_data_idle(host);
614 sd_clear_error(host);
615 return err;
616 }
617
618 return 0;
619}
620
621static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
622 u8 opcode, u32 *phase_map)
623{
624 int err, i;
625 u32 raw_phase_map = 0;
626
627 for (i = MAX_PHASE; i >= 0; i--) {
628 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
629 if (err == 0)
630 raw_phase_map |= 1 << i;
631 }
632
633 if (phase_map)
634 *phase_map = raw_phase_map;
635
636 return 0;
637}
638
639static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
640{
641 int err, i;
642 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
643 u8 final_phase;
644
645 for (i = 0; i < RX_TUNING_CNT; i++) {
646 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
647 if (err < 0)
648 return err;
649
650 if (raw_phase_map[i] == 0)
651 break;
652 }
653
654 phase_map = 0xFFFFFFFF;
655 for (i = 0; i < RX_TUNING_CNT; i++) {
656 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
657 i, raw_phase_map[i]);
658 phase_map &= raw_phase_map[i];
659 }
660 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
661
662 if (phase_map) {
663 final_phase = sd_search_final_phase(host, phase_map);
664 if (final_phase == 0xFF)
665 return -EINVAL;
666
667 err = sd_change_phase(host, final_phase);
668 if (err < 0)
669 return err;
670 } else {
671 return -EINVAL;
672 }
673
674 return 0;
675}
676
677static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
678{
679 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
680 struct rtsx_pcr *pcr = host->pcr;
681 struct mmc_command *cmd = mrq->cmd;
682 struct mmc_data *data = mrq->data;
683 unsigned int data_size = 0;
c3481955 684 int err;
ff984e57
WW		 685
686 if (host->eject) {
687 cmd->error = -ENOMEDIUM;
688 goto finish;
689 }
690
c3481955
WW		 691 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
692 if (err) {
693 cmd->error = err;
694 goto finish;
695 }
696
ff984e57
WW		 697 mutex_lock(&pcr->pcr_mutex);
698
699 rtsx_pci_start_run(pcr);
700
701 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
702 host->initial_mode, host->double_clk, host->vpclk);
703 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
704 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
705 CARD_SHARE_MASK, CARD_SHARE_48_SD);
706
707 mutex_lock(&host->host_mutex);
708 host->mrq = mrq;
709 mutex_unlock(&host->host_mutex);
710
711 if (mrq->data)
712 data_size = data->blocks * data->blksz;
713
714 if (!data_size || mmc_op_multi(cmd->opcode) ||
715 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
716 (cmd->opcode == MMC_WRITE_BLOCK)) {
717 sd_send_cmd_get_rsp(host, cmd);
718
719 if (!cmd->error && data_size) {
720 sd_rw_multi(host, mrq);
721
722 if (mmc_op_multi(cmd->opcode) && mrq->stop)
723 sd_send_cmd_get_rsp(host, mrq->stop);
724 }
725 } else {
726 sd_normal_rw(host, mrq);
727 }
728
729 if (mrq->data) {
730 if (cmd->error || data->error)
731 data->bytes_xfered = 0;
732 else
733 data->bytes_xfered = data->blocks * data->blksz;
734 }
735
736 mutex_unlock(&pcr->pcr_mutex);
737
738finish:
739 if (cmd->error)
740 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
741
742 mutex_lock(&host->host_mutex);
743 host->mrq = NULL;
744 mutex_unlock(&host->host_mutex);
745
746 mmc_request_done(mmc, mrq);
747}
748
749static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
750 unsigned char bus_width)
751{
752 int err = 0;
753 u8 width[] = {
754 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
755 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
756 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
757 };
758
759 if (bus_width <= MMC_BUS_WIDTH_8)
760 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
761 0x03, width[bus_width]);
762
763 return err;
764}
765
766static int sd_power_on(struct realtek_pci_sdmmc *host)
767{
768 struct rtsx_pcr *pcr = host->pcr;
769 int err;
770
d88691be
WW		 771 if (host->power_state == SDMMC_POWER_ON)
772 return 0;
773
ff984e57
WW		 774 rtsx_pci_init_cmd(pcr);
775 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
776 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
777 CARD_SHARE_MASK, CARD_SHARE_48_SD);
778 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
779 SD_CLK_EN, SD_CLK_EN);
780 err = rtsx_pci_send_cmd(pcr, 100);
781 if (err < 0)
782 return err;
783
784 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
785 if (err < 0)
786 return err;
787
788 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
789 if (err < 0)
790 return err;
791
792 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
793 if (err < 0)
794 return err;
795
d88691be 796 host->power_state = SDMMC_POWER_ON;
ff984e57
WW		 797 return 0;
798}
799
800static int sd_power_off(struct realtek_pci_sdmmc *host)
801{
802 struct rtsx_pcr *pcr = host->pcr;
803 int err;
804
d88691be
WW		 805 host->power_state = SDMMC_POWER_OFF;
806
ff984e57
WW		 807 rtsx_pci_init_cmd(pcr);
808
809 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
810 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
811
812 err = rtsx_pci_send_cmd(pcr, 100);
813 if (err < 0)
814 return err;
815
816 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
817 if (err < 0)
818 return err;
819
820 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
821}
822
823static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
824 unsigned char power_mode)
825{
826 int err;
827
828 if (power_mode == MMC_POWER_OFF)
829 err = sd_power_off(host);
830 else
831 err = sd_power_on(host);
832
833 return err;
834}
835
836static int sd_set_timing(struct realtek_pci_sdmmc *host,
837 unsigned char timing, bool *ddr_mode)
838{
839 struct rtsx_pcr *pcr = host->pcr;
840 int err = 0;
841
842 *ddr_mode = false;
843
844 rtsx_pci_init_cmd(pcr);
845
846 switch (timing) {
847 case MMC_TIMING_UHS_SDR104:
848 case MMC_TIMING_UHS_SDR50:
849 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
850 0x0C | SD_ASYNC_FIFO_NOT_RST,
851 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
852 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
853 CLK_LOW_FREQ, CLK_LOW_FREQ);
854 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
855 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
856 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
857 break;
858
859 case MMC_TIMING_UHS_DDR50:
860 *ddr_mode = true;
861
862 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
863 0x0C | SD_ASYNC_FIFO_NOT_RST,
864 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
865 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
866 CLK_LOW_FREQ, CLK_LOW_FREQ);
867 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
868 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
869 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
870 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
871 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
872 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
873 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
874 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
875 break;
876
877 case MMC_TIMING_MMC_HS:
878 case MMC_TIMING_SD_HS:
879 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
880 0x0C, SD_20_MODE);
881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
882 CLK_LOW_FREQ, CLK_LOW_FREQ);
883 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
884 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
885 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
886 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
887 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
888 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
889 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
890 break;
891
892 default:
893 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
894 SD_CFG1, 0x0C, SD_20_MODE);
895 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
896 CLK_LOW_FREQ, CLK_LOW_FREQ);
897 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
898 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
899 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
900 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
901 SD_PUSH_POINT_CTL, 0xFF, 0);
902 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
903 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
904 break;
905 }
906
907 err = rtsx_pci_send_cmd(pcr, 100);
908
909 return err;
910}
911
912static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
913{
914 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
915 struct rtsx_pcr *pcr = host->pcr;
916
917 if (host->eject)
918 return;
919
c3481955
WW		 920 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
921 return;
922
ff984e57
WW		 923 mutex_lock(&pcr->pcr_mutex);
924
925 rtsx_pci_start_run(pcr);
926
927 sd_set_bus_width(host, ios->bus_width);
928 sd_set_power_mode(host, ios->power_mode);
929 sd_set_timing(host, ios->timing, &host->ddr_mode);
930
931 host->vpclk = false;
932 host->double_clk = true;
933
934 switch (ios->timing) {
935 case MMC_TIMING_UHS_SDR104:
936 case MMC_TIMING_UHS_SDR50:
937 host->ssc_depth = RTSX_SSC_DEPTH_2M;
938 host->vpclk = true;
939 host->double_clk = false;
940 break;
941 case MMC_TIMING_UHS_DDR50:
942 case MMC_TIMING_UHS_SDR25:
943 host->ssc_depth = RTSX_SSC_DEPTH_1M;
944 break;
945 default:
946 host->ssc_depth = RTSX_SSC_DEPTH_500K;
947 break;
948 }
949
950 host->initial_mode = (ios->clock <= 1000000) ? true : false;
951
952 host->clock = ios->clock;
953 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
954 host->initial_mode, host->double_clk, host->vpclk);
955
956 mutex_unlock(&pcr->pcr_mutex);
957}
958
959static int sdmmc_get_ro(struct mmc_host *mmc)
960{
961 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
962 struct rtsx_pcr *pcr = host->pcr;
963 int ro = 0;
964 u32 val;
965
966 if (host->eject)
967 return -ENOMEDIUM;
968
969 mutex_lock(&pcr->pcr_mutex);
970
971 rtsx_pci_start_run(pcr);
972
973 /* Check SD mechanical write-protect switch */
974 val = rtsx_pci_readl(pcr, RTSX_BIPR);
975 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
976 if (val & SD_WRITE_PROTECT)
977 ro = 1;
978
979 mutex_unlock(&pcr->pcr_mutex);
980
981 return ro;
982}
983
984static int sdmmc_get_cd(struct mmc_host *mmc)
985{
986 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
987 struct rtsx_pcr *pcr = host->pcr;
988 int cd = 0;
989 u32 val;
990
991 if (host->eject)
992 return -ENOMEDIUM;
993
994 mutex_lock(&pcr->pcr_mutex);
995
996 rtsx_pci_start_run(pcr);
997
998 /* Check SD card detect */
999 val = rtsx_pci_card_exist(pcr);
1000 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1001 if (val & SD_EXIST)
1002 cd = 1;
1003
1004 mutex_unlock(&pcr->pcr_mutex);
1005
1006 return cd;
1007}
1008
1009static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1010{
1011 struct rtsx_pcr *pcr = host->pcr;
1012 int err;
1013 u8 stat;
1014
1015 /* Reference to Signal Voltage Switch Sequence in SD spec.
1016 * Wait for a period of time so that the card can drive SD_CMD and
1017 * SD_DAT[3:0] to low after sending back CMD11 response.
1018 */
1019 mdelay(1);
1020
1021 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1022 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1023 * abort the voltage switch sequence;
1024 */
1025 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1026 if (err < 0)
1027 return err;
1028
1029 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1030 SD_DAT1_STATUS | SD_DAT0_STATUS))
1031 return -EINVAL;
1032
1033 /* Stop toggle SD clock */
1034 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1035 0xFF, SD_CLK_FORCE_STOP);
1036 if (err < 0)
1037 return err;
1038
1039 return 0;
1040}
1041
1042static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1043{
1044 struct rtsx_pcr *pcr = host->pcr;
1045 int err;
1046 u8 stat, mask, val;
1047
1048 /* Wait 1.8V output of voltage regulator in card stable */
1049 msleep(50);
1050
1051 /* Toggle SD clock again */
1052 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1053 if (err < 0)
1054 return err;
1055
1056 /* Wait for a period of time so that the card can drive
1057 * SD_DAT[3:0] to high at 1.8V
1058 */
1059 msleep(20);
1060
1061 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1062 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1063 if (err < 0)
1064 return err;
1065
1066 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1067 SD_DAT1_STATUS | SD_DAT0_STATUS;
1068 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1069 SD_DAT1_STATUS | SD_DAT0_STATUS;
1070 if ((stat & mask) != val) {
1071 dev_dbg(sdmmc_dev(host),
1072 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1073 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1074 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1075 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1076 return -EINVAL;
1077 }
1078
1079 return 0;
1080}
1081
ff984e57
WW		 1082static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1083{
1084 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1085 struct rtsx_pcr *pcr = host->pcr;
1086 int err = 0;
1087 u8 voltage;
1088
1089 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1090 __func__, ios->signal_voltage);
1091
1092 if (host->eject)
1093 return -ENOMEDIUM;
1094
c3481955
WW		 1095 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1096 if (err)
1097 return err;
1098
ff984e57
WW		 1099 mutex_lock(&pcr->pcr_mutex);
1100
1101 rtsx_pci_start_run(pcr);
1102
1103 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
ef85e736 1104 voltage = OUTPUT_3V3;
ff984e57 1105 else
ef85e736 1106 voltage = OUTPUT_1V8;
ff984e57 1107
ef85e736 1108 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1109 err = sd_wait_voltage_stable_1(host);
1110 if (err < 0)
1111 goto out;
1112 }
1113
ef85e736 1114 err = rtsx_pci_switch_output_voltage(pcr, voltage);
ff984e57
WW		 1115 if (err < 0)
1116 goto out;
1117
ef85e736 1118 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1119 err = sd_wait_voltage_stable_2(host);
1120 if (err < 0)
1121 goto out;
1122 }
1123
1124 /* Stop toggle SD clock in idle */
1125 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1126 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1127
1128out:
1129 mutex_unlock(&pcr->pcr_mutex);
1130
1131 return err;
1132}
1133
1134static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1135{
1136 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1137 struct rtsx_pcr *pcr = host->pcr;
1138 int err = 0;
1139
1140 if (host->eject)
1141 return -ENOMEDIUM;
1142
c3481955
WW		 1143 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1144 if (err)
1145 return err;
1146
ff984e57
WW		 1147 mutex_lock(&pcr->pcr_mutex);
1148
1149 rtsx_pci_start_run(pcr);
1150
1151 if (!host->ddr_mode)
1152 err = sd_tuning_rx(host, MMC_SEND_TUNING_BLOCK);
1153
1154 mutex_unlock(&pcr->pcr_mutex);
1155
1156 return err;
1157}
1158
1159static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1160 .request = sdmmc_request,
1161 .set_ios = sdmmc_set_ios,
1162 .get_ro = sdmmc_get_ro,
1163 .get_cd = sdmmc_get_cd,
1164 .start_signal_voltage_switch = sdmmc_switch_voltage,
1165 .execute_tuning = sdmmc_execute_tuning,
1166};
1167
1168#ifdef CONFIG_PM
1169static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1170 pm_message_t state)
1171{
1172 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1173 struct mmc_host *mmc = host->mmc;
1174 int err;
1175
1176 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1177
1178 err = mmc_suspend_host(mmc);
1179 if (err)
1180 return err;
1181
1182 return 0;
1183}
1184
1185static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1186{
1187 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1188 struct mmc_host *mmc = host->mmc;
1189
1190 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1191
1192 return mmc_resume_host(mmc);
1193}
1194#else /* CONFIG_PM */
1195#define rtsx_pci_sdmmc_suspend NULL
1196#define rtsx_pci_sdmmc_resume NULL
1197#endif /* CONFIG_PM */
1198
1199static void init_extra_caps(struct realtek_pci_sdmmc *host)
1200{
1201 struct mmc_host *mmc = host->mmc;
1202 struct rtsx_pcr *pcr = host->pcr;
1203
1204 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1205
1206 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1207 mmc->caps |= MMC_CAP_UHS_SDR50;
1208 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1209 mmc->caps |= MMC_CAP_UHS_SDR104;
1210 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1211 mmc->caps |= MMC_CAP_UHS_DDR50;
1212 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1213 mmc->caps |= MMC_CAP_1_8V_DDR;
1214 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1215 mmc->caps |= MMC_CAP_8_BIT_DATA;
1216}
1217
1218static void realtek_init_host(struct realtek_pci_sdmmc *host)
1219{
1220 struct mmc_host *mmc = host->mmc;
1221
1222 mmc->f_min = 250000;
1223 mmc->f_max = 208000000;
1224 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1225 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1226 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1227 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1228 mmc->max_current_330 = 400;
1229 mmc->max_current_180 = 800;
1230 mmc->ops = &realtek_pci_sdmmc_ops;
1231
1232 init_extra_caps(host);
1233
1234 mmc->max_segs = 256;
1235 mmc->max_seg_size = 65536;
1236 mmc->max_blk_size = 512;
1237 mmc->max_blk_count = 65535;
1238 mmc->max_req_size = 524288;
1239}
1240
1241static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1242{
1243 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1244
1245 mmc_detect_change(host->mmc, 0);
1246}
1247
1248static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1249{
1250 struct mmc_host *mmc;
1251 struct realtek_pci_sdmmc *host;
1252 struct rtsx_pcr *pcr;
1253 struct pcr_handle *handle = pdev->dev.platform_data;
1254
1255 if (!handle)
1256 return -ENXIO;
1257
1258 pcr = handle->pcr;
1259 if (!pcr)
1260 return -ENXIO;
1261
1262 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1263
1264 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1265 if (!mmc)
1266 return -ENOMEM;
1267
1268 host = mmc_priv(mmc);
1269 host->pcr = pcr;
1270 host->mmc = mmc;
1271 host->pdev = pdev;
d88691be 1272 host->power_state = SDMMC_POWER_OFF;
ff984e57
WW		 1273 platform_set_drvdata(pdev, host);
1274 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1275 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1276
1277 mutex_init(&host->host_mutex);
1278
1279 realtek_init_host(host);
1280
1281 mmc_add_host(mmc);
1282
1283 return 0;
1284}
1285
1286static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1287{
1288 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1289 struct rtsx_pcr *pcr;
1290 struct mmc_host *mmc;
1291
1292 if (!host)
1293 return 0;
1294
1295 pcr = host->pcr;
1296 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1297 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1298 mmc = host->mmc;
1299 host->eject = true;
1300
1301 mutex_lock(&host->host_mutex);
1302 if (host->mrq) {
1303 dev_dbg(&(pdev->dev),
1304 "%s: Controller removed during transfer\n",
1305 mmc_hostname(mmc));
1306
1307 rtsx_pci_complete_unfinished_transfer(pcr);
1308
1309 host->mrq->cmd->error = -ENOMEDIUM;
1310 if (host->mrq->stop)
1311 host->mrq->stop->error = -ENOMEDIUM;
1312 mmc_request_done(mmc, host->mrq);
1313 }
1314 mutex_unlock(&host->host_mutex);
1315
1316 mmc_remove_host(mmc);
1317 mmc_free_host(mmc);
1318
ff984e57
WW		 1319 dev_dbg(&(pdev->dev),
1320 ": Realtek PCI-E SDMMC controller has been removed\n");
1321
1322 return 0;
1323}
1324
1325static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1326 {
1327 .name = DRV_NAME_RTSX_PCI_SDMMC,
1328 }, {
1329 /* sentinel */
1330 }
1331};
1332MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1333
1334static struct platform_driver rtsx_pci_sdmmc_driver = {
1335 .probe = rtsx_pci_sdmmc_drv_probe,
1336 .remove = rtsx_pci_sdmmc_drv_remove,
1337 .id_table = rtsx_pci_sdmmc_ids,
1338 .suspend = rtsx_pci_sdmmc_suspend,
1339 .resume = rtsx_pci_sdmmc_resume,
1340 .driver = {
1341 .owner = THIS_MODULE,
1342 .name = DRV_NAME_RTSX_PCI_SDMMC,
1343 },
1344};
1345module_platform_driver(rtsx_pci_sdmmc_driver);
1346
1347MODULE_LICENSE("GPL");
1348MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1349MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
Linux kernel - Deliverables
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