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be518018 TK |
1 | /* |
2 | * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver | |
3 | * | |
4 | * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de> | |
5 | * | |
08c55e22 | 6 | * Current driver maintained by Ben Dooks and Simtec Electronics |
7 | * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org> | |
8 | * | |
be518018 TK |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/mmc/host.h> | |
18 | #include <linux/platform_device.h> | |
f87e6d00 | 19 | #include <linux/cpufreq.h> |
9bdd203b BD |
20 | #include <linux/debugfs.h> |
21 | #include <linux/seq_file.h> | |
ec976d6e | 22 | #include <linux/gpio.h> |
be518018 TK |
23 | #include <linux/irq.h> |
24 | #include <linux/io.h> | |
25 | ||
36437412 | 26 | #include <plat/gpio-cfg.h> |
7ad14f83 | 27 | #include <mach/dma.h> |
b0161caa | 28 | #include <mach/gpio-samsung.h> |
be518018 | 29 | |
436d42c6 | 30 | #include <linux/platform_data/mmc-s3cmci.h> |
edb5a98e | 31 | |
be518018 TK |
32 | #include "s3cmci.h" |
33 | ||
34 | #define DRIVER_NAME "s3c-mci" | |
35 | ||
24fae0fe KK |
36 | #define S3C2410_SDICON (0x00) |
37 | #define S3C2410_SDIPRE (0x04) | |
38 | #define S3C2410_SDICMDARG (0x08) | |
39 | #define S3C2410_SDICMDCON (0x0C) | |
40 | #define S3C2410_SDICMDSTAT (0x10) | |
41 | #define S3C2410_SDIRSP0 (0x14) | |
42 | #define S3C2410_SDIRSP1 (0x18) | |
43 | #define S3C2410_SDIRSP2 (0x1C) | |
44 | #define S3C2410_SDIRSP3 (0x20) | |
45 | #define S3C2410_SDITIMER (0x24) | |
46 | #define S3C2410_SDIBSIZE (0x28) | |
47 | #define S3C2410_SDIDCON (0x2C) | |
48 | #define S3C2410_SDIDCNT (0x30) | |
49 | #define S3C2410_SDIDSTA (0x34) | |
50 | #define S3C2410_SDIFSTA (0x38) | |
51 | ||
52 | #define S3C2410_SDIDATA (0x3C) | |
53 | #define S3C2410_SDIIMSK (0x40) | |
54 | ||
55 | #define S3C2440_SDIDATA (0x40) | |
56 | #define S3C2440_SDIIMSK (0x3C) | |
57 | ||
58 | #define S3C2440_SDICON_SDRESET (1 << 8) | |
59 | #define S3C2410_SDICON_SDIOIRQ (1 << 3) | |
60 | #define S3C2410_SDICON_FIFORESET (1 << 1) | |
61 | #define S3C2410_SDICON_CLOCKTYPE (1 << 0) | |
62 | ||
63 | #define S3C2410_SDICMDCON_LONGRSP (1 << 10) | |
64 | #define S3C2410_SDICMDCON_WAITRSP (1 << 9) | |
65 | #define S3C2410_SDICMDCON_CMDSTART (1 << 8) | |
66 | #define S3C2410_SDICMDCON_SENDERHOST (1 << 6) | |
67 | #define S3C2410_SDICMDCON_INDEX (0x3f) | |
68 | ||
69 | #define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12) | |
70 | #define S3C2410_SDICMDSTAT_CMDSENT (1 << 11) | |
71 | #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10) | |
72 | #define S3C2410_SDICMDSTAT_RSPFIN (1 << 9) | |
73 | ||
74 | #define S3C2440_SDIDCON_DS_WORD (2 << 22) | |
75 | #define S3C2410_SDIDCON_TXAFTERRESP (1 << 20) | |
76 | #define S3C2410_SDIDCON_RXAFTERCMD (1 << 19) | |
77 | #define S3C2410_SDIDCON_BLOCKMODE (1 << 17) | |
78 | #define S3C2410_SDIDCON_WIDEBUS (1 << 16) | |
79 | #define S3C2410_SDIDCON_DMAEN (1 << 15) | |
80 | #define S3C2410_SDIDCON_STOP (1 << 14) | |
81 | #define S3C2440_SDIDCON_DATSTART (1 << 14) | |
82 | ||
83 | #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12) | |
84 | #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12) | |
85 | ||
86 | #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) | |
87 | ||
88 | #define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9) | |
89 | #define S3C2410_SDIDSTA_FIFOFAIL (1 << 8) | |
90 | #define S3C2410_SDIDSTA_CRCFAIL (1 << 7) | |
91 | #define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6) | |
92 | #define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5) | |
93 | #define S3C2410_SDIDSTA_XFERFINISH (1 << 4) | |
94 | #define S3C2410_SDIDSTA_TXDATAON (1 << 1) | |
95 | #define S3C2410_SDIDSTA_RXDATAON (1 << 0) | |
96 | ||
97 | #define S3C2440_SDIFSTA_FIFORESET (1 << 16) | |
98 | #define S3C2440_SDIFSTA_FIFOFAIL (3 << 14) | |
99 | #define S3C2410_SDIFSTA_TFDET (1 << 13) | |
100 | #define S3C2410_SDIFSTA_RFDET (1 << 12) | |
101 | #define S3C2410_SDIFSTA_COUNTMASK (0x7f) | |
102 | ||
103 | #define S3C2410_SDIIMSK_RESPONSECRC (1 << 17) | |
104 | #define S3C2410_SDIIMSK_CMDSENT (1 << 16) | |
105 | #define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15) | |
106 | #define S3C2410_SDIIMSK_RESPONSEND (1 << 14) | |
107 | #define S3C2410_SDIIMSK_SDIOIRQ (1 << 12) | |
108 | #define S3C2410_SDIIMSK_FIFOFAIL (1 << 11) | |
109 | #define S3C2410_SDIIMSK_CRCSTATUS (1 << 10) | |
110 | #define S3C2410_SDIIMSK_DATACRC (1 << 9) | |
111 | #define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8) | |
112 | #define S3C2410_SDIIMSK_DATAFINISH (1 << 7) | |
113 | #define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4) | |
114 | #define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2) | |
115 | #define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0) | |
116 | ||
be518018 TK |
117 | enum dbg_channels { |
118 | dbg_err = (1 << 0), | |
119 | dbg_debug = (1 << 1), | |
120 | dbg_info = (1 << 2), | |
121 | dbg_irq = (1 << 3), | |
122 | dbg_sg = (1 << 4), | |
123 | dbg_dma = (1 << 5), | |
124 | dbg_pio = (1 << 6), | |
125 | dbg_fail = (1 << 7), | |
126 | dbg_conf = (1 << 8), | |
127 | }; | |
128 | ||
9c2e7e40 | 129 | static const int dbgmap_err = dbg_fail; |
be518018 | 130 | static const int dbgmap_info = dbg_info | dbg_conf; |
9c2e7e40 | 131 | static const int dbgmap_debug = dbg_err | dbg_debug; |
be518018 TK |
132 | |
133 | #define dbg(host, channels, args...) \ | |
134 | do { \ | |
135 | if (dbgmap_err & channels) \ | |
136 | dev_err(&host->pdev->dev, args); \ | |
137 | else if (dbgmap_info & channels) \ | |
138 | dev_info(&host->pdev->dev, args); \ | |
139 | else if (dbgmap_debug & channels) \ | |
140 | dev_dbg(&host->pdev->dev, args); \ | |
141 | } while (0) | |
142 | ||
be518018 TK |
143 | static struct s3c2410_dma_client s3cmci_dma_client = { |
144 | .name = "s3c-mci", | |
145 | }; | |
146 | ||
147 | static void finalize_request(struct s3cmci_host *host); | |
148 | static void s3cmci_send_request(struct mmc_host *mmc); | |
149 | static void s3cmci_reset(struct s3cmci_host *host); | |
150 | ||
151 | #ifdef CONFIG_MMC_DEBUG | |
152 | ||
153 | static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) | |
154 | { | |
155 | u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize; | |
156 | u32 datcon, datcnt, datsta, fsta, imask; | |
157 | ||
158 | con = readl(host->base + S3C2410_SDICON); | |
159 | pre = readl(host->base + S3C2410_SDIPRE); | |
160 | cmdarg = readl(host->base + S3C2410_SDICMDARG); | |
161 | cmdcon = readl(host->base + S3C2410_SDICMDCON); | |
162 | cmdsta = readl(host->base + S3C2410_SDICMDSTAT); | |
163 | r0 = readl(host->base + S3C2410_SDIRSP0); | |
164 | r1 = readl(host->base + S3C2410_SDIRSP1); | |
165 | r2 = readl(host->base + S3C2410_SDIRSP2); | |
166 | r3 = readl(host->base + S3C2410_SDIRSP3); | |
167 | timer = readl(host->base + S3C2410_SDITIMER); | |
168 | bsize = readl(host->base + S3C2410_SDIBSIZE); | |
169 | datcon = readl(host->base + S3C2410_SDIDCON); | |
170 | datcnt = readl(host->base + S3C2410_SDIDCNT); | |
171 | datsta = readl(host->base + S3C2410_SDIDSTA); | |
172 | fsta = readl(host->base + S3C2410_SDIFSTA); | |
173 | imask = readl(host->base + host->sdiimsk); | |
174 | ||
175 | dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n", | |
176 | prefix, con, pre, timer); | |
177 | ||
178 | dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n", | |
179 | prefix, cmdcon, cmdarg, cmdsta); | |
180 | ||
181 | dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]" | |
182 | " DSTA:[%08x] DCNT:[%08x]\n", | |
183 | prefix, datcon, fsta, datsta, datcnt); | |
184 | ||
185 | dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]" | |
186 | " R2:[%08x] R3:[%08x]\n", | |
187 | prefix, r0, r1, r2, r3); | |
188 | } | |
189 | ||
190 | static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, | |
191 | int stop) | |
192 | { | |
193 | snprintf(host->dbgmsg_cmd, 300, | |
194 | "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u", | |
195 | host->ccnt, (stop ? " (STOP)" : ""), | |
196 | cmd->opcode, cmd->arg, cmd->flags, cmd->retries); | |
197 | ||
198 | if (cmd->data) { | |
199 | snprintf(host->dbgmsg_dat, 300, | |
200 | "#%u bsize:%u blocks:%u bytes:%u", | |
201 | host->dcnt, cmd->data->blksz, | |
202 | cmd->data->blocks, | |
203 | cmd->data->blocks * cmd->data->blksz); | |
204 | } else { | |
205 | host->dbgmsg_dat[0] = '\0'; | |
206 | } | |
207 | } | |
208 | ||
209 | static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd, | |
210 | int fail) | |
211 | { | |
212 | unsigned int dbglvl = fail ? dbg_fail : dbg_debug; | |
213 | ||
214 | if (!cmd) | |
215 | return; | |
216 | ||
217 | if (cmd->error == 0) { | |
218 | dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n", | |
219 | host->dbgmsg_cmd, cmd->resp[0]); | |
220 | } else { | |
221 | dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n", | |
222 | cmd->error, host->dbgmsg_cmd, host->status); | |
223 | } | |
224 | ||
225 | if (!cmd->data) | |
226 | return; | |
227 | ||
228 | if (cmd->data->error == 0) { | |
229 | dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat); | |
230 | } else { | |
231 | dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n", | |
232 | cmd->data->error, host->dbgmsg_dat, | |
233 | readl(host->base + S3C2410_SDIDCNT)); | |
234 | } | |
235 | } | |
236 | #else | |
237 | static void dbg_dumpcmd(struct s3cmci_host *host, | |
238 | struct mmc_command *cmd, int fail) { } | |
239 | ||
240 | static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, | |
241 | int stop) { } | |
242 | ||
243 | static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { } | |
244 | ||
245 | #endif /* CONFIG_MMC_DEBUG */ | |
246 | ||
26f14947 BD |
247 | /** |
248 | * s3cmci_host_usedma - return whether the host is using dma or pio | |
249 | * @host: The host state | |
250 | * | |
251 | * Return true if the host is using DMA to transfer data, else false | |
252 | * to use PIO mode. Will return static data depending on the driver | |
253 | * configuration. | |
254 | */ | |
255 | static inline bool s3cmci_host_usedma(struct s3cmci_host *host) | |
256 | { | |
257 | #ifdef CONFIG_MMC_S3C_PIO | |
258 | return false; | |
259 | #elif defined(CONFIG_MMC_S3C_DMA) | |
260 | return true; | |
261 | #else | |
262 | return host->dodma; | |
263 | #endif | |
264 | } | |
265 | ||
68c5ed59 BD |
266 | /** |
267 | * s3cmci_host_canpio - return true if host has pio code available | |
268 | * | |
269 | * Return true if the driver has been compiled with the PIO support code | |
270 | * available. | |
271 | */ | |
272 | static inline bool s3cmci_host_canpio(void) | |
273 | { | |
274 | #ifdef CONFIG_MMC_S3C_PIO | |
275 | return true; | |
276 | #else | |
277 | return false; | |
278 | #endif | |
279 | } | |
280 | ||
be518018 TK |
281 | static inline u32 enable_imask(struct s3cmci_host *host, u32 imask) |
282 | { | |
283 | u32 newmask; | |
284 | ||
285 | newmask = readl(host->base + host->sdiimsk); | |
286 | newmask |= imask; | |
287 | ||
288 | writel(newmask, host->base + host->sdiimsk); | |
289 | ||
290 | return newmask; | |
291 | } | |
292 | ||
293 | static inline u32 disable_imask(struct s3cmci_host *host, u32 imask) | |
294 | { | |
295 | u32 newmask; | |
296 | ||
297 | newmask = readl(host->base + host->sdiimsk); | |
298 | newmask &= ~imask; | |
299 | ||
300 | writel(newmask, host->base + host->sdiimsk); | |
301 | ||
302 | return newmask; | |
303 | } | |
304 | ||
305 | static inline void clear_imask(struct s3cmci_host *host) | |
306 | { | |
c2258893 BD |
307 | u32 mask = readl(host->base + host->sdiimsk); |
308 | ||
309 | /* preserve the SDIO IRQ mask state */ | |
310 | mask &= S3C2410_SDIIMSK_SDIOIRQ; | |
311 | writel(mask, host->base + host->sdiimsk); | |
312 | } | |
313 | ||
314 | /** | |
315 | * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled | |
316 | * @host: The host to check. | |
317 | * | |
318 | * Test to see if the SDIO interrupt is being signalled in case the | |
319 | * controller has failed to re-detect a card interrupt. Read GPE8 and | |
320 | * see if it is low and if so, signal a SDIO interrupt. | |
321 | * | |
322 | * This is currently called if a request is finished (we assume that the | |
323 | * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is | |
324 | * already being indicated. | |
325 | */ | |
326 | static void s3cmci_check_sdio_irq(struct s3cmci_host *host) | |
327 | { | |
328 | if (host->sdio_irqen) { | |
329 | if (gpio_get_value(S3C2410_GPE(8)) == 0) { | |
a3c76eb9 | 330 | pr_debug("%s: signalling irq\n", __func__); |
c2258893 BD |
331 | mmc_signal_sdio_irq(host->mmc); |
332 | } | |
333 | } | |
be518018 TK |
334 | } |
335 | ||
336 | static inline int get_data_buffer(struct s3cmci_host *host, | |
088a78af | 337 | u32 *bytes, u32 **pointer) |
be518018 TK |
338 | { |
339 | struct scatterlist *sg; | |
340 | ||
341 | if (host->pio_active == XFER_NONE) | |
342 | return -EINVAL; | |
343 | ||
344 | if ((!host->mrq) || (!host->mrq->data)) | |
345 | return -EINVAL; | |
346 | ||
347 | if (host->pio_sgptr >= host->mrq->data->sg_len) { | |
348 | dbg(host, dbg_debug, "no more buffers (%i/%i)\n", | |
349 | host->pio_sgptr, host->mrq->data->sg_len); | |
350 | return -EBUSY; | |
351 | } | |
352 | sg = &host->mrq->data->sg[host->pio_sgptr]; | |
353 | ||
088a78af | 354 | *bytes = sg->length; |
be518018 TK |
355 | *pointer = sg_virt(sg); |
356 | ||
357 | host->pio_sgptr++; | |
358 | ||
359 | dbg(host, dbg_sg, "new buffer (%i/%i)\n", | |
360 | host->pio_sgptr, host->mrq->data->sg_len); | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static inline u32 fifo_count(struct s3cmci_host *host) | |
366 | { | |
367 | u32 fifostat = readl(host->base + S3C2410_SDIFSTA); | |
368 | ||
369 | fifostat &= S3C2410_SDIFSTA_COUNTMASK; | |
088a78af | 370 | return fifostat; |
be518018 TK |
371 | } |
372 | ||
373 | static inline u32 fifo_free(struct s3cmci_host *host) | |
374 | { | |
375 | u32 fifostat = readl(host->base + S3C2410_SDIFSTA); | |
376 | ||
377 | fifostat &= S3C2410_SDIFSTA_COUNTMASK; | |
088a78af | 378 | return 63 - fifostat; |
be518018 TK |
379 | } |
380 | ||
c2258893 BD |
381 | /** |
382 | * s3cmci_enable_irq - enable IRQ, after having disabled it. | |
383 | * @host: The device state. | |
384 | * @more: True if more IRQs are expected from transfer. | |
385 | * | |
386 | * Enable the main IRQ if needed after it has been disabled. | |
387 | * | |
388 | * The IRQ can be one of the following states: | |
389 | * - disabled during IDLE | |
390 | * - disabled whilst processing data | |
391 | * - enabled during transfer | |
392 | * - enabled whilst awaiting SDIO interrupt detection | |
393 | */ | |
394 | static void s3cmci_enable_irq(struct s3cmci_host *host, bool more) | |
395 | { | |
396 | unsigned long flags; | |
397 | bool enable = false; | |
398 | ||
399 | local_irq_save(flags); | |
400 | ||
401 | host->irq_enabled = more; | |
402 | host->irq_disabled = false; | |
403 | ||
404 | enable = more | host->sdio_irqen; | |
405 | ||
406 | if (host->irq_state != enable) { | |
407 | host->irq_state = enable; | |
408 | ||
409 | if (enable) | |
410 | enable_irq(host->irq); | |
411 | else | |
412 | disable_irq(host->irq); | |
413 | } | |
414 | ||
415 | local_irq_restore(flags); | |
416 | } | |
417 | ||
418 | /** | |
419 | * | |
420 | */ | |
421 | static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer) | |
422 | { | |
423 | unsigned long flags; | |
424 | ||
425 | local_irq_save(flags); | |
426 | ||
a3c76eb9 | 427 | /* pr_debug("%s: transfer %d\n", __func__, transfer); */ |
c2258893 BD |
428 | |
429 | host->irq_disabled = transfer; | |
430 | ||
431 | if (transfer && host->irq_state) { | |
432 | host->irq_state = false; | |
433 | disable_irq(host->irq); | |
434 | } | |
435 | ||
436 | local_irq_restore(flags); | |
437 | } | |
438 | ||
be518018 TK |
439 | static void do_pio_read(struct s3cmci_host *host) |
440 | { | |
441 | int res; | |
442 | u32 fifo; | |
18280fff | 443 | u32 *ptr; |
088a78af | 444 | u32 fifo_words; |
be518018 TK |
445 | void __iomem *from_ptr; |
446 | ||
447 | /* write real prescaler to host, it might be set slow to fix */ | |
448 | writel(host->prescaler, host->base + S3C2410_SDIPRE); | |
449 | ||
450 | from_ptr = host->base + host->sdidata; | |
451 | ||
452 | while ((fifo = fifo_count(host))) { | |
088a78af CW |
453 | if (!host->pio_bytes) { |
454 | res = get_data_buffer(host, &host->pio_bytes, | |
be518018 TK |
455 | &host->pio_ptr); |
456 | if (res) { | |
457 | host->pio_active = XFER_NONE; | |
458 | host->complete_what = COMPLETION_FINALIZE; | |
459 | ||
460 | dbg(host, dbg_pio, "pio_read(): " | |
461 | "complete (no more data).\n"); | |
462 | return; | |
463 | } | |
464 | ||
465 | dbg(host, dbg_pio, | |
466 | "pio_read(): new target: [%i]@[%p]\n", | |
088a78af | 467 | host->pio_bytes, host->pio_ptr); |
be518018 TK |
468 | } |
469 | ||
470 | dbg(host, dbg_pio, | |
471 | "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n", | |
088a78af | 472 | fifo, host->pio_bytes, |
be518018 TK |
473 | readl(host->base + S3C2410_SDIDCNT)); |
474 | ||
088a78af CW |
475 | /* If we have reached the end of the block, we can |
476 | * read a word and get 1 to 3 bytes. If we in the | |
477 | * middle of the block, we have to read full words, | |
478 | * otherwise we will write garbage, so round down to | |
479 | * an even multiple of 4. */ | |
480 | if (fifo >= host->pio_bytes) | |
481 | fifo = host->pio_bytes; | |
482 | else | |
483 | fifo -= fifo & 3; | |
484 | ||
485 | host->pio_bytes -= fifo; | |
be518018 TK |
486 | host->pio_count += fifo; |
487 | ||
088a78af | 488 | fifo_words = fifo >> 2; |
18280fff | 489 | ptr = host->pio_ptr; |
088a78af | 490 | while (fifo_words--) |
18280fff | 491 | *ptr++ = readl(from_ptr); |
492 | host->pio_ptr = ptr; | |
088a78af CW |
493 | |
494 | if (fifo & 3) { | |
495 | u32 n = fifo & 3; | |
496 | u32 data = readl(from_ptr); | |
497 | u8 *p = (u8 *)host->pio_ptr; | |
498 | ||
499 | while (n--) { | |
500 | *p++ = data; | |
501 | data >>= 8; | |
502 | } | |
503 | } | |
be518018 TK |
504 | } |
505 | ||
088a78af CW |
506 | if (!host->pio_bytes) { |
507 | res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr); | |
be518018 TK |
508 | if (res) { |
509 | dbg(host, dbg_pio, | |
510 | "pio_read(): complete (no more buffers).\n"); | |
511 | host->pio_active = XFER_NONE; | |
512 | host->complete_what = COMPLETION_FINALIZE; | |
513 | ||
514 | return; | |
515 | } | |
516 | } | |
517 | ||
518 | enable_imask(host, | |
519 | S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST); | |
520 | } | |
521 | ||
522 | static void do_pio_write(struct s3cmci_host *host) | |
523 | { | |
524 | void __iomem *to_ptr; | |
525 | int res; | |
526 | u32 fifo; | |
18280fff | 527 | u32 *ptr; |
be518018 TK |
528 | |
529 | to_ptr = host->base + host->sdidata; | |
530 | ||
99424488 | 531 | while ((fifo = fifo_free(host)) > 3) { |
088a78af CW |
532 | if (!host->pio_bytes) { |
533 | res = get_data_buffer(host, &host->pio_bytes, | |
be518018 TK |
534 | &host->pio_ptr); |
535 | if (res) { | |
536 | dbg(host, dbg_pio, | |
537 | "pio_write(): complete (no more data).\n"); | |
538 | host->pio_active = XFER_NONE; | |
539 | ||
540 | return; | |
541 | } | |
542 | ||
543 | dbg(host, dbg_pio, | |
544 | "pio_write(): new source: [%i]@[%p]\n", | |
088a78af | 545 | host->pio_bytes, host->pio_ptr); |
be518018 TK |
546 | |
547 | } | |
548 | ||
088a78af CW |
549 | /* If we have reached the end of the block, we have to |
550 | * write exactly the remaining number of bytes. If we | |
551 | * in the middle of the block, we have to write full | |
552 | * words, so round down to an even multiple of 4. */ | |
553 | if (fifo >= host->pio_bytes) | |
554 | fifo = host->pio_bytes; | |
555 | else | |
556 | fifo -= fifo & 3; | |
be518018 | 557 | |
088a78af | 558 | host->pio_bytes -= fifo; |
be518018 TK |
559 | host->pio_count += fifo; |
560 | ||
088a78af | 561 | fifo = (fifo + 3) >> 2; |
18280fff | 562 | ptr = host->pio_ptr; |
be518018 | 563 | while (fifo--) |
18280fff | 564 | writel(*ptr++, to_ptr); |
565 | host->pio_ptr = ptr; | |
be518018 TK |
566 | } |
567 | ||
568 | enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); | |
569 | } | |
570 | ||
571 | static void pio_tasklet(unsigned long data) | |
572 | { | |
573 | struct s3cmci_host *host = (struct s3cmci_host *) data; | |
574 | ||
c2258893 | 575 | s3cmci_disable_irq(host, true); |
d643b5f7 | 576 | |
be518018 TK |
577 | if (host->pio_active == XFER_WRITE) |
578 | do_pio_write(host); | |
579 | ||
580 | if (host->pio_active == XFER_READ) | |
581 | do_pio_read(host); | |
582 | ||
583 | if (host->complete_what == COMPLETION_FINALIZE) { | |
584 | clear_imask(host); | |
585 | if (host->pio_active != XFER_NONE) { | |
586 | dbg(host, dbg_err, "unfinished %s " | |
088a78af | 587 | "- pio_count:[%u] pio_bytes:[%u]\n", |
be518018 | 588 | (host->pio_active == XFER_READ) ? "read" : "write", |
088a78af | 589 | host->pio_count, host->pio_bytes); |
be518018 | 590 | |
7c14450e BD |
591 | if (host->mrq->data) |
592 | host->mrq->data->error = -EINVAL; | |
be518018 TK |
593 | } |
594 | ||
c2258893 | 595 | s3cmci_enable_irq(host, false); |
be518018 | 596 | finalize_request(host); |
d643b5f7 | 597 | } else |
c2258893 | 598 | s3cmci_enable_irq(host, true); |
be518018 TK |
599 | } |
600 | ||
601 | /* | |
602 | * ISR for SDI Interface IRQ | |
603 | * Communication between driver and ISR works as follows: | |
604 | * host->mrq points to current request | |
605 | * host->complete_what Indicates when the request is considered done | |
606 | * COMPLETION_CMDSENT when the command was sent | |
607 | * COMPLETION_RSPFIN when a response was received | |
608 | * COMPLETION_XFERFINISH when the data transfer is finished | |
609 | * COMPLETION_XFERFINISH_RSPFIN both of the above. | |
610 | * host->complete_request is the completion-object the driver waits for | |
611 | * | |
612 | * 1) Driver sets up host->mrq and host->complete_what | |
613 | * 2) Driver prepares the transfer | |
614 | * 3) Driver enables interrupts | |
615 | * 4) Driver starts transfer | |
616 | * 5) Driver waits for host->complete_rquest | |
617 | * 6) ISR checks for request status (errors and success) | |
618 | * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error | |
619 | * 7) ISR completes host->complete_request | |
620 | * 8) ISR disables interrupts | |
621 | * 9) Driver wakes up and takes care of the request | |
622 | * | |
623 | * Note: "->error"-fields are expected to be set to 0 before the request | |
624 | * was issued by mmc.c - therefore they are only set, when an error | |
625 | * contition comes up | |
626 | */ | |
627 | ||
628 | static irqreturn_t s3cmci_irq(int irq, void *dev_id) | |
629 | { | |
630 | struct s3cmci_host *host = dev_id; | |
631 | struct mmc_command *cmd; | |
632 | u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk; | |
c2258893 | 633 | u32 mci_cclear = 0, mci_dclear; |
be518018 TK |
634 | unsigned long iflags; |
635 | ||
c2258893 BD |
636 | mci_dsta = readl(host->base + S3C2410_SDIDSTA); |
637 | mci_imsk = readl(host->base + host->sdiimsk); | |
638 | ||
639 | if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) { | |
640 | if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) { | |
641 | mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT; | |
642 | writel(mci_dclear, host->base + S3C2410_SDIDSTA); | |
643 | ||
644 | mmc_signal_sdio_irq(host->mmc); | |
645 | return IRQ_HANDLED; | |
646 | } | |
647 | } | |
648 | ||
be518018 TK |
649 | spin_lock_irqsave(&host->complete_lock, iflags); |
650 | ||
651 | mci_csta = readl(host->base + S3C2410_SDICMDSTAT); | |
be518018 TK |
652 | mci_dcnt = readl(host->base + S3C2410_SDIDCNT); |
653 | mci_fsta = readl(host->base + S3C2410_SDIFSTA); | |
be518018 TK |
654 | mci_dclear = 0; |
655 | ||
656 | if ((host->complete_what == COMPLETION_NONE) || | |
657 | (host->complete_what == COMPLETION_FINALIZE)) { | |
658 | host->status = "nothing to complete"; | |
659 | clear_imask(host); | |
660 | goto irq_out; | |
661 | } | |
662 | ||
663 | if (!host->mrq) { | |
664 | host->status = "no active mrq"; | |
665 | clear_imask(host); | |
666 | goto irq_out; | |
667 | } | |
668 | ||
669 | cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd; | |
670 | ||
671 | if (!cmd) { | |
672 | host->status = "no active cmd"; | |
673 | clear_imask(host); | |
674 | goto irq_out; | |
675 | } | |
676 | ||
26f14947 | 677 | if (!s3cmci_host_usedma(host)) { |
be518018 TK |
678 | if ((host->pio_active == XFER_WRITE) && |
679 | (mci_fsta & S3C2410_SDIFSTA_TFDET)) { | |
680 | ||
681 | disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); | |
682 | tasklet_schedule(&host->pio_tasklet); | |
683 | host->status = "pio tx"; | |
684 | } | |
685 | ||
686 | if ((host->pio_active == XFER_READ) && | |
687 | (mci_fsta & S3C2410_SDIFSTA_RFDET)) { | |
688 | ||
689 | disable_imask(host, | |
690 | S3C2410_SDIIMSK_RXFIFOHALF | | |
691 | S3C2410_SDIIMSK_RXFIFOLAST); | |
692 | ||
693 | tasklet_schedule(&host->pio_tasklet); | |
694 | host->status = "pio rx"; | |
695 | } | |
696 | } | |
697 | ||
698 | if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { | |
ff8c804f | 699 | dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n"); |
be518018 TK |
700 | cmd->error = -ETIMEDOUT; |
701 | host->status = "error: command timeout"; | |
702 | goto fail_transfer; | |
703 | } | |
704 | ||
705 | if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) { | |
706 | if (host->complete_what == COMPLETION_CMDSENT) { | |
707 | host->status = "ok: command sent"; | |
708 | goto close_transfer; | |
709 | } | |
710 | ||
711 | mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT; | |
712 | } | |
713 | ||
714 | if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) { | |
715 | if (cmd->flags & MMC_RSP_CRC) { | |
679f0f8a HW |
716 | if (host->mrq->cmd->flags & MMC_RSP_136) { |
717 | dbg(host, dbg_irq, | |
718 | "fixup: ignore CRC fail with long rsp\n"); | |
719 | } else { | |
720 | /* note, we used to fail the transfer | |
721 | * here, but it seems that this is just | |
722 | * the hardware getting it wrong. | |
723 | * | |
724 | * cmd->error = -EILSEQ; | |
725 | * host->status = "error: bad command crc"; | |
726 | * goto fail_transfer; | |
727 | */ | |
728 | } | |
be518018 TK |
729 | } |
730 | ||
731 | mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL; | |
732 | } | |
733 | ||
734 | if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) { | |
735 | if (host->complete_what == COMPLETION_RSPFIN) { | |
736 | host->status = "ok: command response received"; | |
737 | goto close_transfer; | |
738 | } | |
739 | ||
740 | if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) | |
741 | host->complete_what = COMPLETION_XFERFINISH; | |
742 | ||
743 | mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN; | |
744 | } | |
745 | ||
746 | /* errors handled after this point are only relevant | |
747 | when a data transfer is in progress */ | |
748 | ||
749 | if (!cmd->data) | |
750 | goto clear_status_bits; | |
751 | ||
752 | /* Check for FIFO failure */ | |
753 | if (host->is2440) { | |
754 | if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) { | |
ff8c804f | 755 | dbg(host, dbg_err, "FIFO failure\n"); |
be518018 TK |
756 | host->mrq->data->error = -EILSEQ; |
757 | host->status = "error: 2440 fifo failure"; | |
758 | goto fail_transfer; | |
759 | } | |
760 | } else { | |
761 | if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) { | |
ff8c804f | 762 | dbg(host, dbg_err, "FIFO failure\n"); |
be518018 TK |
763 | cmd->data->error = -EILSEQ; |
764 | host->status = "error: fifo failure"; | |
765 | goto fail_transfer; | |
766 | } | |
767 | } | |
768 | ||
769 | if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) { | |
ff8c804f | 770 | dbg(host, dbg_err, "bad data crc (outgoing)\n"); |
be518018 TK |
771 | cmd->data->error = -EILSEQ; |
772 | host->status = "error: bad data crc (outgoing)"; | |
773 | goto fail_transfer; | |
774 | } | |
775 | ||
776 | if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) { | |
ff8c804f | 777 | dbg(host, dbg_err, "bad data crc (incoming)\n"); |
be518018 TK |
778 | cmd->data->error = -EILSEQ; |
779 | host->status = "error: bad data crc (incoming)"; | |
780 | goto fail_transfer; | |
781 | } | |
782 | ||
783 | if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) { | |
ff8c804f | 784 | dbg(host, dbg_err, "data timeout\n"); |
be518018 TK |
785 | cmd->data->error = -ETIMEDOUT; |
786 | host->status = "error: data timeout"; | |
787 | goto fail_transfer; | |
788 | } | |
789 | ||
790 | if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) { | |
791 | if (host->complete_what == COMPLETION_XFERFINISH) { | |
792 | host->status = "ok: data transfer completed"; | |
793 | goto close_transfer; | |
794 | } | |
795 | ||
796 | if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) | |
797 | host->complete_what = COMPLETION_RSPFIN; | |
798 | ||
799 | mci_dclear |= S3C2410_SDIDSTA_XFERFINISH; | |
800 | } | |
801 | ||
802 | clear_status_bits: | |
803 | writel(mci_cclear, host->base + S3C2410_SDICMDSTAT); | |
804 | writel(mci_dclear, host->base + S3C2410_SDIDSTA); | |
805 | ||
806 | goto irq_out; | |
807 | ||
808 | fail_transfer: | |
809 | host->pio_active = XFER_NONE; | |
810 | ||
811 | close_transfer: | |
812 | host->complete_what = COMPLETION_FINALIZE; | |
813 | ||
814 | clear_imask(host); | |
815 | tasklet_schedule(&host->pio_tasklet); | |
816 | ||
817 | goto irq_out; | |
818 | ||
819 | irq_out: | |
820 | dbg(host, dbg_irq, | |
821 | "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n", | |
822 | mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status); | |
823 | ||
824 | spin_unlock_irqrestore(&host->complete_lock, iflags); | |
825 | return IRQ_HANDLED; | |
826 | ||
827 | } | |
828 | ||
829 | /* | |
830 | * ISR for the CardDetect Pin | |
831 | */ | |
832 | ||
833 | static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id) | |
834 | { | |
835 | struct s3cmci_host *host = (struct s3cmci_host *)dev_id; | |
836 | ||
837 | dbg(host, dbg_irq, "card detect\n"); | |
838 | ||
2de5f79d | 839 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); |
be518018 TK |
840 | |
841 | return IRQ_HANDLED; | |
842 | } | |
843 | ||
5d304400 BD |
844 | static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch, |
845 | void *buf_id, int size, | |
846 | enum s3c2410_dma_buffresult result) | |
be518018 TK |
847 | { |
848 | struct s3cmci_host *host = buf_id; | |
849 | unsigned long iflags; | |
850 | u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt; | |
851 | ||
852 | mci_csta = readl(host->base + S3C2410_SDICMDSTAT); | |
853 | mci_dsta = readl(host->base + S3C2410_SDIDSTA); | |
854 | mci_fsta = readl(host->base + S3C2410_SDIFSTA); | |
855 | mci_dcnt = readl(host->base + S3C2410_SDIDCNT); | |
856 | ||
857 | BUG_ON(!host->mrq); | |
858 | BUG_ON(!host->mrq->data); | |
859 | BUG_ON(!host->dmatogo); | |
860 | ||
861 | spin_lock_irqsave(&host->complete_lock, iflags); | |
862 | ||
863 | if (result != S3C2410_RES_OK) { | |
864 | dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x " | |
865 | "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n", | |
866 | mci_csta, mci_dsta, mci_fsta, | |
867 | mci_dcnt, result, host->dmatogo); | |
868 | ||
869 | goto fail_request; | |
870 | } | |
871 | ||
872 | host->dmatogo--; | |
873 | if (host->dmatogo) { | |
874 | dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] " | |
875 | "DCNT:[%08x] toGo:%u\n", | |
876 | size, mci_dsta, mci_dcnt, host->dmatogo); | |
877 | ||
878 | goto out; | |
879 | } | |
880 | ||
881 | dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n", | |
882 | size, mci_dsta, mci_dcnt); | |
883 | ||
68c5ed59 | 884 | host->dma_complete = 1; |
be518018 TK |
885 | host->complete_what = COMPLETION_FINALIZE; |
886 | ||
887 | out: | |
888 | tasklet_schedule(&host->pio_tasklet); | |
889 | spin_unlock_irqrestore(&host->complete_lock, iflags); | |
890 | return; | |
891 | ||
be518018 TK |
892 | fail_request: |
893 | host->mrq->data->error = -EINVAL; | |
894 | host->complete_what = COMPLETION_FINALIZE; | |
e6130aef | 895 | clear_imask(host); |
be518018 | 896 | |
e6130aef | 897 | goto out; |
be518018 TK |
898 | } |
899 | ||
900 | static void finalize_request(struct s3cmci_host *host) | |
901 | { | |
902 | struct mmc_request *mrq = host->mrq; | |
3423d80a | 903 | struct mmc_command *cmd; |
be518018 TK |
904 | int debug_as_failure = 0; |
905 | ||
906 | if (host->complete_what != COMPLETION_FINALIZE) | |
907 | return; | |
908 | ||
909 | if (!mrq) | |
910 | return; | |
3423d80a | 911 | cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; |
be518018 TK |
912 | |
913 | if (cmd->data && (cmd->error == 0) && | |
914 | (cmd->data->error == 0)) { | |
26f14947 | 915 | if (s3cmci_host_usedma(host) && (!host->dma_complete)) { |
68c5ed59 BD |
916 | dbg(host, dbg_dma, "DMA Missing (%d)!\n", |
917 | host->dma_complete); | |
be518018 TK |
918 | return; |
919 | } | |
920 | } | |
921 | ||
922 | /* Read response from controller. */ | |
923 | cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0); | |
924 | cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1); | |
925 | cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2); | |
926 | cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3); | |
927 | ||
928 | writel(host->prescaler, host->base + S3C2410_SDIPRE); | |
929 | ||
930 | if (cmd->error) | |
931 | debug_as_failure = 1; | |
932 | ||
933 | if (cmd->data && cmd->data->error) | |
934 | debug_as_failure = 1; | |
935 | ||
936 | dbg_dumpcmd(host, cmd, debug_as_failure); | |
937 | ||
938 | /* Cleanup controller */ | |
939 | writel(0, host->base + S3C2410_SDICMDARG); | |
bdbc9c3a | 940 | writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); |
be518018 | 941 | writel(0, host->base + S3C2410_SDICMDCON); |
e6130aef | 942 | clear_imask(host); |
be518018 TK |
943 | |
944 | if (cmd->data && cmd->error) | |
945 | cmd->data->error = cmd->error; | |
946 | ||
947 | if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) { | |
948 | host->cmd_is_stop = 1; | |
949 | s3cmci_send_request(host->mmc); | |
950 | return; | |
951 | } | |
952 | ||
953 | /* If we have no data transfer we are finished here */ | |
954 | if (!mrq->data) | |
955 | goto request_done; | |
956 | ||
25985edc | 957 | /* Calculate the amout of bytes transfer if there was no error */ |
be518018 TK |
958 | if (mrq->data->error == 0) { |
959 | mrq->data->bytes_xfered = | |
960 | (mrq->data->blocks * mrq->data->blksz); | |
961 | } else { | |
962 | mrq->data->bytes_xfered = 0; | |
963 | } | |
964 | ||
25985edc | 965 | /* If we had an error while transferring data we flush the |
be518018 TK |
966 | * DMA channel and the fifo to clear out any garbage. */ |
967 | if (mrq->data->error != 0) { | |
26f14947 | 968 | if (s3cmci_host_usedma(host)) |
be518018 TK |
969 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); |
970 | ||
971 | if (host->is2440) { | |
972 | /* Clear failure register and reset fifo. */ | |
973 | writel(S3C2440_SDIFSTA_FIFORESET | | |
974 | S3C2440_SDIFSTA_FIFOFAIL, | |
975 | host->base + S3C2410_SDIFSTA); | |
976 | } else { | |
977 | u32 mci_con; | |
978 | ||
979 | /* reset fifo */ | |
980 | mci_con = readl(host->base + S3C2410_SDICON); | |
981 | mci_con |= S3C2410_SDICON_FIFORESET; | |
982 | ||
983 | writel(mci_con, host->base + S3C2410_SDICON); | |
984 | } | |
985 | } | |
986 | ||
987 | request_done: | |
988 | host->complete_what = COMPLETION_NONE; | |
989 | host->mrq = NULL; | |
c2258893 BD |
990 | |
991 | s3cmci_check_sdio_irq(host); | |
be518018 TK |
992 | mmc_request_done(host->mmc, mrq); |
993 | } | |
994 | ||
5d304400 | 995 | static void s3cmci_dma_setup(struct s3cmci_host *host, |
51ddf31d | 996 | enum dma_data_direction source) |
be518018 | 997 | { |
51ddf31d | 998 | static enum dma_data_direction last_source = -1; |
be518018 TK |
999 | static int setup_ok; |
1000 | ||
1001 | if (last_source == source) | |
1002 | return; | |
1003 | ||
1004 | last_source = source; | |
1005 | ||
8970ef47 | 1006 | s3c2410_dma_devconfig(host->dma, source, |
be518018 TK |
1007 | host->mem->start + host->sdidata); |
1008 | ||
1009 | if (!setup_ok) { | |
fe9db6cb | 1010 | s3c2410_dma_config(host->dma, 4); |
be518018 TK |
1011 | s3c2410_dma_set_buffdone_fn(host->dma, |
1012 | s3cmci_dma_done_callback); | |
1013 | s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); | |
1014 | setup_ok = 1; | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | static void s3cmci_send_command(struct s3cmci_host *host, | |
1019 | struct mmc_command *cmd) | |
1020 | { | |
1021 | u32 ccon, imsk; | |
1022 | ||
1023 | imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT | | |
1024 | S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT | | |
1025 | S3C2410_SDIIMSK_RESPONSECRC; | |
1026 | ||
1027 | enable_imask(host, imsk); | |
1028 | ||
1029 | if (cmd->data) | |
1030 | host->complete_what = COMPLETION_XFERFINISH_RSPFIN; | |
1031 | else if (cmd->flags & MMC_RSP_PRESENT) | |
1032 | host->complete_what = COMPLETION_RSPFIN; | |
1033 | else | |
1034 | host->complete_what = COMPLETION_CMDSENT; | |
1035 | ||
1036 | writel(cmd->arg, host->base + S3C2410_SDICMDARG); | |
1037 | ||
1038 | ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX; | |
1039 | ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART; | |
1040 | ||
1041 | if (cmd->flags & MMC_RSP_PRESENT) | |
1042 | ccon |= S3C2410_SDICMDCON_WAITRSP; | |
1043 | ||
1044 | if (cmd->flags & MMC_RSP_136) | |
1045 | ccon |= S3C2410_SDICMDCON_LONGRSP; | |
1046 | ||
1047 | writel(ccon, host->base + S3C2410_SDICMDCON); | |
1048 | } | |
1049 | ||
1050 | static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data) | |
1051 | { | |
1052 | u32 dcon, imsk, stoptries = 3; | |
1053 | ||
1054 | /* write DCON register */ | |
1055 | ||
1056 | if (!data) { | |
1057 | writel(0, host->base + S3C2410_SDIDCON); | |
1058 | return 0; | |
1059 | } | |
1060 | ||
7e9c7b64 BD |
1061 | if ((data->blksz & 3) != 0) { |
1062 | /* We cannot deal with unaligned blocks with more than | |
25985edc | 1063 | * one block being transferred. */ |
7e9c7b64 | 1064 | |
088a78af CW |
1065 | if (data->blocks > 1) { |
1066 | pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz); | |
7e9c7b64 | 1067 | return -EINVAL; |
088a78af | 1068 | } |
7e9c7b64 BD |
1069 | } |
1070 | ||
be518018 TK |
1071 | while (readl(host->base + S3C2410_SDIDSTA) & |
1072 | (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) { | |
1073 | ||
1074 | dbg(host, dbg_err, | |
1075 | "mci_setup_data() transfer stillin progress.\n"); | |
1076 | ||
bdbc9c3a | 1077 | writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); |
be518018 TK |
1078 | s3cmci_reset(host); |
1079 | ||
1080 | if ((stoptries--) == 0) { | |
1081 | dbg_dumpregs(host, "DRF"); | |
1082 | return -EINVAL; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK; | |
1087 | ||
26f14947 | 1088 | if (s3cmci_host_usedma(host)) |
be518018 TK |
1089 | dcon |= S3C2410_SDIDCON_DMAEN; |
1090 | ||
1091 | if (host->bus_width == MMC_BUS_WIDTH_4) | |
1092 | dcon |= S3C2410_SDIDCON_WIDEBUS; | |
1093 | ||
1094 | if (!(data->flags & MMC_DATA_STREAM)) | |
1095 | dcon |= S3C2410_SDIDCON_BLOCKMODE; | |
1096 | ||
1097 | if (data->flags & MMC_DATA_WRITE) { | |
1098 | dcon |= S3C2410_SDIDCON_TXAFTERRESP; | |
1099 | dcon |= S3C2410_SDIDCON_XFER_TXSTART; | |
1100 | } | |
1101 | ||
1102 | if (data->flags & MMC_DATA_READ) { | |
1103 | dcon |= S3C2410_SDIDCON_RXAFTERCMD; | |
1104 | dcon |= S3C2410_SDIDCON_XFER_RXSTART; | |
1105 | } | |
1106 | ||
1107 | if (host->is2440) { | |
1108 | dcon |= S3C2440_SDIDCON_DS_WORD; | |
1109 | dcon |= S3C2440_SDIDCON_DATSTART; | |
1110 | } | |
1111 | ||
1112 | writel(dcon, host->base + S3C2410_SDIDCON); | |
1113 | ||
1114 | /* write BSIZE register */ | |
1115 | ||
1116 | writel(data->blksz, host->base + S3C2410_SDIBSIZE); | |
1117 | ||
1118 | /* add to IMASK register */ | |
1119 | imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC | | |
1120 | S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH; | |
1121 | ||
1122 | enable_imask(host, imsk); | |
1123 | ||
1124 | /* write TIMER register */ | |
1125 | ||
1126 | if (host->is2440) { | |
1127 | writel(0x007FFFFF, host->base + S3C2410_SDITIMER); | |
1128 | } else { | |
1129 | writel(0x0000FFFF, host->base + S3C2410_SDITIMER); | |
1130 | ||
1131 | /* FIX: set slow clock to prevent timeouts on read */ | |
1132 | if (data->flags & MMC_DATA_READ) | |
1133 | writel(0xFF, host->base + S3C2410_SDIPRE); | |
1134 | } | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) | |
1140 | ||
1141 | static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data) | |
1142 | { | |
1143 | int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; | |
1144 | ||
1145 | BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); | |
1146 | ||
1147 | host->pio_sgptr = 0; | |
088a78af | 1148 | host->pio_bytes = 0; |
be518018 TK |
1149 | host->pio_count = 0; |
1150 | host->pio_active = rw ? XFER_WRITE : XFER_READ; | |
1151 | ||
1152 | if (rw) { | |
1153 | do_pio_write(host); | |
1154 | enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); | |
1155 | } else { | |
1156 | enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF | |
1157 | | S3C2410_SDIIMSK_RXFIFOLAST); | |
1158 | } | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) | |
1164 | { | |
1165 | int dma_len, i; | |
68c5ed59 | 1166 | int rw = data->flags & MMC_DATA_WRITE; |
be518018 TK |
1167 | |
1168 | BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); | |
1169 | ||
51ddf31d | 1170 | s3cmci_dma_setup(host, rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
be518018 TK |
1171 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); |
1172 | ||
1173 | dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
68c5ed59 | 1174 | rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
be518018 TK |
1175 | |
1176 | if (dma_len == 0) | |
1177 | return -ENOMEM; | |
1178 | ||
1179 | host->dma_complete = 0; | |
1180 | host->dmatogo = dma_len; | |
1181 | ||
1182 | for (i = 0; i < dma_len; i++) { | |
1183 | int res; | |
1184 | ||
68c5ed59 BD |
1185 | dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i, |
1186 | sg_dma_address(&data->sg[i]), | |
1187 | sg_dma_len(&data->sg[i])); | |
be518018 | 1188 | |
68c5ed59 | 1189 | res = s3c2410_dma_enqueue(host->dma, host, |
be518018 TK |
1190 | sg_dma_address(&data->sg[i]), |
1191 | sg_dma_len(&data->sg[i])); | |
1192 | ||
1193 | if (res) { | |
1194 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); | |
1195 | return -EBUSY; | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START); | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static void s3cmci_send_request(struct mmc_host *mmc) | |
1205 | { | |
1206 | struct s3cmci_host *host = mmc_priv(mmc); | |
1207 | struct mmc_request *mrq = host->mrq; | |
1208 | struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; | |
1209 | ||
1210 | host->ccnt++; | |
1211 | prepare_dbgmsg(host, cmd, host->cmd_is_stop); | |
1212 | ||
1213 | /* Clear command, data and fifo status registers | |
1214 | Fifo clear only necessary on 2440, but doesn't hurt on 2410 | |
1215 | */ | |
1216 | writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT); | |
1217 | writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA); | |
1218 | writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA); | |
1219 | ||
1220 | if (cmd->data) { | |
1221 | int res = s3cmci_setup_data(host, cmd->data); | |
1222 | ||
1223 | host->dcnt++; | |
1224 | ||
1225 | if (res) { | |
ff8c804f BD |
1226 | dbg(host, dbg_err, "setup data error %d\n", res); |
1227 | cmd->error = res; | |
1228 | cmd->data->error = res; | |
be518018 TK |
1229 | |
1230 | mmc_request_done(mmc, mrq); | |
1231 | return; | |
1232 | } | |
1233 | ||
26f14947 | 1234 | if (s3cmci_host_usedma(host)) |
be518018 TK |
1235 | res = s3cmci_prepare_dma(host, cmd->data); |
1236 | else | |
1237 | res = s3cmci_prepare_pio(host, cmd->data); | |
1238 | ||
1239 | if (res) { | |
ff8c804f | 1240 | dbg(host, dbg_err, "data prepare error %d\n", res); |
be518018 TK |
1241 | cmd->error = res; |
1242 | cmd->data->error = res; | |
1243 | ||
1244 | mmc_request_done(mmc, mrq); | |
1245 | return; | |
1246 | } | |
1247 | } | |
1248 | ||
1249 | /* Send command */ | |
1250 | s3cmci_send_command(host, cmd); | |
1251 | ||
1252 | /* Enable Interrupt */ | |
c2258893 | 1253 | s3cmci_enable_irq(host, true); |
be518018 TK |
1254 | } |
1255 | ||
87dd9803 | 1256 | static int s3cmci_card_present(struct mmc_host *mmc) |
50a84570 | 1257 | { |
87dd9803 | 1258 | struct s3cmci_host *host = mmc_priv(mmc); |
50a84570 BD |
1259 | struct s3c24xx_mci_pdata *pdata = host->pdata; |
1260 | int ret; | |
1261 | ||
dc2ed552 | 1262 | if (pdata->no_detect) |
50a84570 BD |
1263 | return -ENOSYS; |
1264 | ||
916a3077 | 1265 | ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1; |
50a84570 BD |
1266 | return ret ^ pdata->detect_invert; |
1267 | } | |
1268 | ||
be518018 TK |
1269 | static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
1270 | { | |
1271 | struct s3cmci_host *host = mmc_priv(mmc); | |
1272 | ||
1273 | host->status = "mmc request"; | |
1274 | host->cmd_is_stop = 0; | |
1275 | host->mrq = mrq; | |
1276 | ||
87dd9803 | 1277 | if (s3cmci_card_present(mmc) == 0) { |
50a84570 BD |
1278 | dbg(host, dbg_err, "%s: no medium present\n", __func__); |
1279 | host->mrq->cmd->error = -ENOMEDIUM; | |
1280 | mmc_request_done(mmc, mrq); | |
1281 | } else | |
1282 | s3cmci_send_request(mmc); | |
be518018 TK |
1283 | } |
1284 | ||
f87e6d00 | 1285 | static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios) |
1286 | { | |
1287 | u32 mci_psc; | |
1288 | ||
1289 | /* Set clock */ | |
1290 | for (mci_psc = 0; mci_psc < 255; mci_psc++) { | |
1291 | host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1)); | |
1292 | ||
1293 | if (host->real_rate <= ios->clock) | |
1294 | break; | |
1295 | } | |
1296 | ||
1297 | if (mci_psc > 255) | |
1298 | mci_psc = 255; | |
1299 | ||
1300 | host->prescaler = mci_psc; | |
1301 | writel(host->prescaler, host->base + S3C2410_SDIPRE); | |
1302 | ||
1303 | /* If requested clock is 0, real_rate will be 0, too */ | |
1304 | if (ios->clock == 0) | |
1305 | host->real_rate = 0; | |
1306 | } | |
1307 | ||
be518018 TK |
1308 | static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1309 | { | |
1310 | struct s3cmci_host *host = mmc_priv(mmc); | |
f87e6d00 | 1311 | u32 mci_con; |
be518018 TK |
1312 | |
1313 | /* Set the power state */ | |
1314 | ||
1315 | mci_con = readl(host->base + S3C2410_SDICON); | |
1316 | ||
1317 | switch (ios->power_mode) { | |
1318 | case MMC_POWER_ON: | |
1319 | case MMC_POWER_UP: | |
b9929f0e SN |
1320 | /* Configure GPE5...GPE10 pins in SD mode */ |
1321 | s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2), | |
1322 | S3C_GPIO_PULL_NONE); | |
be518018 | 1323 | |
edb5a98e BD |
1324 | if (host->pdata->set_power) |
1325 | host->pdata->set_power(ios->power_mode, ios->vdd); | |
1326 | ||
be518018 TK |
1327 | if (!host->is2440) |
1328 | mci_con |= S3C2410_SDICON_FIFORESET; | |
1329 | ||
1330 | break; | |
1331 | ||
1332 | case MMC_POWER_OFF: | |
1333 | default: | |
916a3077 | 1334 | gpio_direction_output(S3C2410_GPE(5), 0); |
be518018 TK |
1335 | |
1336 | if (host->is2440) | |
1337 | mci_con |= S3C2440_SDICON_SDRESET; | |
1338 | ||
edb5a98e BD |
1339 | if (host->pdata->set_power) |
1340 | host->pdata->set_power(ios->power_mode, ios->vdd); | |
1341 | ||
be518018 TK |
1342 | break; |
1343 | } | |
1344 | ||
f87e6d00 | 1345 | s3cmci_set_clk(host, ios); |
be518018 TK |
1346 | |
1347 | /* Set CLOCK_ENABLE */ | |
1348 | if (ios->clock) | |
1349 | mci_con |= S3C2410_SDICON_CLOCKTYPE; | |
1350 | else | |
1351 | mci_con &= ~S3C2410_SDICON_CLOCKTYPE; | |
1352 | ||
1353 | writel(mci_con, host->base + S3C2410_SDICON); | |
1354 | ||
1355 | if ((ios->power_mode == MMC_POWER_ON) || | |
1356 | (ios->power_mode == MMC_POWER_UP)) { | |
1357 | dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n", | |
1358 | host->real_rate/1000, ios->clock/1000); | |
1359 | } else { | |
1360 | dbg(host, dbg_conf, "powered down.\n"); | |
1361 | } | |
1362 | ||
1363 | host->bus_width = ios->bus_width; | |
1364 | } | |
1365 | ||
1366 | static void s3cmci_reset(struct s3cmci_host *host) | |
1367 | { | |
1368 | u32 con = readl(host->base + S3C2410_SDICON); | |
1369 | ||
1370 | con |= S3C2440_SDICON_SDRESET; | |
1371 | writel(con, host->base + S3C2410_SDICON); | |
1372 | } | |
1373 | ||
edb5a98e BD |
1374 | static int s3cmci_get_ro(struct mmc_host *mmc) |
1375 | { | |
1376 | struct s3cmci_host *host = mmc_priv(mmc); | |
cf0984c8 BD |
1377 | struct s3c24xx_mci_pdata *pdata = host->pdata; |
1378 | int ret; | |
edb5a98e | 1379 | |
00acfaee | 1380 | if (pdata->no_wprotect) |
edb5a98e BD |
1381 | return 0; |
1382 | ||
c78402e9 BD |
1383 | ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0; |
1384 | ret ^= pdata->wprotect_invert; | |
cf0984c8 BD |
1385 | |
1386 | return ret; | |
edb5a98e BD |
1387 | } |
1388 | ||
c2258893 BD |
1389 | static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1390 | { | |
1391 | struct s3cmci_host *host = mmc_priv(mmc); | |
1392 | unsigned long flags; | |
1393 | u32 con; | |
1394 | ||
1395 | local_irq_save(flags); | |
1396 | ||
1397 | con = readl(host->base + S3C2410_SDICON); | |
1398 | host->sdio_irqen = enable; | |
1399 | ||
1400 | if (enable == host->sdio_irqen) | |
1401 | goto same_state; | |
1402 | ||
1403 | if (enable) { | |
1404 | con |= S3C2410_SDICON_SDIOIRQ; | |
1405 | enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ); | |
1406 | ||
1407 | if (!host->irq_state && !host->irq_disabled) { | |
1408 | host->irq_state = true; | |
1409 | enable_irq(host->irq); | |
1410 | } | |
1411 | } else { | |
1412 | disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ); | |
1413 | con &= ~S3C2410_SDICON_SDIOIRQ; | |
1414 | ||
1415 | if (!host->irq_enabled && host->irq_state) { | |
1416 | disable_irq_nosync(host->irq); | |
1417 | host->irq_state = false; | |
1418 | } | |
1419 | } | |
1420 | ||
1421 | writel(con, host->base + S3C2410_SDICON); | |
1422 | ||
1423 | same_state: | |
1424 | local_irq_restore(flags); | |
1425 | ||
1426 | s3cmci_check_sdio_irq(host); | |
1427 | } | |
1428 | ||
be518018 TK |
1429 | static struct mmc_host_ops s3cmci_ops = { |
1430 | .request = s3cmci_request, | |
1431 | .set_ios = s3cmci_set_ios, | |
edb5a98e | 1432 | .get_ro = s3cmci_get_ro, |
87dd9803 | 1433 | .get_cd = s3cmci_card_present, |
c2258893 | 1434 | .enable_sdio_irq = s3cmci_enable_sdio_irq, |
edb5a98e BD |
1435 | }; |
1436 | ||
1437 | static struct s3c24xx_mci_pdata s3cmci_def_pdata = { | |
1438 | /* This is currently here to avoid a number of if (host->pdata) | |
af901ca1 | 1439 | * checks. Any zero fields to ensure reasonable defaults are picked. */ |
c212808a LPC |
1440 | .no_wprotect = 1, |
1441 | .no_detect = 1, | |
be518018 TK |
1442 | }; |
1443 | ||
f87e6d00 | 1444 | #ifdef CONFIG_CPU_FREQ |
1445 | ||
1446 | static int s3cmci_cpufreq_transition(struct notifier_block *nb, | |
1447 | unsigned long val, void *data) | |
1448 | { | |
1449 | struct s3cmci_host *host; | |
1450 | struct mmc_host *mmc; | |
1451 | unsigned long newclk; | |
1452 | unsigned long flags; | |
1453 | ||
1454 | host = container_of(nb, struct s3cmci_host, freq_transition); | |
1455 | newclk = clk_get_rate(host->clk); | |
1456 | mmc = host->mmc; | |
1457 | ||
1458 | if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) || | |
1459 | (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) { | |
1460 | spin_lock_irqsave(&mmc->lock, flags); | |
1461 | ||
1462 | host->clk_rate = newclk; | |
1463 | ||
1464 | if (mmc->ios.power_mode != MMC_POWER_OFF && | |
1465 | mmc->ios.clock != 0) | |
1466 | s3cmci_set_clk(host, &mmc->ios); | |
1467 | ||
1468 | spin_unlock_irqrestore(&mmc->lock, flags); | |
1469 | } | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static inline int s3cmci_cpufreq_register(struct s3cmci_host *host) | |
1475 | { | |
1476 | host->freq_transition.notifier_call = s3cmci_cpufreq_transition; | |
1477 | ||
1478 | return cpufreq_register_notifier(&host->freq_transition, | |
1479 | CPUFREQ_TRANSITION_NOTIFIER); | |
1480 | } | |
1481 | ||
1482 | static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host) | |
1483 | { | |
1484 | cpufreq_unregister_notifier(&host->freq_transition, | |
1485 | CPUFREQ_TRANSITION_NOTIFIER); | |
1486 | } | |
1487 | ||
1488 | #else | |
1489 | static inline int s3cmci_cpufreq_register(struct s3cmci_host *host) | |
1490 | { | |
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host) | |
1495 | { | |
1496 | } | |
1497 | #endif | |
1498 | ||
916a3077 | 1499 | |
9bdd203b BD |
1500 | #ifdef CONFIG_DEBUG_FS |
1501 | ||
1502 | static int s3cmci_state_show(struct seq_file *seq, void *v) | |
1503 | { | |
1504 | struct s3cmci_host *host = seq->private; | |
1505 | ||
1506 | seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base); | |
1507 | seq_printf(seq, "Clock rate = %ld\n", host->clk_rate); | |
1508 | seq_printf(seq, "Prescale = %d\n", host->prescaler); | |
1509 | seq_printf(seq, "is2440 = %d\n", host->is2440); | |
1510 | seq_printf(seq, "IRQ = %d\n", host->irq); | |
c2258893 BD |
1511 | seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled); |
1512 | seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled); | |
1513 | seq_printf(seq, "IRQ state = %d\n", host->irq_state); | |
9bdd203b | 1514 | seq_printf(seq, "CD IRQ = %d\n", host->irq_cd); |
26f14947 | 1515 | seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host)); |
9bdd203b BD |
1516 | seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk); |
1517 | seq_printf(seq, "SDIDATA at %d\n", host->sdidata); | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | static int s3cmci_state_open(struct inode *inode, struct file *file) | |
1523 | { | |
1524 | return single_open(file, s3cmci_state_show, inode->i_private); | |
1525 | } | |
1526 | ||
1527 | static const struct file_operations s3cmci_fops_state = { | |
1528 | .owner = THIS_MODULE, | |
1529 | .open = s3cmci_state_open, | |
1530 | .read = seq_read, | |
1531 | .llseek = seq_lseek, | |
1532 | .release = single_release, | |
1533 | }; | |
1534 | ||
1535 | #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r } | |
1536 | ||
1537 | struct s3cmci_reg { | |
1538 | unsigned short addr; | |
1539 | unsigned char *name; | |
1540 | } debug_regs[] = { | |
1541 | DBG_REG(CON), | |
1542 | DBG_REG(PRE), | |
1543 | DBG_REG(CMDARG), | |
1544 | DBG_REG(CMDCON), | |
1545 | DBG_REG(CMDSTAT), | |
1546 | DBG_REG(RSP0), | |
1547 | DBG_REG(RSP1), | |
1548 | DBG_REG(RSP2), | |
1549 | DBG_REG(RSP3), | |
1550 | DBG_REG(TIMER), | |
1551 | DBG_REG(BSIZE), | |
1552 | DBG_REG(DCON), | |
1553 | DBG_REG(DCNT), | |
1554 | DBG_REG(DSTA), | |
1555 | DBG_REG(FSTA), | |
1556 | {} | |
1557 | }; | |
1558 | ||
1559 | static int s3cmci_regs_show(struct seq_file *seq, void *v) | |
1560 | { | |
1561 | struct s3cmci_host *host = seq->private; | |
1562 | struct s3cmci_reg *rptr = debug_regs; | |
1563 | ||
1564 | for (; rptr->name; rptr++) | |
1565 | seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name, | |
1566 | readl(host->base + rptr->addr)); | |
1567 | ||
1568 | seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk)); | |
1569 | ||
1570 | return 0; | |
1571 | } | |
1572 | ||
1573 | static int s3cmci_regs_open(struct inode *inode, struct file *file) | |
1574 | { | |
1575 | return single_open(file, s3cmci_regs_show, inode->i_private); | |
1576 | } | |
1577 | ||
1578 | static const struct file_operations s3cmci_fops_regs = { | |
1579 | .owner = THIS_MODULE, | |
1580 | .open = s3cmci_regs_open, | |
1581 | .read = seq_read, | |
1582 | .llseek = seq_lseek, | |
1583 | .release = single_release, | |
1584 | }; | |
1585 | ||
1586 | static void s3cmci_debugfs_attach(struct s3cmci_host *host) | |
1587 | { | |
1588 | struct device *dev = &host->pdev->dev; | |
1589 | ||
1590 | host->debug_root = debugfs_create_dir(dev_name(dev), NULL); | |
1591 | if (IS_ERR(host->debug_root)) { | |
1592 | dev_err(dev, "failed to create debugfs root\n"); | |
1593 | return; | |
1594 | } | |
1595 | ||
1596 | host->debug_state = debugfs_create_file("state", 0444, | |
1597 | host->debug_root, host, | |
1598 | &s3cmci_fops_state); | |
1599 | ||
1600 | if (IS_ERR(host->debug_state)) | |
1601 | dev_err(dev, "failed to create debug state file\n"); | |
1602 | ||
1603 | host->debug_regs = debugfs_create_file("regs", 0444, | |
1604 | host->debug_root, host, | |
1605 | &s3cmci_fops_regs); | |
1606 | ||
1607 | if (IS_ERR(host->debug_regs)) | |
1608 | dev_err(dev, "failed to create debug regs file\n"); | |
1609 | } | |
1610 | ||
1611 | static void s3cmci_debugfs_remove(struct s3cmci_host *host) | |
1612 | { | |
1613 | debugfs_remove(host->debug_regs); | |
1614 | debugfs_remove(host->debug_state); | |
1615 | debugfs_remove(host->debug_root); | |
1616 | } | |
1617 | ||
1618 | #else | |
1619 | static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { } | |
1620 | static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { } | |
1621 | ||
1622 | #endif /* CONFIG_DEBUG_FS */ | |
1623 | ||
c3be1efd | 1624 | static int s3cmci_probe(struct platform_device *pdev) |
be518018 TK |
1625 | { |
1626 | struct s3cmci_host *host; | |
1627 | struct mmc_host *mmc; | |
1628 | int ret; | |
44d0e199 | 1629 | int is2440; |
916a3077 | 1630 | int i; |
44d0e199 BD |
1631 | |
1632 | is2440 = platform_get_device_id(pdev)->driver_data; | |
be518018 TK |
1633 | |
1634 | mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev); | |
1635 | if (!mmc) { | |
1636 | ret = -ENOMEM; | |
1637 | goto probe_out; | |
1638 | } | |
1639 | ||
916a3077 BD |
1640 | for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) { |
1641 | ret = gpio_request(i, dev_name(&pdev->dev)); | |
1642 | if (ret) { | |
1643 | dev_err(&pdev->dev, "failed to get gpio %d\n", i); | |
1644 | ||
1645 | for (i--; i >= S3C2410_GPE(5); i--) | |
1646 | gpio_free(i); | |
1647 | ||
1648 | goto probe_free_host; | |
1649 | } | |
1650 | } | |
1651 | ||
be518018 TK |
1652 | host = mmc_priv(mmc); |
1653 | host->mmc = mmc; | |
1654 | host->pdev = pdev; | |
1655 | host->is2440 = is2440; | |
1656 | ||
edb5a98e BD |
1657 | host->pdata = pdev->dev.platform_data; |
1658 | if (!host->pdata) { | |
1659 | pdev->dev.platform_data = &s3cmci_def_pdata; | |
1660 | host->pdata = &s3cmci_def_pdata; | |
1661 | } | |
1662 | ||
be518018 TK |
1663 | spin_lock_init(&host->complete_lock); |
1664 | tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host); | |
1665 | ||
1666 | if (is2440) { | |
1667 | host->sdiimsk = S3C2440_SDIIMSK; | |
1668 | host->sdidata = S3C2440_SDIDATA; | |
1669 | host->clk_div = 1; | |
1670 | } else { | |
1671 | host->sdiimsk = S3C2410_SDIIMSK; | |
1672 | host->sdidata = S3C2410_SDIDATA; | |
1673 | host->clk_div = 2; | |
1674 | } | |
1675 | ||
be518018 TK |
1676 | host->complete_what = COMPLETION_NONE; |
1677 | host->pio_active = XFER_NONE; | |
1678 | ||
26f14947 | 1679 | #ifdef CONFIG_MMC_S3C_PIODMA |
60c2c0d5 | 1680 | host->dodma = host->pdata->use_dma; |
26f14947 BD |
1681 | #endif |
1682 | ||
be518018 TK |
1683 | host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1684 | if (!host->mem) { | |
1685 | dev_err(&pdev->dev, | |
4aa6ded9 | 1686 | "failed to get io memory region resource.\n"); |
be518018 TK |
1687 | |
1688 | ret = -ENOENT; | |
916a3077 | 1689 | goto probe_free_gpio; |
be518018 TK |
1690 | } |
1691 | ||
1692 | host->mem = request_mem_region(host->mem->start, | |
da52a7ca | 1693 | resource_size(host->mem), pdev->name); |
be518018 TK |
1694 | |
1695 | if (!host->mem) { | |
1696 | dev_err(&pdev->dev, "failed to request io memory region.\n"); | |
1697 | ret = -ENOENT; | |
916a3077 | 1698 | goto probe_free_gpio; |
be518018 TK |
1699 | } |
1700 | ||
da52a7ca | 1701 | host->base = ioremap(host->mem->start, resource_size(host->mem)); |
5d304400 | 1702 | if (!host->base) { |
be518018 TK |
1703 | dev_err(&pdev->dev, "failed to ioremap() io memory region.\n"); |
1704 | ret = -EINVAL; | |
1705 | goto probe_free_mem_region; | |
1706 | } | |
1707 | ||
1708 | host->irq = platform_get_irq(pdev, 0); | |
1709 | if (host->irq == 0) { | |
4aa6ded9 | 1710 | dev_err(&pdev->dev, "failed to get interrupt resource.\n"); |
be518018 TK |
1711 | ret = -EINVAL; |
1712 | goto probe_iounmap; | |
1713 | } | |
1714 | ||
1715 | if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) { | |
1716 | dev_err(&pdev->dev, "failed to request mci interrupt.\n"); | |
1717 | ret = -ENOENT; | |
1718 | goto probe_iounmap; | |
1719 | } | |
1720 | ||
1721 | /* We get spurious interrupts even when we have set the IMSK | |
1722 | * register to ignore everything, so use disable_irq() to make | |
1723 | * ensure we don't lock the system with un-serviceable requests. */ | |
1724 | ||
1725 | disable_irq(host->irq); | |
c2258893 | 1726 | host->irq_state = false; |
be518018 | 1727 | |
00acfaee | 1728 | if (!host->pdata->no_detect) { |
916a3077 BD |
1729 | ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect"); |
1730 | if (ret) { | |
1731 | dev_err(&pdev->dev, "failed to get detect gpio\n"); | |
1732 | goto probe_free_irq; | |
1733 | } | |
be518018 | 1734 | |
c78402e9 | 1735 | host->irq_cd = gpio_to_irq(host->pdata->gpio_detect); |
00acfaee BD |
1736 | |
1737 | if (host->irq_cd >= 0) { | |
1738 | if (request_irq(host->irq_cd, s3cmci_irq_cd, | |
1739 | IRQF_TRIGGER_RISING | | |
1740 | IRQF_TRIGGER_FALLING, | |
1741 | DRIVER_NAME, host)) { | |
1742 | dev_err(&pdev->dev, | |
1743 | "can't get card detect irq.\n"); | |
1744 | ret = -ENOENT; | |
1745 | goto probe_free_gpio_cd; | |
1746 | } | |
1747 | } else { | |
1748 | dev_warn(&pdev->dev, | |
1749 | "host detect has no irq available\n"); | |
1750 | gpio_direction_input(host->pdata->gpio_detect); | |
55d70f5a | 1751 | } |
00acfaee BD |
1752 | } else |
1753 | host->irq_cd = -1; | |
be518018 | 1754 | |
00acfaee | 1755 | if (!host->pdata->no_wprotect) { |
916a3077 BD |
1756 | ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp"); |
1757 | if (ret) { | |
1758 | dev_err(&pdev->dev, "failed to get writeprotect\n"); | |
1759 | goto probe_free_irq_cd; | |
1760 | } | |
1761 | ||
1762 | gpio_direction_input(host->pdata->gpio_wprotect); | |
1763 | } | |
edb5a98e | 1764 | |
68c5ed59 BD |
1765 | /* depending on the dma state, get a dma channel to use. */ |
1766 | ||
1767 | if (s3cmci_host_usedma(host)) { | |
1768 | host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client, | |
1769 | host); | |
1770 | if (host->dma < 0) { | |
1771 | dev_err(&pdev->dev, "cannot get DMA channel.\n"); | |
1772 | if (!s3cmci_host_canpio()) { | |
1773 | ret = -EBUSY; | |
1774 | goto probe_free_gpio_wp; | |
1775 | } else { | |
1776 | dev_warn(&pdev->dev, "falling back to PIO.\n"); | |
1777 | host->dodma = 0; | |
1778 | } | |
1779 | } | |
be518018 TK |
1780 | } |
1781 | ||
1782 | host->clk = clk_get(&pdev->dev, "sdi"); | |
1783 | if (IS_ERR(host->clk)) { | |
1784 | dev_err(&pdev->dev, "failed to find clock source.\n"); | |
1785 | ret = PTR_ERR(host->clk); | |
1786 | host->clk = NULL; | |
68c5ed59 | 1787 | goto probe_free_dma; |
be518018 TK |
1788 | } |
1789 | ||
1790 | ret = clk_enable(host->clk); | |
1791 | if (ret) { | |
1792 | dev_err(&pdev->dev, "failed to enable clock source.\n"); | |
1793 | goto clk_free; | |
1794 | } | |
1795 | ||
1796 | host->clk_rate = clk_get_rate(host->clk); | |
1797 | ||
1798 | mmc->ops = &s3cmci_ops; | |
edb5a98e | 1799 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
5a2c4fe0 | 1800 | #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ |
c2258893 | 1801 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
5a2c4fe0 BD |
1802 | #else |
1803 | mmc->caps = MMC_CAP_4_BIT_DATA; | |
1804 | #endif | |
be518018 TK |
1805 | mmc->f_min = host->clk_rate / (host->clk_div * 256); |
1806 | mmc->f_max = host->clk_rate / host->clk_div; | |
1807 | ||
edb5a98e BD |
1808 | if (host->pdata->ocr_avail) |
1809 | mmc->ocr_avail = host->pdata->ocr_avail; | |
1810 | ||
be518018 TK |
1811 | mmc->max_blk_count = 4095; |
1812 | mmc->max_blk_size = 4095; | |
1813 | mmc->max_req_size = 4095 * 512; | |
1814 | mmc->max_seg_size = mmc->max_req_size; | |
1815 | ||
a36274e0 | 1816 | mmc->max_segs = 128; |
be518018 TK |
1817 | |
1818 | dbg(host, dbg_debug, | |
1819 | "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n", | |
1820 | (host->is2440?"2440":""), | |
1821 | host->base, host->irq, host->irq_cd, host->dma); | |
1822 | ||
f87e6d00 | 1823 | ret = s3cmci_cpufreq_register(host); |
1824 | if (ret) { | |
1825 | dev_err(&pdev->dev, "failed to register cpufreq\n"); | |
1826 | goto free_dmabuf; | |
1827 | } | |
1828 | ||
be518018 TK |
1829 | ret = mmc_add_host(mmc); |
1830 | if (ret) { | |
1831 | dev_err(&pdev->dev, "failed to add mmc host.\n"); | |
f87e6d00 | 1832 | goto free_cpufreq; |
be518018 TK |
1833 | } |
1834 | ||
9bdd203b BD |
1835 | s3cmci_debugfs_attach(host); |
1836 | ||
be518018 | 1837 | platform_set_drvdata(pdev, mmc); |
5a2c4fe0 BD |
1838 | dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc), |
1839 | s3cmci_host_usedma(host) ? "dma" : "pio", | |
1840 | mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw"); | |
be518018 TK |
1841 | |
1842 | return 0; | |
1843 | ||
f87e6d00 | 1844 | free_cpufreq: |
1845 | s3cmci_cpufreq_deregister(host); | |
1846 | ||
be518018 TK |
1847 | free_dmabuf: |
1848 | clk_disable(host->clk); | |
1849 | ||
1850 | clk_free: | |
1851 | clk_put(host->clk); | |
1852 | ||
68c5ed59 BD |
1853 | probe_free_dma: |
1854 | if (s3cmci_host_usedma(host)) | |
1855 | s3c2410_dma_free(host->dma, &s3cmci_dma_client); | |
1856 | ||
916a3077 | 1857 | probe_free_gpio_wp: |
00acfaee | 1858 | if (!host->pdata->no_wprotect) |
916a3077 BD |
1859 | gpio_free(host->pdata->gpio_wprotect); |
1860 | ||
1861 | probe_free_gpio_cd: | |
00acfaee | 1862 | if (!host->pdata->no_detect) |
916a3077 BD |
1863 | gpio_free(host->pdata->gpio_detect); |
1864 | ||
be518018 | 1865 | probe_free_irq_cd: |
55d70f5a BD |
1866 | if (host->irq_cd >= 0) |
1867 | free_irq(host->irq_cd, host); | |
be518018 TK |
1868 | |
1869 | probe_free_irq: | |
1870 | free_irq(host->irq, host); | |
1871 | ||
1872 | probe_iounmap: | |
1873 | iounmap(host->base); | |
1874 | ||
1875 | probe_free_mem_region: | |
da52a7ca | 1876 | release_mem_region(host->mem->start, resource_size(host->mem)); |
be518018 | 1877 | |
916a3077 BD |
1878 | probe_free_gpio: |
1879 | for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) | |
1880 | gpio_free(i); | |
1881 | ||
be518018 TK |
1882 | probe_free_host: |
1883 | mmc_free_host(mmc); | |
916a3077 | 1884 | |
be518018 TK |
1885 | probe_out: |
1886 | return ret; | |
1887 | } | |
1888 | ||
907b2cd6 BD |
1889 | static void s3cmci_shutdown(struct platform_device *pdev) |
1890 | { | |
1891 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1892 | struct s3cmci_host *host = mmc_priv(mmc); | |
1893 | ||
1894 | if (host->irq_cd >= 0) | |
1895 | free_irq(host->irq_cd, host); | |
1896 | ||
9bdd203b | 1897 | s3cmci_debugfs_remove(host); |
f87e6d00 | 1898 | s3cmci_cpufreq_deregister(host); |
907b2cd6 BD |
1899 | mmc_remove_host(mmc); |
1900 | clk_disable(host->clk); | |
1901 | } | |
1902 | ||
6e0ee714 | 1903 | static int s3cmci_remove(struct platform_device *pdev) |
be518018 TK |
1904 | { |
1905 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1906 | struct s3cmci_host *host = mmc_priv(mmc); | |
916a3077 BD |
1907 | struct s3c24xx_mci_pdata *pd = host->pdata; |
1908 | int i; | |
be518018 | 1909 | |
907b2cd6 | 1910 | s3cmci_shutdown(pdev); |
be518018 | 1911 | |
be518018 TK |
1912 | clk_put(host->clk); |
1913 | ||
1914 | tasklet_disable(&host->pio_tasklet); | |
68c5ed59 BD |
1915 | |
1916 | if (s3cmci_host_usedma(host)) | |
1917 | s3c2410_dma_free(host->dma, &s3cmci_dma_client); | |
be518018 | 1918 | |
be518018 TK |
1919 | free_irq(host->irq, host); |
1920 | ||
00acfaee | 1921 | if (!pd->no_wprotect) |
916a3077 BD |
1922 | gpio_free(pd->gpio_wprotect); |
1923 | ||
00acfaee | 1924 | if (!pd->no_detect) |
916a3077 BD |
1925 | gpio_free(pd->gpio_detect); |
1926 | ||
1927 | for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) | |
1928 | gpio_free(i); | |
1929 | ||
1930 | ||
be518018 | 1931 | iounmap(host->base); |
da52a7ca | 1932 | release_mem_region(host->mem->start, resource_size(host->mem)); |
be518018 TK |
1933 | |
1934 | mmc_free_host(mmc); | |
1935 | return 0; | |
1936 | } | |
1937 | ||
44d0e199 BD |
1938 | static struct platform_device_id s3cmci_driver_ids[] = { |
1939 | { | |
1940 | .name = "s3c2410-sdi", | |
1941 | .driver_data = 0, | |
1942 | }, { | |
1943 | .name = "s3c2412-sdi", | |
1944 | .driver_data = 1, | |
1945 | }, { | |
1946 | .name = "s3c2440-sdi", | |
1947 | .driver_data = 1, | |
1948 | }, | |
1949 | { } | |
1950 | }; | |
be518018 | 1951 | |
44d0e199 | 1952 | MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids); |
be518018 | 1953 | |
44d0e199 | 1954 | static struct platform_driver s3cmci_driver = { |
50d7fa9a BD |
1955 | .driver = { |
1956 | .name = "s3c-sdi", | |
1957 | .owner = THIS_MODULE, | |
50d7fa9a | 1958 | }, |
44d0e199 BD |
1959 | .id_table = s3cmci_driver_ids, |
1960 | .probe = s3cmci_probe, | |
0433c143 | 1961 | .remove = s3cmci_remove, |
907b2cd6 | 1962 | .shutdown = s3cmci_shutdown, |
be518018 TK |
1963 | }; |
1964 | ||
d1f81a64 | 1965 | module_platform_driver(s3cmci_driver); |
be518018 TK |
1966 | |
1967 | MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver"); | |
1968 | MODULE_LICENSE("GPL v2"); | |
08c55e22 | 1969 | MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>"); |