Commit | Line | Data |
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95f25efe WS |
1 | /* |
2 | * Freescale eSDHC i.MX controller driver for the platform bus. | |
3 | * | |
4 | * derived from the OF-version. | |
5 | * | |
6 | * Copyright (c) 2010 Pengutronix e.K. | |
035ff831 | 7 | * Author: Wolfram Sang <kernel@pengutronix.de> |
95f25efe WS |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
0c6d49ce | 18 | #include <linux/gpio.h> |
66506f76 | 19 | #include <linux/module.h> |
e149860d | 20 | #include <linux/slab.h> |
95f25efe | 21 | #include <linux/mmc/host.h> |
58ac8177 RZ |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> | |
fbe5fdd1 | 24 | #include <linux/mmc/slot-gpio.h> |
abfafc2d SG |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/of_gpio.h> | |
e62d8b8f | 28 | #include <linux/pinctrl/consumer.h> |
82906b13 | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
89d7e5c1 | 30 | #include <linux/pm_runtime.h> |
95f25efe WS |
31 | #include "sdhci-pltfm.h" |
32 | #include "sdhci-esdhc.h" | |
33 | ||
60bf6396 | 34 | #define ESDHC_CTRL_D3CD 0x08 |
58ac8177 | 35 | /* VENDOR SPEC register */ |
60bf6396 SG |
36 | #define ESDHC_VENDOR_SPEC 0xc0 |
37 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) | |
0322191e | 38 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
fed2f6e2 | 39 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
60bf6396 SG |
40 | #define ESDHC_WTMK_LVL 0x44 |
41 | #define ESDHC_MIX_CTRL 0x48 | |
de5bdbff | 42 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
2a15f981 | 43 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
0322191e DA |
44 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
45 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) | |
46 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) | |
2a15f981 SG |
47 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
48 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 | |
d131a71c DA |
49 | /* Tuning bits */ |
50 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 | |
58ac8177 | 51 | |
602519b2 DA |
52 | /* dll control register */ |
53 | #define ESDHC_DLL_CTRL 0x60 | |
54 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 | |
55 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 | |
56 | ||
0322191e DA |
57 | /* tune control register */ |
58 | #define ESDHC_TUNE_CTRL_STATUS 0x68 | |
59 | #define ESDHC_TUNE_CTRL_STEP 1 | |
60 | #define ESDHC_TUNE_CTRL_MIN 0 | |
61 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) | |
62 | ||
6e9fd28e DA |
63 | #define ESDHC_TUNING_CTRL 0xcc |
64 | #define ESDHC_STD_TUNING_EN (1 << 24) | |
65 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ | |
66 | #define ESDHC_TUNING_START_TAP 0x1 | |
67 | ||
ad93220d DA |
68 | /* pinctrl state */ |
69 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" | |
70 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" | |
71 | ||
af51079e SH |
72 | /* |
73 | * Our interpretation of the SDHCI_HOST_CONTROL register | |
74 | */ | |
75 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | |
76 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
77 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
78 | ||
97e4ba6a RZ |
79 | /* |
80 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: | |
81 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, | |
82 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. | |
83 | * Define this macro DMA error INT for fsl eSDHC | |
84 | */ | |
60bf6396 | 85 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
97e4ba6a | 86 | |
58ac8177 RZ |
87 | /* |
88 | * The CMDTYPE of the CMD register (offset 0xE) should be set to | |
89 | * "11" when the STOP CMD12 is issued on imx53 to abort one | |
90 | * open ended multi-blk IO. Otherwise the TC INT wouldn't | |
91 | * be generated. | |
92 | * In exact block transfer, the controller doesn't complete the | |
93 | * operations automatically as required at the end of the | |
94 | * transfer and remains on hold if the abort command is not sent. | |
95 | * As a result, the TC flag is not asserted and SW received timeout | |
96 | * exeception. Bit1 of Vendor Spec registor is used to fix it. | |
97 | */ | |
31fbb301 SG |
98 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
99 | /* | |
100 | * The flag enables the workaround for ESDHC errata ENGcm07207 which | |
101 | * affects i.MX25 and i.MX35. | |
102 | */ | |
103 | #define ESDHC_FLAG_ENGCM07207 BIT(2) | |
9d61c009 SG |
104 | /* |
105 | * The flag tells that the ESDHC controller is an USDHC block that is | |
106 | * integrated on the i.MX6 series. | |
107 | */ | |
108 | #define ESDHC_FLAG_USDHC BIT(3) | |
6e9fd28e DA |
109 | /* The IP supports manual tuning process */ |
110 | #define ESDHC_FLAG_MAN_TUNING BIT(4) | |
111 | /* The IP supports standard tuning process */ | |
112 | #define ESDHC_FLAG_STD_TUNING BIT(5) | |
113 | /* The IP has SDHCI_CAPABILITIES_1 register */ | |
114 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) | |
18094430 DA |
115 | /* |
116 | * The IP has errata ERR004536 | |
117 | * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, | |
118 | * when reading data from the card | |
119 | */ | |
120 | #define ESDHC_FLAG_ERR004536 BIT(7) | |
e149860d | 121 | |
f47c4bbf SG |
122 | struct esdhc_soc_data { |
123 | u32 flags; | |
124 | }; | |
125 | ||
126 | static struct esdhc_soc_data esdhc_imx25_data = { | |
127 | .flags = ESDHC_FLAG_ENGCM07207, | |
128 | }; | |
129 | ||
130 | static struct esdhc_soc_data esdhc_imx35_data = { | |
131 | .flags = ESDHC_FLAG_ENGCM07207, | |
132 | }; | |
133 | ||
134 | static struct esdhc_soc_data esdhc_imx51_data = { | |
135 | .flags = 0, | |
136 | }; | |
137 | ||
138 | static struct esdhc_soc_data esdhc_imx53_data = { | |
139 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, | |
140 | }; | |
141 | ||
142 | static struct esdhc_soc_data usdhc_imx6q_data = { | |
6e9fd28e DA |
143 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
144 | }; | |
145 | ||
146 | static struct esdhc_soc_data usdhc_imx6sl_data = { | |
147 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
18094430 | 148 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536, |
57ed3314 SG |
149 | }; |
150 | ||
e149860d | 151 | struct pltfm_imx_data { |
e149860d | 152 | u32 scratchpad; |
e62d8b8f | 153 | struct pinctrl *pinctrl; |
ad93220d DA |
154 | struct pinctrl_state *pins_default; |
155 | struct pinctrl_state *pins_100mhz; | |
156 | struct pinctrl_state *pins_200mhz; | |
f47c4bbf | 157 | const struct esdhc_soc_data *socdata; |
842afc02 | 158 | struct esdhc_platform_data boarddata; |
52dac615 SH |
159 | struct clk *clk_ipg; |
160 | struct clk *clk_ahb; | |
161 | struct clk *clk_per; | |
361b8482 LS |
162 | enum { |
163 | NO_CMD_PENDING, /* no multiblock command pending*/ | |
164 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ | |
165 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ | |
166 | } multiblock_status; | |
de5bdbff | 167 | u32 is_ddr; |
e149860d RZ |
168 | }; |
169 | ||
f8cbf461 | 170 | static const struct platform_device_id imx_esdhc_devtype[] = { |
57ed3314 SG |
171 | { |
172 | .name = "sdhci-esdhc-imx25", | |
f47c4bbf | 173 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
57ed3314 SG |
174 | }, { |
175 | .name = "sdhci-esdhc-imx35", | |
f47c4bbf | 176 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
57ed3314 SG |
177 | }, { |
178 | .name = "sdhci-esdhc-imx51", | |
f47c4bbf | 179 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
57ed3314 SG |
180 | }, { |
181 | /* sentinel */ | |
182 | } | |
183 | }; | |
184 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); | |
185 | ||
abfafc2d | 186 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
f47c4bbf SG |
187 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
188 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, | |
189 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, | |
190 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, | |
6e9fd28e | 191 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
f47c4bbf | 192 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
abfafc2d SG |
193 | { /* sentinel */ } |
194 | }; | |
195 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); | |
196 | ||
57ed3314 SG |
197 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
198 | { | |
f47c4bbf | 199 | return data->socdata == &esdhc_imx25_data; |
57ed3314 SG |
200 | } |
201 | ||
202 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) | |
203 | { | |
f47c4bbf | 204 | return data->socdata == &esdhc_imx53_data; |
57ed3314 SG |
205 | } |
206 | ||
95a2482a SG |
207 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
208 | { | |
f47c4bbf | 209 | return data->socdata == &usdhc_imx6q_data; |
95a2482a SG |
210 | } |
211 | ||
9d61c009 SG |
212 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
213 | { | |
f47c4bbf | 214 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
9d61c009 SG |
215 | } |
216 | ||
95f25efe WS |
217 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
218 | { | |
219 | void __iomem *base = host->ioaddr + (reg & ~0x3); | |
220 | u32 shift = (reg & 0x3) * 8; | |
221 | ||
222 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); | |
223 | } | |
224 | ||
7e29c306 WS |
225 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
226 | { | |
361b8482 LS |
227 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
228 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
7e29c306 WS |
229 | u32 val = readl(host->ioaddr + reg); |
230 | ||
0322191e DA |
231 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
232 | u32 fsl_prss = val; | |
233 | /* save the least 20 bits */ | |
234 | val = fsl_prss & 0x000FFFFF; | |
235 | /* move dat[0-3] bits */ | |
236 | val |= (fsl_prss & 0x0F000000) >> 4; | |
237 | /* move cmd line bit */ | |
238 | val |= (fsl_prss & 0x00800000) << 1; | |
239 | } | |
240 | ||
97e4ba6a | 241 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
6b4fb671 DA |
242 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
243 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
244 | val &= 0xffff0000; | |
245 | ||
97e4ba6a RZ |
246 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
247 | * ADMA2 capability of esdhc, but this bit is messed up on | |
248 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they | |
249 | * don't actually support ADMA2). So set the BROKEN_ADMA | |
250 | * uirk on MX25/35 platforms. | |
251 | */ | |
252 | ||
253 | if (val & SDHCI_CAN_DO_ADMA1) { | |
254 | val &= ~SDHCI_CAN_DO_ADMA1; | |
255 | val |= SDHCI_CAN_DO_ADMA2; | |
256 | } | |
257 | } | |
258 | ||
6e9fd28e DA |
259 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
260 | if (esdhc_is_usdhc(imx_data)) { | |
261 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
262 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; | |
263 | else | |
264 | /* imx6q/dl does not have cap_1 register, fake one */ | |
265 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | |
888824bb DA |
266 | | SDHCI_SUPPORT_SDR50 |
267 | | SDHCI_USE_SDR50_TUNING; | |
6e9fd28e DA |
268 | } |
269 | } | |
0322191e | 270 | |
9d61c009 | 271 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
0322191e DA |
272 | val = 0; |
273 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; | |
274 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; | |
275 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; | |
276 | } | |
277 | ||
97e4ba6a | 278 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
60bf6396 SG |
279 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
280 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
97e4ba6a RZ |
281 | val |= SDHCI_INT_ADMA_ERROR; |
282 | } | |
361b8482 LS |
283 | |
284 | /* | |
285 | * mask off the interrupt we get in response to the manually | |
286 | * sent CMD12 | |
287 | */ | |
288 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && | |
289 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { | |
290 | val &= ~SDHCI_INT_RESPONSE; | |
291 | writel(SDHCI_INT_RESPONSE, host->ioaddr + | |
292 | SDHCI_INT_STATUS); | |
293 | imx_data->multiblock_status = NO_CMD_PENDING; | |
294 | } | |
97e4ba6a RZ |
295 | } |
296 | ||
7e29c306 WS |
297 | return val; |
298 | } | |
299 | ||
300 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) | |
301 | { | |
e149860d RZ |
302 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
303 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0d58864b TL |
304 | u32 data; |
305 | ||
306 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { | |
b7321042 | 307 | if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { |
0d58864b TL |
308 | /* |
309 | * Clear and then set D3CD bit to avoid missing the | |
310 | * card interrupt. This is a eSDHC controller problem | |
311 | * so we need to apply the following workaround: clear | |
312 | * and set D3CD bit will make eSDHC re-sample the card | |
313 | * interrupt. In case a card interrupt was lost, | |
314 | * re-sample it by the following steps. | |
315 | */ | |
316 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); | |
60bf6396 | 317 | data &= ~ESDHC_CTRL_D3CD; |
0d58864b | 318 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
60bf6396 | 319 | data |= ESDHC_CTRL_D3CD; |
0d58864b TL |
320 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
321 | } | |
915be485 DA |
322 | |
323 | if (val & SDHCI_INT_ADMA_ERROR) { | |
324 | val &= ~SDHCI_INT_ADMA_ERROR; | |
325 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
326 | } | |
0d58864b | 327 | } |
7e29c306 | 328 | |
f47c4bbf | 329 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
330 | && (reg == SDHCI_INT_STATUS) |
331 | && (val & SDHCI_INT_DATA_END))) { | |
332 | u32 v; | |
60bf6396 SG |
333 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
334 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
335 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
361b8482 LS |
336 | |
337 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) | |
338 | { | |
339 | /* send a manual CMD12 with RESPTYP=none */ | |
340 | data = MMC_STOP_TRANSMISSION << 24 | | |
341 | SDHCI_CMD_ABORTCMD << 16; | |
342 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); | |
343 | imx_data->multiblock_status = WAIT_FOR_INT; | |
344 | } | |
58ac8177 RZ |
345 | } |
346 | ||
7e29c306 WS |
347 | writel(val, host->ioaddr + reg); |
348 | } | |
349 | ||
95f25efe WS |
350 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
351 | { | |
ef4d0888 SG |
352 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
353 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0322191e DA |
354 | u16 ret = 0; |
355 | u32 val; | |
ef4d0888 | 356 | |
95a2482a | 357 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
ef4d0888 | 358 | reg ^= 2; |
9d61c009 | 359 | if (esdhc_is_usdhc(imx_data)) { |
ef4d0888 SG |
360 | /* |
361 | * The usdhc register returns a wrong host version. | |
362 | * Correct it here. | |
363 | */ | |
364 | return SDHCI_SPEC_300; | |
365 | } | |
95a2482a | 366 | } |
95f25efe | 367 | |
0322191e DA |
368 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
369 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
370 | if (val & ESDHC_VENDOR_SPEC_VSELECT) | |
371 | ret |= SDHCI_CTRL_VDD_180; | |
372 | ||
9d61c009 | 373 | if (esdhc_is_usdhc(imx_data)) { |
6e9fd28e DA |
374 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
375 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
376 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
377 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ | |
378 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
0322191e DA |
379 | } |
380 | ||
6e9fd28e DA |
381 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
382 | ret |= SDHCI_CTRL_EXEC_TUNING; | |
383 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) | |
384 | ret |= SDHCI_CTRL_TUNED_CLK; | |
385 | ||
0322191e DA |
386 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
387 | ||
388 | return ret; | |
389 | } | |
390 | ||
7dd109ef DA |
391 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
392 | if (esdhc_is_usdhc(imx_data)) { | |
393 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
394 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; | |
395 | /* Swap AC23 bit */ | |
396 | if (m & ESDHC_MIX_CTRL_AC23EN) { | |
397 | ret &= ~ESDHC_MIX_CTRL_AC23EN; | |
398 | ret |= SDHCI_TRNS_AUTO_CMD23; | |
399 | } | |
400 | } else { | |
401 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); | |
402 | } | |
403 | ||
404 | return ret; | |
405 | } | |
406 | ||
95f25efe WS |
407 | return readw(host->ioaddr + reg); |
408 | } | |
409 | ||
410 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |
411 | { | |
412 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
e149860d | 413 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
0322191e | 414 | u32 new_val = 0; |
95f25efe WS |
415 | |
416 | switch (reg) { | |
0322191e DA |
417 | case SDHCI_CLOCK_CONTROL: |
418 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
419 | if (val & SDHCI_CLOCK_CARD_EN) | |
420 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
421 | else | |
422 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
eeed7026 | 423 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
0322191e DA |
424 | return; |
425 | case SDHCI_HOST_CONTROL2: | |
426 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
427 | if (val & SDHCI_CTRL_VDD_180) | |
428 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; | |
429 | else | |
430 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; | |
431 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | |
6e9fd28e DA |
432 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
433 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
434 | if (val & SDHCI_CTRL_TUNED_CLK) | |
435 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
436 | else | |
437 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
438 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); | |
439 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
440 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
441 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
8b2bb0ad DA |
442 | if (val & SDHCI_CTRL_TUNED_CLK) { |
443 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
444 | } else { | |
445 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
446 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; | |
447 | } | |
448 | ||
6e9fd28e | 449 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
6e9fd28e DA |
450 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
451 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; | |
452 | } else { | |
6e9fd28e | 453 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
6e9fd28e DA |
454 | } |
455 | ||
6e9fd28e DA |
456 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
457 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
458 | } | |
0322191e | 459 | return; |
95f25efe | 460 | case SDHCI_TRANSFER_MODE: |
f47c4bbf | 461 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
462 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
463 | && (host->cmd->data->blocks > 1) | |
464 | && (host->cmd->data->flags & MMC_DATA_READ)) { | |
465 | u32 v; | |
60bf6396 SG |
466 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
467 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
468 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 | 469 | } |
69f54698 | 470 | |
9d61c009 | 471 | if (esdhc_is_usdhc(imx_data)) { |
69f54698 | 472 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
2a15f981 SG |
473 | /* Swap AC23 bit */ |
474 | if (val & SDHCI_TRNS_AUTO_CMD23) { | |
475 | val &= ~SDHCI_TRNS_AUTO_CMD23; | |
476 | val |= ESDHC_MIX_CTRL_AC23EN; | |
477 | } | |
478 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); | |
69f54698 SG |
479 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
480 | } else { | |
481 | /* | |
482 | * Postpone this write, we must do it together with a | |
483 | * command write that is down below. | |
484 | */ | |
485 | imx_data->scratchpad = val; | |
486 | } | |
95f25efe WS |
487 | return; |
488 | case SDHCI_COMMAND: | |
361b8482 | 489 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
58ac8177 | 490 | val |= SDHCI_CMD_ABORTCMD; |
95a2482a | 491 | |
361b8482 | 492 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
f47c4bbf | 493 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
361b8482 LS |
494 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
495 | ||
9d61c009 | 496 | if (esdhc_is_usdhc(imx_data)) |
95a2482a SG |
497 | writel(val << 16, |
498 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
69f54698 | 499 | else |
95a2482a SG |
500 | writel(val << 16 | imx_data->scratchpad, |
501 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
95f25efe WS |
502 | return; |
503 | case SDHCI_BLOCK_SIZE: | |
504 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
505 | break; | |
506 | } | |
507 | esdhc_clrset_le(host, 0xffff, val, reg); | |
508 | } | |
509 | ||
510 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) | |
511 | { | |
9a0985b7 WC |
512 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
513 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
95f25efe | 514 | u32 new_val; |
af51079e | 515 | u32 mask; |
95f25efe WS |
516 | |
517 | switch (reg) { | |
518 | case SDHCI_POWER_CONTROL: | |
519 | /* | |
520 | * FSL put some DMA bits here | |
521 | * If your board has a regulator, code should be here | |
522 | */ | |
523 | return; | |
524 | case SDHCI_HOST_CONTROL: | |
6b40d182 | 525 | /* FSL messed up here, so we need to manually compose it. */ |
af51079e | 526 | new_val = val & SDHCI_CTRL_LED; |
7122bbb0 | 527 | /* ensure the endianness */ |
95f25efe | 528 | new_val |= ESDHC_HOST_CONTROL_LE; |
9a0985b7 WC |
529 | /* bits 8&9 are reserved on mx25 */ |
530 | if (!is_imx25_esdhc(imx_data)) { | |
531 | /* DMA mode bits are shifted */ | |
532 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; | |
533 | } | |
95f25efe | 534 | |
af51079e SH |
535 | /* |
536 | * Do not touch buswidth bits here. This is done in | |
537 | * esdhc_pltfm_bus_width. | |
f6825748 MF |
538 | * Do not touch the D3CD bit either which is used for the |
539 | * SDIO interrupt errata workaround. | |
af51079e | 540 | */ |
f6825748 | 541 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
af51079e SH |
542 | |
543 | esdhc_clrset_le(host, mask, new_val, reg); | |
95f25efe WS |
544 | return; |
545 | } | |
546 | esdhc_clrset_le(host, 0xff, val, reg); | |
913413c3 SG |
547 | |
548 | /* | |
549 | * The esdhc has a design violation to SDHC spec which tells | |
550 | * that software reset should not affect card detection circuit. | |
551 | * But esdhc clears its SYSCTL register bits [0..2] during the | |
552 | * software reset. This will stop those clocks that card detection | |
553 | * circuit relies on. To work around it, we turn the clocks on back | |
554 | * to keep card detection circuit functional. | |
555 | */ | |
58c8c4fb | 556 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
913413c3 | 557 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
58c8c4fb SG |
558 | /* |
559 | * The reset on usdhc fails to clear MIX_CTRL register. | |
560 | * Do it manually here. | |
561 | */ | |
de5bdbff | 562 | if (esdhc_is_usdhc(imx_data)) { |
d131a71c DA |
563 | /* the tuning bits should be kept during reset */ |
564 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
565 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, | |
566 | host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff DA |
567 | imx_data->is_ddr = 0; |
568 | } | |
58c8c4fb | 569 | } |
95f25efe WS |
570 | } |
571 | ||
0ddf03c9 LS |
572 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
573 | { | |
574 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
575 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
576 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
577 | ||
a974862f | 578 | if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) |
0ddf03c9 LS |
579 | return boarddata->f_max; |
580 | else | |
a974862f | 581 | return pltfm_host->clock; |
0ddf03c9 LS |
582 | } |
583 | ||
95f25efe WS |
584 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
585 | { | |
586 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
587 | ||
a974862f | 588 | return pltfm_host->clock / 256 / 16; |
95f25efe WS |
589 | } |
590 | ||
8ba9580a LS |
591 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
592 | unsigned int clock) | |
593 | { | |
594 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
fed2f6e2 | 595 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
a974862f | 596 | unsigned int host_clock = pltfm_host->clock; |
d31fc00a DA |
597 | int pre_div = 2; |
598 | int div = 1; | |
fed2f6e2 | 599 | u32 temp, val; |
d31fc00a | 600 | |
fed2f6e2 | 601 | if (clock == 0) { |
1650d0c7 RK |
602 | host->mmc->actual_clock = 0; |
603 | ||
9d61c009 | 604 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
605 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
606 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
607 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
608 | } | |
373073ef | 609 | return; |
fed2f6e2 | 610 | } |
d31fc00a | 611 | |
de5bdbff | 612 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
5f7886c5 DA |
613 | pre_div = 1; |
614 | ||
d31fc00a DA |
615 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
616 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
617 | | ESDHC_CLOCK_MASK); | |
618 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
619 | ||
620 | while (host_clock / pre_div / 16 > clock && pre_div < 256) | |
621 | pre_div *= 2; | |
622 | ||
623 | while (host_clock / pre_div / div > clock && div < 16) | |
624 | div++; | |
625 | ||
e76b8559 | 626 | host->mmc->actual_clock = host_clock / pre_div / div; |
d31fc00a | 627 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
e76b8559 | 628 | clock, host->mmc->actual_clock); |
d31fc00a | 629 | |
de5bdbff DA |
630 | if (imx_data->is_ddr) |
631 | pre_div >>= 2; | |
632 | else | |
633 | pre_div >>= 1; | |
d31fc00a DA |
634 | div--; |
635 | ||
636 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | |
637 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
638 | | (div << ESDHC_DIVIDER_SHIFT) | |
639 | | (pre_div << ESDHC_PREDIV_SHIFT)); | |
640 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
fed2f6e2 | 641 | |
9d61c009 | 642 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
643 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
644 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
645 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
646 | } | |
647 | ||
d31fc00a | 648 | mdelay(1); |
8ba9580a LS |
649 | } |
650 | ||
913413c3 SG |
651 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
652 | { | |
842afc02 SG |
653 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
654 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
655 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
913413c3 SG |
656 | |
657 | switch (boarddata->wp_type) { | |
658 | case ESDHC_WP_GPIO: | |
fbe5fdd1 | 659 | return mmc_gpio_get_ro(host->mmc); |
913413c3 SG |
660 | case ESDHC_WP_CONTROLLER: |
661 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
662 | SDHCI_WRITE_PROTECT); | |
663 | case ESDHC_WP_NONE: | |
664 | break; | |
665 | } | |
666 | ||
667 | return -ENOSYS; | |
668 | } | |
669 | ||
2317f56c | 670 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
af51079e SH |
671 | { |
672 | u32 ctrl; | |
673 | ||
674 | switch (width) { | |
675 | case MMC_BUS_WIDTH_8: | |
676 | ctrl = ESDHC_CTRL_8BITBUS; | |
677 | break; | |
678 | case MMC_BUS_WIDTH_4: | |
679 | ctrl = ESDHC_CTRL_4BITBUS; | |
680 | break; | |
681 | default: | |
682 | ctrl = 0; | |
683 | break; | |
684 | } | |
685 | ||
686 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | |
687 | SDHCI_HOST_CONTROL); | |
af51079e SH |
688 | } |
689 | ||
0322191e DA |
690 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
691 | { | |
692 | u32 reg; | |
693 | ||
694 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ | |
695 | mdelay(1); | |
696 | ||
697 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
698 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | | |
699 | ESDHC_MIX_CTRL_FBCLK_SEL; | |
700 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
701 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
702 | dev_dbg(mmc_dev(host->mmc), | |
703 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", | |
704 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); | |
705 | } | |
706 | ||
0322191e DA |
707 | static void esdhc_post_tuning(struct sdhci_host *host) |
708 | { | |
709 | u32 reg; | |
710 | ||
711 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
712 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; | |
713 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
714 | } | |
715 | ||
716 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |
717 | { | |
718 | int min, max, avg, ret; | |
719 | ||
720 | /* find the mininum delay first which can pass tuning */ | |
721 | min = ESDHC_TUNE_CTRL_MIN; | |
722 | while (min < ESDHC_TUNE_CTRL_MAX) { | |
723 | esdhc_prepare_tuning(host, min); | |
d1785326 | 724 | if (!mmc_send_tuning(host->mmc)) |
0322191e DA |
725 | break; |
726 | min += ESDHC_TUNE_CTRL_STEP; | |
727 | } | |
728 | ||
729 | /* find the maxinum delay which can not pass tuning */ | |
730 | max = min + ESDHC_TUNE_CTRL_STEP; | |
731 | while (max < ESDHC_TUNE_CTRL_MAX) { | |
732 | esdhc_prepare_tuning(host, max); | |
d1785326 | 733 | if (mmc_send_tuning(host->mmc)) { |
0322191e DA |
734 | max -= ESDHC_TUNE_CTRL_STEP; |
735 | break; | |
736 | } | |
737 | max += ESDHC_TUNE_CTRL_STEP; | |
738 | } | |
739 | ||
740 | /* use average delay to get the best timing */ | |
741 | avg = (min + max) / 2; | |
742 | esdhc_prepare_tuning(host, avg); | |
d1785326 | 743 | ret = mmc_send_tuning(host->mmc); |
0322191e DA |
744 | esdhc_post_tuning(host); |
745 | ||
746 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", | |
747 | ret ? "failed" : "passed", avg, ret); | |
748 | ||
749 | return ret; | |
750 | } | |
751 | ||
ad93220d DA |
752 | static int esdhc_change_pinstate(struct sdhci_host *host, |
753 | unsigned int uhs) | |
754 | { | |
755 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
756 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
757 | struct pinctrl_state *pinctrl; | |
758 | ||
759 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); | |
760 | ||
761 | if (IS_ERR(imx_data->pinctrl) || | |
762 | IS_ERR(imx_data->pins_default) || | |
763 | IS_ERR(imx_data->pins_100mhz) || | |
764 | IS_ERR(imx_data->pins_200mhz)) | |
765 | return -EINVAL; | |
766 | ||
767 | switch (uhs) { | |
768 | case MMC_TIMING_UHS_SDR50: | |
769 | pinctrl = imx_data->pins_100mhz; | |
770 | break; | |
771 | case MMC_TIMING_UHS_SDR104: | |
429a5b45 | 772 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
773 | pinctrl = imx_data->pins_200mhz; |
774 | break; | |
775 | default: | |
776 | /* back to default state for other legacy timing */ | |
777 | pinctrl = imx_data->pins_default; | |
778 | } | |
779 | ||
780 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); | |
781 | } | |
782 | ||
850a29b8 | 783 | static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
ad93220d DA |
784 | { |
785 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
786 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
602519b2 | 787 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
ad93220d | 788 | |
850a29b8 | 789 | switch (timing) { |
ad93220d | 790 | case MMC_TIMING_UHS_SDR12: |
ad93220d | 791 | case MMC_TIMING_UHS_SDR25: |
ad93220d | 792 | case MMC_TIMING_UHS_SDR50: |
ad93220d | 793 | case MMC_TIMING_UHS_SDR104: |
429a5b45 | 794 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
795 | break; |
796 | case MMC_TIMING_UHS_DDR50: | |
69f5bf38 | 797 | case MMC_TIMING_MMC_DDR52: |
de5bdbff DA |
798 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | |
799 | ESDHC_MIX_CTRL_DDREN, | |
800 | host->ioaddr + ESDHC_MIX_CTRL); | |
801 | imx_data->is_ddr = 1; | |
602519b2 DA |
802 | if (boarddata->delay_line) { |
803 | u32 v; | |
804 | v = boarddata->delay_line << | |
805 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | | |
806 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); | |
807 | if (is_imx53_esdhc(imx_data)) | |
808 | v <<= 1; | |
809 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); | |
810 | } | |
ad93220d DA |
811 | break; |
812 | } | |
813 | ||
850a29b8 | 814 | esdhc_change_pinstate(host, timing); |
ad93220d DA |
815 | } |
816 | ||
0718e59a RK |
817 | static void esdhc_reset(struct sdhci_host *host, u8 mask) |
818 | { | |
819 | sdhci_reset(host, mask); | |
820 | ||
821 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
822 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
823 | } | |
824 | ||
10fd0ad9 AD |
825 | static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) |
826 | { | |
827 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
828 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
829 | ||
830 | return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; | |
831 | } | |
832 | ||
e33eb8e2 AD |
833 | static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
834 | { | |
835 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
836 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
837 | ||
838 | /* use maximum timeout counter */ | |
839 | sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, | |
840 | SDHCI_TIMEOUT_CONTROL); | |
841 | } | |
842 | ||
6e9fd28e | 843 | static struct sdhci_ops sdhci_esdhc_ops = { |
e149860d | 844 | .read_l = esdhc_readl_le, |
0c6d49ce | 845 | .read_w = esdhc_readw_le, |
e149860d | 846 | .write_l = esdhc_writel_le, |
0c6d49ce WS |
847 | .write_w = esdhc_writew_le, |
848 | .write_b = esdhc_writeb_le, | |
8ba9580a | 849 | .set_clock = esdhc_pltfm_set_clock, |
0ddf03c9 | 850 | .get_max_clock = esdhc_pltfm_get_max_clock, |
0c6d49ce | 851 | .get_min_clock = esdhc_pltfm_get_min_clock, |
10fd0ad9 | 852 | .get_max_timeout_count = esdhc_get_max_timeout_count, |
913413c3 | 853 | .get_ro = esdhc_pltfm_get_ro, |
e33eb8e2 | 854 | .set_timeout = esdhc_set_timeout, |
2317f56c | 855 | .set_bus_width = esdhc_pltfm_set_bus_width, |
ad93220d | 856 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
0718e59a | 857 | .reset = esdhc_reset, |
0c6d49ce WS |
858 | }; |
859 | ||
1db5eebf | 860 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
97e4ba6a RZ |
861 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
862 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
863 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
85d6509d | 864 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
85d6509d SG |
865 | .ops = &sdhci_esdhc_ops, |
866 | }; | |
867 | ||
abfafc2d | 868 | #ifdef CONFIG_OF |
c3be1efd | 869 | static int |
abfafc2d | 870 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
07bf2b54 | 871 | struct sdhci_host *host, |
abfafc2d SG |
872 | struct esdhc_platform_data *boarddata) |
873 | { | |
874 | struct device_node *np = pdev->dev.of_node; | |
875 | ||
876 | if (!np) | |
877 | return -ENODEV; | |
878 | ||
7f217794 | 879 | if (of_get_property(np, "non-removable", NULL)) |
abfafc2d SG |
880 | boarddata->cd_type = ESDHC_CD_PERMANENT; |
881 | ||
882 | if (of_get_property(np, "fsl,cd-controller", NULL)) | |
883 | boarddata->cd_type = ESDHC_CD_CONTROLLER; | |
884 | ||
885 | if (of_get_property(np, "fsl,wp-controller", NULL)) | |
886 | boarddata->wp_type = ESDHC_WP_CONTROLLER; | |
887 | ||
888 | boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); | |
889 | if (gpio_is_valid(boarddata->cd_gpio)) | |
890 | boarddata->cd_type = ESDHC_CD_GPIO; | |
891 | ||
892 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
893 | if (gpio_is_valid(boarddata->wp_gpio)) | |
894 | boarddata->wp_type = ESDHC_WP_GPIO; | |
895 | ||
af51079e SH |
896 | of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); |
897 | ||
0ddf03c9 LS |
898 | of_property_read_u32(np, "max-frequency", &boarddata->f_max); |
899 | ||
ad93220d DA |
900 | if (of_find_property(np, "no-1-8-v", NULL)) |
901 | boarddata->support_vsel = false; | |
902 | else | |
903 | boarddata->support_vsel = true; | |
904 | ||
602519b2 DA |
905 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
906 | boarddata->delay_line = 0; | |
907 | ||
07bf2b54 SH |
908 | mmc_of_parse_voltage(np, &host->ocr_mask); |
909 | ||
15064119 FE |
910 | /* call to generic mmc_of_parse to support additional capabilities */ |
911 | return mmc_of_parse(host->mmc); | |
abfafc2d SG |
912 | } |
913 | #else | |
914 | static inline int | |
915 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, | |
07bf2b54 | 916 | struct sdhci_host *host, |
abfafc2d SG |
917 | struct esdhc_platform_data *boarddata) |
918 | { | |
919 | return -ENODEV; | |
920 | } | |
921 | #endif | |
922 | ||
c3be1efd | 923 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
95f25efe | 924 | { |
abfafc2d SG |
925 | const struct of_device_id *of_id = |
926 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); | |
85d6509d SG |
927 | struct sdhci_pltfm_host *pltfm_host; |
928 | struct sdhci_host *host; | |
929 | struct esdhc_platform_data *boarddata; | |
0c6d49ce | 930 | int err; |
e149860d | 931 | struct pltfm_imx_data *imx_data; |
7ccddeb0 | 932 | bool dt = true; |
95f25efe | 933 | |
0e748234 | 934 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); |
85d6509d SG |
935 | if (IS_ERR(host)) |
936 | return PTR_ERR(host); | |
937 | ||
938 | pltfm_host = sdhci_priv(host); | |
939 | ||
e3af31c6 | 940 | imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); |
abfafc2d SG |
941 | if (!imx_data) { |
942 | err = -ENOMEM; | |
e3af31c6 | 943 | goto free_sdhci; |
abfafc2d | 944 | } |
57ed3314 | 945 | |
f47c4bbf SG |
946 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
947 | pdev->id_entry->driver_data; | |
85d6509d SG |
948 | pltfm_host->priv = imx_data; |
949 | ||
52dac615 SH |
950 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
951 | if (IS_ERR(imx_data->clk_ipg)) { | |
952 | err = PTR_ERR(imx_data->clk_ipg); | |
e3af31c6 | 953 | goto free_sdhci; |
95f25efe | 954 | } |
52dac615 SH |
955 | |
956 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
957 | if (IS_ERR(imx_data->clk_ahb)) { | |
958 | err = PTR_ERR(imx_data->clk_ahb); | |
e3af31c6 | 959 | goto free_sdhci; |
52dac615 SH |
960 | } |
961 | ||
962 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); | |
963 | if (IS_ERR(imx_data->clk_per)) { | |
964 | err = PTR_ERR(imx_data->clk_per); | |
e3af31c6 | 965 | goto free_sdhci; |
52dac615 SH |
966 | } |
967 | ||
968 | pltfm_host->clk = imx_data->clk_per; | |
a974862f | 969 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
52dac615 SH |
970 | clk_prepare_enable(imx_data->clk_per); |
971 | clk_prepare_enable(imx_data->clk_ipg); | |
972 | clk_prepare_enable(imx_data->clk_ahb); | |
95f25efe | 973 | |
ad93220d | 974 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
e62d8b8f DA |
975 | if (IS_ERR(imx_data->pinctrl)) { |
976 | err = PTR_ERR(imx_data->pinctrl); | |
e3af31c6 | 977 | goto disable_clk; |
e62d8b8f DA |
978 | } |
979 | ||
ad93220d DA |
980 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
981 | PINCTRL_STATE_DEFAULT); | |
cd529af7 DB |
982 | if (IS_ERR(imx_data->pins_default)) |
983 | dev_warn(mmc_dev(host->mmc), "could not get default state\n"); | |
ad93220d | 984 | |
b8915282 | 985 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
37865fe9 | 986 | |
f47c4bbf | 987 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
0c6d49ce | 988 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
97e4ba6a RZ |
989 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
990 | | SDHCI_QUIRK_BROKEN_ADMA; | |
0c6d49ce | 991 | |
f750ba9b SG |
992 | /* |
993 | * The imx6q ROM code will change the default watermark level setting | |
994 | * to something insane. Change it back here. | |
995 | */ | |
69ed60e0 | 996 | if (esdhc_is_usdhc(imx_data)) { |
60bf6396 | 997 | writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); |
69ed60e0 | 998 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
e2997c94 | 999 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
18094430 DA |
1000 | |
1001 | /* | |
1002 | * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL | |
1003 | * TO1.1, it's harmless for MX6SL | |
1004 | */ | |
1005 | writel(readl(host->ioaddr + 0x6c) | BIT(7), | |
1006 | host->ioaddr + 0x6c); | |
69ed60e0 | 1007 | } |
f750ba9b | 1008 | |
6e9fd28e DA |
1009 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
1010 | sdhci_esdhc_ops.platform_execute_tuning = | |
1011 | esdhc_executing_tuning; | |
8b2bb0ad DA |
1012 | |
1013 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
1014 | writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | | |
1015 | ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, | |
1016 | host->ioaddr + ESDHC_TUNING_CTRL); | |
1017 | ||
18094430 DA |
1018 | if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) |
1019 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
1020 | ||
842afc02 | 1021 | boarddata = &imx_data->boarddata; |
07bf2b54 | 1022 | if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) { |
abfafc2d SG |
1023 | if (!host->mmc->parent->platform_data) { |
1024 | dev_err(mmc_dev(host->mmc), "no board data!\n"); | |
1025 | err = -EINVAL; | |
e3af31c6 | 1026 | goto disable_clk; |
abfafc2d SG |
1027 | } |
1028 | imx_data->boarddata = *((struct esdhc_platform_data *) | |
1029 | host->mmc->parent->platform_data); | |
7ccddeb0 FE |
1030 | dt = false; |
1031 | } | |
1032 | /* write_protect */ | |
1033 | if (boarddata->wp_type == ESDHC_WP_GPIO && !dt) { | |
1034 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); | |
1035 | if (err) { | |
1036 | dev_err(mmc_dev(host->mmc), | |
1037 | "failed to request write-protect gpio!\n"); | |
1038 | goto disable_clk; | |
1039 | } | |
1040 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; | |
abfafc2d | 1041 | } |
913413c3 | 1042 | |
913413c3 | 1043 | /* card_detect */ |
7ccddeb0 FE |
1044 | switch (boarddata->cd_type) { |
1045 | case ESDHC_CD_GPIO: | |
1046 | if (dt) | |
1047 | break; | |
1048 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); | |
1049 | if (err) { | |
1050 | dev_err(mmc_dev(host->mmc), | |
1051 | "failed to request card-detect gpio!\n"); | |
1052 | goto disable_clk; | |
1053 | } | |
1054 | /* fall through */ | |
1055 | ||
1056 | case ESDHC_CD_CONTROLLER: | |
1057 | /* we have a working card_detect back */ | |
7e29c306 | 1058 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
7ccddeb0 FE |
1059 | break; |
1060 | ||
1061 | case ESDHC_CD_PERMANENT: | |
1062 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; | |
1063 | break; | |
1064 | ||
1065 | case ESDHC_CD_NONE: | |
1066 | break; | |
1067 | } | |
16a790bc | 1068 | |
af51079e SH |
1069 | switch (boarddata->max_bus_width) { |
1070 | case 8: | |
1071 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; | |
1072 | break; | |
1073 | case 4: | |
1074 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1075 | break; | |
1076 | case 1: | |
1077 | default: | |
1078 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; | |
1079 | break; | |
1080 | } | |
1081 | ||
ad93220d | 1082 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
cd529af7 DB |
1083 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && |
1084 | !IS_ERR(imx_data->pins_default)) { | |
ad93220d DA |
1085 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, |
1086 | ESDHC_PINCTRL_STATE_100MHZ); | |
1087 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
1088 | ESDHC_PINCTRL_STATE_200MHZ); | |
1089 | if (IS_ERR(imx_data->pins_100mhz) || | |
1090 | IS_ERR(imx_data->pins_200mhz)) { | |
1091 | dev_warn(mmc_dev(host->mmc), | |
1092 | "could not get ultra high speed state, work on normal mode\n"); | |
1093 | /* fall back to not support uhs by specify no 1.8v quirk */ | |
1094 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1095 | } | |
1096 | } else { | |
1097 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1098 | } | |
1099 | ||
85d6509d SG |
1100 | err = sdhci_add_host(host); |
1101 | if (err) | |
e3af31c6 | 1102 | goto disable_clk; |
85d6509d | 1103 | |
89d7e5c1 | 1104 | pm_runtime_set_active(&pdev->dev); |
89d7e5c1 DA |
1105 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1106 | pm_runtime_use_autosuspend(&pdev->dev); | |
1107 | pm_suspend_ignore_children(&pdev->dev, 1); | |
77903c01 | 1108 | pm_runtime_enable(&pdev->dev); |
89d7e5c1 | 1109 | |
95f25efe | 1110 | return 0; |
7e29c306 | 1111 | |
e3af31c6 | 1112 | disable_clk: |
52dac615 SH |
1113 | clk_disable_unprepare(imx_data->clk_per); |
1114 | clk_disable_unprepare(imx_data->clk_ipg); | |
1115 | clk_disable_unprepare(imx_data->clk_ahb); | |
e3af31c6 | 1116 | free_sdhci: |
85d6509d SG |
1117 | sdhci_pltfm_free(pdev); |
1118 | return err; | |
95f25efe WS |
1119 | } |
1120 | ||
6e0ee714 | 1121 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
95f25efe | 1122 | { |
85d6509d | 1123 | struct sdhci_host *host = platform_get_drvdata(pdev); |
95f25efe | 1124 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
e149860d | 1125 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
85d6509d SG |
1126 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
1127 | ||
0b414368 | 1128 | pm_runtime_get_sync(&pdev->dev); |
89d7e5c1 | 1129 | pm_runtime_disable(&pdev->dev); |
0b414368 | 1130 | pm_runtime_put_noidle(&pdev->dev); |
89d7e5c1 | 1131 | |
0b414368 UH |
1132 | sdhci_remove_host(host, dead); |
1133 | ||
1134 | clk_disable_unprepare(imx_data->clk_per); | |
1135 | clk_disable_unprepare(imx_data->clk_ipg); | |
1136 | clk_disable_unprepare(imx_data->clk_ahb); | |
52dac615 | 1137 | |
85d6509d SG |
1138 | sdhci_pltfm_free(pdev); |
1139 | ||
1140 | return 0; | |
95f25efe WS |
1141 | } |
1142 | ||
162d6f98 | 1143 | #ifdef CONFIG_PM |
89d7e5c1 DA |
1144 | static int sdhci_esdhc_runtime_suspend(struct device *dev) |
1145 | { | |
1146 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1147 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1148 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1149 | int ret; | |
1150 | ||
1151 | ret = sdhci_runtime_suspend_host(host); | |
1152 | ||
be138554 RK |
1153 | if (!sdhci_sdio_irq_enabled(host)) { |
1154 | clk_disable_unprepare(imx_data->clk_per); | |
1155 | clk_disable_unprepare(imx_data->clk_ipg); | |
1156 | } | |
89d7e5c1 DA |
1157 | clk_disable_unprepare(imx_data->clk_ahb); |
1158 | ||
1159 | return ret; | |
1160 | } | |
1161 | ||
1162 | static int sdhci_esdhc_runtime_resume(struct device *dev) | |
1163 | { | |
1164 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1165 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1166 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1167 | ||
be138554 RK |
1168 | if (!sdhci_sdio_irq_enabled(host)) { |
1169 | clk_prepare_enable(imx_data->clk_per); | |
1170 | clk_prepare_enable(imx_data->clk_ipg); | |
1171 | } | |
89d7e5c1 DA |
1172 | clk_prepare_enable(imx_data->clk_ahb); |
1173 | ||
1174 | return sdhci_runtime_resume_host(host); | |
1175 | } | |
1176 | #endif | |
1177 | ||
1178 | static const struct dev_pm_ops sdhci_esdhc_pmops = { | |
1179 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) | |
1180 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, | |
1181 | sdhci_esdhc_runtime_resume, NULL) | |
1182 | }; | |
1183 | ||
85d6509d SG |
1184 | static struct platform_driver sdhci_esdhc_imx_driver = { |
1185 | .driver = { | |
1186 | .name = "sdhci-esdhc-imx", | |
abfafc2d | 1187 | .of_match_table = imx_esdhc_dt_ids, |
89d7e5c1 | 1188 | .pm = &sdhci_esdhc_pmops, |
85d6509d | 1189 | }, |
57ed3314 | 1190 | .id_table = imx_esdhc_devtype, |
85d6509d | 1191 | .probe = sdhci_esdhc_imx_probe, |
0433c143 | 1192 | .remove = sdhci_esdhc_imx_remove, |
95f25efe | 1193 | }; |
85d6509d | 1194 | |
d1f81a64 | 1195 | module_platform_driver(sdhci_esdhc_imx_driver); |
85d6509d SG |
1196 | |
1197 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); | |
035ff831 | 1198 | MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); |
85d6509d | 1199 | MODULE_LICENSE("GPL v2"); |