Commit | Line | Data |
---|---|---|
95f25efe WS |
1 | /* |
2 | * Freescale eSDHC i.MX controller driver for the platform bus. | |
3 | * | |
4 | * derived from the OF-version. | |
5 | * | |
6 | * Copyright (c) 2010 Pengutronix e.K. | |
7 | * Author: Wolfram Sang <w.sang@pengutronix.de> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
0c6d49ce | 18 | #include <linux/gpio.h> |
66506f76 | 19 | #include <linux/module.h> |
e149860d | 20 | #include <linux/slab.h> |
95f25efe | 21 | #include <linux/mmc/host.h> |
58ac8177 RZ |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> | |
fbe5fdd1 | 24 | #include <linux/mmc/slot-gpio.h> |
abfafc2d SG |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/of_gpio.h> | |
e62d8b8f | 28 | #include <linux/pinctrl/consumer.h> |
82906b13 | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
89d7e5c1 | 30 | #include <linux/pm_runtime.h> |
95f25efe WS |
31 | #include "sdhci-pltfm.h" |
32 | #include "sdhci-esdhc.h" | |
33 | ||
60bf6396 | 34 | #define ESDHC_CTRL_D3CD 0x08 |
58ac8177 | 35 | /* VENDOR SPEC register */ |
60bf6396 SG |
36 | #define ESDHC_VENDOR_SPEC 0xc0 |
37 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) | |
0322191e | 38 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
fed2f6e2 | 39 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
60bf6396 SG |
40 | #define ESDHC_WTMK_LVL 0x44 |
41 | #define ESDHC_MIX_CTRL 0x48 | |
de5bdbff | 42 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
2a15f981 | 43 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
0322191e DA |
44 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
45 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) | |
46 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) | |
2a15f981 SG |
47 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
48 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 | |
d131a71c DA |
49 | /* Tuning bits */ |
50 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 | |
58ac8177 | 51 | |
602519b2 DA |
52 | /* dll control register */ |
53 | #define ESDHC_DLL_CTRL 0x60 | |
54 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 | |
55 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 | |
56 | ||
0322191e DA |
57 | /* tune control register */ |
58 | #define ESDHC_TUNE_CTRL_STATUS 0x68 | |
59 | #define ESDHC_TUNE_CTRL_STEP 1 | |
60 | #define ESDHC_TUNE_CTRL_MIN 0 | |
61 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) | |
62 | ||
6e9fd28e DA |
63 | #define ESDHC_TUNING_CTRL 0xcc |
64 | #define ESDHC_STD_TUNING_EN (1 << 24) | |
65 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ | |
66 | #define ESDHC_TUNING_START_TAP 0x1 | |
67 | ||
0322191e DA |
68 | #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64 |
69 | ||
ad93220d DA |
70 | /* pinctrl state */ |
71 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" | |
72 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" | |
73 | ||
af51079e SH |
74 | /* |
75 | * Our interpretation of the SDHCI_HOST_CONTROL register | |
76 | */ | |
77 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | |
78 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
79 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
80 | ||
97e4ba6a RZ |
81 | /* |
82 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: | |
83 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, | |
84 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. | |
85 | * Define this macro DMA error INT for fsl eSDHC | |
86 | */ | |
60bf6396 | 87 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
97e4ba6a | 88 | |
58ac8177 RZ |
89 | /* |
90 | * The CMDTYPE of the CMD register (offset 0xE) should be set to | |
91 | * "11" when the STOP CMD12 is issued on imx53 to abort one | |
92 | * open ended multi-blk IO. Otherwise the TC INT wouldn't | |
93 | * be generated. | |
94 | * In exact block transfer, the controller doesn't complete the | |
95 | * operations automatically as required at the end of the | |
96 | * transfer and remains on hold if the abort command is not sent. | |
97 | * As a result, the TC flag is not asserted and SW received timeout | |
98 | * exeception. Bit1 of Vendor Spec registor is used to fix it. | |
99 | */ | |
31fbb301 SG |
100 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
101 | /* | |
102 | * The flag enables the workaround for ESDHC errata ENGcm07207 which | |
103 | * affects i.MX25 and i.MX35. | |
104 | */ | |
105 | #define ESDHC_FLAG_ENGCM07207 BIT(2) | |
9d61c009 SG |
106 | /* |
107 | * The flag tells that the ESDHC controller is an USDHC block that is | |
108 | * integrated on the i.MX6 series. | |
109 | */ | |
110 | #define ESDHC_FLAG_USDHC BIT(3) | |
6e9fd28e DA |
111 | /* The IP supports manual tuning process */ |
112 | #define ESDHC_FLAG_MAN_TUNING BIT(4) | |
113 | /* The IP supports standard tuning process */ | |
114 | #define ESDHC_FLAG_STD_TUNING BIT(5) | |
115 | /* The IP has SDHCI_CAPABILITIES_1 register */ | |
116 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) | |
e149860d | 117 | |
f47c4bbf SG |
118 | struct esdhc_soc_data { |
119 | u32 flags; | |
120 | }; | |
121 | ||
122 | static struct esdhc_soc_data esdhc_imx25_data = { | |
123 | .flags = ESDHC_FLAG_ENGCM07207, | |
124 | }; | |
125 | ||
126 | static struct esdhc_soc_data esdhc_imx35_data = { | |
127 | .flags = ESDHC_FLAG_ENGCM07207, | |
128 | }; | |
129 | ||
130 | static struct esdhc_soc_data esdhc_imx51_data = { | |
131 | .flags = 0, | |
132 | }; | |
133 | ||
134 | static struct esdhc_soc_data esdhc_imx53_data = { | |
135 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, | |
136 | }; | |
137 | ||
138 | static struct esdhc_soc_data usdhc_imx6q_data = { | |
6e9fd28e DA |
139 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
140 | }; | |
141 | ||
142 | static struct esdhc_soc_data usdhc_imx6sl_data = { | |
143 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
144 | | ESDHC_FLAG_HAVE_CAP1, | |
57ed3314 SG |
145 | }; |
146 | ||
e149860d | 147 | struct pltfm_imx_data { |
e149860d | 148 | u32 scratchpad; |
e62d8b8f | 149 | struct pinctrl *pinctrl; |
ad93220d DA |
150 | struct pinctrl_state *pins_default; |
151 | struct pinctrl_state *pins_100mhz; | |
152 | struct pinctrl_state *pins_200mhz; | |
f47c4bbf | 153 | const struct esdhc_soc_data *socdata; |
842afc02 | 154 | struct esdhc_platform_data boarddata; |
52dac615 SH |
155 | struct clk *clk_ipg; |
156 | struct clk *clk_ahb; | |
157 | struct clk *clk_per; | |
361b8482 LS |
158 | enum { |
159 | NO_CMD_PENDING, /* no multiblock command pending*/ | |
160 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ | |
161 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ | |
162 | } multiblock_status; | |
0322191e | 163 | u32 uhs_mode; |
de5bdbff | 164 | u32 is_ddr; |
e149860d RZ |
165 | }; |
166 | ||
57ed3314 SG |
167 | static struct platform_device_id imx_esdhc_devtype[] = { |
168 | { | |
169 | .name = "sdhci-esdhc-imx25", | |
f47c4bbf | 170 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
57ed3314 SG |
171 | }, { |
172 | .name = "sdhci-esdhc-imx35", | |
f47c4bbf | 173 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
57ed3314 SG |
174 | }, { |
175 | .name = "sdhci-esdhc-imx51", | |
f47c4bbf | 176 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
57ed3314 SG |
177 | }, { |
178 | /* sentinel */ | |
179 | } | |
180 | }; | |
181 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); | |
182 | ||
abfafc2d | 183 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
f47c4bbf SG |
184 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
185 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, | |
186 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, | |
187 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, | |
6e9fd28e | 188 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
f47c4bbf | 189 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
abfafc2d SG |
190 | { /* sentinel */ } |
191 | }; | |
192 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); | |
193 | ||
57ed3314 SG |
194 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
195 | { | |
f47c4bbf | 196 | return data->socdata == &esdhc_imx25_data; |
57ed3314 SG |
197 | } |
198 | ||
199 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) | |
200 | { | |
f47c4bbf | 201 | return data->socdata == &esdhc_imx53_data; |
57ed3314 SG |
202 | } |
203 | ||
95a2482a SG |
204 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
205 | { | |
f47c4bbf | 206 | return data->socdata == &usdhc_imx6q_data; |
95a2482a SG |
207 | } |
208 | ||
9d61c009 SG |
209 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
210 | { | |
f47c4bbf | 211 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
9d61c009 SG |
212 | } |
213 | ||
95f25efe WS |
214 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
215 | { | |
216 | void __iomem *base = host->ioaddr + (reg & ~0x3); | |
217 | u32 shift = (reg & 0x3) * 8; | |
218 | ||
219 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); | |
220 | } | |
221 | ||
7e29c306 WS |
222 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
223 | { | |
361b8482 LS |
224 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
225 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
7e29c306 WS |
226 | u32 val = readl(host->ioaddr + reg); |
227 | ||
0322191e DA |
228 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
229 | u32 fsl_prss = val; | |
230 | /* save the least 20 bits */ | |
231 | val = fsl_prss & 0x000FFFFF; | |
232 | /* move dat[0-3] bits */ | |
233 | val |= (fsl_prss & 0x0F000000) >> 4; | |
234 | /* move cmd line bit */ | |
235 | val |= (fsl_prss & 0x00800000) << 1; | |
236 | } | |
237 | ||
97e4ba6a | 238 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
6b4fb671 DA |
239 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
240 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
241 | val &= 0xffff0000; | |
242 | ||
97e4ba6a RZ |
243 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
244 | * ADMA2 capability of esdhc, but this bit is messed up on | |
245 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they | |
246 | * don't actually support ADMA2). So set the BROKEN_ADMA | |
247 | * uirk on MX25/35 platforms. | |
248 | */ | |
249 | ||
250 | if (val & SDHCI_CAN_DO_ADMA1) { | |
251 | val &= ~SDHCI_CAN_DO_ADMA1; | |
252 | val |= SDHCI_CAN_DO_ADMA2; | |
253 | } | |
254 | } | |
255 | ||
6e9fd28e DA |
256 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
257 | if (esdhc_is_usdhc(imx_data)) { | |
258 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
259 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; | |
260 | else | |
261 | /* imx6q/dl does not have cap_1 register, fake one */ | |
262 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | |
888824bb DA |
263 | | SDHCI_SUPPORT_SDR50 |
264 | | SDHCI_USE_SDR50_TUNING; | |
6e9fd28e DA |
265 | } |
266 | } | |
0322191e | 267 | |
9d61c009 | 268 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
0322191e DA |
269 | val = 0; |
270 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; | |
271 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; | |
272 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; | |
273 | } | |
274 | ||
97e4ba6a | 275 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
60bf6396 SG |
276 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
277 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
97e4ba6a RZ |
278 | val |= SDHCI_INT_ADMA_ERROR; |
279 | } | |
361b8482 LS |
280 | |
281 | /* | |
282 | * mask off the interrupt we get in response to the manually | |
283 | * sent CMD12 | |
284 | */ | |
285 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && | |
286 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { | |
287 | val &= ~SDHCI_INT_RESPONSE; | |
288 | writel(SDHCI_INT_RESPONSE, host->ioaddr + | |
289 | SDHCI_INT_STATUS); | |
290 | imx_data->multiblock_status = NO_CMD_PENDING; | |
291 | } | |
97e4ba6a RZ |
292 | } |
293 | ||
7e29c306 WS |
294 | return val; |
295 | } | |
296 | ||
297 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) | |
298 | { | |
e149860d RZ |
299 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
300 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0d58864b TL |
301 | u32 data; |
302 | ||
303 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { | |
0d58864b TL |
304 | if (val & SDHCI_INT_CARD_INT) { |
305 | /* | |
306 | * Clear and then set D3CD bit to avoid missing the | |
307 | * card interrupt. This is a eSDHC controller problem | |
308 | * so we need to apply the following workaround: clear | |
309 | * and set D3CD bit will make eSDHC re-sample the card | |
310 | * interrupt. In case a card interrupt was lost, | |
311 | * re-sample it by the following steps. | |
312 | */ | |
313 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); | |
60bf6396 | 314 | data &= ~ESDHC_CTRL_D3CD; |
0d58864b | 315 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
60bf6396 | 316 | data |= ESDHC_CTRL_D3CD; |
0d58864b TL |
317 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
318 | } | |
319 | } | |
7e29c306 | 320 | |
f47c4bbf | 321 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
322 | && (reg == SDHCI_INT_STATUS) |
323 | && (val & SDHCI_INT_DATA_END))) { | |
324 | u32 v; | |
60bf6396 SG |
325 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
326 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
327 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
361b8482 LS |
328 | |
329 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) | |
330 | { | |
331 | /* send a manual CMD12 with RESPTYP=none */ | |
332 | data = MMC_STOP_TRANSMISSION << 24 | | |
333 | SDHCI_CMD_ABORTCMD << 16; | |
334 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); | |
335 | imx_data->multiblock_status = WAIT_FOR_INT; | |
336 | } | |
58ac8177 RZ |
337 | } |
338 | ||
97e4ba6a RZ |
339 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { |
340 | if (val & SDHCI_INT_ADMA_ERROR) { | |
341 | val &= ~SDHCI_INT_ADMA_ERROR; | |
60bf6396 | 342 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; |
97e4ba6a RZ |
343 | } |
344 | } | |
345 | ||
7e29c306 WS |
346 | writel(val, host->ioaddr + reg); |
347 | } | |
348 | ||
95f25efe WS |
349 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
350 | { | |
ef4d0888 SG |
351 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
352 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0322191e DA |
353 | u16 ret = 0; |
354 | u32 val; | |
ef4d0888 | 355 | |
95a2482a | 356 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
ef4d0888 | 357 | reg ^= 2; |
9d61c009 | 358 | if (esdhc_is_usdhc(imx_data)) { |
ef4d0888 SG |
359 | /* |
360 | * The usdhc register returns a wrong host version. | |
361 | * Correct it here. | |
362 | */ | |
363 | return SDHCI_SPEC_300; | |
364 | } | |
95a2482a | 365 | } |
95f25efe | 366 | |
0322191e DA |
367 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
368 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
369 | if (val & ESDHC_VENDOR_SPEC_VSELECT) | |
370 | ret |= SDHCI_CTRL_VDD_180; | |
371 | ||
9d61c009 | 372 | if (esdhc_is_usdhc(imx_data)) { |
6e9fd28e DA |
373 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
374 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
375 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
376 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ | |
377 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
0322191e DA |
378 | } |
379 | ||
6e9fd28e DA |
380 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
381 | ret |= SDHCI_CTRL_EXEC_TUNING; | |
382 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) | |
383 | ret |= SDHCI_CTRL_TUNED_CLK; | |
384 | ||
0322191e DA |
385 | ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); |
386 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | |
387 | ||
388 | return ret; | |
389 | } | |
390 | ||
7dd109ef DA |
391 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
392 | if (esdhc_is_usdhc(imx_data)) { | |
393 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
394 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; | |
395 | /* Swap AC23 bit */ | |
396 | if (m & ESDHC_MIX_CTRL_AC23EN) { | |
397 | ret &= ~ESDHC_MIX_CTRL_AC23EN; | |
398 | ret |= SDHCI_TRNS_AUTO_CMD23; | |
399 | } | |
400 | } else { | |
401 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); | |
402 | } | |
403 | ||
404 | return ret; | |
405 | } | |
406 | ||
95f25efe WS |
407 | return readw(host->ioaddr + reg); |
408 | } | |
409 | ||
410 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |
411 | { | |
412 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
e149860d | 413 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
0322191e | 414 | u32 new_val = 0; |
95f25efe WS |
415 | |
416 | switch (reg) { | |
0322191e DA |
417 | case SDHCI_CLOCK_CONTROL: |
418 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
419 | if (val & SDHCI_CLOCK_CARD_EN) | |
420 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
421 | else | |
422 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
423 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | |
424 | return; | |
425 | case SDHCI_HOST_CONTROL2: | |
426 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
427 | if (val & SDHCI_CTRL_VDD_180) | |
428 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; | |
429 | else | |
430 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; | |
431 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | |
432 | imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; | |
6e9fd28e DA |
433 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
434 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
435 | if (val & SDHCI_CTRL_TUNED_CLK) | |
436 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
437 | else | |
438 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
439 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); | |
440 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
441 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
442 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
8b2bb0ad DA |
443 | if (val & SDHCI_CTRL_TUNED_CLK) { |
444 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
445 | } else { | |
446 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
447 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; | |
448 | } | |
449 | ||
6e9fd28e | 450 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
6e9fd28e DA |
451 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
452 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; | |
453 | } else { | |
6e9fd28e | 454 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
6e9fd28e DA |
455 | } |
456 | ||
6e9fd28e DA |
457 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
458 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
459 | } | |
0322191e | 460 | return; |
95f25efe | 461 | case SDHCI_TRANSFER_MODE: |
f47c4bbf | 462 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
463 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
464 | && (host->cmd->data->blocks > 1) | |
465 | && (host->cmd->data->flags & MMC_DATA_READ)) { | |
466 | u32 v; | |
60bf6396 SG |
467 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
468 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
469 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 | 470 | } |
69f54698 | 471 | |
9d61c009 | 472 | if (esdhc_is_usdhc(imx_data)) { |
69f54698 | 473 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
2a15f981 SG |
474 | /* Swap AC23 bit */ |
475 | if (val & SDHCI_TRNS_AUTO_CMD23) { | |
476 | val &= ~SDHCI_TRNS_AUTO_CMD23; | |
477 | val |= ESDHC_MIX_CTRL_AC23EN; | |
478 | } | |
479 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); | |
69f54698 SG |
480 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
481 | } else { | |
482 | /* | |
483 | * Postpone this write, we must do it together with a | |
484 | * command write that is down below. | |
485 | */ | |
486 | imx_data->scratchpad = val; | |
487 | } | |
95f25efe WS |
488 | return; |
489 | case SDHCI_COMMAND: | |
361b8482 | 490 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
58ac8177 | 491 | val |= SDHCI_CMD_ABORTCMD; |
95a2482a | 492 | |
361b8482 | 493 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
f47c4bbf | 494 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
361b8482 LS |
495 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
496 | ||
9d61c009 | 497 | if (esdhc_is_usdhc(imx_data)) |
95a2482a SG |
498 | writel(val << 16, |
499 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
69f54698 | 500 | else |
95a2482a SG |
501 | writel(val << 16 | imx_data->scratchpad, |
502 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
95f25efe WS |
503 | return; |
504 | case SDHCI_BLOCK_SIZE: | |
505 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
506 | break; | |
507 | } | |
508 | esdhc_clrset_le(host, 0xffff, val, reg); | |
509 | } | |
510 | ||
511 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) | |
512 | { | |
9a0985b7 WC |
513 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
514 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
95f25efe | 515 | u32 new_val; |
af51079e | 516 | u32 mask; |
95f25efe WS |
517 | |
518 | switch (reg) { | |
519 | case SDHCI_POWER_CONTROL: | |
520 | /* | |
521 | * FSL put some DMA bits here | |
522 | * If your board has a regulator, code should be here | |
523 | */ | |
524 | return; | |
525 | case SDHCI_HOST_CONTROL: | |
6b40d182 | 526 | /* FSL messed up here, so we need to manually compose it. */ |
af51079e | 527 | new_val = val & SDHCI_CTRL_LED; |
7122bbb0 | 528 | /* ensure the endianness */ |
95f25efe | 529 | new_val |= ESDHC_HOST_CONTROL_LE; |
9a0985b7 WC |
530 | /* bits 8&9 are reserved on mx25 */ |
531 | if (!is_imx25_esdhc(imx_data)) { | |
532 | /* DMA mode bits are shifted */ | |
533 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; | |
534 | } | |
95f25efe | 535 | |
af51079e SH |
536 | /* |
537 | * Do not touch buswidth bits here. This is done in | |
538 | * esdhc_pltfm_bus_width. | |
f6825748 MF |
539 | * Do not touch the D3CD bit either which is used for the |
540 | * SDIO interrupt errata workaround. | |
af51079e | 541 | */ |
f6825748 | 542 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
af51079e SH |
543 | |
544 | esdhc_clrset_le(host, mask, new_val, reg); | |
95f25efe WS |
545 | return; |
546 | } | |
547 | esdhc_clrset_le(host, 0xff, val, reg); | |
913413c3 SG |
548 | |
549 | /* | |
550 | * The esdhc has a design violation to SDHC spec which tells | |
551 | * that software reset should not affect card detection circuit. | |
552 | * But esdhc clears its SYSCTL register bits [0..2] during the | |
553 | * software reset. This will stop those clocks that card detection | |
554 | * circuit relies on. To work around it, we turn the clocks on back | |
555 | * to keep card detection circuit functional. | |
556 | */ | |
58c8c4fb | 557 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
913413c3 | 558 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
58c8c4fb SG |
559 | /* |
560 | * The reset on usdhc fails to clear MIX_CTRL register. | |
561 | * Do it manually here. | |
562 | */ | |
de5bdbff | 563 | if (esdhc_is_usdhc(imx_data)) { |
d131a71c DA |
564 | /* the tuning bits should be kept during reset */ |
565 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
566 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, | |
567 | host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff DA |
568 | imx_data->is_ddr = 0; |
569 | } | |
58c8c4fb | 570 | } |
95f25efe WS |
571 | } |
572 | ||
0ddf03c9 LS |
573 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
574 | { | |
575 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
576 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
577 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
578 | ||
a974862f | 579 | if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) |
0ddf03c9 LS |
580 | return boarddata->f_max; |
581 | else | |
a974862f | 582 | return pltfm_host->clock; |
0ddf03c9 LS |
583 | } |
584 | ||
95f25efe WS |
585 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
586 | { | |
587 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
588 | ||
a974862f | 589 | return pltfm_host->clock / 256 / 16; |
95f25efe WS |
590 | } |
591 | ||
8ba9580a LS |
592 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
593 | unsigned int clock) | |
594 | { | |
595 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
fed2f6e2 | 596 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
a974862f | 597 | unsigned int host_clock = pltfm_host->clock; |
d31fc00a DA |
598 | int pre_div = 2; |
599 | int div = 1; | |
fed2f6e2 | 600 | u32 temp, val; |
d31fc00a | 601 | |
fed2f6e2 | 602 | if (clock == 0) { |
9d61c009 | 603 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
604 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
605 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
606 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
607 | } | |
d31fc00a | 608 | goto out; |
fed2f6e2 | 609 | } |
d31fc00a | 610 | |
de5bdbff | 611 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
5f7886c5 DA |
612 | pre_div = 1; |
613 | ||
d31fc00a DA |
614 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
615 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
616 | | ESDHC_CLOCK_MASK); | |
617 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
618 | ||
619 | while (host_clock / pre_div / 16 > clock && pre_div < 256) | |
620 | pre_div *= 2; | |
621 | ||
622 | while (host_clock / pre_div / div > clock && div < 16) | |
623 | div++; | |
624 | ||
e76b8559 | 625 | host->mmc->actual_clock = host_clock / pre_div / div; |
d31fc00a | 626 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
e76b8559 | 627 | clock, host->mmc->actual_clock); |
d31fc00a | 628 | |
de5bdbff DA |
629 | if (imx_data->is_ddr) |
630 | pre_div >>= 2; | |
631 | else | |
632 | pre_div >>= 1; | |
d31fc00a DA |
633 | div--; |
634 | ||
635 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | |
636 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
637 | | (div << ESDHC_DIVIDER_SHIFT) | |
638 | | (pre_div << ESDHC_PREDIV_SHIFT)); | |
639 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
fed2f6e2 | 640 | |
9d61c009 | 641 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
642 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
643 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
644 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
645 | } | |
646 | ||
d31fc00a DA |
647 | mdelay(1); |
648 | out: | |
649 | host->clock = clock; | |
8ba9580a LS |
650 | } |
651 | ||
913413c3 SG |
652 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
653 | { | |
842afc02 SG |
654 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
655 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
656 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
913413c3 SG |
657 | |
658 | switch (boarddata->wp_type) { | |
659 | case ESDHC_WP_GPIO: | |
fbe5fdd1 | 660 | return mmc_gpio_get_ro(host->mmc); |
913413c3 SG |
661 | case ESDHC_WP_CONTROLLER: |
662 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
663 | SDHCI_WRITE_PROTECT); | |
664 | case ESDHC_WP_NONE: | |
665 | break; | |
666 | } | |
667 | ||
668 | return -ENOSYS; | |
669 | } | |
670 | ||
af51079e SH |
671 | static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) |
672 | { | |
673 | u32 ctrl; | |
674 | ||
675 | switch (width) { | |
676 | case MMC_BUS_WIDTH_8: | |
677 | ctrl = ESDHC_CTRL_8BITBUS; | |
678 | break; | |
679 | case MMC_BUS_WIDTH_4: | |
680 | ctrl = ESDHC_CTRL_4BITBUS; | |
681 | break; | |
682 | default: | |
683 | ctrl = 0; | |
684 | break; | |
685 | } | |
686 | ||
687 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | |
688 | SDHCI_HOST_CONTROL); | |
689 | ||
690 | return 0; | |
691 | } | |
692 | ||
0322191e DA |
693 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
694 | { | |
695 | u32 reg; | |
696 | ||
697 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ | |
698 | mdelay(1); | |
699 | ||
ce090a4e | 700 | pm_runtime_get_sync(host->mmc->parent); |
0322191e DA |
701 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); |
702 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | | |
703 | ESDHC_MIX_CTRL_FBCLK_SEL; | |
704 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
705 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
706 | dev_dbg(mmc_dev(host->mmc), | |
707 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", | |
708 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); | |
709 | } | |
710 | ||
711 | static void esdhc_request_done(struct mmc_request *mrq) | |
712 | { | |
713 | complete(&mrq->completion); | |
714 | } | |
715 | ||
716 | static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) | |
717 | { | |
718 | struct mmc_command cmd = {0}; | |
a50145f9 | 719 | struct mmc_request mrq = {NULL}; |
0322191e DA |
720 | struct mmc_data data = {0}; |
721 | struct scatterlist sg; | |
722 | char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; | |
723 | ||
724 | cmd.opcode = opcode; | |
725 | cmd.arg = 0; | |
726 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | |
727 | ||
728 | data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; | |
729 | data.blocks = 1; | |
730 | data.flags = MMC_DATA_READ; | |
731 | data.sg = &sg; | |
732 | data.sg_len = 1; | |
733 | ||
734 | sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); | |
735 | ||
736 | mrq.cmd = &cmd; | |
737 | mrq.cmd->mrq = &mrq; | |
738 | mrq.data = &data; | |
739 | mrq.data->mrq = &mrq; | |
740 | mrq.cmd->data = mrq.data; | |
741 | ||
742 | mrq.done = esdhc_request_done; | |
743 | init_completion(&(mrq.completion)); | |
744 | ||
745 | disable_irq(host->irq); | |
746 | spin_lock(&host->lock); | |
747 | host->mrq = &mrq; | |
748 | ||
749 | sdhci_send_command(host, mrq.cmd); | |
750 | ||
751 | spin_unlock(&host->lock); | |
752 | enable_irq(host->irq); | |
753 | ||
754 | wait_for_completion(&mrq.completion); | |
755 | ||
756 | if (cmd.error) | |
757 | return cmd.error; | |
758 | if (data.error) | |
759 | return data.error; | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | static void esdhc_post_tuning(struct sdhci_host *host) | |
765 | { | |
766 | u32 reg; | |
767 | ||
768 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
769 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; | |
770 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
771 | } | |
772 | ||
773 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |
774 | { | |
775 | int min, max, avg, ret; | |
776 | ||
777 | /* find the mininum delay first which can pass tuning */ | |
778 | min = ESDHC_TUNE_CTRL_MIN; | |
779 | while (min < ESDHC_TUNE_CTRL_MAX) { | |
780 | esdhc_prepare_tuning(host, min); | |
781 | if (!esdhc_send_tuning_cmd(host, opcode)) | |
782 | break; | |
783 | min += ESDHC_TUNE_CTRL_STEP; | |
784 | } | |
785 | ||
786 | /* find the maxinum delay which can not pass tuning */ | |
787 | max = min + ESDHC_TUNE_CTRL_STEP; | |
788 | while (max < ESDHC_TUNE_CTRL_MAX) { | |
789 | esdhc_prepare_tuning(host, max); | |
790 | if (esdhc_send_tuning_cmd(host, opcode)) { | |
791 | max -= ESDHC_TUNE_CTRL_STEP; | |
792 | break; | |
793 | } | |
794 | max += ESDHC_TUNE_CTRL_STEP; | |
795 | } | |
796 | ||
797 | /* use average delay to get the best timing */ | |
798 | avg = (min + max) / 2; | |
799 | esdhc_prepare_tuning(host, avg); | |
800 | ret = esdhc_send_tuning_cmd(host, opcode); | |
801 | esdhc_post_tuning(host); | |
802 | ||
803 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", | |
804 | ret ? "failed" : "passed", avg, ret); | |
805 | ||
806 | return ret; | |
807 | } | |
808 | ||
ad93220d DA |
809 | static int esdhc_change_pinstate(struct sdhci_host *host, |
810 | unsigned int uhs) | |
811 | { | |
812 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
813 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
814 | struct pinctrl_state *pinctrl; | |
815 | ||
816 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); | |
817 | ||
818 | if (IS_ERR(imx_data->pinctrl) || | |
819 | IS_ERR(imx_data->pins_default) || | |
820 | IS_ERR(imx_data->pins_100mhz) || | |
821 | IS_ERR(imx_data->pins_200mhz)) | |
822 | return -EINVAL; | |
823 | ||
824 | switch (uhs) { | |
825 | case MMC_TIMING_UHS_SDR50: | |
826 | pinctrl = imx_data->pins_100mhz; | |
827 | break; | |
828 | case MMC_TIMING_UHS_SDR104: | |
429a5b45 | 829 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
830 | pinctrl = imx_data->pins_200mhz; |
831 | break; | |
832 | default: | |
833 | /* back to default state for other legacy timing */ | |
834 | pinctrl = imx_data->pins_default; | |
835 | } | |
836 | ||
837 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); | |
838 | } | |
839 | ||
840 | static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) | |
841 | { | |
842 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
843 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
602519b2 | 844 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
ad93220d DA |
845 | |
846 | switch (uhs) { | |
847 | case MMC_TIMING_UHS_SDR12: | |
848 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; | |
849 | break; | |
850 | case MMC_TIMING_UHS_SDR25: | |
851 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; | |
852 | break; | |
853 | case MMC_TIMING_UHS_SDR50: | |
854 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; | |
855 | break; | |
856 | case MMC_TIMING_UHS_SDR104: | |
429a5b45 | 857 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
858 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; |
859 | break; | |
860 | case MMC_TIMING_UHS_DDR50: | |
861 | imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; | |
de5bdbff DA |
862 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | |
863 | ESDHC_MIX_CTRL_DDREN, | |
864 | host->ioaddr + ESDHC_MIX_CTRL); | |
865 | imx_data->is_ddr = 1; | |
602519b2 DA |
866 | if (boarddata->delay_line) { |
867 | u32 v; | |
868 | v = boarddata->delay_line << | |
869 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | | |
870 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); | |
871 | if (is_imx53_esdhc(imx_data)) | |
872 | v <<= 1; | |
873 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); | |
874 | } | |
ad93220d DA |
875 | break; |
876 | } | |
877 | ||
878 | return esdhc_change_pinstate(host, uhs); | |
879 | } | |
880 | ||
6e9fd28e | 881 | static struct sdhci_ops sdhci_esdhc_ops = { |
e149860d | 882 | .read_l = esdhc_readl_le, |
0c6d49ce | 883 | .read_w = esdhc_readw_le, |
e149860d | 884 | .write_l = esdhc_writel_le, |
0c6d49ce WS |
885 | .write_w = esdhc_writew_le, |
886 | .write_b = esdhc_writeb_le, | |
8ba9580a | 887 | .set_clock = esdhc_pltfm_set_clock, |
0ddf03c9 | 888 | .get_max_clock = esdhc_pltfm_get_max_clock, |
0c6d49ce | 889 | .get_min_clock = esdhc_pltfm_get_min_clock, |
913413c3 | 890 | .get_ro = esdhc_pltfm_get_ro, |
af51079e | 891 | .platform_bus_width = esdhc_pltfm_bus_width, |
ad93220d | 892 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
0c6d49ce WS |
893 | }; |
894 | ||
1db5eebf | 895 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
97e4ba6a RZ |
896 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
897 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
898 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
85d6509d | 899 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
85d6509d SG |
900 | .ops = &sdhci_esdhc_ops, |
901 | }; | |
902 | ||
abfafc2d | 903 | #ifdef CONFIG_OF |
c3be1efd | 904 | static int |
abfafc2d SG |
905 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
906 | struct esdhc_platform_data *boarddata) | |
907 | { | |
908 | struct device_node *np = pdev->dev.of_node; | |
909 | ||
910 | if (!np) | |
911 | return -ENODEV; | |
912 | ||
7f217794 | 913 | if (of_get_property(np, "non-removable", NULL)) |
abfafc2d SG |
914 | boarddata->cd_type = ESDHC_CD_PERMANENT; |
915 | ||
916 | if (of_get_property(np, "fsl,cd-controller", NULL)) | |
917 | boarddata->cd_type = ESDHC_CD_CONTROLLER; | |
918 | ||
919 | if (of_get_property(np, "fsl,wp-controller", NULL)) | |
920 | boarddata->wp_type = ESDHC_WP_CONTROLLER; | |
921 | ||
922 | boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); | |
923 | if (gpio_is_valid(boarddata->cd_gpio)) | |
924 | boarddata->cd_type = ESDHC_CD_GPIO; | |
925 | ||
926 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
927 | if (gpio_is_valid(boarddata->wp_gpio)) | |
928 | boarddata->wp_type = ESDHC_WP_GPIO; | |
929 | ||
af51079e SH |
930 | of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); |
931 | ||
0ddf03c9 LS |
932 | of_property_read_u32(np, "max-frequency", &boarddata->f_max); |
933 | ||
ad93220d DA |
934 | if (of_find_property(np, "no-1-8-v", NULL)) |
935 | boarddata->support_vsel = false; | |
936 | else | |
937 | boarddata->support_vsel = true; | |
938 | ||
602519b2 DA |
939 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
940 | boarddata->delay_line = 0; | |
941 | ||
abfafc2d SG |
942 | return 0; |
943 | } | |
944 | #else | |
945 | static inline int | |
946 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, | |
947 | struct esdhc_platform_data *boarddata) | |
948 | { | |
949 | return -ENODEV; | |
950 | } | |
951 | #endif | |
952 | ||
c3be1efd | 953 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
95f25efe | 954 | { |
abfafc2d SG |
955 | const struct of_device_id *of_id = |
956 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); | |
85d6509d SG |
957 | struct sdhci_pltfm_host *pltfm_host; |
958 | struct sdhci_host *host; | |
959 | struct esdhc_platform_data *boarddata; | |
0c6d49ce | 960 | int err; |
e149860d | 961 | struct pltfm_imx_data *imx_data; |
95f25efe | 962 | |
0e748234 | 963 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); |
85d6509d SG |
964 | if (IS_ERR(host)) |
965 | return PTR_ERR(host); | |
966 | ||
967 | pltfm_host = sdhci_priv(host); | |
968 | ||
e3af31c6 | 969 | imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); |
abfafc2d SG |
970 | if (!imx_data) { |
971 | err = -ENOMEM; | |
e3af31c6 | 972 | goto free_sdhci; |
abfafc2d | 973 | } |
57ed3314 | 974 | |
f47c4bbf SG |
975 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
976 | pdev->id_entry->driver_data; | |
85d6509d SG |
977 | pltfm_host->priv = imx_data; |
978 | ||
52dac615 SH |
979 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
980 | if (IS_ERR(imx_data->clk_ipg)) { | |
981 | err = PTR_ERR(imx_data->clk_ipg); | |
e3af31c6 | 982 | goto free_sdhci; |
95f25efe | 983 | } |
52dac615 SH |
984 | |
985 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
986 | if (IS_ERR(imx_data->clk_ahb)) { | |
987 | err = PTR_ERR(imx_data->clk_ahb); | |
e3af31c6 | 988 | goto free_sdhci; |
52dac615 SH |
989 | } |
990 | ||
991 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); | |
992 | if (IS_ERR(imx_data->clk_per)) { | |
993 | err = PTR_ERR(imx_data->clk_per); | |
e3af31c6 | 994 | goto free_sdhci; |
52dac615 SH |
995 | } |
996 | ||
997 | pltfm_host->clk = imx_data->clk_per; | |
a974862f | 998 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
52dac615 SH |
999 | clk_prepare_enable(imx_data->clk_per); |
1000 | clk_prepare_enable(imx_data->clk_ipg); | |
1001 | clk_prepare_enable(imx_data->clk_ahb); | |
95f25efe | 1002 | |
ad93220d | 1003 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
e62d8b8f DA |
1004 | if (IS_ERR(imx_data->pinctrl)) { |
1005 | err = PTR_ERR(imx_data->pinctrl); | |
e3af31c6 | 1006 | goto disable_clk; |
e62d8b8f DA |
1007 | } |
1008 | ||
ad93220d DA |
1009 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
1010 | PINCTRL_STATE_DEFAULT); | |
1011 | if (IS_ERR(imx_data->pins_default)) { | |
1012 | err = PTR_ERR(imx_data->pins_default); | |
1013 | dev_err(mmc_dev(host->mmc), "could not get default state\n"); | |
1014 | goto disable_clk; | |
1015 | } | |
1016 | ||
b8915282 | 1017 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
37865fe9 | 1018 | |
f47c4bbf | 1019 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
0c6d49ce | 1020 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
97e4ba6a RZ |
1021 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
1022 | | SDHCI_QUIRK_BROKEN_ADMA; | |
0c6d49ce | 1023 | |
f750ba9b SG |
1024 | /* |
1025 | * The imx6q ROM code will change the default watermark level setting | |
1026 | * to something insane. Change it back here. | |
1027 | */ | |
69ed60e0 | 1028 | if (esdhc_is_usdhc(imx_data)) { |
60bf6396 | 1029 | writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); |
69ed60e0 | 1030 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
e2997c94 | 1031 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
69ed60e0 | 1032 | } |
f750ba9b | 1033 | |
6e9fd28e DA |
1034 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
1035 | sdhci_esdhc_ops.platform_execute_tuning = | |
1036 | esdhc_executing_tuning; | |
8b2bb0ad DA |
1037 | |
1038 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
1039 | writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | | |
1040 | ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, | |
1041 | host->ioaddr + ESDHC_TUNING_CTRL); | |
1042 | ||
842afc02 | 1043 | boarddata = &imx_data->boarddata; |
abfafc2d SG |
1044 | if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { |
1045 | if (!host->mmc->parent->platform_data) { | |
1046 | dev_err(mmc_dev(host->mmc), "no board data!\n"); | |
1047 | err = -EINVAL; | |
e3af31c6 | 1048 | goto disable_clk; |
abfafc2d SG |
1049 | } |
1050 | imx_data->boarddata = *((struct esdhc_platform_data *) | |
1051 | host->mmc->parent->platform_data); | |
1052 | } | |
913413c3 SG |
1053 | |
1054 | /* write_protect */ | |
1055 | if (boarddata->wp_type == ESDHC_WP_GPIO) { | |
fbe5fdd1 | 1056 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); |
0c6d49ce | 1057 | if (err) { |
fbe5fdd1 SG |
1058 | dev_err(mmc_dev(host->mmc), |
1059 | "failed to request write-protect gpio!\n"); | |
1060 | goto disable_clk; | |
0c6d49ce | 1061 | } |
fbe5fdd1 | 1062 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; |
913413c3 SG |
1063 | } |
1064 | ||
1065 | /* card_detect */ | |
913413c3 SG |
1066 | switch (boarddata->cd_type) { |
1067 | case ESDHC_CD_GPIO: | |
214fc309 | 1068 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); |
7e29c306 | 1069 | if (err) { |
913413c3 | 1070 | dev_err(mmc_dev(host->mmc), |
fbe5fdd1 | 1071 | "failed to request card-detect gpio!\n"); |
e3af31c6 | 1072 | goto disable_clk; |
7e29c306 | 1073 | } |
913413c3 | 1074 | /* fall through */ |
7e29c306 | 1075 | |
913413c3 SG |
1076 | case ESDHC_CD_CONTROLLER: |
1077 | /* we have a working card_detect back */ | |
7e29c306 | 1078 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
913413c3 SG |
1079 | break; |
1080 | ||
1081 | case ESDHC_CD_PERMANENT: | |
e526003b | 1082 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
913413c3 SG |
1083 | break; |
1084 | ||
1085 | case ESDHC_CD_NONE: | |
1086 | break; | |
0c6d49ce | 1087 | } |
16a790bc | 1088 | |
af51079e SH |
1089 | switch (boarddata->max_bus_width) { |
1090 | case 8: | |
1091 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; | |
1092 | break; | |
1093 | case 4: | |
1094 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1095 | break; | |
1096 | case 1: | |
1097 | default: | |
1098 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; | |
1099 | break; | |
1100 | } | |
1101 | ||
ad93220d | 1102 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
9d61c009 | 1103 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) { |
ad93220d DA |
1104 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, |
1105 | ESDHC_PINCTRL_STATE_100MHZ); | |
1106 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
1107 | ESDHC_PINCTRL_STATE_200MHZ); | |
1108 | if (IS_ERR(imx_data->pins_100mhz) || | |
1109 | IS_ERR(imx_data->pins_200mhz)) { | |
1110 | dev_warn(mmc_dev(host->mmc), | |
1111 | "could not get ultra high speed state, work on normal mode\n"); | |
1112 | /* fall back to not support uhs by specify no 1.8v quirk */ | |
1113 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1114 | } | |
1115 | } else { | |
1116 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1117 | } | |
1118 | ||
85d6509d SG |
1119 | err = sdhci_add_host(host); |
1120 | if (err) | |
e3af31c6 | 1121 | goto disable_clk; |
85d6509d | 1122 | |
89d7e5c1 DA |
1123 | pm_runtime_set_active(&pdev->dev); |
1124 | pm_runtime_enable(&pdev->dev); | |
1125 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
1126 | pm_runtime_use_autosuspend(&pdev->dev); | |
1127 | pm_suspend_ignore_children(&pdev->dev, 1); | |
1128 | ||
95f25efe | 1129 | return 0; |
7e29c306 | 1130 | |
e3af31c6 | 1131 | disable_clk: |
52dac615 SH |
1132 | clk_disable_unprepare(imx_data->clk_per); |
1133 | clk_disable_unprepare(imx_data->clk_ipg); | |
1134 | clk_disable_unprepare(imx_data->clk_ahb); | |
e3af31c6 | 1135 | free_sdhci: |
85d6509d SG |
1136 | sdhci_pltfm_free(pdev); |
1137 | return err; | |
95f25efe WS |
1138 | } |
1139 | ||
6e0ee714 | 1140 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
95f25efe | 1141 | { |
85d6509d | 1142 | struct sdhci_host *host = platform_get_drvdata(pdev); |
95f25efe | 1143 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
e149860d | 1144 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
85d6509d SG |
1145 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
1146 | ||
1147 | sdhci_remove_host(host, dead); | |
0c6d49ce | 1148 | |
89d7e5c1 DA |
1149 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1150 | pm_runtime_disable(&pdev->dev); | |
1151 | ||
a7f2be94 DA |
1152 | if (!IS_ENABLED(CONFIG_PM_RUNTIME)) { |
1153 | clk_disable_unprepare(imx_data->clk_per); | |
1154 | clk_disable_unprepare(imx_data->clk_ipg); | |
1155 | clk_disable_unprepare(imx_data->clk_ahb); | |
1156 | } | |
52dac615 | 1157 | |
85d6509d SG |
1158 | sdhci_pltfm_free(pdev); |
1159 | ||
1160 | return 0; | |
95f25efe WS |
1161 | } |
1162 | ||
89d7e5c1 DA |
1163 | #ifdef CONFIG_PM_RUNTIME |
1164 | static int sdhci_esdhc_runtime_suspend(struct device *dev) | |
1165 | { | |
1166 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1167 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1168 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1169 | int ret; | |
1170 | ||
1171 | ret = sdhci_runtime_suspend_host(host); | |
1172 | ||
be138554 RK |
1173 | if (!sdhci_sdio_irq_enabled(host)) { |
1174 | clk_disable_unprepare(imx_data->clk_per); | |
1175 | clk_disable_unprepare(imx_data->clk_ipg); | |
1176 | } | |
89d7e5c1 DA |
1177 | clk_disable_unprepare(imx_data->clk_ahb); |
1178 | ||
1179 | return ret; | |
1180 | } | |
1181 | ||
1182 | static int sdhci_esdhc_runtime_resume(struct device *dev) | |
1183 | { | |
1184 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1185 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1186 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1187 | ||
be138554 RK |
1188 | if (!sdhci_sdio_irq_enabled(host)) { |
1189 | clk_prepare_enable(imx_data->clk_per); | |
1190 | clk_prepare_enable(imx_data->clk_ipg); | |
1191 | } | |
89d7e5c1 DA |
1192 | clk_prepare_enable(imx_data->clk_ahb); |
1193 | ||
1194 | return sdhci_runtime_resume_host(host); | |
1195 | } | |
1196 | #endif | |
1197 | ||
1198 | static const struct dev_pm_ops sdhci_esdhc_pmops = { | |
1199 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) | |
1200 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, | |
1201 | sdhci_esdhc_runtime_resume, NULL) | |
1202 | }; | |
1203 | ||
85d6509d SG |
1204 | static struct platform_driver sdhci_esdhc_imx_driver = { |
1205 | .driver = { | |
1206 | .name = "sdhci-esdhc-imx", | |
1207 | .owner = THIS_MODULE, | |
abfafc2d | 1208 | .of_match_table = imx_esdhc_dt_ids, |
89d7e5c1 | 1209 | .pm = &sdhci_esdhc_pmops, |
85d6509d | 1210 | }, |
57ed3314 | 1211 | .id_table = imx_esdhc_devtype, |
85d6509d | 1212 | .probe = sdhci_esdhc_imx_probe, |
0433c143 | 1213 | .remove = sdhci_esdhc_imx_remove, |
95f25efe | 1214 | }; |
85d6509d | 1215 | |
d1f81a64 | 1216 | module_platform_driver(sdhci_esdhc_imx_driver); |
85d6509d SG |
1217 | |
1218 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); | |
1219 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); | |
1220 | MODULE_LICENSE("GPL v2"); |