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1 | /* |
2 | * Arasan Secure Digital Host Controller Interface. | |
3 | * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> | |
4 | * Copyright (c) 2012 Wind River Systems, Inc. | |
5 | * Copyright (C) 2013 Pengutronix e.K. | |
6 | * Copyright (C) 2013 Xilinx Inc. | |
7 | * | |
8 | * Based on sdhci-of-esdhc.c | |
9 | * | |
10 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
11 | * Copyright (c) 2009 MontaVista Software, Inc. | |
12 | * | |
13 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
14 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or (at | |
19 | * your option) any later version. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include "sdhci-pltfm.h" | |
24 | ||
25 | #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c | |
26 | ||
27 | #define CLK_CTRL_TIMEOUT_SHIFT 16 | |
28 | #define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT) | |
29 | #define CLK_CTRL_TIMEOUT_MIN_EXP 13 | |
30 | ||
31 | /** | |
32 | * struct sdhci_arasan_data | |
33 | * @clk_ahb: Pointer to the AHB clock | |
34 | */ | |
35 | struct sdhci_arasan_data { | |
36 | struct clk *clk_ahb; | |
37 | }; | |
38 | ||
39 | static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) | |
40 | { | |
41 | u32 div; | |
42 | unsigned long freq; | |
43 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
44 | ||
45 | div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET); | |
46 | div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT; | |
47 | ||
48 | freq = clk_get_rate(pltfm_host->clk); | |
49 | freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div); | |
50 | ||
51 | return freq; | |
52 | } | |
53 | ||
54 | static struct sdhci_ops sdhci_arasan_ops = { | |
55 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | |
56 | .get_timeout_clock = sdhci_arasan_get_timeout_clock, | |
2317f56c | 57 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 58 | .reset = sdhci_reset, |
e3ec3a3d SB |
59 | }; |
60 | ||
61 | static struct sdhci_pltfm_data sdhci_arasan_pdata = { | |
62 | .ops = &sdhci_arasan_ops, | |
63 | }; | |
64 | ||
65 | #ifdef CONFIG_PM_SLEEP | |
66 | /** | |
67 | * sdhci_arasan_suspend - Suspend method for the driver | |
68 | * @dev: Address of the device structure | |
69 | * Returns 0 on success and error value on error | |
70 | * | |
71 | * Put the device in a low power state. | |
72 | */ | |
73 | static int sdhci_arasan_suspend(struct device *dev) | |
74 | { | |
75 | struct platform_device *pdev = to_platform_device(dev); | |
76 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
77 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
78 | struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv; | |
79 | int ret; | |
80 | ||
81 | ret = sdhci_suspend_host(host); | |
82 | if (ret) | |
83 | return ret; | |
84 | ||
85 | clk_disable(pltfm_host->clk); | |
86 | clk_disable(sdhci_arasan->clk_ahb); | |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
91 | /** | |
92 | * sdhci_arasan_resume - Resume method for the driver | |
93 | * @dev: Address of the device structure | |
94 | * Returns 0 on success and error value on error | |
95 | * | |
96 | * Resume operation after suspend | |
97 | */ | |
98 | static int sdhci_arasan_resume(struct device *dev) | |
99 | { | |
100 | struct platform_device *pdev = to_platform_device(dev); | |
101 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
102 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
103 | struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv; | |
104 | int ret; | |
105 | ||
106 | ret = clk_enable(sdhci_arasan->clk_ahb); | |
107 | if (ret) { | |
108 | dev_err(dev, "Cannot enable AHB clock.\n"); | |
109 | return ret; | |
110 | } | |
111 | ||
112 | ret = clk_enable(pltfm_host->clk); | |
113 | if (ret) { | |
114 | dev_err(dev, "Cannot enable SD clock.\n"); | |
115 | clk_disable(sdhci_arasan->clk_ahb); | |
116 | return ret; | |
117 | } | |
118 | ||
119 | return sdhci_resume_host(host); | |
120 | } | |
121 | #endif /* ! CONFIG_PM_SLEEP */ | |
122 | ||
123 | static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, | |
124 | sdhci_arasan_resume); | |
125 | ||
126 | static int sdhci_arasan_probe(struct platform_device *pdev) | |
127 | { | |
128 | int ret; | |
129 | struct clk *clk_xin; | |
130 | struct sdhci_host *host; | |
131 | struct sdhci_pltfm_host *pltfm_host; | |
132 | struct sdhci_arasan_data *sdhci_arasan; | |
133 | ||
134 | sdhci_arasan = devm_kzalloc(&pdev->dev, sizeof(*sdhci_arasan), | |
135 | GFP_KERNEL); | |
136 | if (!sdhci_arasan) | |
137 | return -ENOMEM; | |
138 | ||
139 | sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); | |
140 | if (IS_ERR(sdhci_arasan->clk_ahb)) { | |
141 | dev_err(&pdev->dev, "clk_ahb clock not found.\n"); | |
142 | return PTR_ERR(sdhci_arasan->clk_ahb); | |
143 | } | |
144 | ||
145 | clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); | |
146 | if (IS_ERR(clk_xin)) { | |
147 | dev_err(&pdev->dev, "clk_xin clock not found.\n"); | |
148 | return PTR_ERR(clk_xin); | |
149 | } | |
150 | ||
151 | ret = clk_prepare_enable(sdhci_arasan->clk_ahb); | |
152 | if (ret) { | |
153 | dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); | |
154 | return ret; | |
155 | } | |
156 | ||
157 | ret = clk_prepare_enable(clk_xin); | |
158 | if (ret) { | |
159 | dev_err(&pdev->dev, "Unable to enable SD clock.\n"); | |
160 | goto clk_dis_ahb; | |
161 | } | |
162 | ||
163 | host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, 0); | |
164 | if (IS_ERR(host)) { | |
165 | ret = PTR_ERR(host); | |
166 | dev_err(&pdev->dev, "platform init failed (%u)\n", ret); | |
167 | goto clk_disable_all; | |
168 | } | |
169 | ||
170 | sdhci_get_of_property(pdev); | |
171 | pltfm_host = sdhci_priv(host); | |
172 | pltfm_host->priv = sdhci_arasan; | |
173 | pltfm_host->clk = clk_xin; | |
174 | ||
175 | ret = sdhci_add_host(host); | |
176 | if (ret) { | |
177 | dev_err(&pdev->dev, "platform register failed (%u)\n", ret); | |
178 | goto err_pltfm_free; | |
179 | } | |
180 | ||
181 | return 0; | |
182 | ||
183 | err_pltfm_free: | |
184 | sdhci_pltfm_free(pdev); | |
185 | clk_disable_all: | |
186 | clk_disable_unprepare(clk_xin); | |
187 | clk_dis_ahb: | |
188 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
189 | ||
190 | return ret; | |
191 | } | |
192 | ||
193 | static int sdhci_arasan_remove(struct platform_device *pdev) | |
194 | { | |
195 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
196 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
197 | struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv; | |
198 | ||
199 | clk_disable_unprepare(pltfm_host->clk); | |
200 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
201 | ||
202 | return sdhci_pltfm_unregister(pdev); | |
203 | } | |
204 | ||
205 | static const struct of_device_id sdhci_arasan_of_match[] = { | |
206 | { .compatible = "arasan,sdhci-8.9a" }, | |
207 | { } | |
208 | }; | |
209 | MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); | |
210 | ||
211 | static struct platform_driver sdhci_arasan_driver = { | |
212 | .driver = { | |
213 | .name = "sdhci-arasan", | |
214 | .owner = THIS_MODULE, | |
215 | .of_match_table = sdhci_arasan_of_match, | |
216 | .pm = &sdhci_arasan_dev_pm_ops, | |
217 | }, | |
218 | .probe = sdhci_arasan_probe, | |
219 | .remove = sdhci_arasan_remove, | |
220 | }; | |
221 | ||
222 | module_platform_driver(sdhci_arasan_driver); | |
223 | ||
224 | MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); | |
225 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); | |
226 | MODULE_LICENSE("GPL"); |