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mmc: sdhci-pci: Fix card detect race for Intel BXT/APL
[deliverable/linux.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
e1bfad6d 23#include <linux/mmc/mmc.h>
b177bc91
AP		 24#include <linux/scatterlist.h>
25#include <linux/io.h>
0f201655 26#include <linux/gpio.h>
66fd8ad5 27#include <linux/pm_runtime.h>
ff59c520 28#include <linux/mmc/slot-gpio.h>
52c506f0 29#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 30
31#include "sdhci.h"
522624f9 32#include "sdhci-pci.h"
01acf691 33#include "sdhci-pci-o2micro.h"
22606405
PO		 34
35/*****************************************************************************\
36 * *
37 * Hardware specific quirk handling *
38 * *
39\*****************************************************************************/
40
41static int ricoh_probe(struct sdhci_pci_chip *chip)
42{
c99436fb
CB		 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 46 return 0;
47}
48
49static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50{
51 slot->host->caps =
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 54
ccc92c23
ML		 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
57
58 SDHCI_TIMEOUT_CLK_UNIT |
59 SDHCI_CAN_VDD_330 |
1a1f1f04 60 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 61 SDHCI_CAN_DO_SDMA;
62 return 0;
63}
64
65static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66{
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
69 during suspend */
70 msleep(500);
22606405
PO		 71 return 0;
72}
73
74static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .probe = ricoh_probe,
84938294
VK		 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 79};
80
ccc92c23
ML		 81static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
88};
89
22606405
PO		 90static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93};
94
95static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
99};
100
101static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 103 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 106};
107
43e968ce
DB		 108static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
110};
111
68077b02
ML		 112static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113{
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 return 0;
116}
117
f9ee3eab
AC		 118/*
119 * ADMA operation is disabled for Moorestown platform due to
120 * hardware bugs.
121 */
35ac6f08 122static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 123{
124 /*
35ac6f08
JP		 125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
f9ee3eab
AC		 127 */
128 chip->num_slots = 1;
129 return 0;
130}
131
296e0b03
AS		 132static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133{
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 return 0;
136}
137
162d6f98 138#ifdef CONFIG_PM
66fd8ad5 139
c5e027a4 140static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 141{
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
144
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 return IRQ_HANDLED;
147}
148
c5e027a4 149static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 150{
c5e027a4 151 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 152
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
155
c5e027a4
AH		 156 if (!gpio_is_valid(gpio))
157 return;
158
66fd8ad5
AH		 159 err = gpio_request(gpio, "sd_cd");
160 if (err < 0)
161 goto out;
162
163 err = gpio_direction_input(gpio);
164 if (err < 0)
165 goto out_free;
166
167 irq = gpio_to_irq(gpio);
168 if (irq < 0)
169 goto out_free;
170
c5e027a4 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 if (err)
174 goto out_free;
175
176 slot->cd_gpio = gpio;
177 slot->cd_irq = irq;
66fd8ad5 178
c5e027a4 179 return;
66fd8ad5
AH		 180
181out_free:
182 gpio_free(gpio);
183out:
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 185}
186
c5e027a4 187static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 188{
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 191 if (gpio_is_valid(slot->cd_gpio))
192 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 193}
194
195#else
196
c5e027a4
AH		 197static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
198{
199}
200
201static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
202{
203}
66fd8ad5
AH		 204
205#endif
206
0d013bcf
AH		 207static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
208{
66fd8ad5 209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 212 return 0;
213}
214
93933508
AH		 215static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
216{
012e4671 217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 218 return 0;
219}
220
f9ee3eab
AC		 221static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 223 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 224};
225
35ac6f08 226static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 228 .probe = mrst_hc_probe,
f9ee3eab
AC		 229};
230
29229052
XS		 231static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 233 .allow_runtime_pm = true,
77a0122e 234 .own_cd_for_runtime_pm = true,
29229052
XS		 235};
236
0d013bcf
AH		 237static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 240 .allow_runtime_pm = true,
93933508 241 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 242};
243
244static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 246 .allow_runtime_pm = true,
0d013bcf 247 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 248};
249
296e0b03
AS		 250static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
252 .probe_slot = pch_hc_probe_slot,
253};
254
c9faff6c
AH		 255static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
256{
257 u8 reg;
258
259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
260 reg |= 0x10;
261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 /* For eMMC, minimum is 1us but give it 9us for good measure */
263 udelay(9);
264 reg &= ~0x10;
265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 /* For eMMC, minimum is 200us but give it 300us for good measure */
267 usleep_range(300, 1000);
268}
269
e1bfad6d
AH		 270static int spt_select_drive_strength(struct sdhci_host *host,
271 struct mmc_card *card,
272 unsigned int max_dtr,
273 int host_drv, int card_drv, int *drv_type)
274{
275 int drive_strength;
276
277 if (sdhci_pci_spt_drive_strength > 0)
278 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
279 else
1ca89685 280 drive_strength = 0; /* Default 50-ohm */
e1bfad6d
AH		 281
282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 drive_strength = 0; /* Default 50-ohm */
284
285 return drive_strength;
286}
287
288/* Try to read the drive strength from the card */
289static void spt_read_drive_strength(struct sdhci_host *host)
290{
291 u32 val, i, t;
292 u16 m;
293
294 if (sdhci_pci_spt_drive_strength)
295 return;
296
297 sdhci_pci_spt_drive_strength = -1;
298
299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 if (m != 3 && m != 5)
301 return;
302 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
303 if (val & 0x3)
304 return;
305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 for (i = 0; i < 1000; i++) {
314 val = sdhci_readl(host, SDHCI_INT_STATUS);
315 if (val & 0xffff8000)
316 return;
317 if (val & 0x20)
318 break;
319 udelay(1);
320 }
321 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
322 if (!(val & 0x800))
323 return;
324 for (i = 0; i < 47; i++)
325 val = sdhci_readl(host, SDHCI_BUFFER);
326 t = val & 0xf00;
327 if (t != 0x200 && t != 0x300)
328 return;
329
330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
331}
332
163cbe31
AH		 333static int bxt_get_cd(struct mmc_host *mmc)
334{
335 int gpio_cd = mmc_gpio_get_cd(mmc);
336 struct sdhci_host *host = mmc_priv(mmc);
337 unsigned long flags;
338 int ret = 0;
339
340 if (!gpio_cd)
341 return 0;
342
343 pm_runtime_get_sync(mmc->parent);
344
345 spin_lock_irqsave(&host->lock, flags);
346
347 if (host->flags & SDHCI_DEVICE_DEAD)
348 goto out;
349
350 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
351out:
352 spin_unlock_irqrestore(&host->lock, flags);
353
354 pm_runtime_mark_last_busy(mmc->parent);
355 pm_runtime_put_autosuspend(mmc->parent);
356
357 return ret;
358}
359
728ef3d1
AH		 360static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
361{
c9faff6c 362 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8
AH		 363 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
364 MMC_CAP_BUS_WIDTH_TEST |
365 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1 366 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 367 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 368 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
369 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
e1bfad6d
AH		 370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
371 spt_read_drive_strength(slot->host);
372 slot->select_drive_strength = spt_select_drive_strength;
373 }
728ef3d1
AH		 374 return 0;
375}
376
377static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
378{
6aab23a8
AH		 379 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
380 MMC_CAP_BUS_WIDTH_TEST |
381 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 382 return 0;
383}
384
ff59c520
AH		 385static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
386{
6aab23a8
AH		 387 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
388 MMC_CAP_WAIT_WHILE_BUSY;
ff59c520
AH		 389 slot->cd_con_id = NULL;
390 slot->cd_idx = 0;
391 slot->cd_override_level = true;
163cbe31
AH		 392 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
393 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD)
394 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
395
ff59c520
AH		 396 return 0;
397}
398
728ef3d1
AH		 399static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
400 .allow_runtime_pm = true,
401 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 403 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 404 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 405 SDHCI_QUIRK2_STOP_WITH_TC,
728ef3d1
AH		 406};
407
408static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 409 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 410 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
411 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 412 .allow_runtime_pm = true,
413 .probe_slot = byt_sdio_probe_slot,
414};
415
416static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 417 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 418 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 419 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
420 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 421 .allow_runtime_pm = true,
77a0122e 422 .own_cd_for_runtime_pm = true,
ff59c520 423 .probe_slot = byt_sd_probe_slot,
728ef3d1
AH		 424};
425
8776a165
DC		 426/* Define Host controllers for Intel Merrifield platform */
427#define INTEL_MRFL_EMMC_0 0
428#define INTEL_MRFL_EMMC_1 1
429
430static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
431{
432 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
433 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
434 /* SD support is not ready yet */
435 return -ENODEV;
436
437 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
438 MMC_CAP_1_8V_DDR;
439
440 return 0;
441}
442
443static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 445 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
446 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 447 .allow_runtime_pm = true,
8776a165
DC		 448 .probe_slot = intel_mrfl_mmc_probe_slot,
449};
450
26daa1ed
JL		 451/* O2Micro extra registers */
452#define O2_SD_LOCK_WP 0xD3
453#define O2_SD_MULTI_VCC3V 0xEE
454#define O2_SD_CLKREQ 0xEC
455#define O2_SD_CAPS 0xE0
456#define O2_SD_ADMA1 0xE2
457#define O2_SD_ADMA2 0xE7
458#define O2_SD_INF_MOD 0xF1
459
45211e21
PO		 460static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
461{
462 u8 scratch;
463 int ret;
464
465 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
466 if (ret)
467 return ret;
468
469 /*
470 * Turn PMOS on [bit 0], set over current detection to 2.4 V
471 * [bit 1:2] and enable over current debouncing [bit 6].
472 */
473 if (on)
474 scratch |= 0x47;
475 else
476 scratch &= ~0x47;
477
7582041f 478 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 479}
480
481static int jmicron_probe(struct sdhci_pci_chip *chip)
482{
483 int ret;
8f230f45 484 u16 mmcdev = 0;
45211e21 485
93fc48c7
PO		 486 if (chip->pdev->revision == 0) {
487 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
488 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 489 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 490 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 491 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 492 }
493
4489428a
PO		 494 /*
495 * JMicron chips can have two interfaces to the same hardware
496 * in order to work around limitations in Microsoft's driver.
497 * We need to make sure we only bind to one of them.
498 *
499 * This code assumes two things:
500 *
501 * 1. The PCI code adds subfunctions in order.
502 *
503 * 2. The MMC interface has a lower subfunction number
504 * than the SD interface.
505 */
8f230f45
TI		 506 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
507 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
508 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
509 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
510
511 if (mmcdev) {
4489428a
PO		 512 struct pci_dev *sd_dev;
513
514 sd_dev = NULL;
515 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 516 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 517 if ((PCI_SLOT(chip->pdev->devfn) ==
518 PCI_SLOT(sd_dev->devfn)) &&
519 (chip->pdev->bus == sd_dev->bus))
520 break;
521 }
522
523 if (sd_dev) {
524 pci_dev_put(sd_dev);
525 dev_info(&chip->pdev->dev, "Refusing to bind to "
526 "secondary interface.\n");
527 return -ENODEV;
528 }
529 }
530
45211e21
PO		 531 /*
532 * JMicron chips need a bit of a nudge to enable the power
533 * output pins.
534 */
535 ret = jmicron_pmos(chip, 1);
536 if (ret) {
537 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
538 return ret;
539 }
540
82b0e23a
TI		 541 /* quirk for unsable RO-detection on JM388 chips */
542 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
543 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
544 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
545
45211e21
PO		 546 return 0;
547}
548
4489428a
PO		 549static void jmicron_enable_mmc(struct sdhci_host *host, int on)
550{
551 u8 scratch;
552
553 scratch = readb(host->ioaddr + 0xC0);
554
555 if (on)
556 scratch |= 0x01;
557 else
558 scratch &= ~0x01;
559
560 writeb(scratch, host->ioaddr + 0xC0);
561}
562
563static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
564{
2134a922
PO		 565 if (slot->chip->pdev->revision == 0) {
566 u16 version;
567
568 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
569 version = (version & SDHCI_VENDOR_VER_MASK) >>
570 SDHCI_VENDOR_VER_SHIFT;
571
572 /*
573 * Older versions of the chip have lots of nasty glitches
574 * in the ADMA engine. It's best just to avoid it
575 * completely.
576 */
577 if (version < 0xAC)
578 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
579 }
580
8f230f45
TI		 581 /* JM388 MMC doesn't support 1.8V while SD supports it */
582 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
583 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
584 MMC_VDD_29_30 | MMC_VDD_30_31 |
585 MMC_VDD_165_195; /* allow 1.8V */
586 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
587 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
588 }
589
4489428a
PO		 590 /*
591 * The secondary interface requires a bit set to get the
592 * interrupts.
593 */
8f230f45
TI		 594 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
595 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 596 jmicron_enable_mmc(slot->host, 1);
597
d75c1084
TI		 598 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
599
4489428a
PO		 600 return 0;
601}
602
1e72859e 603static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 604{
1e72859e
PO		 605 if (dead)
606 return;
607
8f230f45
TI		 608 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
609 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 610 jmicron_enable_mmc(slot->host, 0);
611}
612
29495aa0 613static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 614{
615 int i;
616
8f230f45
TI		 617 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
618 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 619 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 620 jmicron_enable_mmc(chip->slots[i]->host, 0);
621 }
622
623 return 0;
624}
625
45211e21
PO		 626static int jmicron_resume(struct sdhci_pci_chip *chip)
627{
4489428a
PO		 628 int ret, i;
629
8f230f45
TI		 630 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
631 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 632 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 633 jmicron_enable_mmc(chip->slots[i]->host, 1);
634 }
45211e21
PO		 635
636 ret = jmicron_pmos(chip, 1);
637 if (ret) {
638 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
639 return ret;
640 }
641
642 return 0;
643}
644
26daa1ed 645static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 646 .probe = sdhci_pci_o2_probe,
647 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
143b648d 648 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
01acf691
AL		 649 .probe_slot = sdhci_pci_o2_probe_slot,
650 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 651};
652
22606405 653static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 654 .probe = jmicron_probe,
655
4489428a
PO		 656 .probe_slot = jmicron_probe_slot,
657 .remove_slot = jmicron_remove_slot,
658
659 .suspend = jmicron_suspend,
45211e21 660 .resume = jmicron_resume,
22606405
PO		 661};
662
a7a6186c
NP		 663/* SysKonnect CardBus2SDIO extra registers */
664#define SYSKT_CTRL 0x200
665#define SYSKT_RDFIFO_STAT 0x204
666#define SYSKT_WRFIFO_STAT 0x208
667#define SYSKT_POWER_DATA 0x20c
668#define SYSKT_POWER_330 0xef
669#define SYSKT_POWER_300 0xf8
670#define SYSKT_POWER_184 0xcc
671#define SYSKT_POWER_CMD 0x20d
672#define SYSKT_POWER_START (1 << 7)
673#define SYSKT_POWER_STATUS 0x20e
674#define SYSKT_POWER_STATUS_OK (1 << 0)
675#define SYSKT_BOARD_REV 0x210
676#define SYSKT_CHIP_REV 0x211
677#define SYSKT_CONF_DATA 0x212
678#define SYSKT_CONF_DATA_1V8 (1 << 2)
679#define SYSKT_CONF_DATA_2V5 (1 << 1)
680#define SYSKT_CONF_DATA_3V3 (1 << 0)
681
682static int syskt_probe(struct sdhci_pci_chip *chip)
683{
684 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
685 chip->pdev->class &= ~0x0000FF;
686 chip->pdev->class |= PCI_SDHCI_IFDMA;
687 }
688 return 0;
689}
690
691static int syskt_probe_slot(struct sdhci_pci_slot *slot)
692{
693 int tm, ps;
694
695 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
696 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
697 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
698 "board rev %d.%d, chip rev %d.%d\n",
699 board_rev >> 4, board_rev & 0xf,
700 chip_rev >> 4, chip_rev & 0xf);
701 if (chip_rev >= 0x20)
702 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
703
704 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
705 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
706 udelay(50);
707 tm = 10; /* Wait max 1 ms */
708 do {
709 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
710 if (ps & SYSKT_POWER_STATUS_OK)
711 break;
712 udelay(100);
713 } while (--tm);
714 if (!tm) {
715 dev_err(&slot->chip->pdev->dev,
716 "power regulator never stabilized");
717 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
718 return -ENODEV;
719 }
720
721 return 0;
722}
723
724static const struct sdhci_pci_fixes sdhci_syskt = {
725 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
726 .probe = syskt_probe,
727 .probe_slot = syskt_probe_slot,
728};
729
557b0697
HW		 730static int via_probe(struct sdhci_pci_chip *chip)
731{
732 if (chip->pdev->revision == 0x10)
733 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
734
735 return 0;
736}
737
738static const struct sdhci_pci_fixes sdhci_via = {
739 .probe = via_probe,
740};
741
9107ebbf
MC		 742static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
743{
744 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
745 return 0;
746}
747
748static const struct sdhci_pci_fixes sdhci_rtsx = {
749 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 750 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 751 SDHCI_QUIRK2_BROKEN_DDR50,
752 .probe_slot = rtsx_probe_slot,
753};
754
b5e97d6e
VW		 755/*AMD chipset generation*/
756enum amd_chipset_gen {
757 AMD_CHIPSET_BEFORE_ML,
758 AMD_CHIPSET_CZ,
759 AMD_CHIPSET_NL,
760 AMD_CHIPSET_UNKNOWN,
761};
762
d44f88da
VW		 763static int amd_probe(struct sdhci_pci_chip *chip)
764{
765 struct pci_dev *smbus_dev;
b5e97d6e 766 enum amd_chipset_gen gen;
d44f88da
VW		 767
768 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
769 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 770 if (smbus_dev) {
771 gen = AMD_CHIPSET_BEFORE_ML;
772 } else {
773 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
774 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
775 if (smbus_dev) {
776 if (smbus_dev->revision < 0x51)
777 gen = AMD_CHIPSET_CZ;
778 else
779 gen = AMD_CHIPSET_NL;
780 } else {
781 gen = AMD_CHIPSET_UNKNOWN;
782 }
783 }
d44f88da 784
b5e97d6e 785 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
d44f88da 786 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
e765bfa2
VW		 787 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
788 }
d44f88da
VW		 789
790 return 0;
791}
792
793static const struct sdhci_pci_fixes sdhci_amd = {
794 .probe = amd_probe,
795};
796
9647f84d 797static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 798 {
799 .vendor = PCI_VENDOR_ID_RICOH,
800 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 801 .subvendor = PCI_ANY_ID,
b8c86fc5 802 .subdevice = PCI_ANY_ID,
22606405 803 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 804 },
805
ccc92c23
ML		 806 {
807 .vendor = PCI_VENDOR_ID_RICOH,
808 .device = 0x843,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
811 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
812 },
813
568133eb
PC		 814 {
815 .vendor = PCI_VENDOR_ID_RICOH,
816 .device = 0xe822,
817 .subvendor = PCI_ANY_ID,
818 .subdevice = PCI_ANY_ID,
819 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
820 },
821
5fd11c07
MI		 822 {
823 .vendor = PCI_VENDOR_ID_RICOH,
824 .device = 0xe823,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
828 },
829
b8c86fc5
PO		 830 {
831 .vendor = PCI_VENDOR_ID_ENE,
832 .device = PCI_DEVICE_ID_ENE_CB712_SD,
833 .subvendor = PCI_ANY_ID,
834 .subdevice = PCI_ANY_ID,
22606405 835 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 836 },
837
838 {
839 .vendor = PCI_VENDOR_ID_ENE,
840 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
22606405 843 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 844 },
845
846 {
847 .vendor = PCI_VENDOR_ID_ENE,
848 .device = PCI_DEVICE_ID_ENE_CB714_SD,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
22606405 851 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 852 },
853
854 {
855 .vendor = PCI_VENDOR_ID_ENE,
856 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
857 .subvendor = PCI_ANY_ID,
858 .subdevice = PCI_ANY_ID,
22606405 859 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 860 },
861
862 {
863 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 864 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 865 .subvendor = PCI_ANY_ID,
866 .subdevice = PCI_ANY_ID,
22606405 867 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 868 },
869
870 {
871 .vendor = PCI_VENDOR_ID_JMICRON,
872 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
873 .subvendor = PCI_ANY_ID,
874 .subdevice = PCI_ANY_ID,
22606405 875 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 876 },
877
4489428a
PO		 878 {
879 .vendor = PCI_VENDOR_ID_JMICRON,
880 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
881 .subvendor = PCI_ANY_ID,
882 .subdevice = PCI_ANY_ID,
883 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 884 },
885
886 {
887 .vendor = PCI_VENDOR_ID_JMICRON,
888 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
889 .subvendor = PCI_ANY_ID,
890 .subdevice = PCI_ANY_ID,
891 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
892 },
893
894 {
895 .vendor = PCI_VENDOR_ID_JMICRON,
896 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
897 .subvendor = PCI_ANY_ID,
898 .subdevice = PCI_ANY_ID,
899 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 900 },
901
a7a6186c
NP		 902 {
903 .vendor = PCI_VENDOR_ID_SYSKONNECT,
904 .device = 0x8000,
905 .subvendor = PCI_ANY_ID,
906 .subdevice = PCI_ANY_ID,
907 .driver_data = (kernel_ulong_t)&sdhci_syskt,
908 },
909
557b0697
HW		 910 {
911 .vendor = PCI_VENDOR_ID_VIA,
912 .device = 0x95d0,
913 .subvendor = PCI_ANY_ID,
914 .subdevice = PCI_ANY_ID,
915 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 916 },
917
918 {
919 .vendor = PCI_VENDOR_ID_REALTEK,
920 .device = 0x5250,
921 .subvendor = PCI_ANY_ID,
922 .subdevice = PCI_ANY_ID,
923 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 924 },
925
43e968ce
DB		 926 {
927 .vendor = PCI_VENDOR_ID_INTEL,
928 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
929 .subvendor = PCI_ANY_ID,
930 .subdevice = PCI_ANY_ID,
931 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
932 },
933
29229052
XS		 934 {
935 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 936 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
937 .subvendor = PCI_ANY_ID,
938 .subdevice = PCI_ANY_ID,
939 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
940 },
941
942 {
943 .vendor = PCI_VENDOR_ID_INTEL,
944 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
945 .subvendor = PCI_ANY_ID,
946 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 947 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
948 },
949
950 {
951 .vendor = PCI_VENDOR_ID_INTEL,
952 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
953 .subvendor = PCI_ANY_ID,
954 .subdevice = PCI_ANY_ID,
955 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 956 },
957
958 {
959 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 960 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
961 .subvendor = PCI_ANY_ID,
962 .subdevice = PCI_ANY_ID,
963 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
964 },
965
966 {
967 .vendor = PCI_VENDOR_ID_INTEL,
968 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
969 .subvendor = PCI_ANY_ID,
970 .subdevice = PCI_ANY_ID,
0d013bcf 971 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 972 },
973
974 {
975 .vendor = PCI_VENDOR_ID_INTEL,
976 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
977 .subvendor = PCI_ANY_ID,
978 .subdevice = PCI_ANY_ID,
0d013bcf 979 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 980 },
981
982 {
983 .vendor = PCI_VENDOR_ID_INTEL,
984 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
985 .subvendor = PCI_ANY_ID,
986 .subdevice = PCI_ANY_ID,
0d013bcf 987 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 988 },
989
990 {
991 .vendor = PCI_VENDOR_ID_INTEL,
992 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
993 .subvendor = PCI_ANY_ID,
994 .subdevice = PCI_ANY_ID,
0d013bcf 995 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 996 },
997
296e0b03
AS		 998 {
999 .vendor = PCI_VENDOR_ID_INTEL,
1000 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1001 .subvendor = PCI_ANY_ID,
1002 .subdevice = PCI_ANY_ID,
1003 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1004 },
1005
1006 {
1007 .vendor = PCI_VENDOR_ID_INTEL,
1008 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1009 .subvendor = PCI_ANY_ID,
1010 .subdevice = PCI_ANY_ID,
1011 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1012 },
1013
728ef3d1
AH		 1014 {
1015 .vendor = PCI_VENDOR_ID_INTEL,
1016 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1017 .subvendor = PCI_ANY_ID,
1018 .subdevice = PCI_ANY_ID,
1019 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1020 },
1021
1022 {
1023 .vendor = PCI_VENDOR_ID_INTEL,
1024 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1025 .subvendor = PCI_ANY_ID,
1026 .subdevice = PCI_ANY_ID,
1027 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1028 },
1029
1030 {
1031 .vendor = PCI_VENDOR_ID_INTEL,
1032 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1033 .subvendor = PCI_ANY_ID,
1034 .subdevice = PCI_ANY_ID,
1035 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1036 },
1037
30d025c0
AH		 1038 {
1039 .vendor = PCI_VENDOR_ID_INTEL,
1040 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1041 .subvendor = PCI_ANY_ID,
1042 .subdevice = PCI_ANY_ID,
1043 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1044 },
1045
066173b6
AC		 1046 {
1047 .vendor = PCI_VENDOR_ID_INTEL,
1048 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1049 .subvendor = PCI_ANY_ID,
1050 .subdevice = PCI_ANY_ID,
1051 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1052 },
1053
1054 {
1055 .vendor = PCI_VENDOR_ID_INTEL,
1056 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1057 .subvendor = PCI_ANY_ID,
1058 .subdevice = PCI_ANY_ID,
1059 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1060 },
1061
1062 {
1063 .vendor = PCI_VENDOR_ID_INTEL,
1064 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1065 .subvendor = PCI_ANY_ID,
1066 .subdevice = PCI_ANY_ID,
1067 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1068 },
d052068a
EE		 1069
1070 {
1071 .vendor = PCI_VENDOR_ID_INTEL,
1072 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1073 .subvendor = PCI_ANY_ID,
1074 .subdevice = PCI_ANY_ID,
1075 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1076 },
1077
1078 {
1079 .vendor = PCI_VENDOR_ID_INTEL,
1080 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1081 .subvendor = PCI_ANY_ID,
1082 .subdevice = PCI_ANY_ID,
1083 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1084 },
1085
1086 {
1087 .vendor = PCI_VENDOR_ID_INTEL,
1088 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1089 .subvendor = PCI_ANY_ID,
1090 .subdevice = PCI_ANY_ID,
1091 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1092 },
1093
1094 {
1095 .vendor = PCI_VENDOR_ID_INTEL,
1096 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1097 .subvendor = PCI_ANY_ID,
1098 .subdevice = PCI_ANY_ID,
1099 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1100 },
1101
1102 {
1103 .vendor = PCI_VENDOR_ID_INTEL,
1104 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1105 .subvendor = PCI_ANY_ID,
1106 .subdevice = PCI_ANY_ID,
1107 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1108 },
1109
8776a165
DC		 1110 {
1111 .vendor = PCI_VENDOR_ID_INTEL,
1112 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1113 .subvendor = PCI_ANY_ID,
1114 .subdevice = PCI_ANY_ID,
1115 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1116 },
1f7f2652
AH		 1117
1118 {
1119 .vendor = PCI_VENDOR_ID_INTEL,
1120 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1121 .subvendor = PCI_ANY_ID,
1122 .subdevice = PCI_ANY_ID,
1123 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1124 },
1125
1126 {
1127 .vendor = PCI_VENDOR_ID_INTEL,
1128 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1129 .subvendor = PCI_ANY_ID,
1130 .subdevice = PCI_ANY_ID,
1131 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1132 },
1133
1134 {
1135 .vendor = PCI_VENDOR_ID_INTEL,
1136 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1137 .subvendor = PCI_ANY_ID,
1138 .subdevice = PCI_ANY_ID,
1139 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1140 },
1141
06bf9c56
AH		 1142 {
1143 .vendor = PCI_VENDOR_ID_INTEL,
1144 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1145 .subvendor = PCI_ANY_ID,
1146 .subdevice = PCI_ANY_ID,
1147 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1148 },
1149
4fd4c065
AH		 1150 {
1151 .vendor = PCI_VENDOR_ID_INTEL,
1152 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1153 .subvendor = PCI_ANY_ID,
1154 .subdevice = PCI_ANY_ID,
1155 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1156 },
1157
1158 {
1159 .vendor = PCI_VENDOR_ID_INTEL,
1160 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1164 },
1165
1166 {
1167 .vendor = PCI_VENDOR_ID_INTEL,
1168 .device = PCI_DEVICE_ID_INTEL_BXT_SD,
1169 .subvendor = PCI_ANY_ID,
1170 .subdevice = PCI_ANY_ID,
1171 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1172 },
1173
1174 {
1175 .vendor = PCI_VENDOR_ID_INTEL,
1176 .device = PCI_DEVICE_ID_INTEL_APL_EMMC,
1177 .subvendor = PCI_ANY_ID,
1178 .subdevice = PCI_ANY_ID,
1179 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1180 },
1181
1182 {
1183 .vendor = PCI_VENDOR_ID_INTEL,
1184 .device = PCI_DEVICE_ID_INTEL_APL_SDIO,
1185 .subvendor = PCI_ANY_ID,
1186 .subdevice = PCI_ANY_ID,
1187 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1188 },
1189
1190 {
1191 .vendor = PCI_VENDOR_ID_INTEL,
1192 .device = PCI_DEVICE_ID_INTEL_APL_SD,
1193 .subvendor = PCI_ANY_ID,
1194 .subdevice = PCI_ANY_ID,
1195 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1196 },
1197
26daa1ed
JL		 1198 {
1199 .vendor = PCI_VENDOR_ID_O2,
1200 .device = PCI_DEVICE_ID_O2_8120,
1201 .subvendor = PCI_ANY_ID,
1202 .subdevice = PCI_ANY_ID,
1203 .driver_data = (kernel_ulong_t)&sdhci_o2,
1204 },
1205
1206 {
1207 .vendor = PCI_VENDOR_ID_O2,
1208 .device = PCI_DEVICE_ID_O2_8220,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
1211 .driver_data = (kernel_ulong_t)&sdhci_o2,
1212 },
1213
1214 {
1215 .vendor = PCI_VENDOR_ID_O2,
1216 .device = PCI_DEVICE_ID_O2_8221,
1217 .subvendor = PCI_ANY_ID,
1218 .subdevice = PCI_ANY_ID,
1219 .driver_data = (kernel_ulong_t)&sdhci_o2,
1220 },
1221
1222 {
1223 .vendor = PCI_VENDOR_ID_O2,
1224 .device = PCI_DEVICE_ID_O2_8320,
1225 .subvendor = PCI_ANY_ID,
1226 .subdevice = PCI_ANY_ID,
1227 .driver_data = (kernel_ulong_t)&sdhci_o2,
1228 },
1229
1230 {
1231 .vendor = PCI_VENDOR_ID_O2,
1232 .device = PCI_DEVICE_ID_O2_8321,
1233 .subvendor = PCI_ANY_ID,
1234 .subdevice = PCI_ANY_ID,
1235 .driver_data = (kernel_ulong_t)&sdhci_o2,
1236 },
1237
01acf691
AL		 1238 {
1239 .vendor = PCI_VENDOR_ID_O2,
1240 .device = PCI_DEVICE_ID_O2_FUJIN2,
1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
1243 .driver_data = (kernel_ulong_t)&sdhci_o2,
1244 },
1245
1246 {
1247 .vendor = PCI_VENDOR_ID_O2,
1248 .device = PCI_DEVICE_ID_O2_SDS0,
1249 .subvendor = PCI_ANY_ID,
1250 .subdevice = PCI_ANY_ID,
1251 .driver_data = (kernel_ulong_t)&sdhci_o2,
1252 },
1253
1254 {
1255 .vendor = PCI_VENDOR_ID_O2,
1256 .device = PCI_DEVICE_ID_O2_SDS1,
1257 .subvendor = PCI_ANY_ID,
1258 .subdevice = PCI_ANY_ID,
1259 .driver_data = (kernel_ulong_t)&sdhci_o2,
1260 },
1261
1262 {
1263 .vendor = PCI_VENDOR_ID_O2,
1264 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1265 .subvendor = PCI_ANY_ID,
1266 .subdevice = PCI_ANY_ID,
1267 .driver_data = (kernel_ulong_t)&sdhci_o2,
1268 },
1269
1270 {
1271 .vendor = PCI_VENDOR_ID_O2,
1272 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1273 .subvendor = PCI_ANY_ID,
1274 .subdevice = PCI_ANY_ID,
1275 .driver_data = (kernel_ulong_t)&sdhci_o2,
1276 },
d44f88da
VW		 1277 {
1278 .vendor = PCI_VENDOR_ID_AMD,
1279 .device = PCI_ANY_ID,
1280 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1281 .class_mask = 0xFFFF00,
1282 .subvendor = PCI_ANY_ID,
1283 .subdevice = PCI_ANY_ID,
1284 .driver_data = (kernel_ulong_t)&sdhci_amd,
1285 },
b8c86fc5
PO		 1286 { /* Generic SD host controller */
1287 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1288 },
1289
1290 { /* end: all zeroes */ },
1291};
1292
1293MODULE_DEVICE_TABLE(pci, pci_ids);
1294
b8c86fc5
PO		 1295/*****************************************************************************\
1296 * *
1297 * SDHCI core callbacks *
1298 * *
1299\*****************************************************************************/
1300
1301static int sdhci_pci_enable_dma(struct sdhci_host *host)
1302{
1303 struct sdhci_pci_slot *slot;
1304 struct pci_dev *pdev;
3828ecaa 1305 int ret = -1;
b8c86fc5
PO		 1306
1307 slot = sdhci_priv(host);
1308 pdev = slot->chip->pdev;
1309
1310 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1311 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1312 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1313 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1314 "doesn't fully claim to support it.\n");
1315 }
1316
3828ecaa
AH		 1317 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1318 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1319 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1320 } else {
1321 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1322 if (ret)
1323 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1324 }
1325 }
1326 if (ret)
1327 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 1328 if (ret)
1329 return ret;
1330
1331 pci_set_master(pdev);
1332
1333 return 0;
1334}
1335
2317f56c 1336static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1337{
1338 u8 ctrl;
1339
1340 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1341
1342 switch (width) {
1343 case MMC_BUS_WIDTH_8:
1344 ctrl |= SDHCI_CTRL_8BITBUS;
1345 ctrl &= ~SDHCI_CTRL_4BITBUS;
1346 break;
1347 case MMC_BUS_WIDTH_4:
1348 ctrl |= SDHCI_CTRL_4BITBUS;
1349 ctrl &= ~SDHCI_CTRL_8BITBUS;
1350 break;
1351 default:
1352 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1353 break;
1354 }
1355
1356 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1357}
1358
c9faff6c 1359static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1360{
1361 struct sdhci_pci_slot *slot = sdhci_priv(host);
1362 int rst_n_gpio = slot->rst_n_gpio;
1363
1364 if (!gpio_is_valid(rst_n_gpio))
1365 return;
1366 gpio_set_value_cansleep(rst_n_gpio, 0);
1367 /* For eMMC, minimum is 1us but give it 10us for good measure */
1368 udelay(10);
1369 gpio_set_value_cansleep(rst_n_gpio, 1);
1370 /* For eMMC, minimum is 200us but give it 300us for good measure */
1371 usleep_range(300, 1000);
1372}
1373
c9faff6c
AH		 1374static void sdhci_pci_hw_reset(struct sdhci_host *host)
1375{
1376 struct sdhci_pci_slot *slot = sdhci_priv(host);
1377
1378 if (slot->hw_reset)
1379 slot->hw_reset(host);
1380}
1381
e1bfad6d
AH		 1382static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1383 struct mmc_card *card,
1384 unsigned int max_dtr, int host_drv,
1385 int card_drv, int *drv_type)
1386{
1387 struct sdhci_pci_slot *slot = sdhci_priv(host);
1388
1389 if (!slot->select_drive_strength)
1390 return 0;
1391
1392 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1393 card_drv, drv_type);
1394}
1395
c915568d 1396static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1397 .set_clock = sdhci_set_clock,
b8c86fc5 1398 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1399 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1400 .reset = sdhci_reset,
96d7b78c 1401 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1402 .hw_reset = sdhci_pci_hw_reset,
e1bfad6d 1403 .select_drive_strength = sdhci_pci_select_drive_strength,
b8c86fc5
PO		 1404};
1405
1406/*****************************************************************************\
1407 * *
1408 * Suspend/resume *
1409 * *
1410\*****************************************************************************/
1411
1412#ifdef CONFIG_PM
1413
29495aa0 1414static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1415{
29495aa0 1416 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1417 struct sdhci_pci_chip *chip;
1418 struct sdhci_pci_slot *slot;
5f619704 1419 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1420 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1421 int i, ret;
1422
1423 chip = pci_get_drvdata(pdev);
1424 if (!chip)
1425 return 0;
1426
b177bc91 1427 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1428 slot = chip->slots[i];
1429 if (!slot)
1430 continue;
1431
29495aa0 1432 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1433
b678b91f
AL		 1434 if (ret)
1435 goto err_pci_suspend;
2f4cbb3d 1436
5f619704
DD		 1437 slot_pm_flags = slot->host->mmc->pm_flags;
1438 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1439 sdhci_enable_irq_wakeups(slot->host);
1440
1441 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1442 }
1443
4489428a 1444 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1445 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1446 if (ret)
1447 goto err_pci_suspend;
4489428a
PO		 1448 }
1449
2f4cbb3d 1450 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1451 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1452 device_init_wakeup(dev, true);
1453 else
1454 device_init_wakeup(dev, false);
1455 } else
1456 device_init_wakeup(dev, false);
b8c86fc5
PO		 1457
1458 return 0;
b678b91f
AL		 1459
1460err_pci_suspend:
1461 while (--i >= 0)
1462 sdhci_resume_host(chip->slots[i]->host);
1463 return ret;
b8c86fc5
PO		 1464}
1465
29495aa0 1466static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1467{
29495aa0 1468 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1469 struct sdhci_pci_chip *chip;
1470 struct sdhci_pci_slot *slot;
1471 int i, ret;
1472
1473 chip = pci_get_drvdata(pdev);
1474 if (!chip)
1475 return 0;
1476
45211e21
PO		 1477 if (chip->fixes && chip->fixes->resume) {
1478 ret = chip->fixes->resume(chip);
1479 if (ret)
1480 return ret;
1481 }
1482
b177bc91 1483 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1484 slot = chip->slots[i];
1485 if (!slot)
1486 continue;
1487
1488 ret = sdhci_resume_host(slot->host);
1489 if (ret)
1490 return ret;
1491 }
1492
1493 return 0;
1494}
1495
66fd8ad5
AH		 1496static int sdhci_pci_runtime_suspend(struct device *dev)
1497{
923a231c 1498 struct pci_dev *pdev = to_pci_dev(dev);
66fd8ad5
AH		 1499 struct sdhci_pci_chip *chip;
1500 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1501 int i, ret;
1502
1503 chip = pci_get_drvdata(pdev);
1504 if (!chip)
1505 return 0;
1506
1507 for (i = 0; i < chip->num_slots; i++) {
1508 slot = chip->slots[i];
1509 if (!slot)
1510 continue;
1511
1512 ret = sdhci_runtime_suspend_host(slot->host);
1513
b678b91f
AL		 1514 if (ret)
1515 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1516 }
1517
1518 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1519 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1520 if (ret)
1521 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1522 }
1523
1524 return 0;
b678b91f
AL		 1525
1526err_pci_runtime_suspend:
1527 while (--i >= 0)
1528 sdhci_runtime_resume_host(chip->slots[i]->host);
1529 return ret;
66fd8ad5
AH		 1530}
1531
1532static int sdhci_pci_runtime_resume(struct device *dev)
1533{
923a231c 1534 struct pci_dev *pdev = to_pci_dev(dev);
66fd8ad5
AH		 1535 struct sdhci_pci_chip *chip;
1536 struct sdhci_pci_slot *slot;
1537 int i, ret;
1538
1539 chip = pci_get_drvdata(pdev);
1540 if (!chip)
1541 return 0;
1542
1543 if (chip->fixes && chip->fixes->resume) {
1544 ret = chip->fixes->resume(chip);
1545 if (ret)
1546 return ret;
1547 }
1548
1549 for (i = 0; i < chip->num_slots; i++) {
1550 slot = chip->slots[i];
1551 if (!slot)
1552 continue;
1553
1554 ret = sdhci_runtime_resume_host(slot->host);
1555 if (ret)
1556 return ret;
1557 }
1558
1559 return 0;
1560}
1561
162d6f98
RW		 1562#else /* CONFIG_PM */
1563
1564#define sdhci_pci_suspend NULL
1565#define sdhci_pci_resume NULL
1566
1567#endif /* CONFIG_PM */
66fd8ad5
AH		 1568
1569static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1570 .suspend = sdhci_pci_suspend,
1571 .resume = sdhci_pci_resume,
f3a92b1a 1572 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1573 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1574};
1575
b8c86fc5
PO		 1576/*****************************************************************************\
1577 * *
1578 * Device probing/removal *
1579 * *
1580\*****************************************************************************/
1581
c3be1efd 1582static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1583 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1584 int slotno)
b8c86fc5
PO		 1585{
1586 struct sdhci_pci_slot *slot;
1587 struct sdhci_host *host;
52c506f0 1588 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1589
1590 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1591 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1592 return ERR_PTR(-ENODEV);
1593 }
1594
90b3e6c5 1595 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1596 dev_err(&pdev->dev, "Invalid iomem size. You may "
1597 "experience problems.\n");
1598 }
1599
1600 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1601 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1602 return ERR_PTR(-ENODEV);
1603 }
1604
1605 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1606 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1607 return ERR_PTR(-ENODEV);
1608 }
1609
1610 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1611 if (IS_ERR(host)) {
c60a32cd 1612 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1613 return ERR_CAST(host);
b8c86fc5
PO		 1614 }
1615
1616 slot = sdhci_priv(host);
1617
1618 slot->chip = chip;
1619 slot->host = host;
1620 slot->pci_bar = bar;
0f201655 1621 slot->rst_n_gpio = -EINVAL;
c5e027a4 1622 slot->cd_gpio = -EINVAL;
ff59c520 1623 slot->cd_idx = -1;
b8c86fc5 1624
52c506f0
AH		 1625 /* Retrieve platform data if there is any */
1626 if (*sdhci_pci_get_data)
1627 slot->data = sdhci_pci_get_data(pdev, slotno);
1628
1629 if (slot->data) {
1630 if (slot->data->setup) {
1631 ret = slot->data->setup(slot->data);
1632 if (ret) {
1633 dev_err(&pdev->dev, "platform setup failed\n");
1634 goto free;
1635 }
1636 }
c5e027a4
AH		 1637 slot->rst_n_gpio = slot->data->rst_n_gpio;
1638 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1639 }
1640
b8c86fc5
PO		 1641 host->hw_name = "PCI";
1642 host->ops = &sdhci_pci_ops;
1643 host->quirks = chip->quirks;
f3c55a7b 1644 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1645
1646 host->irq = pdev->irq;
1647
1648 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1649 if (ret) {
1650 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1651 goto cleanup;
b8c86fc5
PO		 1652 }
1653
092f82ed 1654 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1655 if (!host->ioaddr) {
1656 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1657 ret = -ENOMEM;
b8c86fc5
PO		 1658 goto release;
1659 }
1660
4489428a
PO		 1661 if (chip->fixes && chip->fixes->probe_slot) {
1662 ret = chip->fixes->probe_slot(slot);
1663 if (ret)
1664 goto unmap;
1665 }
1666
c5e027a4
AH		 1667 if (gpio_is_valid(slot->rst_n_gpio)) {
1668 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1669 gpio_direction_output(slot->rst_n_gpio, 1);
1670 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1671 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1672 } else {
1673 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1674 slot->rst_n_gpio = -EINVAL;
1675 }
1676 }
1677
2f4cbb3d 1678 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1679 host->mmc->slotno = slotno;
a08b17be 1680 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1681
ff59c520
AH		 1682 if (slot->cd_idx >= 0 &&
1683 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1684 slot->cd_override_level, 0, NULL)) {
1685 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1686 slot->cd_idx = -1;
1687 }
1688
b8c86fc5
PO		 1689 ret = sdhci_add_host(host);
1690 if (ret)
4489428a 1691 goto remove;
b8c86fc5 1692
c5e027a4
AH		 1693 sdhci_pci_add_own_cd(slot);
1694
77a0122e
AH		 1695 /*
1696 * Check if the chip needs a separate GPIO for card detect to wake up
1697 * from runtime suspend. If it is not there, don't allow runtime PM.
1698 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1699 */
945be38c 1700 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1701 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1702 chip->allow_runtime_pm = false;
1703
b8c86fc5
PO		 1704 return slot;
1705
4489428a 1706remove:
c5e027a4
AH		 1707 if (gpio_is_valid(slot->rst_n_gpio))
1708 gpio_free(slot->rst_n_gpio);
1709
4489428a 1710 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1711 chip->fixes->remove_slot(slot, 0);
4489428a 1712
b8c86fc5
PO		 1713unmap:
1714 iounmap(host->ioaddr);
1715
1716release:
1717 pci_release_region(pdev, bar);
c60a32cd 1718
52c506f0
AH		 1719cleanup:
1720 if (slot->data && slot->data->cleanup)
1721 slot->data->cleanup(slot->data);
1722
c60a32cd 1723free:
b8c86fc5
PO		 1724 sdhci_free_host(host);
1725
1726 return ERR_PTR(ret);
1727}
1728
1729static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1730{
1e72859e
PO		 1731 int dead;
1732 u32 scratch;
1733
c5e027a4
AH		 1734 sdhci_pci_remove_own_cd(slot);
1735
1e72859e
PO		 1736 dead = 0;
1737 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1738 if (scratch == (u32)-1)
1739 dead = 1;
1740
1741 sdhci_remove_host(slot->host, dead);
4489428a 1742
c5e027a4
AH		 1743 if (gpio_is_valid(slot->rst_n_gpio))
1744 gpio_free(slot->rst_n_gpio);
1745
4489428a 1746 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1747 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1748
52c506f0
AH		 1749 if (slot->data && slot->data->cleanup)
1750 slot->data->cleanup(slot->data);
1751
b8c86fc5 1752 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1753
b8c86fc5
PO		 1754 sdhci_free_host(slot->host);
1755}
1756
c3be1efd 1757static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1758{
1759 pm_runtime_put_noidle(dev);
1760 pm_runtime_allow(dev);
1761 pm_runtime_set_autosuspend_delay(dev, 50);
1762 pm_runtime_use_autosuspend(dev);
1763 pm_suspend_ignore_children(dev, 1);
1764}
1765
6e0ee714 1766static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1767{
1768 pm_runtime_forbid(dev);
1769 pm_runtime_get_noresume(dev);
1770}
1771
c3be1efd 1772static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1773 const struct pci_device_id *ent)
1774{
1775 struct sdhci_pci_chip *chip;
1776 struct sdhci_pci_slot *slot;
1777
cf5e23e1 1778 u8 slots, first_bar;
b8c86fc5
PO		 1779 int ret, i;
1780
1781 BUG_ON(pdev == NULL);
1782 BUG_ON(ent == NULL);
1783
b8c86fc5 1784 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1785 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1786
1787 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1788 if (ret)
1789 return ret;
1790
1791 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1792 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1793 if (slots == 0)
1794 return -ENODEV;
1795
1796 BUG_ON(slots > MAX_SLOTS);
1797
1798 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1799 if (ret)
1800 return ret;
1801
1802 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1803
1804 if (first_bar > 5) {
1805 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1806 return -ENODEV;
1807 }
1808
1809 ret = pci_enable_device(pdev);
1810 if (ret)
1811 return ret;
1812
1813 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1814 if (!chip) {
1815 ret = -ENOMEM;
1816 goto err;
1817 }
1818
1819 chip->pdev = pdev;
b177bc91 1820 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1821 if (chip->fixes) {
22606405 1822 chip->quirks = chip->fixes->quirks;
f3c55a7b 1823 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1824 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1825 }
b8c86fc5
PO		 1826 chip->num_slots = slots;
1827
1828 pci_set_drvdata(pdev, chip);
1829
22606405
PO		 1830 if (chip->fixes && chip->fixes->probe) {
1831 ret = chip->fixes->probe(chip);
1832 if (ret)
1833 goto free;
1834 }
1835
225d85fe
AC		 1836 slots = chip->num_slots; /* Quirk may have changed this */
1837
b177bc91 1838 for (i = 0; i < slots; i++) {
52c506f0 1839 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1840 if (IS_ERR(slot)) {
b177bc91 1841 for (i--; i >= 0; i--)
b8c86fc5
PO		 1842 sdhci_pci_remove_slot(chip->slots[i]);
1843 ret = PTR_ERR(slot);
1844 goto free;
1845 }
1846
1847 chip->slots[i] = slot;
1848 }
1849
c43fd774
AH		 1850 if (chip->allow_runtime_pm)
1851 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1852
b8c86fc5
PO		 1853 return 0;
1854
1855free:
1856 pci_set_drvdata(pdev, NULL);
1857 kfree(chip);
1858
1859err:
1860 pci_disable_device(pdev);
1861 return ret;
1862}
1863
6e0ee714 1864static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1865{
1866 int i;
1867 struct sdhci_pci_chip *chip;
1868
1869 chip = pci_get_drvdata(pdev);
1870
1871 if (chip) {
c43fd774
AH		 1872 if (chip->allow_runtime_pm)
1873 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1874
b177bc91 1875 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1876 sdhci_pci_remove_slot(chip->slots[i]);
1877
1878 pci_set_drvdata(pdev, NULL);
1879 kfree(chip);
1880 }
1881
1882 pci_disable_device(pdev);
1883}
1884
1885static struct pci_driver sdhci_driver = {
b177bc91 1886 .name = "sdhci-pci",
b8c86fc5 1887 .id_table = pci_ids,
b177bc91 1888 .probe = sdhci_pci_probe,
0433c143 1889 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1890 .driver = {
1891 .pm = &sdhci_pci_pm_ops
1892 },
b8c86fc5
PO		 1893};
1894
acc69646 1895module_pci_driver(sdhci_driver);
b8c86fc5 1896
32710e8f 1897MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1898MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1899MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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