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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...
[deliverable/linux.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655 25#include <linux/gpio.h>
66fd8ad5 26#include <linux/pm_runtime.h>
ff59c520 27#include <linux/mmc/slot-gpio.h>
52c506f0 28#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 29
30#include "sdhci.h"
522624f9 31#include "sdhci-pci.h"
01acf691 32#include "sdhci-pci-o2micro.h"
22606405
PO		 33
34/*****************************************************************************\
35 * *
36 * Hardware specific quirk handling *
37 * *
38\*****************************************************************************/
39
40static int ricoh_probe(struct sdhci_pci_chip *chip)
41{
c99436fb
CB		 42 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
43 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 44 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 45 return 0;
46}
47
48static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
49{
50 slot->host->caps =
51 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
52 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 53
ccc92c23
ML		 54 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
55 & SDHCI_CLOCK_BASE_MASK) |
56
57 SDHCI_TIMEOUT_CLK_UNIT |
58 SDHCI_CAN_VDD_330 |
1a1f1f04 59 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 60 SDHCI_CAN_DO_SDMA;
61 return 0;
62}
63
64static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
65{
66 /* Apply a delay to allow controller to settle */
67 /* Otherwise it becomes confused if card state changed
68 during suspend */
69 msleep(500);
22606405
PO		 70 return 0;
71}
72
73static const struct sdhci_pci_fixes sdhci_ricoh = {
74 .probe = ricoh_probe,
84938294
VK		 75 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
76 SDHCI_QUIRK_FORCE_DMA |
77 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 78};
79
ccc92c23
ML		 80static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
81 .probe_slot = ricoh_mmc_probe_slot,
82 .resume = ricoh_mmc_resume,
83 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
84 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
85 SDHCI_QUIRK_NO_CARD_NO_RESET |
86 SDHCI_QUIRK_MISSING_CAPS
87};
88
22606405
PO		 89static const struct sdhci_pci_fixes sdhci_ene_712 = {
90 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
91 SDHCI_QUIRK_BROKEN_DMA,
92};
93
94static const struct sdhci_pci_fixes sdhci_ene_714 = {
95 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
96 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
97 SDHCI_QUIRK_BROKEN_DMA,
98};
99
100static const struct sdhci_pci_fixes sdhci_cafe = {
101 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 102 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 103 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 104 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 105};
106
43e968ce
DB		 107static const struct sdhci_pci_fixes sdhci_intel_qrk = {
108 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
109};
110
68077b02
ML		 111static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
112{
113 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
114 return 0;
115}
116
f9ee3eab
AC		 117/*
118 * ADMA operation is disabled for Moorestown platform due to
119 * hardware bugs.
120 */
35ac6f08 121static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 122{
123 /*
35ac6f08
JP		 124 * slots number is fixed here for MRST as SDIO3/5 are never used and
125 * have hardware bugs.
f9ee3eab
AC		 126 */
127 chip->num_slots = 1;
128 return 0;
129}
130
296e0b03
AS		 131static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
132{
133 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
134 return 0;
135}
136
66fd8ad5
AH		 137#ifdef CONFIG_PM_RUNTIME
138
c5e027a4 139static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 140{
141 struct sdhci_pci_slot *slot = dev_id;
142 struct sdhci_host *host = slot->host;
143
144 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
145 return IRQ_HANDLED;
146}
147
c5e027a4 148static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 149{
c5e027a4 150 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 151
152 slot->cd_gpio = -EINVAL;
153 slot->cd_irq = -EINVAL;
154
c5e027a4
AH		 155 if (!gpio_is_valid(gpio))
156 return;
157
66fd8ad5
AH		 158 err = gpio_request(gpio, "sd_cd");
159 if (err < 0)
160 goto out;
161
162 err = gpio_direction_input(gpio);
163 if (err < 0)
164 goto out_free;
165
166 irq = gpio_to_irq(gpio);
167 if (irq < 0)
168 goto out_free;
169
c5e027a4 170 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 171 IRQF_TRIGGER_FALLING, "sd_cd", slot);
172 if (err)
173 goto out_free;
174
175 slot->cd_gpio = gpio;
176 slot->cd_irq = irq;
66fd8ad5 177
c5e027a4 178 return;
66fd8ad5
AH		 179
180out_free:
181 gpio_free(gpio);
182out:
183 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 184}
185
c5e027a4 186static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 187{
188 if (slot->cd_irq >= 0)
189 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 190 if (gpio_is_valid(slot->cd_gpio))
191 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 192}
193
194#else
195
c5e027a4
AH		 196static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
197{
198}
199
200static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
201{
202}
66fd8ad5
AH		 203
204#endif
205
0d013bcf
AH		 206static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
207{
66fd8ad5 208 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 209 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
210 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 211 return 0;
212}
213
93933508
AH		 214static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
215{
012e4671 216 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 217 return 0;
218}
219
f9ee3eab
AC		 220static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
221 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 222 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 223};
224
35ac6f08 225static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 226 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 227 .probe = mrst_hc_probe,
f9ee3eab
AC		 228};
229
29229052
XS		 230static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
231 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 232 .allow_runtime_pm = true,
77a0122e 233 .own_cd_for_runtime_pm = true,
29229052
XS		 234};
235
0d013bcf
AH		 236static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
237 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 238 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 239 .allow_runtime_pm = true,
93933508 240 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 241};
242
243static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 245 .allow_runtime_pm = true,
0d013bcf 246 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 247};
248
296e0b03
AS		 249static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
250 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
251 .probe_slot = pch_hc_probe_slot,
252};
253
c9faff6c
AH		 254static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
255{
256 u8 reg;
257
258 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
259 reg |= 0x10;
260 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
261 /* For eMMC, minimum is 1us but give it 9us for good measure */
262 udelay(9);
263 reg &= ~0x10;
264 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
265 /* For eMMC, minimum is 200us but give it 300us for good measure */
266 usleep_range(300, 1000);
267}
268
728ef3d1
AH		 269static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
270{
c9faff6c 271 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
f25c3372 272 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR;
728ef3d1 273 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 274 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 275 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
276 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
728ef3d1
AH		 277 return 0;
278}
279
280static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
281{
282 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
283 return 0;
284}
285
ff59c520
AH		 286static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
287{
288 slot->cd_con_id = NULL;
289 slot->cd_idx = 0;
290 slot->cd_override_level = true;
291 return 0;
292}
293
728ef3d1
AH		 294static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
295 .allow_runtime_pm = true,
296 .probe_slot = byt_emmc_probe_slot,
e58e4a0d
AH		 297 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
298 SDHCI_QUIRK2_STOP_WITH_TC,
728ef3d1
AH		 299};
300
301static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
b7574bad
GY		 302 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
303 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 304 .allow_runtime_pm = true,
305 .probe_slot = byt_sdio_probe_slot,
306};
307
308static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
b7574bad 309 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 310 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
311 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 312 .allow_runtime_pm = true,
77a0122e 313 .own_cd_for_runtime_pm = true,
ff59c520 314 .probe_slot = byt_sd_probe_slot,
728ef3d1
AH		 315};
316
8776a165
DC		 317/* Define Host controllers for Intel Merrifield platform */
318#define INTEL_MRFL_EMMC_0 0
319#define INTEL_MRFL_EMMC_1 1
320
321static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
322{
323 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
324 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
325 /* SD support is not ready yet */
326 return -ENODEV;
327
328 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
329 MMC_CAP_1_8V_DDR;
330
331 return 0;
332}
333
334static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
335 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 336 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
337 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 338 .allow_runtime_pm = true,
8776a165
DC		 339 .probe_slot = intel_mrfl_mmc_probe_slot,
340};
341
26daa1ed
JL		 342/* O2Micro extra registers */
343#define O2_SD_LOCK_WP 0xD3
344#define O2_SD_MULTI_VCC3V 0xEE
345#define O2_SD_CLKREQ 0xEC
346#define O2_SD_CAPS 0xE0
347#define O2_SD_ADMA1 0xE2
348#define O2_SD_ADMA2 0xE7
349#define O2_SD_INF_MOD 0xF1
350
45211e21
PO		 351static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
352{
353 u8 scratch;
354 int ret;
355
356 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
357 if (ret)
358 return ret;
359
360 /*
361 * Turn PMOS on [bit 0], set over current detection to 2.4 V
362 * [bit 1:2] and enable over current debouncing [bit 6].
363 */
364 if (on)
365 scratch |= 0x47;
366 else
367 scratch &= ~0x47;
368
369 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
370 if (ret)
371 return ret;
372
373 return 0;
374}
375
376static int jmicron_probe(struct sdhci_pci_chip *chip)
377{
378 int ret;
8f230f45 379 u16 mmcdev = 0;
45211e21 380
93fc48c7
PO		 381 if (chip->pdev->revision == 0) {
382 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
383 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 384 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 385 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 386 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 387 }
388
4489428a
PO		 389 /*
390 * JMicron chips can have two interfaces to the same hardware
391 * in order to work around limitations in Microsoft's driver.
392 * We need to make sure we only bind to one of them.
393 *
394 * This code assumes two things:
395 *
396 * 1. The PCI code adds subfunctions in order.
397 *
398 * 2. The MMC interface has a lower subfunction number
399 * than the SD interface.
400 */
8f230f45
TI		 401 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
402 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
403 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
404 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
405
406 if (mmcdev) {
4489428a
PO		 407 struct pci_dev *sd_dev;
408
409 sd_dev = NULL;
410 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 411 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 412 if ((PCI_SLOT(chip->pdev->devfn) ==
413 PCI_SLOT(sd_dev->devfn)) &&
414 (chip->pdev->bus == sd_dev->bus))
415 break;
416 }
417
418 if (sd_dev) {
419 pci_dev_put(sd_dev);
420 dev_info(&chip->pdev->dev, "Refusing to bind to "
421 "secondary interface.\n");
422 return -ENODEV;
423 }
424 }
425
45211e21
PO		 426 /*
427 * JMicron chips need a bit of a nudge to enable the power
428 * output pins.
429 */
430 ret = jmicron_pmos(chip, 1);
431 if (ret) {
432 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
433 return ret;
434 }
435
82b0e23a
TI		 436 /* quirk for unsable RO-detection on JM388 chips */
437 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
438 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
439 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
440
45211e21
PO		 441 return 0;
442}
443
4489428a
PO		 444static void jmicron_enable_mmc(struct sdhci_host *host, int on)
445{
446 u8 scratch;
447
448 scratch = readb(host->ioaddr + 0xC0);
449
450 if (on)
451 scratch |= 0x01;
452 else
453 scratch &= ~0x01;
454
455 writeb(scratch, host->ioaddr + 0xC0);
456}
457
458static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
459{
2134a922
PO		 460 if (slot->chip->pdev->revision == 0) {
461 u16 version;
462
463 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
464 version = (version & SDHCI_VENDOR_VER_MASK) >>
465 SDHCI_VENDOR_VER_SHIFT;
466
467 /*
468 * Older versions of the chip have lots of nasty glitches
469 * in the ADMA engine. It's best just to avoid it
470 * completely.
471 */
472 if (version < 0xAC)
473 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
474 }
475
8f230f45
TI		 476 /* JM388 MMC doesn't support 1.8V while SD supports it */
477 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
478 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
479 MMC_VDD_29_30 | MMC_VDD_30_31 |
480 MMC_VDD_165_195; /* allow 1.8V */
481 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
482 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
483 }
484
4489428a
PO		 485 /*
486 * The secondary interface requires a bit set to get the
487 * interrupts.
488 */
8f230f45
TI		 489 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
490 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 491 jmicron_enable_mmc(slot->host, 1);
492
d75c1084
TI		 493 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
494
4489428a
PO		 495 return 0;
496}
497
1e72859e 498static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 499{
1e72859e
PO		 500 if (dead)
501 return;
502
8f230f45
TI		 503 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
504 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 505 jmicron_enable_mmc(slot->host, 0);
506}
507
29495aa0 508static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 509{
510 int i;
511
8f230f45
TI		 512 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
513 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 514 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 515 jmicron_enable_mmc(chip->slots[i]->host, 0);
516 }
517
518 return 0;
519}
520
45211e21
PO		 521static int jmicron_resume(struct sdhci_pci_chip *chip)
522{
4489428a
PO		 523 int ret, i;
524
8f230f45
TI		 525 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
526 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 527 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 528 jmicron_enable_mmc(chip->slots[i]->host, 1);
529 }
45211e21
PO		 530
531 ret = jmicron_pmos(chip, 1);
532 if (ret) {
533 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
534 return ret;
535 }
536
537 return 0;
538}
539
26daa1ed 540static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 541 .probe = sdhci_pci_o2_probe,
542 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
543 .probe_slot = sdhci_pci_o2_probe_slot,
544 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 545};
546
22606405 547static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 548 .probe = jmicron_probe,
549
4489428a
PO		 550 .probe_slot = jmicron_probe_slot,
551 .remove_slot = jmicron_remove_slot,
552
553 .suspend = jmicron_suspend,
45211e21 554 .resume = jmicron_resume,
22606405
PO		 555};
556
a7a6186c
NP		 557/* SysKonnect CardBus2SDIO extra registers */
558#define SYSKT_CTRL 0x200
559#define SYSKT_RDFIFO_STAT 0x204
560#define SYSKT_WRFIFO_STAT 0x208
561#define SYSKT_POWER_DATA 0x20c
562#define SYSKT_POWER_330 0xef
563#define SYSKT_POWER_300 0xf8
564#define SYSKT_POWER_184 0xcc
565#define SYSKT_POWER_CMD 0x20d
566#define SYSKT_POWER_START (1 << 7)
567#define SYSKT_POWER_STATUS 0x20e
568#define SYSKT_POWER_STATUS_OK (1 << 0)
569#define SYSKT_BOARD_REV 0x210
570#define SYSKT_CHIP_REV 0x211
571#define SYSKT_CONF_DATA 0x212
572#define SYSKT_CONF_DATA_1V8 (1 << 2)
573#define SYSKT_CONF_DATA_2V5 (1 << 1)
574#define SYSKT_CONF_DATA_3V3 (1 << 0)
575
576static int syskt_probe(struct sdhci_pci_chip *chip)
577{
578 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
579 chip->pdev->class &= ~0x0000FF;
580 chip->pdev->class |= PCI_SDHCI_IFDMA;
581 }
582 return 0;
583}
584
585static int syskt_probe_slot(struct sdhci_pci_slot *slot)
586{
587 int tm, ps;
588
589 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
590 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
591 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
592 "board rev %d.%d, chip rev %d.%d\n",
593 board_rev >> 4, board_rev & 0xf,
594 chip_rev >> 4, chip_rev & 0xf);
595 if (chip_rev >= 0x20)
596 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
597
598 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
599 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
600 udelay(50);
601 tm = 10; /* Wait max 1 ms */
602 do {
603 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
604 if (ps & SYSKT_POWER_STATUS_OK)
605 break;
606 udelay(100);
607 } while (--tm);
608 if (!tm) {
609 dev_err(&slot->chip->pdev->dev,
610 "power regulator never stabilized");
611 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
612 return -ENODEV;
613 }
614
615 return 0;
616}
617
618static const struct sdhci_pci_fixes sdhci_syskt = {
619 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
620 .probe = syskt_probe,
621 .probe_slot = syskt_probe_slot,
622};
623
557b0697
HW		 624static int via_probe(struct sdhci_pci_chip *chip)
625{
626 if (chip->pdev->revision == 0x10)
627 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
628
629 return 0;
630}
631
632static const struct sdhci_pci_fixes sdhci_via = {
633 .probe = via_probe,
634};
635
9107ebbf
MC		 636static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
637{
638 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
639 return 0;
640}
641
642static const struct sdhci_pci_fixes sdhci_rtsx = {
643 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
644 SDHCI_QUIRK2_BROKEN_DDR50,
645 .probe_slot = rtsx_probe_slot,
646};
647
9647f84d 648static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 649 {
650 .vendor = PCI_VENDOR_ID_RICOH,
651 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 652 .subvendor = PCI_ANY_ID,
b8c86fc5 653 .subdevice = PCI_ANY_ID,
22606405 654 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 655 },
656
ccc92c23
ML		 657 {
658 .vendor = PCI_VENDOR_ID_RICOH,
659 .device = 0x843,
660 .subvendor = PCI_ANY_ID,
661 .subdevice = PCI_ANY_ID,
662 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
663 },
664
568133eb
PC		 665 {
666 .vendor = PCI_VENDOR_ID_RICOH,
667 .device = 0xe822,
668 .subvendor = PCI_ANY_ID,
669 .subdevice = PCI_ANY_ID,
670 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
671 },
672
5fd11c07
MI		 673 {
674 .vendor = PCI_VENDOR_ID_RICOH,
675 .device = 0xe823,
676 .subvendor = PCI_ANY_ID,
677 .subdevice = PCI_ANY_ID,
678 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
679 },
680
b8c86fc5
PO		 681 {
682 .vendor = PCI_VENDOR_ID_ENE,
683 .device = PCI_DEVICE_ID_ENE_CB712_SD,
684 .subvendor = PCI_ANY_ID,
685 .subdevice = PCI_ANY_ID,
22606405 686 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 687 },
688
689 {
690 .vendor = PCI_VENDOR_ID_ENE,
691 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
692 .subvendor = PCI_ANY_ID,
693 .subdevice = PCI_ANY_ID,
22606405 694 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 695 },
696
697 {
698 .vendor = PCI_VENDOR_ID_ENE,
699 .device = PCI_DEVICE_ID_ENE_CB714_SD,
700 .subvendor = PCI_ANY_ID,
701 .subdevice = PCI_ANY_ID,
22606405 702 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 703 },
704
705 {
706 .vendor = PCI_VENDOR_ID_ENE,
707 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
708 .subvendor = PCI_ANY_ID,
709 .subdevice = PCI_ANY_ID,
22606405 710 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 711 },
712
713 {
714 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 715 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 716 .subvendor = PCI_ANY_ID,
717 .subdevice = PCI_ANY_ID,
22606405 718 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 719 },
720
721 {
722 .vendor = PCI_VENDOR_ID_JMICRON,
723 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
724 .subvendor = PCI_ANY_ID,
725 .subdevice = PCI_ANY_ID,
22606405 726 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 727 },
728
4489428a
PO		 729 {
730 .vendor = PCI_VENDOR_ID_JMICRON,
731 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
732 .subvendor = PCI_ANY_ID,
733 .subdevice = PCI_ANY_ID,
734 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 735 },
736
737 {
738 .vendor = PCI_VENDOR_ID_JMICRON,
739 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
740 .subvendor = PCI_ANY_ID,
741 .subdevice = PCI_ANY_ID,
742 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
743 },
744
745 {
746 .vendor = PCI_VENDOR_ID_JMICRON,
747 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
750 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 751 },
752
a7a6186c
NP		 753 {
754 .vendor = PCI_VENDOR_ID_SYSKONNECT,
755 .device = 0x8000,
756 .subvendor = PCI_ANY_ID,
757 .subdevice = PCI_ANY_ID,
758 .driver_data = (kernel_ulong_t)&sdhci_syskt,
759 },
760
557b0697
HW		 761 {
762 .vendor = PCI_VENDOR_ID_VIA,
763 .device = 0x95d0,
764 .subvendor = PCI_ANY_ID,
765 .subdevice = PCI_ANY_ID,
766 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 767 },
768
769 {
770 .vendor = PCI_VENDOR_ID_REALTEK,
771 .device = 0x5250,
772 .subvendor = PCI_ANY_ID,
773 .subdevice = PCI_ANY_ID,
774 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 775 },
776
43e968ce
DB		 777 {
778 .vendor = PCI_VENDOR_ID_INTEL,
779 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
780 .subvendor = PCI_ANY_ID,
781 .subdevice = PCI_ANY_ID,
782 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
783 },
784
29229052
XS		 785 {
786 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 787 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
788 .subvendor = PCI_ANY_ID,
789 .subdevice = PCI_ANY_ID,
790 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
791 },
792
793 {
794 .vendor = PCI_VENDOR_ID_INTEL,
795 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
796 .subvendor = PCI_ANY_ID,
797 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 798 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
799 },
800
801 {
802 .vendor = PCI_VENDOR_ID_INTEL,
803 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
806 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 807 },
808
809 {
810 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 811 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
812 .subvendor = PCI_ANY_ID,
813 .subdevice = PCI_ANY_ID,
814 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
815 },
816
817 {
818 .vendor = PCI_VENDOR_ID_INTEL,
819 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
820 .subvendor = PCI_ANY_ID,
821 .subdevice = PCI_ANY_ID,
0d013bcf 822 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 823 },
824
825 {
826 .vendor = PCI_VENDOR_ID_INTEL,
827 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
828 .subvendor = PCI_ANY_ID,
829 .subdevice = PCI_ANY_ID,
0d013bcf 830 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 831 },
832
833 {
834 .vendor = PCI_VENDOR_ID_INTEL,
835 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
836 .subvendor = PCI_ANY_ID,
837 .subdevice = PCI_ANY_ID,
0d013bcf 838 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 839 },
840
841 {
842 .vendor = PCI_VENDOR_ID_INTEL,
843 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
844 .subvendor = PCI_ANY_ID,
845 .subdevice = PCI_ANY_ID,
0d013bcf 846 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 847 },
848
296e0b03
AS		 849 {
850 .vendor = PCI_VENDOR_ID_INTEL,
851 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
852 .subvendor = PCI_ANY_ID,
853 .subdevice = PCI_ANY_ID,
854 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
855 },
856
857 {
858 .vendor = PCI_VENDOR_ID_INTEL,
859 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
860 .subvendor = PCI_ANY_ID,
861 .subdevice = PCI_ANY_ID,
862 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
863 },
864
728ef3d1
AH		 865 {
866 .vendor = PCI_VENDOR_ID_INTEL,
867 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
868 .subvendor = PCI_ANY_ID,
869 .subdevice = PCI_ANY_ID,
870 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
871 },
872
873 {
874 .vendor = PCI_VENDOR_ID_INTEL,
875 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
876 .subvendor = PCI_ANY_ID,
877 .subdevice = PCI_ANY_ID,
878 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
879 },
880
881 {
882 .vendor = PCI_VENDOR_ID_INTEL,
883 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
884 .subvendor = PCI_ANY_ID,
885 .subdevice = PCI_ANY_ID,
886 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
887 },
888
30d025c0
AH		 889 {
890 .vendor = PCI_VENDOR_ID_INTEL,
891 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
892 .subvendor = PCI_ANY_ID,
893 .subdevice = PCI_ANY_ID,
894 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
895 },
896
066173b6
AC		 897 {
898 .vendor = PCI_VENDOR_ID_INTEL,
899 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
900 .subvendor = PCI_ANY_ID,
901 .subdevice = PCI_ANY_ID,
902 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
903 },
904
905 {
906 .vendor = PCI_VENDOR_ID_INTEL,
907 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
908 .subvendor = PCI_ANY_ID,
909 .subdevice = PCI_ANY_ID,
910 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
911 },
912
913 {
914 .vendor = PCI_VENDOR_ID_INTEL,
915 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
916 .subvendor = PCI_ANY_ID,
917 .subdevice = PCI_ANY_ID,
918 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
919 },
d052068a
EE		 920
921 {
922 .vendor = PCI_VENDOR_ID_INTEL,
923 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
924 .subvendor = PCI_ANY_ID,
925 .subdevice = PCI_ANY_ID,
926 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
927 },
928
929 {
930 .vendor = PCI_VENDOR_ID_INTEL,
931 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
932 .subvendor = PCI_ANY_ID,
933 .subdevice = PCI_ANY_ID,
934 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
935 },
936
937 {
938 .vendor = PCI_VENDOR_ID_INTEL,
939 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
940 .subvendor = PCI_ANY_ID,
941 .subdevice = PCI_ANY_ID,
942 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
943 },
944
945 {
946 .vendor = PCI_VENDOR_ID_INTEL,
947 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
948 .subvendor = PCI_ANY_ID,
949 .subdevice = PCI_ANY_ID,
950 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
951 },
952
953 {
954 .vendor = PCI_VENDOR_ID_INTEL,
955 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
956 .subvendor = PCI_ANY_ID,
957 .subdevice = PCI_ANY_ID,
958 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
959 },
960
8776a165
DC		 961 {
962 .vendor = PCI_VENDOR_ID_INTEL,
963 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
964 .subvendor = PCI_ANY_ID,
965 .subdevice = PCI_ANY_ID,
966 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
967 },
26daa1ed
JL		 968 {
969 .vendor = PCI_VENDOR_ID_O2,
970 .device = PCI_DEVICE_ID_O2_8120,
971 .subvendor = PCI_ANY_ID,
972 .subdevice = PCI_ANY_ID,
973 .driver_data = (kernel_ulong_t)&sdhci_o2,
974 },
975
976 {
977 .vendor = PCI_VENDOR_ID_O2,
978 .device = PCI_DEVICE_ID_O2_8220,
979 .subvendor = PCI_ANY_ID,
980 .subdevice = PCI_ANY_ID,
981 .driver_data = (kernel_ulong_t)&sdhci_o2,
982 },
983
984 {
985 .vendor = PCI_VENDOR_ID_O2,
986 .device = PCI_DEVICE_ID_O2_8221,
987 .subvendor = PCI_ANY_ID,
988 .subdevice = PCI_ANY_ID,
989 .driver_data = (kernel_ulong_t)&sdhci_o2,
990 },
991
992 {
993 .vendor = PCI_VENDOR_ID_O2,
994 .device = PCI_DEVICE_ID_O2_8320,
995 .subvendor = PCI_ANY_ID,
996 .subdevice = PCI_ANY_ID,
997 .driver_data = (kernel_ulong_t)&sdhci_o2,
998 },
999
1000 {
1001 .vendor = PCI_VENDOR_ID_O2,
1002 .device = PCI_DEVICE_ID_O2_8321,
1003 .subvendor = PCI_ANY_ID,
1004 .subdevice = PCI_ANY_ID,
1005 .driver_data = (kernel_ulong_t)&sdhci_o2,
1006 },
1007
01acf691
AL		 1008 {
1009 .vendor = PCI_VENDOR_ID_O2,
1010 .device = PCI_DEVICE_ID_O2_FUJIN2,
1011 .subvendor = PCI_ANY_ID,
1012 .subdevice = PCI_ANY_ID,
1013 .driver_data = (kernel_ulong_t)&sdhci_o2,
1014 },
1015
1016 {
1017 .vendor = PCI_VENDOR_ID_O2,
1018 .device = PCI_DEVICE_ID_O2_SDS0,
1019 .subvendor = PCI_ANY_ID,
1020 .subdevice = PCI_ANY_ID,
1021 .driver_data = (kernel_ulong_t)&sdhci_o2,
1022 },
1023
1024 {
1025 .vendor = PCI_VENDOR_ID_O2,
1026 .device = PCI_DEVICE_ID_O2_SDS1,
1027 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID,
1029 .driver_data = (kernel_ulong_t)&sdhci_o2,
1030 },
1031
1032 {
1033 .vendor = PCI_VENDOR_ID_O2,
1034 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1035 .subvendor = PCI_ANY_ID,
1036 .subdevice = PCI_ANY_ID,
1037 .driver_data = (kernel_ulong_t)&sdhci_o2,
1038 },
1039
1040 {
1041 .vendor = PCI_VENDOR_ID_O2,
1042 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1043 .subvendor = PCI_ANY_ID,
1044 .subdevice = PCI_ANY_ID,
1045 .driver_data = (kernel_ulong_t)&sdhci_o2,
1046 },
1047
b8c86fc5
PO		 1048 { /* Generic SD host controller */
1049 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1050 },
1051
1052 { /* end: all zeroes */ },
1053};
1054
1055MODULE_DEVICE_TABLE(pci, pci_ids);
1056
b8c86fc5
PO		 1057/*****************************************************************************\
1058 * *
1059 * SDHCI core callbacks *
1060 * *
1061\*****************************************************************************/
1062
1063static int sdhci_pci_enable_dma(struct sdhci_host *host)
1064{
1065 struct sdhci_pci_slot *slot;
1066 struct pci_dev *pdev;
1067 int ret;
1068
1069 slot = sdhci_priv(host);
1070 pdev = slot->chip->pdev;
1071
1072 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1073 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1074 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1075 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1076 "doesn't fully claim to support it.\n");
1077 }
1078
284901a9 1079 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 1080 if (ret)
1081 return ret;
1082
1083 pci_set_master(pdev);
1084
1085 return 0;
1086}
1087
2317f56c 1088static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1089{
1090 u8 ctrl;
1091
1092 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1093
1094 switch (width) {
1095 case MMC_BUS_WIDTH_8:
1096 ctrl |= SDHCI_CTRL_8BITBUS;
1097 ctrl &= ~SDHCI_CTRL_4BITBUS;
1098 break;
1099 case MMC_BUS_WIDTH_4:
1100 ctrl |= SDHCI_CTRL_4BITBUS;
1101 ctrl &= ~SDHCI_CTRL_8BITBUS;
1102 break;
1103 default:
1104 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1105 break;
1106 }
1107
1108 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1109}
1110
c9faff6c 1111static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1112{
1113 struct sdhci_pci_slot *slot = sdhci_priv(host);
1114 int rst_n_gpio = slot->rst_n_gpio;
1115
1116 if (!gpio_is_valid(rst_n_gpio))
1117 return;
1118 gpio_set_value_cansleep(rst_n_gpio, 0);
1119 /* For eMMC, minimum is 1us but give it 10us for good measure */
1120 udelay(10);
1121 gpio_set_value_cansleep(rst_n_gpio, 1);
1122 /* For eMMC, minimum is 200us but give it 300us for good measure */
1123 usleep_range(300, 1000);
1124}
1125
c9faff6c
AH		 1126static void sdhci_pci_hw_reset(struct sdhci_host *host)
1127{
1128 struct sdhci_pci_slot *slot = sdhci_priv(host);
1129
1130 if (slot->hw_reset)
1131 slot->hw_reset(host);
1132}
1133
c915568d 1134static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1135 .set_clock = sdhci_set_clock,
b8c86fc5 1136 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1137 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1138 .reset = sdhci_reset,
96d7b78c 1139 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1140 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1141};
1142
1143/*****************************************************************************\
1144 * *
1145 * Suspend/resume *
1146 * *
1147\*****************************************************************************/
1148
1149#ifdef CONFIG_PM
1150
29495aa0 1151static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1152{
29495aa0 1153 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1154 struct sdhci_pci_chip *chip;
1155 struct sdhci_pci_slot *slot;
5f619704 1156 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1157 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1158 int i, ret;
1159
1160 chip = pci_get_drvdata(pdev);
1161 if (!chip)
1162 return 0;
1163
b177bc91 1164 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1165 slot = chip->slots[i];
1166 if (!slot)
1167 continue;
1168
29495aa0 1169 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1170
b678b91f
AL		 1171 if (ret)
1172 goto err_pci_suspend;
2f4cbb3d 1173
5f619704
DD		 1174 slot_pm_flags = slot->host->mmc->pm_flags;
1175 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1176 sdhci_enable_irq_wakeups(slot->host);
1177
1178 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1179 }
1180
4489428a 1181 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1182 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1183 if (ret)
1184 goto err_pci_suspend;
4489428a
PO		 1185 }
1186
2f4cbb3d 1187 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1188 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1189 device_init_wakeup(dev, true);
1190 else
1191 device_init_wakeup(dev, false);
1192 } else
1193 device_init_wakeup(dev, false);
b8c86fc5
PO		 1194
1195 return 0;
b678b91f
AL		 1196
1197err_pci_suspend:
1198 while (--i >= 0)
1199 sdhci_resume_host(chip->slots[i]->host);
1200 return ret;
b8c86fc5
PO		 1201}
1202
29495aa0 1203static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1204{
29495aa0 1205 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1206 struct sdhci_pci_chip *chip;
1207 struct sdhci_pci_slot *slot;
1208 int i, ret;
1209
1210 chip = pci_get_drvdata(pdev);
1211 if (!chip)
1212 return 0;
1213
45211e21
PO		 1214 if (chip->fixes && chip->fixes->resume) {
1215 ret = chip->fixes->resume(chip);
1216 if (ret)
1217 return ret;
1218 }
1219
b177bc91 1220 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1221 slot = chip->slots[i];
1222 if (!slot)
1223 continue;
1224
1225 ret = sdhci_resume_host(slot->host);
1226 if (ret)
1227 return ret;
1228 }
1229
1230 return 0;
1231}
1232
1233#else /* CONFIG_PM */
1234
1235#define sdhci_pci_suspend NULL
1236#define sdhci_pci_resume NULL
1237
1238#endif /* CONFIG_PM */
1239
66fd8ad5
AH		 1240#ifdef CONFIG_PM_RUNTIME
1241
1242static int sdhci_pci_runtime_suspend(struct device *dev)
1243{
1244 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1245 struct sdhci_pci_chip *chip;
1246 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1247 int i, ret;
1248
1249 chip = pci_get_drvdata(pdev);
1250 if (!chip)
1251 return 0;
1252
1253 for (i = 0; i < chip->num_slots; i++) {
1254 slot = chip->slots[i];
1255 if (!slot)
1256 continue;
1257
1258 ret = sdhci_runtime_suspend_host(slot->host);
1259
b678b91f
AL		 1260 if (ret)
1261 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1262 }
1263
1264 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1265 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1266 if (ret)
1267 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1268 }
1269
1270 return 0;
b678b91f
AL		 1271
1272err_pci_runtime_suspend:
1273 while (--i >= 0)
1274 sdhci_runtime_resume_host(chip->slots[i]->host);
1275 return ret;
66fd8ad5
AH		 1276}
1277
1278static int sdhci_pci_runtime_resume(struct device *dev)
1279{
1280 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1281 struct sdhci_pci_chip *chip;
1282 struct sdhci_pci_slot *slot;
1283 int i, ret;
1284
1285 chip = pci_get_drvdata(pdev);
1286 if (!chip)
1287 return 0;
1288
1289 if (chip->fixes && chip->fixes->resume) {
1290 ret = chip->fixes->resume(chip);
1291 if (ret)
1292 return ret;
1293 }
1294
1295 for (i = 0; i < chip->num_slots; i++) {
1296 slot = chip->slots[i];
1297 if (!slot)
1298 continue;
1299
1300 ret = sdhci_runtime_resume_host(slot->host);
1301 if (ret)
1302 return ret;
1303 }
1304
1305 return 0;
1306}
1307
1308static int sdhci_pci_runtime_idle(struct device *dev)
1309{
1310 return 0;
1311}
1312
66fd8ad5
AH		 1313#endif
1314
1315static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1316 .suspend = sdhci_pci_suspend,
1317 .resume = sdhci_pci_resume,
f3a92b1a
PG		 1318 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1319 sdhci_pci_runtime_resume, sdhci_pci_runtime_idle)
66fd8ad5
AH		 1320};
1321
b8c86fc5
PO		 1322/*****************************************************************************\
1323 * *
1324 * Device probing/removal *
1325 * *
1326\*****************************************************************************/
1327
c3be1efd 1328static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1329 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1330 int slotno)
b8c86fc5
PO		 1331{
1332 struct sdhci_pci_slot *slot;
1333 struct sdhci_host *host;
52c506f0 1334 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1335
1336 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1337 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1338 return ERR_PTR(-ENODEV);
1339 }
1340
90b3e6c5 1341 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1342 dev_err(&pdev->dev, "Invalid iomem size. You may "
1343 "experience problems.\n");
1344 }
1345
1346 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1347 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1348 return ERR_PTR(-ENODEV);
1349 }
1350
1351 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1352 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1353 return ERR_PTR(-ENODEV);
1354 }
1355
1356 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1357 if (IS_ERR(host)) {
c60a32cd 1358 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1359 return ERR_CAST(host);
b8c86fc5
PO		 1360 }
1361
1362 slot = sdhci_priv(host);
1363
1364 slot->chip = chip;
1365 slot->host = host;
1366 slot->pci_bar = bar;
0f201655 1367 slot->rst_n_gpio = -EINVAL;
c5e027a4 1368 slot->cd_gpio = -EINVAL;
ff59c520 1369 slot->cd_idx = -1;
b8c86fc5 1370
52c506f0
AH		 1371 /* Retrieve platform data if there is any */
1372 if (*sdhci_pci_get_data)
1373 slot->data = sdhci_pci_get_data(pdev, slotno);
1374
1375 if (slot->data) {
1376 if (slot->data->setup) {
1377 ret = slot->data->setup(slot->data);
1378 if (ret) {
1379 dev_err(&pdev->dev, "platform setup failed\n");
1380 goto free;
1381 }
1382 }
c5e027a4
AH		 1383 slot->rst_n_gpio = slot->data->rst_n_gpio;
1384 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1385 }
1386
b8c86fc5
PO		 1387 host->hw_name = "PCI";
1388 host->ops = &sdhci_pci_ops;
1389 host->quirks = chip->quirks;
f3c55a7b 1390 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1391
1392 host->irq = pdev->irq;
1393
1394 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1395 if (ret) {
1396 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1397 goto cleanup;
b8c86fc5
PO		 1398 }
1399
092f82ed 1400 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1401 if (!host->ioaddr) {
1402 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1403 ret = -ENOMEM;
b8c86fc5
PO		 1404 goto release;
1405 }
1406
4489428a
PO		 1407 if (chip->fixes && chip->fixes->probe_slot) {
1408 ret = chip->fixes->probe_slot(slot);
1409 if (ret)
1410 goto unmap;
1411 }
1412
c5e027a4
AH		 1413 if (gpio_is_valid(slot->rst_n_gpio)) {
1414 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1415 gpio_direction_output(slot->rst_n_gpio, 1);
1416 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1417 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1418 } else {
1419 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1420 slot->rst_n_gpio = -EINVAL;
1421 }
1422 }
1423
2f4cbb3d 1424 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1425 host->mmc->slotno = slotno;
a08b17be 1426 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1427
ff59c520
AH		 1428 if (slot->cd_idx >= 0 &&
1429 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1430 slot->cd_override_level, 0, NULL)) {
1431 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1432 slot->cd_idx = -1;
1433 }
1434
b8c86fc5
PO		 1435 ret = sdhci_add_host(host);
1436 if (ret)
4489428a 1437 goto remove;
b8c86fc5 1438
c5e027a4
AH		 1439 sdhci_pci_add_own_cd(slot);
1440
77a0122e
AH		 1441 /*
1442 * Check if the chip needs a separate GPIO for card detect to wake up
1443 * from runtime suspend. If it is not there, don't allow runtime PM.
1444 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1445 */
945be38c 1446 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1447 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1448 chip->allow_runtime_pm = false;
1449
b8c86fc5
PO		 1450 return slot;
1451
4489428a 1452remove:
c5e027a4
AH		 1453 if (gpio_is_valid(slot->rst_n_gpio))
1454 gpio_free(slot->rst_n_gpio);
1455
4489428a 1456 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1457 chip->fixes->remove_slot(slot, 0);
4489428a 1458
b8c86fc5
PO		 1459unmap:
1460 iounmap(host->ioaddr);
1461
1462release:
1463 pci_release_region(pdev, bar);
c60a32cd 1464
52c506f0
AH		 1465cleanup:
1466 if (slot->data && slot->data->cleanup)
1467 slot->data->cleanup(slot->data);
1468
c60a32cd 1469free:
b8c86fc5
PO		 1470 sdhci_free_host(host);
1471
1472 return ERR_PTR(ret);
1473}
1474
1475static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1476{
1e72859e
PO		 1477 int dead;
1478 u32 scratch;
1479
c5e027a4
AH		 1480 sdhci_pci_remove_own_cd(slot);
1481
1e72859e
PO		 1482 dead = 0;
1483 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1484 if (scratch == (u32)-1)
1485 dead = 1;
1486
1487 sdhci_remove_host(slot->host, dead);
4489428a 1488
c5e027a4
AH		 1489 if (gpio_is_valid(slot->rst_n_gpio))
1490 gpio_free(slot->rst_n_gpio);
1491
4489428a 1492 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1493 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1494
52c506f0
AH		 1495 if (slot->data && slot->data->cleanup)
1496 slot->data->cleanup(slot->data);
1497
b8c86fc5 1498 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1499
b8c86fc5
PO		 1500 sdhci_free_host(slot->host);
1501}
1502
c3be1efd 1503static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1504{
1505 pm_runtime_put_noidle(dev);
1506 pm_runtime_allow(dev);
1507 pm_runtime_set_autosuspend_delay(dev, 50);
1508 pm_runtime_use_autosuspend(dev);
1509 pm_suspend_ignore_children(dev, 1);
1510}
1511
6e0ee714 1512static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1513{
1514 pm_runtime_forbid(dev);
1515 pm_runtime_get_noresume(dev);
1516}
1517
c3be1efd 1518static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1519 const struct pci_device_id *ent)
1520{
1521 struct sdhci_pci_chip *chip;
1522 struct sdhci_pci_slot *slot;
1523
cf5e23e1 1524 u8 slots, first_bar;
b8c86fc5
PO		 1525 int ret, i;
1526
1527 BUG_ON(pdev == NULL);
1528 BUG_ON(ent == NULL);
1529
b8c86fc5 1530 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1531 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1532
1533 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1534 if (ret)
1535 return ret;
1536
1537 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1538 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1539 if (slots == 0)
1540 return -ENODEV;
1541
1542 BUG_ON(slots > MAX_SLOTS);
1543
1544 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1545 if (ret)
1546 return ret;
1547
1548 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1549
1550 if (first_bar > 5) {
1551 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1552 return -ENODEV;
1553 }
1554
1555 ret = pci_enable_device(pdev);
1556 if (ret)
1557 return ret;
1558
1559 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1560 if (!chip) {
1561 ret = -ENOMEM;
1562 goto err;
1563 }
1564
1565 chip->pdev = pdev;
b177bc91 1566 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1567 if (chip->fixes) {
22606405 1568 chip->quirks = chip->fixes->quirks;
f3c55a7b 1569 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1570 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1571 }
b8c86fc5
PO		 1572 chip->num_slots = slots;
1573
1574 pci_set_drvdata(pdev, chip);
1575
22606405
PO		 1576 if (chip->fixes && chip->fixes->probe) {
1577 ret = chip->fixes->probe(chip);
1578 if (ret)
1579 goto free;
1580 }
1581
225d85fe
AC		 1582 slots = chip->num_slots; /* Quirk may have changed this */
1583
b177bc91 1584 for (i = 0; i < slots; i++) {
52c506f0 1585 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1586 if (IS_ERR(slot)) {
b177bc91 1587 for (i--; i >= 0; i--)
b8c86fc5
PO		 1588 sdhci_pci_remove_slot(chip->slots[i]);
1589 ret = PTR_ERR(slot);
1590 goto free;
1591 }
1592
1593 chip->slots[i] = slot;
1594 }
1595
c43fd774
AH		 1596 if (chip->allow_runtime_pm)
1597 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1598
b8c86fc5
PO		 1599 return 0;
1600
1601free:
1602 pci_set_drvdata(pdev, NULL);
1603 kfree(chip);
1604
1605err:
1606 pci_disable_device(pdev);
1607 return ret;
1608}
1609
6e0ee714 1610static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1611{
1612 int i;
1613 struct sdhci_pci_chip *chip;
1614
1615 chip = pci_get_drvdata(pdev);
1616
1617 if (chip) {
c43fd774
AH		 1618 if (chip->allow_runtime_pm)
1619 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1620
b177bc91 1621 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1622 sdhci_pci_remove_slot(chip->slots[i]);
1623
1624 pci_set_drvdata(pdev, NULL);
1625 kfree(chip);
1626 }
1627
1628 pci_disable_device(pdev);
1629}
1630
1631static struct pci_driver sdhci_driver = {
b177bc91 1632 .name = "sdhci-pci",
b8c86fc5 1633 .id_table = pci_ids,
b177bc91 1634 .probe = sdhci_pci_probe,
0433c143 1635 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1636 .driver = {
1637 .pm = &sdhci_pci_pm_ops
1638 },
b8c86fc5
PO		 1639};
1640
acc69646 1641module_pci_driver(sdhci_driver);
b8c86fc5 1642
32710e8f 1643MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1644MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1645MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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