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mmc: sdhci: add eMMC hardware reset support
[deliverable/linux.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
17#include <linux/pci.h>
18#include <linux/dma-mapping.h>
5a0e3ad6 19#include <linux/slab.h>
ccc92c23 20#include <linux/device.h>
b8c86fc5 21#include <linux/mmc/host.h>
b177bc91
AP		 22#include <linux/scatterlist.h>
23#include <linux/io.h>
b8c86fc5
PO		 24
25#include "sdhci.h"
26
27/*
28 * PCI registers
29 */
30
31#define PCI_SDHCI_IFPIO 0x00
32#define PCI_SDHCI_IFDMA 0x01
33#define PCI_SDHCI_IFVENDOR 0x02
34
35#define PCI_SLOT_INFO 0x40 /* 8 bits */
36#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
37#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
38
39#define MAX_SLOTS 8
40
22606405 41struct sdhci_pci_chip;
4489428a 42struct sdhci_pci_slot;
22606405
PO		 43
44struct sdhci_pci_fixes {
45 unsigned int quirks;
46
b177bc91 47 int (*probe) (struct sdhci_pci_chip *);
45211e21 48
b177bc91
AP		 49 int (*probe_slot) (struct sdhci_pci_slot *);
50 void (*remove_slot) (struct sdhci_pci_slot *, int);
4489428a 51
b177bc91 52 int (*suspend) (struct sdhci_pci_chip *,
4489428a 53 pm_message_t);
b177bc91 54 int (*resume) (struct sdhci_pci_chip *);
22606405
PO		 55};
56
57struct sdhci_pci_slot {
58 struct sdhci_pci_chip *chip;
59 struct sdhci_host *host;
b8c86fc5 60
22606405
PO		 61 int pci_bar;
62};
63
64struct sdhci_pci_chip {
65 struct pci_dev *pdev;
66
67 unsigned int quirks;
68 const struct sdhci_pci_fixes *fixes;
69
70 int num_slots; /* Slots on controller */
71 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
72};
73
74
75/*****************************************************************************\
76 * *
77 * Hardware specific quirk handling *
78 * *
79\*****************************************************************************/
80
81static int ricoh_probe(struct sdhci_pci_chip *chip)
82{
c99436fb
CB		 83 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
84 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 85 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 86 return 0;
87}
88
89static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
90{
91 slot->host->caps =
92 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
93 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 94
ccc92c23
ML		 95 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
96 & SDHCI_CLOCK_BASE_MASK) |
97
98 SDHCI_TIMEOUT_CLK_UNIT |
99 SDHCI_CAN_VDD_330 |
100 SDHCI_CAN_DO_SDMA;
101 return 0;
102}
103
104static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
105{
106 /* Apply a delay to allow controller to settle */
107 /* Otherwise it becomes confused if card state changed
108 during suspend */
109 msleep(500);
22606405
PO		 110 return 0;
111}
112
113static const struct sdhci_pci_fixes sdhci_ricoh = {
114 .probe = ricoh_probe,
84938294
VK		 115 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
116 SDHCI_QUIRK_FORCE_DMA |
117 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 118};
119
ccc92c23
ML		 120static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
121 .probe_slot = ricoh_mmc_probe_slot,
122 .resume = ricoh_mmc_resume,
123 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
124 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
125 SDHCI_QUIRK_NO_CARD_NO_RESET |
126 SDHCI_QUIRK_MISSING_CAPS
127};
128
22606405
PO		 129static const struct sdhci_pci_fixes sdhci_ene_712 = {
130 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
131 SDHCI_QUIRK_BROKEN_DMA,
132};
133
134static const struct sdhci_pci_fixes sdhci_ene_714 = {
135 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
136 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
137 SDHCI_QUIRK_BROKEN_DMA,
138};
139
140static const struct sdhci_pci_fixes sdhci_cafe = {
141 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 142 SDHCI_QUIRK_NO_BUSY_IRQ |
ee53ab5d 143 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 144};
145
68077b02
ML		 146static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
147{
148 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
149 return 0;
150}
151
f9ee3eab
AC		 152/*
153 * ADMA operation is disabled for Moorestown platform due to
154 * hardware bugs.
155 */
35ac6f08 156static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 157{
158 /*
35ac6f08
JP		 159 * slots number is fixed here for MRST as SDIO3/5 are never used and
160 * have hardware bugs.
f9ee3eab
AC		 161 */
162 chip->num_slots = 1;
163 return 0;
164}
165
0d013bcf
AH		 166static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
167{
168 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
169 return 0;
170}
171
f9ee3eab
AC		 172static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
173 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 174 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 175};
176
35ac6f08 177static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 178 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 179 .probe = mrst_hc_probe,
f9ee3eab
AC		 180};
181
29229052
XS		 182static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
183 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
184};
185
0d013bcf
AH		 186static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
187 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
188};
189
190static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 191 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
0d013bcf 192 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 193};
194
26daa1ed
JL		 195/* O2Micro extra registers */
196#define O2_SD_LOCK_WP 0xD3
197#define O2_SD_MULTI_VCC3V 0xEE
198#define O2_SD_CLKREQ 0xEC
199#define O2_SD_CAPS 0xE0
200#define O2_SD_ADMA1 0xE2
201#define O2_SD_ADMA2 0xE7
202#define O2_SD_INF_MOD 0xF1
203
204static int o2_probe(struct sdhci_pci_chip *chip)
205{
206 int ret;
207 u8 scratch;
208
209 switch (chip->pdev->device) {
210 case PCI_DEVICE_ID_O2_8220:
211 case PCI_DEVICE_ID_O2_8221:
212 case PCI_DEVICE_ID_O2_8320:
213 case PCI_DEVICE_ID_O2_8321:
214 /* This extra setup is required due to broken ADMA. */
215 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
216 if (ret)
217 return ret;
218 scratch &= 0x7f;
219 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
220
221 /* Set Multi 3 to VCC3V# */
222 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
223
224 /* Disable CLK_REQ# support after media DET */
225 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
226 if (ret)
227 return ret;
228 scratch |= 0x20;
229 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
230
231 /* Choose capabilities, enable SDMA. We have to write 0x01
232 * to the capabilities register first to unlock it.
233 */
234 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
235 if (ret)
236 return ret;
237 scratch |= 0x01;
238 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
239 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
240
241 /* Disable ADMA1/2 */
242 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
243 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
244
245 /* Disable the infinite transfer mode */
246 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
247 if (ret)
248 return ret;
249 scratch |= 0x08;
250 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
251
252 /* Lock WP */
253 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
254 if (ret)
255 return ret;
256 scratch |= 0x80;
257 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
258 }
259
260 return 0;
261}
262
45211e21
PO		 263static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
264{
265 u8 scratch;
266 int ret;
267
268 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
269 if (ret)
270 return ret;
271
272 /*
273 * Turn PMOS on [bit 0], set over current detection to 2.4 V
274 * [bit 1:2] and enable over current debouncing [bit 6].
275 */
276 if (on)
277 scratch |= 0x47;
278 else
279 scratch &= ~0x47;
280
281 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
282 if (ret)
283 return ret;
284
285 return 0;
286}
287
288static int jmicron_probe(struct sdhci_pci_chip *chip)
289{
290 int ret;
8f230f45 291 u16 mmcdev = 0;
45211e21 292
93fc48c7
PO		 293 if (chip->pdev->revision == 0) {
294 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
295 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 296 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 297 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 298 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 299 }
300
4489428a
PO		 301 /*
302 * JMicron chips can have two interfaces to the same hardware
303 * in order to work around limitations in Microsoft's driver.
304 * We need to make sure we only bind to one of them.
305 *
306 * This code assumes two things:
307 *
308 * 1. The PCI code adds subfunctions in order.
309 *
310 * 2. The MMC interface has a lower subfunction number
311 * than the SD interface.
312 */
8f230f45
TI		 313 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
314 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
315 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
316 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
317
318 if (mmcdev) {
4489428a
PO		 319 struct pci_dev *sd_dev;
320
321 sd_dev = NULL;
322 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 323 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 324 if ((PCI_SLOT(chip->pdev->devfn) ==
325 PCI_SLOT(sd_dev->devfn)) &&
326 (chip->pdev->bus == sd_dev->bus))
327 break;
328 }
329
330 if (sd_dev) {
331 pci_dev_put(sd_dev);
332 dev_info(&chip->pdev->dev, "Refusing to bind to "
333 "secondary interface.\n");
334 return -ENODEV;
335 }
336 }
337
45211e21
PO		 338 /*
339 * JMicron chips need a bit of a nudge to enable the power
340 * output pins.
341 */
342 ret = jmicron_pmos(chip, 1);
343 if (ret) {
344 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
345 return ret;
346 }
347
82b0e23a
TI		 348 /* quirk for unsable RO-detection on JM388 chips */
349 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
350 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
351 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
352
45211e21
PO		 353 return 0;
354}
355
4489428a
PO		 356static void jmicron_enable_mmc(struct sdhci_host *host, int on)
357{
358 u8 scratch;
359
360 scratch = readb(host->ioaddr + 0xC0);
361
362 if (on)
363 scratch |= 0x01;
364 else
365 scratch &= ~0x01;
366
367 writeb(scratch, host->ioaddr + 0xC0);
368}
369
370static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
371{
2134a922
PO		 372 if (slot->chip->pdev->revision == 0) {
373 u16 version;
374
375 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
376 version = (version & SDHCI_VENDOR_VER_MASK) >>
377 SDHCI_VENDOR_VER_SHIFT;
378
379 /*
380 * Older versions of the chip have lots of nasty glitches
381 * in the ADMA engine. It's best just to avoid it
382 * completely.
383 */
384 if (version < 0xAC)
385 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
386 }
387
8f230f45
TI		 388 /* JM388 MMC doesn't support 1.8V while SD supports it */
389 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
390 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
391 MMC_VDD_29_30 | MMC_VDD_30_31 |
392 MMC_VDD_165_195; /* allow 1.8V */
393 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
394 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
395 }
396
4489428a
PO		 397 /*
398 * The secondary interface requires a bit set to get the
399 * interrupts.
400 */
8f230f45
TI		 401 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
402 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 403 jmicron_enable_mmc(slot->host, 1);
404
d75c1084
TI		 405 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
406
4489428a
PO		 407 return 0;
408}
409
1e72859e 410static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 411{
1e72859e
PO		 412 if (dead)
413 return;
414
8f230f45
TI		 415 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
416 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 417 jmicron_enable_mmc(slot->host, 0);
418}
419
420static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
421{
422 int i;
423
8f230f45
TI		 424 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
425 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 426 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 427 jmicron_enable_mmc(chip->slots[i]->host, 0);
428 }
429
430 return 0;
431}
432
45211e21
PO		 433static int jmicron_resume(struct sdhci_pci_chip *chip)
434{
4489428a
PO		 435 int ret, i;
436
8f230f45
TI		 437 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
438 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 439 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 440 jmicron_enable_mmc(chip->slots[i]->host, 1);
441 }
45211e21
PO		 442
443 ret = jmicron_pmos(chip, 1);
444 if (ret) {
445 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
446 return ret;
447 }
448
449 return 0;
450}
451
26daa1ed
JL		 452static const struct sdhci_pci_fixes sdhci_o2 = {
453 .probe = o2_probe,
454};
455
22606405 456static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 457 .probe = jmicron_probe,
458
4489428a
PO		 459 .probe_slot = jmicron_probe_slot,
460 .remove_slot = jmicron_remove_slot,
461
462 .suspend = jmicron_suspend,
45211e21 463 .resume = jmicron_resume,
22606405
PO		 464};
465
a7a6186c
NP		 466/* SysKonnect CardBus2SDIO extra registers */
467#define SYSKT_CTRL 0x200
468#define SYSKT_RDFIFO_STAT 0x204
469#define SYSKT_WRFIFO_STAT 0x208
470#define SYSKT_POWER_DATA 0x20c
471#define SYSKT_POWER_330 0xef
472#define SYSKT_POWER_300 0xf8
473#define SYSKT_POWER_184 0xcc
474#define SYSKT_POWER_CMD 0x20d
475#define SYSKT_POWER_START (1 << 7)
476#define SYSKT_POWER_STATUS 0x20e
477#define SYSKT_POWER_STATUS_OK (1 << 0)
478#define SYSKT_BOARD_REV 0x210
479#define SYSKT_CHIP_REV 0x211
480#define SYSKT_CONF_DATA 0x212
481#define SYSKT_CONF_DATA_1V8 (1 << 2)
482#define SYSKT_CONF_DATA_2V5 (1 << 1)
483#define SYSKT_CONF_DATA_3V3 (1 << 0)
484
485static int syskt_probe(struct sdhci_pci_chip *chip)
486{
487 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
488 chip->pdev->class &= ~0x0000FF;
489 chip->pdev->class |= PCI_SDHCI_IFDMA;
490 }
491 return 0;
492}
493
494static int syskt_probe_slot(struct sdhci_pci_slot *slot)
495{
496 int tm, ps;
497
498 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
499 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
500 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
501 "board rev %d.%d, chip rev %d.%d\n",
502 board_rev >> 4, board_rev & 0xf,
503 chip_rev >> 4, chip_rev & 0xf);
504 if (chip_rev >= 0x20)
505 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
506
507 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
508 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
509 udelay(50);
510 tm = 10; /* Wait max 1 ms */
511 do {
512 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
513 if (ps & SYSKT_POWER_STATUS_OK)
514 break;
515 udelay(100);
516 } while (--tm);
517 if (!tm) {
518 dev_err(&slot->chip->pdev->dev,
519 "power regulator never stabilized");
520 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
521 return -ENODEV;
522 }
523
524 return 0;
525}
526
527static const struct sdhci_pci_fixes sdhci_syskt = {
528 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
529 .probe = syskt_probe,
530 .probe_slot = syskt_probe_slot,
531};
532
557b0697
HW		 533static int via_probe(struct sdhci_pci_chip *chip)
534{
535 if (chip->pdev->revision == 0x10)
536 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
537
538 return 0;
539}
540
541static const struct sdhci_pci_fixes sdhci_via = {
542 .probe = via_probe,
543};
544
22606405 545static const struct pci_device_id pci_ids[] __devinitdata = {
b8c86fc5
PO		 546 {
547 .vendor = PCI_VENDOR_ID_RICOH,
548 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 549 .subvendor = PCI_ANY_ID,
b8c86fc5 550 .subdevice = PCI_ANY_ID,
22606405 551 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 552 },
553
ccc92c23
ML		 554 {
555 .vendor = PCI_VENDOR_ID_RICOH,
556 .device = 0x843,
557 .subvendor = PCI_ANY_ID,
558 .subdevice = PCI_ANY_ID,
559 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
560 },
561
568133eb
PC		 562 {
563 .vendor = PCI_VENDOR_ID_RICOH,
564 .device = 0xe822,
565 .subvendor = PCI_ANY_ID,
566 .subdevice = PCI_ANY_ID,
567 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
568 },
569
5fd11c07
MI		 570 {
571 .vendor = PCI_VENDOR_ID_RICOH,
572 .device = 0xe823,
573 .subvendor = PCI_ANY_ID,
574 .subdevice = PCI_ANY_ID,
575 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
576 },
577
b8c86fc5
PO		 578 {
579 .vendor = PCI_VENDOR_ID_ENE,
580 .device = PCI_DEVICE_ID_ENE_CB712_SD,
581 .subvendor = PCI_ANY_ID,
582 .subdevice = PCI_ANY_ID,
22606405 583 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 584 },
585
586 {
587 .vendor = PCI_VENDOR_ID_ENE,
588 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
589 .subvendor = PCI_ANY_ID,
590 .subdevice = PCI_ANY_ID,
22606405 591 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 592 },
593
594 {
595 .vendor = PCI_VENDOR_ID_ENE,
596 .device = PCI_DEVICE_ID_ENE_CB714_SD,
597 .subvendor = PCI_ANY_ID,
598 .subdevice = PCI_ANY_ID,
22606405 599 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 600 },
601
602 {
603 .vendor = PCI_VENDOR_ID_ENE,
604 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
605 .subvendor = PCI_ANY_ID,
606 .subdevice = PCI_ANY_ID,
22606405 607 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 608 },
609
610 {
611 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 612 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 613 .subvendor = PCI_ANY_ID,
614 .subdevice = PCI_ANY_ID,
22606405 615 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 616 },
617
618 {
619 .vendor = PCI_VENDOR_ID_JMICRON,
620 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
621 .subvendor = PCI_ANY_ID,
622 .subdevice = PCI_ANY_ID,
22606405 623 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 624 },
625
4489428a
PO		 626 {
627 .vendor = PCI_VENDOR_ID_JMICRON,
628 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
629 .subvendor = PCI_ANY_ID,
630 .subdevice = PCI_ANY_ID,
631 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 632 },
633
634 {
635 .vendor = PCI_VENDOR_ID_JMICRON,
636 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
637 .subvendor = PCI_ANY_ID,
638 .subdevice = PCI_ANY_ID,
639 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
640 },
641
642 {
643 .vendor = PCI_VENDOR_ID_JMICRON,
644 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
645 .subvendor = PCI_ANY_ID,
646 .subdevice = PCI_ANY_ID,
647 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 648 },
649
a7a6186c
NP		 650 {
651 .vendor = PCI_VENDOR_ID_SYSKONNECT,
652 .device = 0x8000,
653 .subvendor = PCI_ANY_ID,
654 .subdevice = PCI_ANY_ID,
655 .driver_data = (kernel_ulong_t)&sdhci_syskt,
656 },
657
557b0697
HW		 658 {
659 .vendor = PCI_VENDOR_ID_VIA,
660 .device = 0x95d0,
661 .subvendor = PCI_ANY_ID,
662 .subdevice = PCI_ANY_ID,
663 .driver_data = (kernel_ulong_t)&sdhci_via,
664 },
665
29229052
XS		 666 {
667 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 668 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
669 .subvendor = PCI_ANY_ID,
670 .subdevice = PCI_ANY_ID,
671 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
672 },
673
674 {
675 .vendor = PCI_VENDOR_ID_INTEL,
676 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
677 .subvendor = PCI_ANY_ID,
678 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 679 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
680 },
681
682 {
683 .vendor = PCI_VENDOR_ID_INTEL,
684 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
685 .subvendor = PCI_ANY_ID,
686 .subdevice = PCI_ANY_ID,
687 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 688 },
689
690 {
691 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 692 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
693 .subvendor = PCI_ANY_ID,
694 .subdevice = PCI_ANY_ID,
695 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
696 },
697
698 {
699 .vendor = PCI_VENDOR_ID_INTEL,
700 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
701 .subvendor = PCI_ANY_ID,
702 .subdevice = PCI_ANY_ID,
0d013bcf 703 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 704 },
705
706 {
707 .vendor = PCI_VENDOR_ID_INTEL,
708 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
709 .subvendor = PCI_ANY_ID,
710 .subdevice = PCI_ANY_ID,
0d013bcf 711 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 712 },
713
714 {
715 .vendor = PCI_VENDOR_ID_INTEL,
716 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
717 .subvendor = PCI_ANY_ID,
718 .subdevice = PCI_ANY_ID,
0d013bcf 719 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 720 },
721
722 {
723 .vendor = PCI_VENDOR_ID_INTEL,
724 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
725 .subvendor = PCI_ANY_ID,
726 .subdevice = PCI_ANY_ID,
0d013bcf 727 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 728 },
729
26daa1ed
JL		 730 {
731 .vendor = PCI_VENDOR_ID_O2,
732 .device = PCI_DEVICE_ID_O2_8120,
733 .subvendor = PCI_ANY_ID,
734 .subdevice = PCI_ANY_ID,
735 .driver_data = (kernel_ulong_t)&sdhci_o2,
736 },
737
738 {
739 .vendor = PCI_VENDOR_ID_O2,
740 .device = PCI_DEVICE_ID_O2_8220,
741 .subvendor = PCI_ANY_ID,
742 .subdevice = PCI_ANY_ID,
743 .driver_data = (kernel_ulong_t)&sdhci_o2,
744 },
745
746 {
747 .vendor = PCI_VENDOR_ID_O2,
748 .device = PCI_DEVICE_ID_O2_8221,
749 .subvendor = PCI_ANY_ID,
750 .subdevice = PCI_ANY_ID,
751 .driver_data = (kernel_ulong_t)&sdhci_o2,
752 },
753
754 {
755 .vendor = PCI_VENDOR_ID_O2,
756 .device = PCI_DEVICE_ID_O2_8320,
757 .subvendor = PCI_ANY_ID,
758 .subdevice = PCI_ANY_ID,
759 .driver_data = (kernel_ulong_t)&sdhci_o2,
760 },
761
762 {
763 .vendor = PCI_VENDOR_ID_O2,
764 .device = PCI_DEVICE_ID_O2_8321,
765 .subvendor = PCI_ANY_ID,
766 .subdevice = PCI_ANY_ID,
767 .driver_data = (kernel_ulong_t)&sdhci_o2,
768 },
769
b8c86fc5
PO		 770 { /* Generic SD host controller */
771 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
772 },
773
774 { /* end: all zeroes */ },
775};
776
777MODULE_DEVICE_TABLE(pci, pci_ids);
778
b8c86fc5
PO		 779/*****************************************************************************\
780 * *
781 * SDHCI core callbacks *
782 * *
783\*****************************************************************************/
784
785static int sdhci_pci_enable_dma(struct sdhci_host *host)
786{
787 struct sdhci_pci_slot *slot;
788 struct pci_dev *pdev;
789 int ret;
790
791 slot = sdhci_priv(host);
792 pdev = slot->chip->pdev;
793
794 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
795 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 796 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 797 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
798 "doesn't fully claim to support it.\n");
799 }
800
284901a9 801 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 802 if (ret)
803 return ret;
804
805 pci_set_master(pdev);
806
807 return 0;
808}
809
68077b02
ML		 810static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
811{
812 u8 ctrl;
813
814 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
815
816 switch (width) {
817 case MMC_BUS_WIDTH_8:
818 ctrl |= SDHCI_CTRL_8BITBUS;
819 ctrl &= ~SDHCI_CTRL_4BITBUS;
820 break;
821 case MMC_BUS_WIDTH_4:
822 ctrl |= SDHCI_CTRL_4BITBUS;
823 ctrl &= ~SDHCI_CTRL_8BITBUS;
824 break;
825 default:
826 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
827 break;
828 }
829
830 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
831
832 return 0;
833}
834
b8c86fc5
PO		 835static struct sdhci_ops sdhci_pci_ops = {
836 .enable_dma = sdhci_pci_enable_dma,
68077b02 837 .platform_8bit_width = sdhci_pci_8bit_width,
b8c86fc5
PO		 838};
839
840/*****************************************************************************\
841 * *
842 * Suspend/resume *
843 * *
844\*****************************************************************************/
845
846#ifdef CONFIG_PM
847
b177bc91 848static int sdhci_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b8c86fc5
PO		 849{
850 struct sdhci_pci_chip *chip;
851 struct sdhci_pci_slot *slot;
5f619704 852 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 853 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 854 int i, ret;
855
856 chip = pci_get_drvdata(pdev);
857 if (!chip)
858 return 0;
859
b177bc91 860 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 861 slot = chip->slots[i];
862 if (!slot)
863 continue;
864
865 ret = sdhci_suspend_host(slot->host, state);
866
867 if (ret) {
b177bc91 868 for (i--; i >= 0; i--)
b8c86fc5
PO		 869 sdhci_resume_host(chip->slots[i]->host);
870 return ret;
871 }
2f4cbb3d 872
5f619704
DD		 873 slot_pm_flags = slot->host->mmc->pm_flags;
874 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
875 sdhci_enable_irq_wakeups(slot->host);
876
877 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 878 }
879
4489428a
PO		 880 if (chip->fixes && chip->fixes->suspend) {
881 ret = chip->fixes->suspend(chip, state);
882 if (ret) {
b177bc91 883 for (i = chip->num_slots - 1; i >= 0; i--)
4489428a
PO		 884 sdhci_resume_host(chip->slots[i]->host);
885 return ret;
886 }
887 }
888
b8c86fc5 889 pci_save_state(pdev);
2f4cbb3d 890 if (pm_flags & MMC_PM_KEEP_POWER) {
5f619704
DD		 891 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
892 pci_pme_active(pdev, true);
2f4cbb3d 893 pci_enable_wake(pdev, PCI_D3hot, 1);
5f619704 894 }
2f4cbb3d
NP		 895 pci_set_power_state(pdev, PCI_D3hot);
896 } else {
897 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
898 pci_disable_device(pdev);
899 pci_set_power_state(pdev, pci_choose_state(pdev, state));
900 }
b8c86fc5
PO		 901
902 return 0;
903}
904
b177bc91 905static int sdhci_pci_resume(struct pci_dev *pdev)
b8c86fc5
PO		 906{
907 struct sdhci_pci_chip *chip;
908 struct sdhci_pci_slot *slot;
909 int i, ret;
910
911 chip = pci_get_drvdata(pdev);
912 if (!chip)
913 return 0;
914
915 pci_set_power_state(pdev, PCI_D0);
916 pci_restore_state(pdev);
917 ret = pci_enable_device(pdev);
918 if (ret)
919 return ret;
920
45211e21
PO		 921 if (chip->fixes && chip->fixes->resume) {
922 ret = chip->fixes->resume(chip);
923 if (ret)
924 return ret;
925 }
926
b177bc91 927 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 928 slot = chip->slots[i];
929 if (!slot)
930 continue;
931
932 ret = sdhci_resume_host(slot->host);
933 if (ret)
934 return ret;
935 }
936
937 return 0;
938}
939
940#else /* CONFIG_PM */
941
942#define sdhci_pci_suspend NULL
943#define sdhci_pci_resume NULL
944
945#endif /* CONFIG_PM */
946
947/*****************************************************************************\
948 * *
949 * Device probing/removal *
950 * *
951\*****************************************************************************/
952
953static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
954 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
955{
956 struct sdhci_pci_slot *slot;
957 struct sdhci_host *host;
b8c86fc5
PO		 958 int ret;
959
960 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
961 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
962 return ERR_PTR(-ENODEV);
963 }
964
965 if (pci_resource_len(pdev, bar) != 0x100) {
966 dev_err(&pdev->dev, "Invalid iomem size. You may "
967 "experience problems.\n");
968 }
969
970 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
971 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
972 return ERR_PTR(-ENODEV);
973 }
974
975 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
976 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
977 return ERR_PTR(-ENODEV);
978 }
979
980 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
981 if (IS_ERR(host)) {
c60a32cd 982 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 983 return ERR_CAST(host);
b8c86fc5
PO		 984 }
985
986 slot = sdhci_priv(host);
987
988 slot->chip = chip;
989 slot->host = host;
990 slot->pci_bar = bar;
991
992 host->hw_name = "PCI";
993 host->ops = &sdhci_pci_ops;
994 host->quirks = chip->quirks;
995
996 host->irq = pdev->irq;
997
998 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
999 if (ret) {
1000 dev_err(&pdev->dev, "cannot request region\n");
c60a32cd 1001 goto free;
b8c86fc5
PO		 1002 }
1003
092f82ed 1004 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1005 if (!host->ioaddr) {
1006 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1007 ret = -ENOMEM;
b8c86fc5
PO		 1008 goto release;
1009 }
1010
4489428a
PO		 1011 if (chip->fixes && chip->fixes->probe_slot) {
1012 ret = chip->fixes->probe_slot(slot);
1013 if (ret)
1014 goto unmap;
1015 }
1016
2f4cbb3d
NP		 1017 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1018
b8c86fc5
PO		 1019 ret = sdhci_add_host(host);
1020 if (ret)
4489428a 1021 goto remove;
b8c86fc5
PO		 1022
1023 return slot;
1024
4489428a
PO		 1025remove:
1026 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1027 chip->fixes->remove_slot(slot, 0);
4489428a 1028
b8c86fc5
PO		 1029unmap:
1030 iounmap(host->ioaddr);
1031
1032release:
1033 pci_release_region(pdev, bar);
c60a32cd
DC		 1034
1035free:
b8c86fc5
PO		 1036 sdhci_free_host(host);
1037
1038 return ERR_PTR(ret);
1039}
1040
1041static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1042{
1e72859e
PO		 1043 int dead;
1044 u32 scratch;
1045
1046 dead = 0;
1047 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1048 if (scratch == (u32)-1)
1049 dead = 1;
1050
1051 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1052
1053 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1054 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1055
b8c86fc5 1056 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1057
b8c86fc5
PO		 1058 sdhci_free_host(slot->host);
1059}
1060
1061static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1062 const struct pci_device_id *ent)
1063{
1064 struct sdhci_pci_chip *chip;
1065 struct sdhci_pci_slot *slot;
1066
cf5e23e1 1067 u8 slots, first_bar;
b8c86fc5
PO		 1068 int ret, i;
1069
1070 BUG_ON(pdev == NULL);
1071 BUG_ON(ent == NULL);
1072
b8c86fc5 1073 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1074 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1075
1076 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1077 if (ret)
1078 return ret;
1079
1080 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1081 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1082 if (slots == 0)
1083 return -ENODEV;
1084
1085 BUG_ON(slots > MAX_SLOTS);
1086
1087 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1088 if (ret)
1089 return ret;
1090
1091 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1092
1093 if (first_bar > 5) {
1094 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1095 return -ENODEV;
1096 }
1097
1098 ret = pci_enable_device(pdev);
1099 if (ret)
1100 return ret;
1101
1102 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1103 if (!chip) {
1104 ret = -ENOMEM;
1105 goto err;
1106 }
1107
1108 chip->pdev = pdev;
b177bc91 1109 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
22606405
PO		 1110 if (chip->fixes)
1111 chip->quirks = chip->fixes->quirks;
b8c86fc5
PO		 1112 chip->num_slots = slots;
1113
1114 pci_set_drvdata(pdev, chip);
1115
22606405
PO		 1116 if (chip->fixes && chip->fixes->probe) {
1117 ret = chip->fixes->probe(chip);
1118 if (ret)
1119 goto free;
1120 }
1121
225d85fe
AC		 1122 slots = chip->num_slots; /* Quirk may have changed this */
1123
b177bc91 1124 for (i = 0; i < slots; i++) {
b8c86fc5
PO		 1125 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1126 if (IS_ERR(slot)) {
b177bc91 1127 for (i--; i >= 0; i--)
b8c86fc5
PO		 1128 sdhci_pci_remove_slot(chip->slots[i]);
1129 ret = PTR_ERR(slot);
1130 goto free;
1131 }
1132
1133 chip->slots[i] = slot;
1134 }
1135
1136 return 0;
1137
1138free:
1139 pci_set_drvdata(pdev, NULL);
1140 kfree(chip);
1141
1142err:
1143 pci_disable_device(pdev);
1144 return ret;
1145}
1146
1147static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1148{
1149 int i;
1150 struct sdhci_pci_chip *chip;
1151
1152 chip = pci_get_drvdata(pdev);
1153
1154 if (chip) {
b177bc91 1155 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1156 sdhci_pci_remove_slot(chip->slots[i]);
1157
1158 pci_set_drvdata(pdev, NULL);
1159 kfree(chip);
1160 }
1161
1162 pci_disable_device(pdev);
1163}
1164
1165static struct pci_driver sdhci_driver = {
b177bc91 1166 .name = "sdhci-pci",
b8c86fc5 1167 .id_table = pci_ids,
b177bc91 1168 .probe = sdhci_pci_probe,
b8c86fc5
PO		 1169 .remove = __devexit_p(sdhci_pci_remove),
1170 .suspend = sdhci_pci_suspend,
1171 .resume = sdhci_pci_resume,
1172};
1173
1174/*****************************************************************************\
1175 * *
1176 * Driver init/exit *
1177 * *
1178\*****************************************************************************/
1179
1180static int __init sdhci_drv_init(void)
1181{
1182 return pci_register_driver(&sdhci_driver);
1183}
1184
1185static void __exit sdhci_drv_exit(void)
1186{
1187 pci_unregister_driver(&sdhci_driver);
1188}
1189
1190module_init(sdhci_drv_init);
1191module_exit(sdhci_drv_exit);
1192
32710e8f 1193MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1194MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1195MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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