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b8c86fc5 PO |
1 | /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface |
2 | * | |
3 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or (at | |
8 | * your option) any later version. | |
9 | * | |
10 | * Thanks to the following companies for their support: | |
11 | * | |
12 | * - JMicron (hardware and technical support) | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/highmem.h> | |
88b47679 | 17 | #include <linux/module.h> |
b8c86fc5 PO |
18 | #include <linux/pci.h> |
19 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
ccc92c23 | 21 | #include <linux/device.h> |
b8c86fc5 | 22 | #include <linux/mmc/host.h> |
b177bc91 AP |
23 | #include <linux/scatterlist.h> |
24 | #include <linux/io.h> | |
0f201655 | 25 | #include <linux/gpio.h> |
66fd8ad5 | 26 | #include <linux/pm_runtime.h> |
52c506f0 | 27 | #include <linux/mmc/sdhci-pci-data.h> |
b8c86fc5 PO |
28 | |
29 | #include "sdhci.h" | |
30 | ||
296e0b03 AS |
31 | /* |
32 | * PCI device IDs | |
33 | */ | |
34 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 | |
35 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a | |
728ef3d1 AH |
36 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 |
37 | #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 | |
38 | #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 | |
30d025c0 | 39 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 |
8776a165 | 40 | #define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190 |
d052068a EE |
41 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 |
42 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa | |
43 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb | |
44 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 | |
45 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 | |
296e0b03 | 46 | |
b8c86fc5 PO |
47 | /* |
48 | * PCI registers | |
49 | */ | |
50 | ||
51 | #define PCI_SDHCI_IFPIO 0x00 | |
52 | #define PCI_SDHCI_IFDMA 0x01 | |
53 | #define PCI_SDHCI_IFVENDOR 0x02 | |
54 | ||
55 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ | |
56 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) | |
57 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 | |
58 | ||
59 | #define MAX_SLOTS 8 | |
60 | ||
22606405 | 61 | struct sdhci_pci_chip; |
4489428a | 62 | struct sdhci_pci_slot; |
22606405 PO |
63 | |
64 | struct sdhci_pci_fixes { | |
65 | unsigned int quirks; | |
f3c55a7b | 66 | unsigned int quirks2; |
c43fd774 | 67 | bool allow_runtime_pm; |
22606405 | 68 | |
b177bc91 | 69 | int (*probe) (struct sdhci_pci_chip *); |
45211e21 | 70 | |
b177bc91 AP |
71 | int (*probe_slot) (struct sdhci_pci_slot *); |
72 | void (*remove_slot) (struct sdhci_pci_slot *, int); | |
4489428a | 73 | |
29495aa0 | 74 | int (*suspend) (struct sdhci_pci_chip *); |
b177bc91 | 75 | int (*resume) (struct sdhci_pci_chip *); |
22606405 PO |
76 | }; |
77 | ||
78 | struct sdhci_pci_slot { | |
79 | struct sdhci_pci_chip *chip; | |
80 | struct sdhci_host *host; | |
52c506f0 | 81 | struct sdhci_pci_data *data; |
b8c86fc5 | 82 | |
22606405 | 83 | int pci_bar; |
0f201655 | 84 | int rst_n_gpio; |
66fd8ad5 AH |
85 | int cd_gpio; |
86 | int cd_irq; | |
c9faff6c AH |
87 | |
88 | void (*hw_reset)(struct sdhci_host *host); | |
22606405 PO |
89 | }; |
90 | ||
91 | struct sdhci_pci_chip { | |
92 | struct pci_dev *pdev; | |
93 | ||
94 | unsigned int quirks; | |
f3c55a7b | 95 | unsigned int quirks2; |
c43fd774 | 96 | bool allow_runtime_pm; |
22606405 PO |
97 | const struct sdhci_pci_fixes *fixes; |
98 | ||
99 | int num_slots; /* Slots on controller */ | |
100 | struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ | |
101 | }; | |
102 | ||
103 | ||
104 | /*****************************************************************************\ | |
105 | * * | |
106 | * Hardware specific quirk handling * | |
107 | * * | |
108 | \*****************************************************************************/ | |
109 | ||
110 | static int ricoh_probe(struct sdhci_pci_chip *chip) | |
111 | { | |
c99436fb CB |
112 | if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || |
113 | chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) | |
22606405 | 114 | chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; |
ccc92c23 ML |
115 | return 0; |
116 | } | |
117 | ||
118 | static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
119 | { | |
120 | slot->host->caps = | |
121 | ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) | |
122 | & SDHCI_TIMEOUT_CLK_MASK) | | |
22606405 | 123 | |
ccc92c23 ML |
124 | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) |
125 | & SDHCI_CLOCK_BASE_MASK) | | |
126 | ||
127 | SDHCI_TIMEOUT_CLK_UNIT | | |
128 | SDHCI_CAN_VDD_330 | | |
1a1f1f04 | 129 | SDHCI_CAN_DO_HISPD | |
ccc92c23 ML |
130 | SDHCI_CAN_DO_SDMA; |
131 | return 0; | |
132 | } | |
133 | ||
134 | static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) | |
135 | { | |
136 | /* Apply a delay to allow controller to settle */ | |
137 | /* Otherwise it becomes confused if card state changed | |
138 | during suspend */ | |
139 | msleep(500); | |
22606405 PO |
140 | return 0; |
141 | } | |
142 | ||
143 | static const struct sdhci_pci_fixes sdhci_ricoh = { | |
144 | .probe = ricoh_probe, | |
84938294 VK |
145 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
146 | SDHCI_QUIRK_FORCE_DMA | | |
147 | SDHCI_QUIRK_CLOCK_BEFORE_RESET, | |
22606405 PO |
148 | }; |
149 | ||
ccc92c23 ML |
150 | static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { |
151 | .probe_slot = ricoh_mmc_probe_slot, | |
152 | .resume = ricoh_mmc_resume, | |
153 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | | |
154 | SDHCI_QUIRK_CLOCK_BEFORE_RESET | | |
155 | SDHCI_QUIRK_NO_CARD_NO_RESET | | |
156 | SDHCI_QUIRK_MISSING_CAPS | |
157 | }; | |
158 | ||
22606405 PO |
159 | static const struct sdhci_pci_fixes sdhci_ene_712 = { |
160 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
161 | SDHCI_QUIRK_BROKEN_DMA, | |
162 | }; | |
163 | ||
164 | static const struct sdhci_pci_fixes sdhci_ene_714 = { | |
165 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
166 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | | |
167 | SDHCI_QUIRK_BROKEN_DMA, | |
168 | }; | |
169 | ||
170 | static const struct sdhci_pci_fixes sdhci_cafe = { | |
171 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | | |
a0874897 | 172 | SDHCI_QUIRK_NO_BUSY_IRQ | |
55fc05b7 | 173 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
ee53ab5d | 174 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
22606405 PO |
175 | }; |
176 | ||
68077b02 ML |
177 | static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) |
178 | { | |
179 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
180 | return 0; | |
181 | } | |
182 | ||
f9ee3eab AC |
183 | /* |
184 | * ADMA operation is disabled for Moorestown platform due to | |
185 | * hardware bugs. | |
186 | */ | |
35ac6f08 | 187 | static int mrst_hc_probe(struct sdhci_pci_chip *chip) |
f9ee3eab AC |
188 | { |
189 | /* | |
35ac6f08 JP |
190 | * slots number is fixed here for MRST as SDIO3/5 are never used and |
191 | * have hardware bugs. | |
f9ee3eab AC |
192 | */ |
193 | chip->num_slots = 1; | |
194 | return 0; | |
195 | } | |
196 | ||
296e0b03 AS |
197 | static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) |
198 | { | |
199 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
200 | return 0; | |
201 | } | |
202 | ||
66fd8ad5 AH |
203 | #ifdef CONFIG_PM_RUNTIME |
204 | ||
c5e027a4 | 205 | static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) |
66fd8ad5 AH |
206 | { |
207 | struct sdhci_pci_slot *slot = dev_id; | |
208 | struct sdhci_host *host = slot->host; | |
209 | ||
210 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
211 | return IRQ_HANDLED; | |
212 | } | |
213 | ||
c5e027a4 | 214 | static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 | 215 | { |
c5e027a4 | 216 | int err, irq, gpio = slot->cd_gpio; |
66fd8ad5 AH |
217 | |
218 | slot->cd_gpio = -EINVAL; | |
219 | slot->cd_irq = -EINVAL; | |
220 | ||
c5e027a4 AH |
221 | if (!gpio_is_valid(gpio)) |
222 | return; | |
223 | ||
66fd8ad5 AH |
224 | err = gpio_request(gpio, "sd_cd"); |
225 | if (err < 0) | |
226 | goto out; | |
227 | ||
228 | err = gpio_direction_input(gpio); | |
229 | if (err < 0) | |
230 | goto out_free; | |
231 | ||
232 | irq = gpio_to_irq(gpio); | |
233 | if (irq < 0) | |
234 | goto out_free; | |
235 | ||
c5e027a4 | 236 | err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | |
66fd8ad5 AH |
237 | IRQF_TRIGGER_FALLING, "sd_cd", slot); |
238 | if (err) | |
239 | goto out_free; | |
240 | ||
241 | slot->cd_gpio = gpio; | |
242 | slot->cd_irq = irq; | |
66fd8ad5 | 243 | |
c5e027a4 | 244 | return; |
66fd8ad5 AH |
245 | |
246 | out_free: | |
247 | gpio_free(gpio); | |
248 | out: | |
249 | dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); | |
66fd8ad5 AH |
250 | } |
251 | ||
c5e027a4 | 252 | static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 AH |
253 | { |
254 | if (slot->cd_irq >= 0) | |
255 | free_irq(slot->cd_irq, slot); | |
c5e027a4 AH |
256 | if (gpio_is_valid(slot->cd_gpio)) |
257 | gpio_free(slot->cd_gpio); | |
66fd8ad5 AH |
258 | } |
259 | ||
260 | #else | |
261 | ||
c5e027a4 AH |
262 | static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
263 | { | |
264 | } | |
265 | ||
266 | static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) | |
267 | { | |
268 | } | |
66fd8ad5 AH |
269 | |
270 | #endif | |
271 | ||
0d013bcf AH |
272 | static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) |
273 | { | |
66fd8ad5 | 274 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; |
da721cf7 AH |
275 | slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | |
276 | MMC_CAP2_HC_ERASE_SZ; | |
0d013bcf AH |
277 | return 0; |
278 | } | |
279 | ||
93933508 AH |
280 | static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) |
281 | { | |
012e4671 | 282 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; |
93933508 AH |
283 | return 0; |
284 | } | |
285 | ||
f9ee3eab AC |
286 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { |
287 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, | |
68077b02 | 288 | .probe_slot = mrst_hc_probe_slot, |
f9ee3eab AC |
289 | }; |
290 | ||
35ac6f08 | 291 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { |
f9ee3eab | 292 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, |
35ac6f08 | 293 | .probe = mrst_hc_probe, |
f9ee3eab AC |
294 | }; |
295 | ||
29229052 XS |
296 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { |
297 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
c43fd774 | 298 | .allow_runtime_pm = true, |
29229052 XS |
299 | }; |
300 | ||
0d013bcf AH |
301 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { |
302 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
f3c55a7b | 303 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, |
c43fd774 | 304 | .allow_runtime_pm = true, |
93933508 | 305 | .probe_slot = mfd_sdio_probe_slot, |
0d013bcf AH |
306 | }; |
307 | ||
308 | static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { | |
29229052 | 309 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
c43fd774 | 310 | .allow_runtime_pm = true, |
0d013bcf | 311 | .probe_slot = mfd_emmc_probe_slot, |
29229052 XS |
312 | }; |
313 | ||
296e0b03 AS |
314 | static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { |
315 | .quirks = SDHCI_QUIRK_BROKEN_ADMA, | |
316 | .probe_slot = pch_hc_probe_slot, | |
317 | }; | |
318 | ||
c9faff6c AH |
319 | static void sdhci_pci_int_hw_reset(struct sdhci_host *host) |
320 | { | |
321 | u8 reg; | |
322 | ||
323 | reg = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
324 | reg |= 0x10; | |
325 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
326 | /* For eMMC, minimum is 1us but give it 9us for good measure */ | |
327 | udelay(9); | |
328 | reg &= ~0x10; | |
329 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
330 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
331 | usleep_range(300, 1000); | |
332 | } | |
333 | ||
728ef3d1 AH |
334 | static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) |
335 | { | |
c9faff6c AH |
336 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | |
337 | MMC_CAP_HW_RESET; | |
728ef3d1 | 338 | slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; |
c9faff6c | 339 | slot->hw_reset = sdhci_pci_int_hw_reset; |
728ef3d1 AH |
340 | return 0; |
341 | } | |
342 | ||
343 | static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) | |
344 | { | |
345 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; | |
346 | return 0; | |
347 | } | |
348 | ||
349 | static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { | |
350 | .allow_runtime_pm = true, | |
351 | .probe_slot = byt_emmc_probe_slot, | |
352 | }; | |
353 | ||
354 | static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { | |
355 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, | |
356 | .allow_runtime_pm = true, | |
357 | .probe_slot = byt_sdio_probe_slot, | |
358 | }; | |
359 | ||
360 | static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { | |
7396e318 AH |
361 | .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON, |
362 | .allow_runtime_pm = true, | |
728ef3d1 AH |
363 | }; |
364 | ||
8776a165 DC |
365 | /* Define Host controllers for Intel Merrifield platform */ |
366 | #define INTEL_MRFL_EMMC_0 0 | |
367 | #define INTEL_MRFL_EMMC_1 1 | |
368 | ||
369 | static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
370 | { | |
371 | if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) && | |
372 | (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1)) | |
373 | /* SD support is not ready yet */ | |
374 | return -ENODEV; | |
375 | ||
376 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | | |
377 | MMC_CAP_1_8V_DDR; | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = { | |
383 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
384 | .probe_slot = intel_mrfl_mmc_probe_slot, | |
385 | }; | |
386 | ||
26daa1ed JL |
387 | /* O2Micro extra registers */ |
388 | #define O2_SD_LOCK_WP 0xD3 | |
389 | #define O2_SD_MULTI_VCC3V 0xEE | |
390 | #define O2_SD_CLKREQ 0xEC | |
391 | #define O2_SD_CAPS 0xE0 | |
392 | #define O2_SD_ADMA1 0xE2 | |
393 | #define O2_SD_ADMA2 0xE7 | |
394 | #define O2_SD_INF_MOD 0xF1 | |
395 | ||
396 | static int o2_probe(struct sdhci_pci_chip *chip) | |
397 | { | |
398 | int ret; | |
399 | u8 scratch; | |
400 | ||
401 | switch (chip->pdev->device) { | |
402 | case PCI_DEVICE_ID_O2_8220: | |
403 | case PCI_DEVICE_ID_O2_8221: | |
404 | case PCI_DEVICE_ID_O2_8320: | |
405 | case PCI_DEVICE_ID_O2_8321: | |
406 | /* This extra setup is required due to broken ADMA. */ | |
407 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
408 | if (ret) | |
409 | return ret; | |
410 | scratch &= 0x7f; | |
411 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
412 | ||
413 | /* Set Multi 3 to VCC3V# */ | |
414 | pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); | |
415 | ||
416 | /* Disable CLK_REQ# support after media DET */ | |
417 | ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); | |
418 | if (ret) | |
419 | return ret; | |
420 | scratch |= 0x20; | |
421 | pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); | |
422 | ||
423 | /* Choose capabilities, enable SDMA. We have to write 0x01 | |
424 | * to the capabilities register first to unlock it. | |
425 | */ | |
426 | ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); | |
427 | if (ret) | |
428 | return ret; | |
429 | scratch |= 0x01; | |
430 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); | |
431 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); | |
432 | ||
433 | /* Disable ADMA1/2 */ | |
434 | pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); | |
435 | pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); | |
436 | ||
437 | /* Disable the infinite transfer mode */ | |
438 | ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); | |
439 | if (ret) | |
440 | return ret; | |
441 | scratch |= 0x08; | |
442 | pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); | |
443 | ||
444 | /* Lock WP */ | |
445 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
446 | if (ret) | |
447 | return ret; | |
448 | scratch |= 0x80; | |
449 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
45211e21 PO |
455 | static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) |
456 | { | |
457 | u8 scratch; | |
458 | int ret; | |
459 | ||
460 | ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); | |
461 | if (ret) | |
462 | return ret; | |
463 | ||
464 | /* | |
465 | * Turn PMOS on [bit 0], set over current detection to 2.4 V | |
466 | * [bit 1:2] and enable over current debouncing [bit 6]. | |
467 | */ | |
468 | if (on) | |
469 | scratch |= 0x47; | |
470 | else | |
471 | scratch &= ~0x47; | |
472 | ||
473 | ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); | |
474 | if (ret) | |
475 | return ret; | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int jmicron_probe(struct sdhci_pci_chip *chip) | |
481 | { | |
482 | int ret; | |
8f230f45 | 483 | u16 mmcdev = 0; |
45211e21 | 484 | |
93fc48c7 PO |
485 | if (chip->pdev->revision == 0) { |
486 | chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | | |
487 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
2134a922 | 488 | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
4a3cba32 | 489 | SDHCI_QUIRK_RESET_AFTER_REQUEST | |
86a6a874 | 490 | SDHCI_QUIRK_BROKEN_SMALL_PIO; |
93fc48c7 PO |
491 | } |
492 | ||
4489428a PO |
493 | /* |
494 | * JMicron chips can have two interfaces to the same hardware | |
495 | * in order to work around limitations in Microsoft's driver. | |
496 | * We need to make sure we only bind to one of them. | |
497 | * | |
498 | * This code assumes two things: | |
499 | * | |
500 | * 1. The PCI code adds subfunctions in order. | |
501 | * | |
502 | * 2. The MMC interface has a lower subfunction number | |
503 | * than the SD interface. | |
504 | */ | |
8f230f45 TI |
505 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) |
506 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; | |
507 | else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) | |
508 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; | |
509 | ||
510 | if (mmcdev) { | |
4489428a PO |
511 | struct pci_dev *sd_dev; |
512 | ||
513 | sd_dev = NULL; | |
514 | while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, | |
8f230f45 | 515 | mmcdev, sd_dev)) != NULL) { |
4489428a PO |
516 | if ((PCI_SLOT(chip->pdev->devfn) == |
517 | PCI_SLOT(sd_dev->devfn)) && | |
518 | (chip->pdev->bus == sd_dev->bus)) | |
519 | break; | |
520 | } | |
521 | ||
522 | if (sd_dev) { | |
523 | pci_dev_put(sd_dev); | |
524 | dev_info(&chip->pdev->dev, "Refusing to bind to " | |
525 | "secondary interface.\n"); | |
526 | return -ENODEV; | |
527 | } | |
528 | } | |
529 | ||
45211e21 PO |
530 | /* |
531 | * JMicron chips need a bit of a nudge to enable the power | |
532 | * output pins. | |
533 | */ | |
534 | ret = jmicron_pmos(chip, 1); | |
535 | if (ret) { | |
536 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
537 | return ret; | |
538 | } | |
539 | ||
82b0e23a TI |
540 | /* quirk for unsable RO-detection on JM388 chips */ |
541 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || | |
542 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
543 | chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; | |
544 | ||
45211e21 PO |
545 | return 0; |
546 | } | |
547 | ||
4489428a PO |
548 | static void jmicron_enable_mmc(struct sdhci_host *host, int on) |
549 | { | |
550 | u8 scratch; | |
551 | ||
552 | scratch = readb(host->ioaddr + 0xC0); | |
553 | ||
554 | if (on) | |
555 | scratch |= 0x01; | |
556 | else | |
557 | scratch &= ~0x01; | |
558 | ||
559 | writeb(scratch, host->ioaddr + 0xC0); | |
560 | } | |
561 | ||
562 | static int jmicron_probe_slot(struct sdhci_pci_slot *slot) | |
563 | { | |
2134a922 PO |
564 | if (slot->chip->pdev->revision == 0) { |
565 | u16 version; | |
566 | ||
567 | version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); | |
568 | version = (version & SDHCI_VENDOR_VER_MASK) >> | |
569 | SDHCI_VENDOR_VER_SHIFT; | |
570 | ||
571 | /* | |
572 | * Older versions of the chip have lots of nasty glitches | |
573 | * in the ADMA engine. It's best just to avoid it | |
574 | * completely. | |
575 | */ | |
576 | if (version < 0xAC) | |
577 | slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
578 | } | |
579 | ||
8f230f45 TI |
580 | /* JM388 MMC doesn't support 1.8V while SD supports it */ |
581 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
582 | slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
583 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
584 | MMC_VDD_165_195; /* allow 1.8V */ | |
585 | slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
586 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ | |
587 | } | |
588 | ||
4489428a PO |
589 | /* |
590 | * The secondary interface requires a bit set to get the | |
591 | * interrupts. | |
592 | */ | |
8f230f45 TI |
593 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
594 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
595 | jmicron_enable_mmc(slot->host, 1); |
596 | ||
d75c1084 TI |
597 | slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; |
598 | ||
4489428a PO |
599 | return 0; |
600 | } | |
601 | ||
1e72859e | 602 | static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) |
4489428a | 603 | { |
1e72859e PO |
604 | if (dead) |
605 | return; | |
606 | ||
8f230f45 TI |
607 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
608 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
609 | jmicron_enable_mmc(slot->host, 0); |
610 | } | |
611 | ||
29495aa0 | 612 | static int jmicron_suspend(struct sdhci_pci_chip *chip) |
4489428a PO |
613 | { |
614 | int i; | |
615 | ||
8f230f45 TI |
616 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
617 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 618 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
619 | jmicron_enable_mmc(chip->slots[i]->host, 0); |
620 | } | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
45211e21 PO |
625 | static int jmicron_resume(struct sdhci_pci_chip *chip) |
626 | { | |
4489428a PO |
627 | int ret, i; |
628 | ||
8f230f45 TI |
629 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
630 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 631 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
632 | jmicron_enable_mmc(chip->slots[i]->host, 1); |
633 | } | |
45211e21 PO |
634 | |
635 | ret = jmicron_pmos(chip, 1); | |
636 | if (ret) { | |
637 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
638 | return ret; | |
639 | } | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
26daa1ed JL |
644 | static const struct sdhci_pci_fixes sdhci_o2 = { |
645 | .probe = o2_probe, | |
646 | }; | |
647 | ||
22606405 | 648 | static const struct sdhci_pci_fixes sdhci_jmicron = { |
45211e21 PO |
649 | .probe = jmicron_probe, |
650 | ||
4489428a PO |
651 | .probe_slot = jmicron_probe_slot, |
652 | .remove_slot = jmicron_remove_slot, | |
653 | ||
654 | .suspend = jmicron_suspend, | |
45211e21 | 655 | .resume = jmicron_resume, |
22606405 PO |
656 | }; |
657 | ||
a7a6186c NP |
658 | /* SysKonnect CardBus2SDIO extra registers */ |
659 | #define SYSKT_CTRL 0x200 | |
660 | #define SYSKT_RDFIFO_STAT 0x204 | |
661 | #define SYSKT_WRFIFO_STAT 0x208 | |
662 | #define SYSKT_POWER_DATA 0x20c | |
663 | #define SYSKT_POWER_330 0xef | |
664 | #define SYSKT_POWER_300 0xf8 | |
665 | #define SYSKT_POWER_184 0xcc | |
666 | #define SYSKT_POWER_CMD 0x20d | |
667 | #define SYSKT_POWER_START (1 << 7) | |
668 | #define SYSKT_POWER_STATUS 0x20e | |
669 | #define SYSKT_POWER_STATUS_OK (1 << 0) | |
670 | #define SYSKT_BOARD_REV 0x210 | |
671 | #define SYSKT_CHIP_REV 0x211 | |
672 | #define SYSKT_CONF_DATA 0x212 | |
673 | #define SYSKT_CONF_DATA_1V8 (1 << 2) | |
674 | #define SYSKT_CONF_DATA_2V5 (1 << 1) | |
675 | #define SYSKT_CONF_DATA_3V3 (1 << 0) | |
676 | ||
677 | static int syskt_probe(struct sdhci_pci_chip *chip) | |
678 | { | |
679 | if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
680 | chip->pdev->class &= ~0x0000FF; | |
681 | chip->pdev->class |= PCI_SDHCI_IFDMA; | |
682 | } | |
683 | return 0; | |
684 | } | |
685 | ||
686 | static int syskt_probe_slot(struct sdhci_pci_slot *slot) | |
687 | { | |
688 | int tm, ps; | |
689 | ||
690 | u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); | |
691 | u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); | |
692 | dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " | |
693 | "board rev %d.%d, chip rev %d.%d\n", | |
694 | board_rev >> 4, board_rev & 0xf, | |
695 | chip_rev >> 4, chip_rev & 0xf); | |
696 | if (chip_rev >= 0x20) | |
697 | slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; | |
698 | ||
699 | writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); | |
700 | writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); | |
701 | udelay(50); | |
702 | tm = 10; /* Wait max 1 ms */ | |
703 | do { | |
704 | ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); | |
705 | if (ps & SYSKT_POWER_STATUS_OK) | |
706 | break; | |
707 | udelay(100); | |
708 | } while (--tm); | |
709 | if (!tm) { | |
710 | dev_err(&slot->chip->pdev->dev, | |
711 | "power regulator never stabilized"); | |
712 | writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); | |
713 | return -ENODEV; | |
714 | } | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
719 | static const struct sdhci_pci_fixes sdhci_syskt = { | |
720 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, | |
721 | .probe = syskt_probe, | |
722 | .probe_slot = syskt_probe_slot, | |
723 | }; | |
724 | ||
557b0697 HW |
725 | static int via_probe(struct sdhci_pci_chip *chip) |
726 | { | |
727 | if (chip->pdev->revision == 0x10) | |
728 | chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | static const struct sdhci_pci_fixes sdhci_via = { | |
734 | .probe = via_probe, | |
735 | }; | |
736 | ||
9647f84d | 737 | static const struct pci_device_id pci_ids[] = { |
b8c86fc5 PO |
738 | { |
739 | .vendor = PCI_VENDOR_ID_RICOH, | |
740 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
22606405 | 741 | .subvendor = PCI_ANY_ID, |
b8c86fc5 | 742 | .subdevice = PCI_ANY_ID, |
22606405 | 743 | .driver_data = (kernel_ulong_t)&sdhci_ricoh, |
b8c86fc5 PO |
744 | }, |
745 | ||
ccc92c23 ML |
746 | { |
747 | .vendor = PCI_VENDOR_ID_RICOH, | |
748 | .device = 0x843, | |
749 | .subvendor = PCI_ANY_ID, | |
750 | .subdevice = PCI_ANY_ID, | |
751 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
752 | }, | |
753 | ||
568133eb PC |
754 | { |
755 | .vendor = PCI_VENDOR_ID_RICOH, | |
756 | .device = 0xe822, | |
757 | .subvendor = PCI_ANY_ID, | |
758 | .subdevice = PCI_ANY_ID, | |
759 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
760 | }, | |
761 | ||
5fd11c07 MI |
762 | { |
763 | .vendor = PCI_VENDOR_ID_RICOH, | |
764 | .device = 0xe823, | |
765 | .subvendor = PCI_ANY_ID, | |
766 | .subdevice = PCI_ANY_ID, | |
767 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
768 | }, | |
769 | ||
b8c86fc5 PO |
770 | { |
771 | .vendor = PCI_VENDOR_ID_ENE, | |
772 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
773 | .subvendor = PCI_ANY_ID, | |
774 | .subdevice = PCI_ANY_ID, | |
22606405 | 775 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
776 | }, |
777 | ||
778 | { | |
779 | .vendor = PCI_VENDOR_ID_ENE, | |
780 | .device = PCI_DEVICE_ID_ENE_CB712_SD_2, | |
781 | .subvendor = PCI_ANY_ID, | |
782 | .subdevice = PCI_ANY_ID, | |
22606405 | 783 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
784 | }, |
785 | ||
786 | { | |
787 | .vendor = PCI_VENDOR_ID_ENE, | |
788 | .device = PCI_DEVICE_ID_ENE_CB714_SD, | |
789 | .subvendor = PCI_ANY_ID, | |
790 | .subdevice = PCI_ANY_ID, | |
22606405 | 791 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
792 | }, |
793 | ||
794 | { | |
795 | .vendor = PCI_VENDOR_ID_ENE, | |
796 | .device = PCI_DEVICE_ID_ENE_CB714_SD_2, | |
797 | .subvendor = PCI_ANY_ID, | |
798 | .subdevice = PCI_ANY_ID, | |
22606405 | 799 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
800 | }, |
801 | ||
802 | { | |
803 | .vendor = PCI_VENDOR_ID_MARVELL, | |
8c5eb880 | 804 | .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, |
b8c86fc5 PO |
805 | .subvendor = PCI_ANY_ID, |
806 | .subdevice = PCI_ANY_ID, | |
22606405 | 807 | .driver_data = (kernel_ulong_t)&sdhci_cafe, |
b8c86fc5 PO |
808 | }, |
809 | ||
810 | { | |
811 | .vendor = PCI_VENDOR_ID_JMICRON, | |
812 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, | |
813 | .subvendor = PCI_ANY_ID, | |
814 | .subdevice = PCI_ANY_ID, | |
22606405 | 815 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, |
b8c86fc5 PO |
816 | }, |
817 | ||
4489428a PO |
818 | { |
819 | .vendor = PCI_VENDOR_ID_JMICRON, | |
820 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, | |
821 | .subvendor = PCI_ANY_ID, | |
822 | .subdevice = PCI_ANY_ID, | |
823 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
8f230f45 TI |
824 | }, |
825 | ||
826 | { | |
827 | .vendor = PCI_VENDOR_ID_JMICRON, | |
828 | .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, | |
829 | .subvendor = PCI_ANY_ID, | |
830 | .subdevice = PCI_ANY_ID, | |
831 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
832 | }, | |
833 | ||
834 | { | |
835 | .vendor = PCI_VENDOR_ID_JMICRON, | |
836 | .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
837 | .subvendor = PCI_ANY_ID, | |
838 | .subdevice = PCI_ANY_ID, | |
839 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
4489428a PO |
840 | }, |
841 | ||
a7a6186c NP |
842 | { |
843 | .vendor = PCI_VENDOR_ID_SYSKONNECT, | |
844 | .device = 0x8000, | |
845 | .subvendor = PCI_ANY_ID, | |
846 | .subdevice = PCI_ANY_ID, | |
847 | .driver_data = (kernel_ulong_t)&sdhci_syskt, | |
848 | }, | |
849 | ||
557b0697 HW |
850 | { |
851 | .vendor = PCI_VENDOR_ID_VIA, | |
852 | .device = 0x95d0, | |
853 | .subvendor = PCI_ANY_ID, | |
854 | .subdevice = PCI_ANY_ID, | |
855 | .driver_data = (kernel_ulong_t)&sdhci_via, | |
856 | }, | |
857 | ||
29229052 XS |
858 | { |
859 | .vendor = PCI_VENDOR_ID_INTEL, | |
f9ee3eab AC |
860 | .device = PCI_DEVICE_ID_INTEL_MRST_SD0, |
861 | .subvendor = PCI_ANY_ID, | |
862 | .subdevice = PCI_ANY_ID, | |
863 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, | |
864 | }, | |
865 | ||
866 | { | |
867 | .vendor = PCI_VENDOR_ID_INTEL, | |
868 | .device = PCI_DEVICE_ID_INTEL_MRST_SD1, | |
869 | .subvendor = PCI_ANY_ID, | |
870 | .subdevice = PCI_ANY_ID, | |
35ac6f08 JP |
871 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, |
872 | }, | |
873 | ||
874 | { | |
875 | .vendor = PCI_VENDOR_ID_INTEL, | |
876 | .device = PCI_DEVICE_ID_INTEL_MRST_SD2, | |
877 | .subvendor = PCI_ANY_ID, | |
878 | .subdevice = PCI_ANY_ID, | |
879 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, | |
f9ee3eab AC |
880 | }, |
881 | ||
882 | { | |
883 | .vendor = PCI_VENDOR_ID_INTEL, | |
29229052 XS |
884 | .device = PCI_DEVICE_ID_INTEL_MFD_SD, |
885 | .subvendor = PCI_ANY_ID, | |
886 | .subdevice = PCI_ANY_ID, | |
887 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, | |
888 | }, | |
889 | ||
890 | { | |
891 | .vendor = PCI_VENDOR_ID_INTEL, | |
892 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, | |
893 | .subvendor = PCI_ANY_ID, | |
894 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 895 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
896 | }, |
897 | ||
898 | { | |
899 | .vendor = PCI_VENDOR_ID_INTEL, | |
900 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, | |
901 | .subvendor = PCI_ANY_ID, | |
902 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 903 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
904 | }, |
905 | ||
906 | { | |
907 | .vendor = PCI_VENDOR_ID_INTEL, | |
908 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, | |
909 | .subvendor = PCI_ANY_ID, | |
910 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 911 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
912 | }, |
913 | ||
914 | { | |
915 | .vendor = PCI_VENDOR_ID_INTEL, | |
916 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, | |
917 | .subvendor = PCI_ANY_ID, | |
918 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 919 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
920 | }, |
921 | ||
296e0b03 AS |
922 | { |
923 | .vendor = PCI_VENDOR_ID_INTEL, | |
924 | .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, | |
925 | .subvendor = PCI_ANY_ID, | |
926 | .subdevice = PCI_ANY_ID, | |
927 | .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, | |
928 | }, | |
929 | ||
930 | { | |
931 | .vendor = PCI_VENDOR_ID_INTEL, | |
932 | .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, | |
933 | .subvendor = PCI_ANY_ID, | |
934 | .subdevice = PCI_ANY_ID, | |
935 | .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, | |
936 | }, | |
937 | ||
728ef3d1 AH |
938 | { |
939 | .vendor = PCI_VENDOR_ID_INTEL, | |
940 | .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, | |
941 | .subvendor = PCI_ANY_ID, | |
942 | .subdevice = PCI_ANY_ID, | |
943 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, | |
944 | }, | |
945 | ||
946 | { | |
947 | .vendor = PCI_VENDOR_ID_INTEL, | |
948 | .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, | |
949 | .subvendor = PCI_ANY_ID, | |
950 | .subdevice = PCI_ANY_ID, | |
951 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, | |
952 | }, | |
953 | ||
954 | { | |
955 | .vendor = PCI_VENDOR_ID_INTEL, | |
956 | .device = PCI_DEVICE_ID_INTEL_BYT_SD, | |
957 | .subvendor = PCI_ANY_ID, | |
958 | .subdevice = PCI_ANY_ID, | |
959 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, | |
960 | }, | |
961 | ||
30d025c0 AH |
962 | { |
963 | .vendor = PCI_VENDOR_ID_INTEL, | |
964 | .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, | |
965 | .subvendor = PCI_ANY_ID, | |
966 | .subdevice = PCI_ANY_ID, | |
967 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, | |
968 | }, | |
969 | ||
d052068a EE |
970 | |
971 | { | |
972 | .vendor = PCI_VENDOR_ID_INTEL, | |
973 | .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, | |
974 | .subvendor = PCI_ANY_ID, | |
975 | .subdevice = PCI_ANY_ID, | |
976 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, | |
977 | }, | |
978 | ||
979 | { | |
980 | .vendor = PCI_VENDOR_ID_INTEL, | |
981 | .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, | |
982 | .subvendor = PCI_ANY_ID, | |
983 | .subdevice = PCI_ANY_ID, | |
984 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, | |
985 | }, | |
986 | ||
987 | { | |
988 | .vendor = PCI_VENDOR_ID_INTEL, | |
989 | .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, | |
990 | .subvendor = PCI_ANY_ID, | |
991 | .subdevice = PCI_ANY_ID, | |
992 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, | |
993 | }, | |
994 | ||
995 | { | |
996 | .vendor = PCI_VENDOR_ID_INTEL, | |
997 | .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, | |
998 | .subvendor = PCI_ANY_ID, | |
999 | .subdevice = PCI_ANY_ID, | |
1000 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, | |
1001 | }, | |
1002 | ||
1003 | { | |
1004 | .vendor = PCI_VENDOR_ID_INTEL, | |
1005 | .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, | |
1006 | .subvendor = PCI_ANY_ID, | |
1007 | .subdevice = PCI_ANY_ID, | |
1008 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, | |
1009 | }, | |
1010 | ||
8776a165 DC |
1011 | { |
1012 | .vendor = PCI_VENDOR_ID_INTEL, | |
1013 | .device = PCI_DEVICE_ID_INTEL_MRFL_MMC, | |
1014 | .subvendor = PCI_ANY_ID, | |
1015 | .subdevice = PCI_ANY_ID, | |
1016 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc, | |
1017 | }, | |
26daa1ed JL |
1018 | { |
1019 | .vendor = PCI_VENDOR_ID_O2, | |
1020 | .device = PCI_DEVICE_ID_O2_8120, | |
1021 | .subvendor = PCI_ANY_ID, | |
1022 | .subdevice = PCI_ANY_ID, | |
1023 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1024 | }, | |
1025 | ||
1026 | { | |
1027 | .vendor = PCI_VENDOR_ID_O2, | |
1028 | .device = PCI_DEVICE_ID_O2_8220, | |
1029 | .subvendor = PCI_ANY_ID, | |
1030 | .subdevice = PCI_ANY_ID, | |
1031 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1032 | }, | |
1033 | ||
1034 | { | |
1035 | .vendor = PCI_VENDOR_ID_O2, | |
1036 | .device = PCI_DEVICE_ID_O2_8221, | |
1037 | .subvendor = PCI_ANY_ID, | |
1038 | .subdevice = PCI_ANY_ID, | |
1039 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1040 | }, | |
1041 | ||
1042 | { | |
1043 | .vendor = PCI_VENDOR_ID_O2, | |
1044 | .device = PCI_DEVICE_ID_O2_8320, | |
1045 | .subvendor = PCI_ANY_ID, | |
1046 | .subdevice = PCI_ANY_ID, | |
1047 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1048 | }, | |
1049 | ||
1050 | { | |
1051 | .vendor = PCI_VENDOR_ID_O2, | |
1052 | .device = PCI_DEVICE_ID_O2_8321, | |
1053 | .subvendor = PCI_ANY_ID, | |
1054 | .subdevice = PCI_ANY_ID, | |
1055 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1056 | }, | |
1057 | ||
b8c86fc5 PO |
1058 | { /* Generic SD host controller */ |
1059 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
1060 | }, | |
1061 | ||
1062 | { /* end: all zeroes */ }, | |
1063 | }; | |
1064 | ||
1065 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
1066 | ||
b8c86fc5 PO |
1067 | /*****************************************************************************\ |
1068 | * * | |
1069 | * SDHCI core callbacks * | |
1070 | * * | |
1071 | \*****************************************************************************/ | |
1072 | ||
1073 | static int sdhci_pci_enable_dma(struct sdhci_host *host) | |
1074 | { | |
1075 | struct sdhci_pci_slot *slot; | |
1076 | struct pci_dev *pdev; | |
1077 | int ret; | |
1078 | ||
1079 | slot = sdhci_priv(host); | |
1080 | pdev = slot->chip->pdev; | |
1081 | ||
1082 | if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && | |
1083 | ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && | |
a13abc7b | 1084 | (host->flags & SDHCI_USE_SDMA)) { |
b8c86fc5 PO |
1085 | dev_warn(&pdev->dev, "Will use DMA mode even though HW " |
1086 | "doesn't fully claim to support it.\n"); | |
1087 | } | |
1088 | ||
284901a9 | 1089 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b8c86fc5 PO |
1090 | if (ret) |
1091 | return ret; | |
1092 | ||
1093 | pci_set_master(pdev); | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | ||
7bc088d3 | 1098 | static int sdhci_pci_bus_width(struct sdhci_host *host, int width) |
68077b02 ML |
1099 | { |
1100 | u8 ctrl; | |
1101 | ||
1102 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1103 | ||
1104 | switch (width) { | |
1105 | case MMC_BUS_WIDTH_8: | |
1106 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1107 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1108 | break; | |
1109 | case MMC_BUS_WIDTH_4: | |
1110 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1111 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1112 | break; | |
1113 | default: | |
1114 | ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); | |
1115 | break; | |
1116 | } | |
1117 | ||
1118 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
c9faff6c | 1123 | static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) |
0f201655 AH |
1124 | { |
1125 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1126 | int rst_n_gpio = slot->rst_n_gpio; | |
1127 | ||
1128 | if (!gpio_is_valid(rst_n_gpio)) | |
1129 | return; | |
1130 | gpio_set_value_cansleep(rst_n_gpio, 0); | |
1131 | /* For eMMC, minimum is 1us but give it 10us for good measure */ | |
1132 | udelay(10); | |
1133 | gpio_set_value_cansleep(rst_n_gpio, 1); | |
1134 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
1135 | usleep_range(300, 1000); | |
1136 | } | |
1137 | ||
c9faff6c AH |
1138 | static void sdhci_pci_hw_reset(struct sdhci_host *host) |
1139 | { | |
1140 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1141 | ||
1142 | if (slot->hw_reset) | |
1143 | slot->hw_reset(host); | |
1144 | } | |
1145 | ||
c915568d | 1146 | static const struct sdhci_ops sdhci_pci_ops = { |
b8c86fc5 | 1147 | .enable_dma = sdhci_pci_enable_dma, |
7bc088d3 | 1148 | .platform_bus_width = sdhci_pci_bus_width, |
0f201655 | 1149 | .hw_reset = sdhci_pci_hw_reset, |
b8c86fc5 PO |
1150 | }; |
1151 | ||
1152 | /*****************************************************************************\ | |
1153 | * * | |
1154 | * Suspend/resume * | |
1155 | * * | |
1156 | \*****************************************************************************/ | |
1157 | ||
1158 | #ifdef CONFIG_PM | |
1159 | ||
29495aa0 | 1160 | static int sdhci_pci_suspend(struct device *dev) |
b8c86fc5 | 1161 | { |
29495aa0 | 1162 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
1163 | struct sdhci_pci_chip *chip; |
1164 | struct sdhci_pci_slot *slot; | |
5f619704 | 1165 | mmc_pm_flag_t slot_pm_flags; |
2f4cbb3d | 1166 | mmc_pm_flag_t pm_flags = 0; |
b8c86fc5 PO |
1167 | int i, ret; |
1168 | ||
1169 | chip = pci_get_drvdata(pdev); | |
1170 | if (!chip) | |
1171 | return 0; | |
1172 | ||
b177bc91 | 1173 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
1174 | slot = chip->slots[i]; |
1175 | if (!slot) | |
1176 | continue; | |
1177 | ||
29495aa0 | 1178 | ret = sdhci_suspend_host(slot->host); |
b8c86fc5 | 1179 | |
b678b91f AL |
1180 | if (ret) |
1181 | goto err_pci_suspend; | |
2f4cbb3d | 1182 | |
5f619704 DD |
1183 | slot_pm_flags = slot->host->mmc->pm_flags; |
1184 | if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) | |
1185 | sdhci_enable_irq_wakeups(slot->host); | |
1186 | ||
1187 | pm_flags |= slot_pm_flags; | |
b8c86fc5 PO |
1188 | } |
1189 | ||
4489428a | 1190 | if (chip->fixes && chip->fixes->suspend) { |
29495aa0 | 1191 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
1192 | if (ret) |
1193 | goto err_pci_suspend; | |
4489428a PO |
1194 | } |
1195 | ||
b8c86fc5 | 1196 | pci_save_state(pdev); |
2f4cbb3d | 1197 | if (pm_flags & MMC_PM_KEEP_POWER) { |
5f619704 DD |
1198 | if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) { |
1199 | pci_pme_active(pdev, true); | |
2f4cbb3d | 1200 | pci_enable_wake(pdev, PCI_D3hot, 1); |
5f619704 | 1201 | } |
2f4cbb3d NP |
1202 | pci_set_power_state(pdev, PCI_D3hot); |
1203 | } else { | |
29495aa0 | 1204 | pci_enable_wake(pdev, PCI_D3hot, 0); |
2f4cbb3d | 1205 | pci_disable_device(pdev); |
29495aa0 | 1206 | pci_set_power_state(pdev, PCI_D3hot); |
2f4cbb3d | 1207 | } |
b8c86fc5 PO |
1208 | |
1209 | return 0; | |
b678b91f AL |
1210 | |
1211 | err_pci_suspend: | |
1212 | while (--i >= 0) | |
1213 | sdhci_resume_host(chip->slots[i]->host); | |
1214 | return ret; | |
b8c86fc5 PO |
1215 | } |
1216 | ||
29495aa0 | 1217 | static int sdhci_pci_resume(struct device *dev) |
b8c86fc5 | 1218 | { |
29495aa0 | 1219 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
1220 | struct sdhci_pci_chip *chip; |
1221 | struct sdhci_pci_slot *slot; | |
1222 | int i, ret; | |
1223 | ||
1224 | chip = pci_get_drvdata(pdev); | |
1225 | if (!chip) | |
1226 | return 0; | |
1227 | ||
1228 | pci_set_power_state(pdev, PCI_D0); | |
1229 | pci_restore_state(pdev); | |
1230 | ret = pci_enable_device(pdev); | |
1231 | if (ret) | |
1232 | return ret; | |
1233 | ||
45211e21 PO |
1234 | if (chip->fixes && chip->fixes->resume) { |
1235 | ret = chip->fixes->resume(chip); | |
1236 | if (ret) | |
1237 | return ret; | |
1238 | } | |
1239 | ||
b177bc91 | 1240 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
1241 | slot = chip->slots[i]; |
1242 | if (!slot) | |
1243 | continue; | |
1244 | ||
1245 | ret = sdhci_resume_host(slot->host); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | } | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | #else /* CONFIG_PM */ | |
1254 | ||
1255 | #define sdhci_pci_suspend NULL | |
1256 | #define sdhci_pci_resume NULL | |
1257 | ||
1258 | #endif /* CONFIG_PM */ | |
1259 | ||
66fd8ad5 AH |
1260 | #ifdef CONFIG_PM_RUNTIME |
1261 | ||
1262 | static int sdhci_pci_runtime_suspend(struct device *dev) | |
1263 | { | |
1264 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1265 | struct sdhci_pci_chip *chip; | |
1266 | struct sdhci_pci_slot *slot; | |
66fd8ad5 AH |
1267 | int i, ret; |
1268 | ||
1269 | chip = pci_get_drvdata(pdev); | |
1270 | if (!chip) | |
1271 | return 0; | |
1272 | ||
1273 | for (i = 0; i < chip->num_slots; i++) { | |
1274 | slot = chip->slots[i]; | |
1275 | if (!slot) | |
1276 | continue; | |
1277 | ||
1278 | ret = sdhci_runtime_suspend_host(slot->host); | |
1279 | ||
b678b91f AL |
1280 | if (ret) |
1281 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1282 | } |
1283 | ||
1284 | if (chip->fixes && chip->fixes->suspend) { | |
29495aa0 | 1285 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
1286 | if (ret) |
1287 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1288 | } |
1289 | ||
1290 | return 0; | |
b678b91f AL |
1291 | |
1292 | err_pci_runtime_suspend: | |
1293 | while (--i >= 0) | |
1294 | sdhci_runtime_resume_host(chip->slots[i]->host); | |
1295 | return ret; | |
66fd8ad5 AH |
1296 | } |
1297 | ||
1298 | static int sdhci_pci_runtime_resume(struct device *dev) | |
1299 | { | |
1300 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1301 | struct sdhci_pci_chip *chip; | |
1302 | struct sdhci_pci_slot *slot; | |
1303 | int i, ret; | |
1304 | ||
1305 | chip = pci_get_drvdata(pdev); | |
1306 | if (!chip) | |
1307 | return 0; | |
1308 | ||
1309 | if (chip->fixes && chip->fixes->resume) { | |
1310 | ret = chip->fixes->resume(chip); | |
1311 | if (ret) | |
1312 | return ret; | |
1313 | } | |
1314 | ||
1315 | for (i = 0; i < chip->num_slots; i++) { | |
1316 | slot = chip->slots[i]; | |
1317 | if (!slot) | |
1318 | continue; | |
1319 | ||
1320 | ret = sdhci_runtime_resume_host(slot->host); | |
1321 | if (ret) | |
1322 | return ret; | |
1323 | } | |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
1328 | static int sdhci_pci_runtime_idle(struct device *dev) | |
1329 | { | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | #else | |
1334 | ||
1335 | #define sdhci_pci_runtime_suspend NULL | |
1336 | #define sdhci_pci_runtime_resume NULL | |
1337 | #define sdhci_pci_runtime_idle NULL | |
1338 | ||
1339 | #endif | |
1340 | ||
1341 | static const struct dev_pm_ops sdhci_pci_pm_ops = { | |
29495aa0 ML |
1342 | .suspend = sdhci_pci_suspend, |
1343 | .resume = sdhci_pci_resume, | |
66fd8ad5 AH |
1344 | .runtime_suspend = sdhci_pci_runtime_suspend, |
1345 | .runtime_resume = sdhci_pci_runtime_resume, | |
1346 | .runtime_idle = sdhci_pci_runtime_idle, | |
1347 | }; | |
1348 | ||
b8c86fc5 PO |
1349 | /*****************************************************************************\ |
1350 | * * | |
1351 | * Device probing/removal * | |
1352 | * * | |
1353 | \*****************************************************************************/ | |
1354 | ||
c3be1efd | 1355 | static struct sdhci_pci_slot *sdhci_pci_probe_slot( |
52c506f0 AH |
1356 | struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, |
1357 | int slotno) | |
b8c86fc5 PO |
1358 | { |
1359 | struct sdhci_pci_slot *slot; | |
1360 | struct sdhci_host *host; | |
52c506f0 | 1361 | int ret, bar = first_bar + slotno; |
b8c86fc5 PO |
1362 | |
1363 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
1364 | dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); | |
1365 | return ERR_PTR(-ENODEV); | |
1366 | } | |
1367 | ||
90b3e6c5 | 1368 | if (pci_resource_len(pdev, bar) < 0x100) { |
b8c86fc5 PO |
1369 | dev_err(&pdev->dev, "Invalid iomem size. You may " |
1370 | "experience problems.\n"); | |
1371 | } | |
1372 | ||
1373 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1374 | dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); | |
1375 | return ERR_PTR(-ENODEV); | |
1376 | } | |
1377 | ||
1378 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1379 | dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); | |
1380 | return ERR_PTR(-ENODEV); | |
1381 | } | |
1382 | ||
1383 | host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); | |
1384 | if (IS_ERR(host)) { | |
c60a32cd | 1385 | dev_err(&pdev->dev, "cannot allocate host\n"); |
dc0fd7b5 | 1386 | return ERR_CAST(host); |
b8c86fc5 PO |
1387 | } |
1388 | ||
1389 | slot = sdhci_priv(host); | |
1390 | ||
1391 | slot->chip = chip; | |
1392 | slot->host = host; | |
1393 | slot->pci_bar = bar; | |
0f201655 | 1394 | slot->rst_n_gpio = -EINVAL; |
c5e027a4 | 1395 | slot->cd_gpio = -EINVAL; |
b8c86fc5 | 1396 | |
52c506f0 AH |
1397 | /* Retrieve platform data if there is any */ |
1398 | if (*sdhci_pci_get_data) | |
1399 | slot->data = sdhci_pci_get_data(pdev, slotno); | |
1400 | ||
1401 | if (slot->data) { | |
1402 | if (slot->data->setup) { | |
1403 | ret = slot->data->setup(slot->data); | |
1404 | if (ret) { | |
1405 | dev_err(&pdev->dev, "platform setup failed\n"); | |
1406 | goto free; | |
1407 | } | |
1408 | } | |
c5e027a4 AH |
1409 | slot->rst_n_gpio = slot->data->rst_n_gpio; |
1410 | slot->cd_gpio = slot->data->cd_gpio; | |
52c506f0 AH |
1411 | } |
1412 | ||
b8c86fc5 PO |
1413 | host->hw_name = "PCI"; |
1414 | host->ops = &sdhci_pci_ops; | |
1415 | host->quirks = chip->quirks; | |
f3c55a7b | 1416 | host->quirks2 = chip->quirks2; |
b8c86fc5 PO |
1417 | |
1418 | host->irq = pdev->irq; | |
1419 | ||
1420 | ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); | |
1421 | if (ret) { | |
1422 | dev_err(&pdev->dev, "cannot request region\n"); | |
52c506f0 | 1423 | goto cleanup; |
b8c86fc5 PO |
1424 | } |
1425 | ||
092f82ed | 1426 | host->ioaddr = pci_ioremap_bar(pdev, bar); |
b8c86fc5 PO |
1427 | if (!host->ioaddr) { |
1428 | dev_err(&pdev->dev, "failed to remap registers\n"); | |
9fdcdbb0 | 1429 | ret = -ENOMEM; |
b8c86fc5 PO |
1430 | goto release; |
1431 | } | |
1432 | ||
4489428a PO |
1433 | if (chip->fixes && chip->fixes->probe_slot) { |
1434 | ret = chip->fixes->probe_slot(slot); | |
1435 | if (ret) | |
1436 | goto unmap; | |
1437 | } | |
1438 | ||
c5e027a4 AH |
1439 | if (gpio_is_valid(slot->rst_n_gpio)) { |
1440 | if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) { | |
1441 | gpio_direction_output(slot->rst_n_gpio, 1); | |
1442 | slot->host->mmc->caps |= MMC_CAP_HW_RESET; | |
c9faff6c | 1443 | slot->hw_reset = sdhci_pci_gpio_hw_reset; |
c5e027a4 AH |
1444 | } else { |
1445 | dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); | |
1446 | slot->rst_n_gpio = -EINVAL; | |
1447 | } | |
1448 | } | |
1449 | ||
2f4cbb3d | 1450 | host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; |
eed222ac | 1451 | host->mmc->slotno = slotno; |
a08b17be | 1452 | host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; |
2f4cbb3d | 1453 | |
b8c86fc5 PO |
1454 | ret = sdhci_add_host(host); |
1455 | if (ret) | |
4489428a | 1456 | goto remove; |
b8c86fc5 | 1457 | |
c5e027a4 AH |
1458 | sdhci_pci_add_own_cd(slot); |
1459 | ||
b8c86fc5 PO |
1460 | return slot; |
1461 | ||
4489428a | 1462 | remove: |
c5e027a4 AH |
1463 | if (gpio_is_valid(slot->rst_n_gpio)) |
1464 | gpio_free(slot->rst_n_gpio); | |
1465 | ||
4489428a | 1466 | if (chip->fixes && chip->fixes->remove_slot) |
1e72859e | 1467 | chip->fixes->remove_slot(slot, 0); |
4489428a | 1468 | |
b8c86fc5 PO |
1469 | unmap: |
1470 | iounmap(host->ioaddr); | |
1471 | ||
1472 | release: | |
1473 | pci_release_region(pdev, bar); | |
c60a32cd | 1474 | |
52c506f0 AH |
1475 | cleanup: |
1476 | if (slot->data && slot->data->cleanup) | |
1477 | slot->data->cleanup(slot->data); | |
1478 | ||
c60a32cd | 1479 | free: |
b8c86fc5 PO |
1480 | sdhci_free_host(host); |
1481 | ||
1482 | return ERR_PTR(ret); | |
1483 | } | |
1484 | ||
1485 | static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) | |
1486 | { | |
1e72859e PO |
1487 | int dead; |
1488 | u32 scratch; | |
1489 | ||
c5e027a4 AH |
1490 | sdhci_pci_remove_own_cd(slot); |
1491 | ||
1e72859e PO |
1492 | dead = 0; |
1493 | scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); | |
1494 | if (scratch == (u32)-1) | |
1495 | dead = 1; | |
1496 | ||
1497 | sdhci_remove_host(slot->host, dead); | |
4489428a | 1498 | |
c5e027a4 AH |
1499 | if (gpio_is_valid(slot->rst_n_gpio)) |
1500 | gpio_free(slot->rst_n_gpio); | |
1501 | ||
4489428a | 1502 | if (slot->chip->fixes && slot->chip->fixes->remove_slot) |
1e72859e | 1503 | slot->chip->fixes->remove_slot(slot, dead); |
4489428a | 1504 | |
52c506f0 AH |
1505 | if (slot->data && slot->data->cleanup) |
1506 | slot->data->cleanup(slot->data); | |
1507 | ||
b8c86fc5 | 1508 | pci_release_region(slot->chip->pdev, slot->pci_bar); |
4489428a | 1509 | |
b8c86fc5 PO |
1510 | sdhci_free_host(slot->host); |
1511 | } | |
1512 | ||
c3be1efd | 1513 | static void sdhci_pci_runtime_pm_allow(struct device *dev) |
66fd8ad5 AH |
1514 | { |
1515 | pm_runtime_put_noidle(dev); | |
1516 | pm_runtime_allow(dev); | |
1517 | pm_runtime_set_autosuspend_delay(dev, 50); | |
1518 | pm_runtime_use_autosuspend(dev); | |
1519 | pm_suspend_ignore_children(dev, 1); | |
1520 | } | |
1521 | ||
6e0ee714 | 1522 | static void sdhci_pci_runtime_pm_forbid(struct device *dev) |
66fd8ad5 AH |
1523 | { |
1524 | pm_runtime_forbid(dev); | |
1525 | pm_runtime_get_noresume(dev); | |
1526 | } | |
1527 | ||
c3be1efd | 1528 | static int sdhci_pci_probe(struct pci_dev *pdev, |
b8c86fc5 PO |
1529 | const struct pci_device_id *ent) |
1530 | { | |
1531 | struct sdhci_pci_chip *chip; | |
1532 | struct sdhci_pci_slot *slot; | |
1533 | ||
cf5e23e1 | 1534 | u8 slots, first_bar; |
b8c86fc5 PO |
1535 | int ret, i; |
1536 | ||
1537 | BUG_ON(pdev == NULL); | |
1538 | BUG_ON(ent == NULL); | |
1539 | ||
b8c86fc5 | 1540 | dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", |
cf5e23e1 | 1541 | (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); |
b8c86fc5 PO |
1542 | |
1543 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1544 | if (ret) | |
1545 | return ret; | |
1546 | ||
1547 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1548 | dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); | |
1549 | if (slots == 0) | |
1550 | return -ENODEV; | |
1551 | ||
1552 | BUG_ON(slots > MAX_SLOTS); | |
1553 | ||
1554 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1555 | if (ret) | |
1556 | return ret; | |
1557 | ||
1558 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1559 | ||
1560 | if (first_bar > 5) { | |
1561 | dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); | |
1562 | return -ENODEV; | |
1563 | } | |
1564 | ||
1565 | ret = pci_enable_device(pdev); | |
1566 | if (ret) | |
1567 | return ret; | |
1568 | ||
1569 | chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); | |
1570 | if (!chip) { | |
1571 | ret = -ENOMEM; | |
1572 | goto err; | |
1573 | } | |
1574 | ||
1575 | chip->pdev = pdev; | |
b177bc91 | 1576 | chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; |
c43fd774 | 1577 | if (chip->fixes) { |
22606405 | 1578 | chip->quirks = chip->fixes->quirks; |
f3c55a7b | 1579 | chip->quirks2 = chip->fixes->quirks2; |
c43fd774 AH |
1580 | chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; |
1581 | } | |
b8c86fc5 PO |
1582 | chip->num_slots = slots; |
1583 | ||
1584 | pci_set_drvdata(pdev, chip); | |
1585 | ||
22606405 PO |
1586 | if (chip->fixes && chip->fixes->probe) { |
1587 | ret = chip->fixes->probe(chip); | |
1588 | if (ret) | |
1589 | goto free; | |
1590 | } | |
1591 | ||
225d85fe AC |
1592 | slots = chip->num_slots; /* Quirk may have changed this */ |
1593 | ||
b177bc91 | 1594 | for (i = 0; i < slots; i++) { |
52c506f0 | 1595 | slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); |
b8c86fc5 | 1596 | if (IS_ERR(slot)) { |
b177bc91 | 1597 | for (i--; i >= 0; i--) |
b8c86fc5 PO |
1598 | sdhci_pci_remove_slot(chip->slots[i]); |
1599 | ret = PTR_ERR(slot); | |
1600 | goto free; | |
1601 | } | |
1602 | ||
1603 | chip->slots[i] = slot; | |
1604 | } | |
1605 | ||
c43fd774 AH |
1606 | if (chip->allow_runtime_pm) |
1607 | sdhci_pci_runtime_pm_allow(&pdev->dev); | |
66fd8ad5 | 1608 | |
b8c86fc5 PO |
1609 | return 0; |
1610 | ||
1611 | free: | |
1612 | pci_set_drvdata(pdev, NULL); | |
1613 | kfree(chip); | |
1614 | ||
1615 | err: | |
1616 | pci_disable_device(pdev); | |
1617 | return ret; | |
1618 | } | |
1619 | ||
6e0ee714 | 1620 | static void sdhci_pci_remove(struct pci_dev *pdev) |
b8c86fc5 PO |
1621 | { |
1622 | int i; | |
1623 | struct sdhci_pci_chip *chip; | |
1624 | ||
1625 | chip = pci_get_drvdata(pdev); | |
1626 | ||
1627 | if (chip) { | |
c43fd774 AH |
1628 | if (chip->allow_runtime_pm) |
1629 | sdhci_pci_runtime_pm_forbid(&pdev->dev); | |
1630 | ||
b177bc91 | 1631 | for (i = 0; i < chip->num_slots; i++) |
b8c86fc5 PO |
1632 | sdhci_pci_remove_slot(chip->slots[i]); |
1633 | ||
1634 | pci_set_drvdata(pdev, NULL); | |
1635 | kfree(chip); | |
1636 | } | |
1637 | ||
1638 | pci_disable_device(pdev); | |
1639 | } | |
1640 | ||
1641 | static struct pci_driver sdhci_driver = { | |
b177bc91 | 1642 | .name = "sdhci-pci", |
b8c86fc5 | 1643 | .id_table = pci_ids, |
b177bc91 | 1644 | .probe = sdhci_pci_probe, |
0433c143 | 1645 | .remove = sdhci_pci_remove, |
66fd8ad5 AH |
1646 | .driver = { |
1647 | .pm = &sdhci_pci_pm_ops | |
1648 | }, | |
b8c86fc5 PO |
1649 | }; |
1650 | ||
acc69646 | 1651 | module_pci_driver(sdhci_driver); |
b8c86fc5 | 1652 | |
32710e8f | 1653 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 PO |
1654 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); |
1655 | MODULE_LICENSE("GPL"); |