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mmc: sdhci-pci: enable the clear transfer mode register quirk for AMD sdhci
[deliverable/linux.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655 25#include <linux/gpio.h>
66fd8ad5 26#include <linux/pm_runtime.h>
ff59c520 27#include <linux/mmc/slot-gpio.h>
52c506f0 28#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 29
30#include "sdhci.h"
522624f9 31#include "sdhci-pci.h"
01acf691 32#include "sdhci-pci-o2micro.h"
22606405
PO		 33
34/*****************************************************************************\
35 * *
36 * Hardware specific quirk handling *
37 * *
38\*****************************************************************************/
39
40static int ricoh_probe(struct sdhci_pci_chip *chip)
41{
c99436fb
CB		 42 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
43 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 44 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 45 return 0;
46}
47
48static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
49{
50 slot->host->caps =
51 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
52 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 53
ccc92c23
ML		 54 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
55 & SDHCI_CLOCK_BASE_MASK) |
56
57 SDHCI_TIMEOUT_CLK_UNIT |
58 SDHCI_CAN_VDD_330 |
1a1f1f04 59 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 60 SDHCI_CAN_DO_SDMA;
61 return 0;
62}
63
64static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
65{
66 /* Apply a delay to allow controller to settle */
67 /* Otherwise it becomes confused if card state changed
68 during suspend */
69 msleep(500);
22606405
PO		 70 return 0;
71}
72
73static const struct sdhci_pci_fixes sdhci_ricoh = {
74 .probe = ricoh_probe,
84938294
VK		 75 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
76 SDHCI_QUIRK_FORCE_DMA |
77 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 78};
79
ccc92c23
ML		 80static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
81 .probe_slot = ricoh_mmc_probe_slot,
82 .resume = ricoh_mmc_resume,
83 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
84 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
85 SDHCI_QUIRK_NO_CARD_NO_RESET |
86 SDHCI_QUIRK_MISSING_CAPS
87};
88
22606405
PO		 89static const struct sdhci_pci_fixes sdhci_ene_712 = {
90 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
91 SDHCI_QUIRK_BROKEN_DMA,
92};
93
94static const struct sdhci_pci_fixes sdhci_ene_714 = {
95 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
96 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
97 SDHCI_QUIRK_BROKEN_DMA,
98};
99
100static const struct sdhci_pci_fixes sdhci_cafe = {
101 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 102 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 103 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 104 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 105};
106
43e968ce
DB		 107static const struct sdhci_pci_fixes sdhci_intel_qrk = {
108 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
109};
110
68077b02
ML		 111static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
112{
113 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
114 return 0;
115}
116
f9ee3eab
AC		 117/*
118 * ADMA operation is disabled for Moorestown platform due to
119 * hardware bugs.
120 */
35ac6f08 121static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 122{
123 /*
35ac6f08
JP		 124 * slots number is fixed here for MRST as SDIO3/5 are never used and
125 * have hardware bugs.
f9ee3eab
AC		 126 */
127 chip->num_slots = 1;
128 return 0;
129}
130
296e0b03
AS		 131static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
132{
133 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
134 return 0;
135}
136
66fd8ad5
AH		 137#ifdef CONFIG_PM_RUNTIME
138
c5e027a4 139static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 140{
141 struct sdhci_pci_slot *slot = dev_id;
142 struct sdhci_host *host = slot->host;
143
144 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
145 return IRQ_HANDLED;
146}
147
c5e027a4 148static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 149{
c5e027a4 150 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 151
152 slot->cd_gpio = -EINVAL;
153 slot->cd_irq = -EINVAL;
154
c5e027a4
AH		 155 if (!gpio_is_valid(gpio))
156 return;
157
66fd8ad5
AH		 158 err = gpio_request(gpio, "sd_cd");
159 if (err < 0)
160 goto out;
161
162 err = gpio_direction_input(gpio);
163 if (err < 0)
164 goto out_free;
165
166 irq = gpio_to_irq(gpio);
167 if (irq < 0)
168 goto out_free;
169
c5e027a4 170 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 171 IRQF_TRIGGER_FALLING, "sd_cd", slot);
172 if (err)
173 goto out_free;
174
175 slot->cd_gpio = gpio;
176 slot->cd_irq = irq;
66fd8ad5 177
c5e027a4 178 return;
66fd8ad5
AH		 179
180out_free:
181 gpio_free(gpio);
182out:
183 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 184}
185
c5e027a4 186static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 187{
188 if (slot->cd_irq >= 0)
189 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 190 if (gpio_is_valid(slot->cd_gpio))
191 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 192}
193
194#else
195
c5e027a4
AH		 196static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
197{
198}
199
200static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
201{
202}
66fd8ad5
AH		 203
204#endif
205
0d013bcf
AH		 206static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
207{
66fd8ad5 208 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 209 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
210 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 211 return 0;
212}
213
93933508
AH		 214static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
215{
012e4671 216 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 217 return 0;
218}
219
f9ee3eab
AC		 220static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
221 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 222 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 223};
224
35ac6f08 225static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 226 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 227 .probe = mrst_hc_probe,
f9ee3eab
AC		 228};
229
29229052
XS		 230static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
231 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 232 .allow_runtime_pm = true,
77a0122e 233 .own_cd_for_runtime_pm = true,
29229052
XS		 234};
235
0d013bcf
AH		 236static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
237 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 238 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 239 .allow_runtime_pm = true,
93933508 240 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 241};
242
243static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 245 .allow_runtime_pm = true,
0d013bcf 246 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 247};
248
296e0b03
AS		 249static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
250 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
251 .probe_slot = pch_hc_probe_slot,
252};
253
c9faff6c
AH		 254static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
255{
256 u8 reg;
257
258 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
259 reg |= 0x10;
260 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
261 /* For eMMC, minimum is 1us but give it 9us for good measure */
262 udelay(9);
263 reg &= ~0x10;
264 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
265 /* For eMMC, minimum is 200us but give it 300us for good measure */
266 usleep_range(300, 1000);
267}
268
728ef3d1
AH		 269static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
270{
c9faff6c 271 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
f25c3372 272 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR;
728ef3d1 273 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 274 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 275 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
276 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
728ef3d1
AH		 277 return 0;
278}
279
280static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
281{
282 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
283 return 0;
284}
285
ff59c520
AH		 286static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
287{
288 slot->cd_con_id = NULL;
289 slot->cd_idx = 0;
290 slot->cd_override_level = true;
291 return 0;
292}
293
728ef3d1
AH		 294static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
295 .allow_runtime_pm = true,
296 .probe_slot = byt_emmc_probe_slot,
e58e4a0d
AH		 297 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
298 SDHCI_QUIRK2_STOP_WITH_TC,
728ef3d1
AH		 299};
300
301static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
b7574bad
GY		 302 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
303 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 304 .allow_runtime_pm = true,
305 .probe_slot = byt_sdio_probe_slot,
306};
307
308static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
b7574bad 309 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 310 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
311 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 312 .allow_runtime_pm = true,
77a0122e 313 .own_cd_for_runtime_pm = true,
ff59c520 314 .probe_slot = byt_sd_probe_slot,
728ef3d1
AH		 315};
316
8776a165
DC		 317/* Define Host controllers for Intel Merrifield platform */
318#define INTEL_MRFL_EMMC_0 0
319#define INTEL_MRFL_EMMC_1 1
320
321static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
322{
323 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
324 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
325 /* SD support is not ready yet */
326 return -ENODEV;
327
328 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
329 MMC_CAP_1_8V_DDR;
330
331 return 0;
332}
333
334static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
335 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 336 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
337 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 338 .allow_runtime_pm = true,
8776a165
DC		 339 .probe_slot = intel_mrfl_mmc_probe_slot,
340};
341
26daa1ed
JL		 342/* O2Micro extra registers */
343#define O2_SD_LOCK_WP 0xD3
344#define O2_SD_MULTI_VCC3V 0xEE
345#define O2_SD_CLKREQ 0xEC
346#define O2_SD_CAPS 0xE0
347#define O2_SD_ADMA1 0xE2
348#define O2_SD_ADMA2 0xE7
349#define O2_SD_INF_MOD 0xF1
350
45211e21
PO		 351static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
352{
353 u8 scratch;
354 int ret;
355
356 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
357 if (ret)
358 return ret;
359
360 /*
361 * Turn PMOS on [bit 0], set over current detection to 2.4 V
362 * [bit 1:2] and enable over current debouncing [bit 6].
363 */
364 if (on)
365 scratch |= 0x47;
366 else
367 scratch &= ~0x47;
368
369 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
370 if (ret)
371 return ret;
372
373 return 0;
374}
375
376static int jmicron_probe(struct sdhci_pci_chip *chip)
377{
378 int ret;
8f230f45 379 u16 mmcdev = 0;
45211e21 380
93fc48c7
PO		 381 if (chip->pdev->revision == 0) {
382 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
383 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 384 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 385 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 386 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 387 }
388
4489428a
PO		 389 /*
390 * JMicron chips can have two interfaces to the same hardware
391 * in order to work around limitations in Microsoft's driver.
392 * We need to make sure we only bind to one of them.
393 *
394 * This code assumes two things:
395 *
396 * 1. The PCI code adds subfunctions in order.
397 *
398 * 2. The MMC interface has a lower subfunction number
399 * than the SD interface.
400 */
8f230f45
TI		 401 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
402 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
403 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
404 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
405
406 if (mmcdev) {
4489428a
PO		 407 struct pci_dev *sd_dev;
408
409 sd_dev = NULL;
410 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 411 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 412 if ((PCI_SLOT(chip->pdev->devfn) ==
413 PCI_SLOT(sd_dev->devfn)) &&
414 (chip->pdev->bus == sd_dev->bus))
415 break;
416 }
417
418 if (sd_dev) {
419 pci_dev_put(sd_dev);
420 dev_info(&chip->pdev->dev, "Refusing to bind to "
421 "secondary interface.\n");
422 return -ENODEV;
423 }
424 }
425
45211e21
PO		 426 /*
427 * JMicron chips need a bit of a nudge to enable the power
428 * output pins.
429 */
430 ret = jmicron_pmos(chip, 1);
431 if (ret) {
432 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
433 return ret;
434 }
435
82b0e23a
TI		 436 /* quirk for unsable RO-detection on JM388 chips */
437 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
438 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
439 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
440
45211e21
PO		 441 return 0;
442}
443
4489428a
PO		 444static void jmicron_enable_mmc(struct sdhci_host *host, int on)
445{
446 u8 scratch;
447
448 scratch = readb(host->ioaddr + 0xC0);
449
450 if (on)
451 scratch |= 0x01;
452 else
453 scratch &= ~0x01;
454
455 writeb(scratch, host->ioaddr + 0xC0);
456}
457
458static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
459{
2134a922
PO		 460 if (slot->chip->pdev->revision == 0) {
461 u16 version;
462
463 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
464 version = (version & SDHCI_VENDOR_VER_MASK) >>
465 SDHCI_VENDOR_VER_SHIFT;
466
467 /*
468 * Older versions of the chip have lots of nasty glitches
469 * in the ADMA engine. It's best just to avoid it
470 * completely.
471 */
472 if (version < 0xAC)
473 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
474 }
475
8f230f45
TI		 476 /* JM388 MMC doesn't support 1.8V while SD supports it */
477 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
478 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
479 MMC_VDD_29_30 | MMC_VDD_30_31 |
480 MMC_VDD_165_195; /* allow 1.8V */
481 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
482 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
483 }
484
4489428a
PO		 485 /*
486 * The secondary interface requires a bit set to get the
487 * interrupts.
488 */
8f230f45
TI		 489 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
490 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 491 jmicron_enable_mmc(slot->host, 1);
492
d75c1084
TI		 493 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
494
4489428a
PO		 495 return 0;
496}
497
1e72859e 498static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 499{
1e72859e
PO		 500 if (dead)
501 return;
502
8f230f45
TI		 503 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
504 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 505 jmicron_enable_mmc(slot->host, 0);
506}
507
29495aa0 508static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 509{
510 int i;
511
8f230f45
TI		 512 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
513 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 514 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 515 jmicron_enable_mmc(chip->slots[i]->host, 0);
516 }
517
518 return 0;
519}
520
45211e21
PO		 521static int jmicron_resume(struct sdhci_pci_chip *chip)
522{
4489428a
PO		 523 int ret, i;
524
8f230f45
TI		 525 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
526 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 527 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 528 jmicron_enable_mmc(chip->slots[i]->host, 1);
529 }
45211e21
PO		 530
531 ret = jmicron_pmos(chip, 1);
532 if (ret) {
533 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
534 return ret;
535 }
536
537 return 0;
538}
539
26daa1ed 540static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 541 .probe = sdhci_pci_o2_probe,
542 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
543 .probe_slot = sdhci_pci_o2_probe_slot,
544 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 545};
546
22606405 547static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 548 .probe = jmicron_probe,
549
4489428a
PO		 550 .probe_slot = jmicron_probe_slot,
551 .remove_slot = jmicron_remove_slot,
552
553 .suspend = jmicron_suspend,
45211e21 554 .resume = jmicron_resume,
22606405
PO		 555};
556
a7a6186c
NP		 557/* SysKonnect CardBus2SDIO extra registers */
558#define SYSKT_CTRL 0x200
559#define SYSKT_RDFIFO_STAT 0x204
560#define SYSKT_WRFIFO_STAT 0x208
561#define SYSKT_POWER_DATA 0x20c
562#define SYSKT_POWER_330 0xef
563#define SYSKT_POWER_300 0xf8
564#define SYSKT_POWER_184 0xcc
565#define SYSKT_POWER_CMD 0x20d
566#define SYSKT_POWER_START (1 << 7)
567#define SYSKT_POWER_STATUS 0x20e
568#define SYSKT_POWER_STATUS_OK (1 << 0)
569#define SYSKT_BOARD_REV 0x210
570#define SYSKT_CHIP_REV 0x211
571#define SYSKT_CONF_DATA 0x212
572#define SYSKT_CONF_DATA_1V8 (1 << 2)
573#define SYSKT_CONF_DATA_2V5 (1 << 1)
574#define SYSKT_CONF_DATA_3V3 (1 << 0)
575
576static int syskt_probe(struct sdhci_pci_chip *chip)
577{
578 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
579 chip->pdev->class &= ~0x0000FF;
580 chip->pdev->class |= PCI_SDHCI_IFDMA;
581 }
582 return 0;
583}
584
585static int syskt_probe_slot(struct sdhci_pci_slot *slot)
586{
587 int tm, ps;
588
589 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
590 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
591 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
592 "board rev %d.%d, chip rev %d.%d\n",
593 board_rev >> 4, board_rev & 0xf,
594 chip_rev >> 4, chip_rev & 0xf);
595 if (chip_rev >= 0x20)
596 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
597
598 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
599 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
600 udelay(50);
601 tm = 10; /* Wait max 1 ms */
602 do {
603 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
604 if (ps & SYSKT_POWER_STATUS_OK)
605 break;
606 udelay(100);
607 } while (--tm);
608 if (!tm) {
609 dev_err(&slot->chip->pdev->dev,
610 "power regulator never stabilized");
611 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
612 return -ENODEV;
613 }
614
615 return 0;
616}
617
618static const struct sdhci_pci_fixes sdhci_syskt = {
619 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
620 .probe = syskt_probe,
621 .probe_slot = syskt_probe_slot,
622};
623
557b0697
HW		 624static int via_probe(struct sdhci_pci_chip *chip)
625{
626 if (chip->pdev->revision == 0x10)
627 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
628
629 return 0;
630}
631
632static const struct sdhci_pci_fixes sdhci_via = {
633 .probe = via_probe,
634};
635
9107ebbf
MC		 636static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
637{
638 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
639 return 0;
640}
641
642static const struct sdhci_pci_fixes sdhci_rtsx = {
643 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
644 SDHCI_QUIRK2_BROKEN_DDR50,
645 .probe_slot = rtsx_probe_slot,
646};
647
d44f88da
VW		 648static int amd_probe(struct sdhci_pci_chip *chip)
649{
650 struct pci_dev *smbus_dev;
651
652 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
653 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
654
655 if (smbus_dev && (smbus_dev->revision < 0x51))
656 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
657
658 return 0;
659}
660
661static const struct sdhci_pci_fixes sdhci_amd = {
662 .probe = amd_probe,
663};
664
9647f84d 665static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 666 {
667 .vendor = PCI_VENDOR_ID_RICOH,
668 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 669 .subvendor = PCI_ANY_ID,
b8c86fc5 670 .subdevice = PCI_ANY_ID,
22606405 671 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 672 },
673
ccc92c23
ML		 674 {
675 .vendor = PCI_VENDOR_ID_RICOH,
676 .device = 0x843,
677 .subvendor = PCI_ANY_ID,
678 .subdevice = PCI_ANY_ID,
679 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
680 },
681
568133eb
PC		 682 {
683 .vendor = PCI_VENDOR_ID_RICOH,
684 .device = 0xe822,
685 .subvendor = PCI_ANY_ID,
686 .subdevice = PCI_ANY_ID,
687 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
688 },
689
5fd11c07
MI		 690 {
691 .vendor = PCI_VENDOR_ID_RICOH,
692 .device = 0xe823,
693 .subvendor = PCI_ANY_ID,
694 .subdevice = PCI_ANY_ID,
695 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
696 },
697
b8c86fc5
PO		 698 {
699 .vendor = PCI_VENDOR_ID_ENE,
700 .device = PCI_DEVICE_ID_ENE_CB712_SD,
701 .subvendor = PCI_ANY_ID,
702 .subdevice = PCI_ANY_ID,
22606405 703 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 704 },
705
706 {
707 .vendor = PCI_VENDOR_ID_ENE,
708 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
709 .subvendor = PCI_ANY_ID,
710 .subdevice = PCI_ANY_ID,
22606405 711 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 712 },
713
714 {
715 .vendor = PCI_VENDOR_ID_ENE,
716 .device = PCI_DEVICE_ID_ENE_CB714_SD,
717 .subvendor = PCI_ANY_ID,
718 .subdevice = PCI_ANY_ID,
22606405 719 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 720 },
721
722 {
723 .vendor = PCI_VENDOR_ID_ENE,
724 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
725 .subvendor = PCI_ANY_ID,
726 .subdevice = PCI_ANY_ID,
22606405 727 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 728 },
729
730 {
731 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 732 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 733 .subvendor = PCI_ANY_ID,
734 .subdevice = PCI_ANY_ID,
22606405 735 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 736 },
737
738 {
739 .vendor = PCI_VENDOR_ID_JMICRON,
740 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
741 .subvendor = PCI_ANY_ID,
742 .subdevice = PCI_ANY_ID,
22606405 743 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 744 },
745
4489428a
PO		 746 {
747 .vendor = PCI_VENDOR_ID_JMICRON,
748 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
749 .subvendor = PCI_ANY_ID,
750 .subdevice = PCI_ANY_ID,
751 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 752 },
753
754 {
755 .vendor = PCI_VENDOR_ID_JMICRON,
756 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
757 .subvendor = PCI_ANY_ID,
758 .subdevice = PCI_ANY_ID,
759 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
760 },
761
762 {
763 .vendor = PCI_VENDOR_ID_JMICRON,
764 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
765 .subvendor = PCI_ANY_ID,
766 .subdevice = PCI_ANY_ID,
767 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 768 },
769
a7a6186c
NP		 770 {
771 .vendor = PCI_VENDOR_ID_SYSKONNECT,
772 .device = 0x8000,
773 .subvendor = PCI_ANY_ID,
774 .subdevice = PCI_ANY_ID,
775 .driver_data = (kernel_ulong_t)&sdhci_syskt,
776 },
777
557b0697
HW		 778 {
779 .vendor = PCI_VENDOR_ID_VIA,
780 .device = 0x95d0,
781 .subvendor = PCI_ANY_ID,
782 .subdevice = PCI_ANY_ID,
783 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 784 },
785
786 {
787 .vendor = PCI_VENDOR_ID_REALTEK,
788 .device = 0x5250,
789 .subvendor = PCI_ANY_ID,
790 .subdevice = PCI_ANY_ID,
791 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 792 },
793
43e968ce
DB		 794 {
795 .vendor = PCI_VENDOR_ID_INTEL,
796 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
797 .subvendor = PCI_ANY_ID,
798 .subdevice = PCI_ANY_ID,
799 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
800 },
801
29229052
XS		 802 {
803 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 804 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
808 },
809
810 {
811 .vendor = PCI_VENDOR_ID_INTEL,
812 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
813 .subvendor = PCI_ANY_ID,
814 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 815 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
816 },
817
818 {
819 .vendor = PCI_VENDOR_ID_INTEL,
820 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
821 .subvendor = PCI_ANY_ID,
822 .subdevice = PCI_ANY_ID,
823 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 824 },
825
826 {
827 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 828 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
829 .subvendor = PCI_ANY_ID,
830 .subdevice = PCI_ANY_ID,
831 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
832 },
833
834 {
835 .vendor = PCI_VENDOR_ID_INTEL,
836 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
837 .subvendor = PCI_ANY_ID,
838 .subdevice = PCI_ANY_ID,
0d013bcf 839 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 840 },
841
842 {
843 .vendor = PCI_VENDOR_ID_INTEL,
844 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
845 .subvendor = PCI_ANY_ID,
846 .subdevice = PCI_ANY_ID,
0d013bcf 847 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 848 },
849
850 {
851 .vendor = PCI_VENDOR_ID_INTEL,
852 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
853 .subvendor = PCI_ANY_ID,
854 .subdevice = PCI_ANY_ID,
0d013bcf 855 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 856 },
857
858 {
859 .vendor = PCI_VENDOR_ID_INTEL,
860 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
861 .subvendor = PCI_ANY_ID,
862 .subdevice = PCI_ANY_ID,
0d013bcf 863 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 864 },
865
296e0b03
AS		 866 {
867 .vendor = PCI_VENDOR_ID_INTEL,
868 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
869 .subvendor = PCI_ANY_ID,
870 .subdevice = PCI_ANY_ID,
871 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
872 },
873
874 {
875 .vendor = PCI_VENDOR_ID_INTEL,
876 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
877 .subvendor = PCI_ANY_ID,
878 .subdevice = PCI_ANY_ID,
879 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
880 },
881
728ef3d1
AH		 882 {
883 .vendor = PCI_VENDOR_ID_INTEL,
884 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
885 .subvendor = PCI_ANY_ID,
886 .subdevice = PCI_ANY_ID,
887 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
888 },
889
890 {
891 .vendor = PCI_VENDOR_ID_INTEL,
892 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
893 .subvendor = PCI_ANY_ID,
894 .subdevice = PCI_ANY_ID,
895 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
896 },
897
898 {
899 .vendor = PCI_VENDOR_ID_INTEL,
900 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
901 .subvendor = PCI_ANY_ID,
902 .subdevice = PCI_ANY_ID,
903 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
904 },
905
30d025c0
AH		 906 {
907 .vendor = PCI_VENDOR_ID_INTEL,
908 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
909 .subvendor = PCI_ANY_ID,
910 .subdevice = PCI_ANY_ID,
911 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
912 },
913
066173b6
AC		 914 {
915 .vendor = PCI_VENDOR_ID_INTEL,
916 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
917 .subvendor = PCI_ANY_ID,
918 .subdevice = PCI_ANY_ID,
919 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
920 },
921
922 {
923 .vendor = PCI_VENDOR_ID_INTEL,
924 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
925 .subvendor = PCI_ANY_ID,
926 .subdevice = PCI_ANY_ID,
927 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
928 },
929
930 {
931 .vendor = PCI_VENDOR_ID_INTEL,
932 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
933 .subvendor = PCI_ANY_ID,
934 .subdevice = PCI_ANY_ID,
935 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
936 },
d052068a
EE		 937
938 {
939 .vendor = PCI_VENDOR_ID_INTEL,
940 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
941 .subvendor = PCI_ANY_ID,
942 .subdevice = PCI_ANY_ID,
943 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
944 },
945
946 {
947 .vendor = PCI_VENDOR_ID_INTEL,
948 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
949 .subvendor = PCI_ANY_ID,
950 .subdevice = PCI_ANY_ID,
951 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
952 },
953
954 {
955 .vendor = PCI_VENDOR_ID_INTEL,
956 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
959 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
960 },
961
962 {
963 .vendor = PCI_VENDOR_ID_INTEL,
964 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
965 .subvendor = PCI_ANY_ID,
966 .subdevice = PCI_ANY_ID,
967 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
968 },
969
970 {
971 .vendor = PCI_VENDOR_ID_INTEL,
972 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
973 .subvendor = PCI_ANY_ID,
974 .subdevice = PCI_ANY_ID,
975 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
976 },
977
8776a165
DC		 978 {
979 .vendor = PCI_VENDOR_ID_INTEL,
980 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
981 .subvendor = PCI_ANY_ID,
982 .subdevice = PCI_ANY_ID,
983 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
984 },
26daa1ed
JL		 985 {
986 .vendor = PCI_VENDOR_ID_O2,
987 .device = PCI_DEVICE_ID_O2_8120,
988 .subvendor = PCI_ANY_ID,
989 .subdevice = PCI_ANY_ID,
990 .driver_data = (kernel_ulong_t)&sdhci_o2,
991 },
992
993 {
994 .vendor = PCI_VENDOR_ID_O2,
995 .device = PCI_DEVICE_ID_O2_8220,
996 .subvendor = PCI_ANY_ID,
997 .subdevice = PCI_ANY_ID,
998 .driver_data = (kernel_ulong_t)&sdhci_o2,
999 },
1000
1001 {
1002 .vendor = PCI_VENDOR_ID_O2,
1003 .device = PCI_DEVICE_ID_O2_8221,
1004 .subvendor = PCI_ANY_ID,
1005 .subdevice = PCI_ANY_ID,
1006 .driver_data = (kernel_ulong_t)&sdhci_o2,
1007 },
1008
1009 {
1010 .vendor = PCI_VENDOR_ID_O2,
1011 .device = PCI_DEVICE_ID_O2_8320,
1012 .subvendor = PCI_ANY_ID,
1013 .subdevice = PCI_ANY_ID,
1014 .driver_data = (kernel_ulong_t)&sdhci_o2,
1015 },
1016
1017 {
1018 .vendor = PCI_VENDOR_ID_O2,
1019 .device = PCI_DEVICE_ID_O2_8321,
1020 .subvendor = PCI_ANY_ID,
1021 .subdevice = PCI_ANY_ID,
1022 .driver_data = (kernel_ulong_t)&sdhci_o2,
1023 },
1024
01acf691
AL		 1025 {
1026 .vendor = PCI_VENDOR_ID_O2,
1027 .device = PCI_DEVICE_ID_O2_FUJIN2,
1028 .subvendor = PCI_ANY_ID,
1029 .subdevice = PCI_ANY_ID,
1030 .driver_data = (kernel_ulong_t)&sdhci_o2,
1031 },
1032
1033 {
1034 .vendor = PCI_VENDOR_ID_O2,
1035 .device = PCI_DEVICE_ID_O2_SDS0,
1036 .subvendor = PCI_ANY_ID,
1037 .subdevice = PCI_ANY_ID,
1038 .driver_data = (kernel_ulong_t)&sdhci_o2,
1039 },
1040
1041 {
1042 .vendor = PCI_VENDOR_ID_O2,
1043 .device = PCI_DEVICE_ID_O2_SDS1,
1044 .subvendor = PCI_ANY_ID,
1045 .subdevice = PCI_ANY_ID,
1046 .driver_data = (kernel_ulong_t)&sdhci_o2,
1047 },
1048
1049 {
1050 .vendor = PCI_VENDOR_ID_O2,
1051 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1052 .subvendor = PCI_ANY_ID,
1053 .subdevice = PCI_ANY_ID,
1054 .driver_data = (kernel_ulong_t)&sdhci_o2,
1055 },
1056
1057 {
1058 .vendor = PCI_VENDOR_ID_O2,
1059 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1060 .subvendor = PCI_ANY_ID,
1061 .subdevice = PCI_ANY_ID,
1062 .driver_data = (kernel_ulong_t)&sdhci_o2,
1063 },
d44f88da
VW		 1064 {
1065 .vendor = PCI_VENDOR_ID_AMD,
1066 .device = PCI_ANY_ID,
1067 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1068 .class_mask = 0xFFFF00,
1069 .subvendor = PCI_ANY_ID,
1070 .subdevice = PCI_ANY_ID,
1071 .driver_data = (kernel_ulong_t)&sdhci_amd,
1072 },
b8c86fc5
PO		 1073 { /* Generic SD host controller */
1074 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1075 },
1076
1077 { /* end: all zeroes */ },
1078};
1079
1080MODULE_DEVICE_TABLE(pci, pci_ids);
1081
b8c86fc5
PO		 1082/*****************************************************************************\
1083 * *
1084 * SDHCI core callbacks *
1085 * *
1086\*****************************************************************************/
1087
1088static int sdhci_pci_enable_dma(struct sdhci_host *host)
1089{
1090 struct sdhci_pci_slot *slot;
1091 struct pci_dev *pdev;
3828ecaa 1092 int ret = -1;
b8c86fc5
PO		 1093
1094 slot = sdhci_priv(host);
1095 pdev = slot->chip->pdev;
1096
1097 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1098 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1099 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1100 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1101 "doesn't fully claim to support it.\n");
1102 }
1103
3828ecaa
AH		 1104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1105 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1106 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1107 } else {
1108 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1109 if (ret)
1110 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1111 }
1112 }
1113 if (ret)
1114 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 1115 if (ret)
1116 return ret;
1117
1118 pci_set_master(pdev);
1119
1120 return 0;
1121}
1122
2317f56c 1123static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1124{
1125 u8 ctrl;
1126
1127 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1128
1129 switch (width) {
1130 case MMC_BUS_WIDTH_8:
1131 ctrl |= SDHCI_CTRL_8BITBUS;
1132 ctrl &= ~SDHCI_CTRL_4BITBUS;
1133 break;
1134 case MMC_BUS_WIDTH_4:
1135 ctrl |= SDHCI_CTRL_4BITBUS;
1136 ctrl &= ~SDHCI_CTRL_8BITBUS;
1137 break;
1138 default:
1139 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1140 break;
1141 }
1142
1143 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1144}
1145
c9faff6c 1146static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1147{
1148 struct sdhci_pci_slot *slot = sdhci_priv(host);
1149 int rst_n_gpio = slot->rst_n_gpio;
1150
1151 if (!gpio_is_valid(rst_n_gpio))
1152 return;
1153 gpio_set_value_cansleep(rst_n_gpio, 0);
1154 /* For eMMC, minimum is 1us but give it 10us for good measure */
1155 udelay(10);
1156 gpio_set_value_cansleep(rst_n_gpio, 1);
1157 /* For eMMC, minimum is 200us but give it 300us for good measure */
1158 usleep_range(300, 1000);
1159}
1160
c9faff6c
AH		 1161static void sdhci_pci_hw_reset(struct sdhci_host *host)
1162{
1163 struct sdhci_pci_slot *slot = sdhci_priv(host);
1164
1165 if (slot->hw_reset)
1166 slot->hw_reset(host);
1167}
1168
c915568d 1169static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1170 .set_clock = sdhci_set_clock,
b8c86fc5 1171 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1172 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1173 .reset = sdhci_reset,
96d7b78c 1174 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1175 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1176};
1177
1178/*****************************************************************************\
1179 * *
1180 * Suspend/resume *
1181 * *
1182\*****************************************************************************/
1183
1184#ifdef CONFIG_PM
1185
29495aa0 1186static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1187{
29495aa0 1188 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1189 struct sdhci_pci_chip *chip;
1190 struct sdhci_pci_slot *slot;
5f619704 1191 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1192 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1193 int i, ret;
1194
1195 chip = pci_get_drvdata(pdev);
1196 if (!chip)
1197 return 0;
1198
b177bc91 1199 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1200 slot = chip->slots[i];
1201 if (!slot)
1202 continue;
1203
29495aa0 1204 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1205
b678b91f
AL		 1206 if (ret)
1207 goto err_pci_suspend;
2f4cbb3d 1208
5f619704
DD		 1209 slot_pm_flags = slot->host->mmc->pm_flags;
1210 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1211 sdhci_enable_irq_wakeups(slot->host);
1212
1213 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1214 }
1215
4489428a 1216 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1217 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1218 if (ret)
1219 goto err_pci_suspend;
4489428a
PO		 1220 }
1221
2f4cbb3d 1222 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1223 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1224 device_init_wakeup(dev, true);
1225 else
1226 device_init_wakeup(dev, false);
1227 } else
1228 device_init_wakeup(dev, false);
b8c86fc5
PO		 1229
1230 return 0;
b678b91f
AL		 1231
1232err_pci_suspend:
1233 while (--i >= 0)
1234 sdhci_resume_host(chip->slots[i]->host);
1235 return ret;
b8c86fc5
PO		 1236}
1237
29495aa0 1238static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1239{
29495aa0 1240 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1241 struct sdhci_pci_chip *chip;
1242 struct sdhci_pci_slot *slot;
1243 int i, ret;
1244
1245 chip = pci_get_drvdata(pdev);
1246 if (!chip)
1247 return 0;
1248
45211e21
PO		 1249 if (chip->fixes && chip->fixes->resume) {
1250 ret = chip->fixes->resume(chip);
1251 if (ret)
1252 return ret;
1253 }
1254
b177bc91 1255 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1256 slot = chip->slots[i];
1257 if (!slot)
1258 continue;
1259
1260 ret = sdhci_resume_host(slot->host);
1261 if (ret)
1262 return ret;
1263 }
1264
1265 return 0;
1266}
1267
1268#else /* CONFIG_PM */
1269
1270#define sdhci_pci_suspend NULL
1271#define sdhci_pci_resume NULL
1272
1273#endif /* CONFIG_PM */
1274
66fd8ad5
AH		 1275#ifdef CONFIG_PM_RUNTIME
1276
1277static int sdhci_pci_runtime_suspend(struct device *dev)
1278{
1279 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1280 struct sdhci_pci_chip *chip;
1281 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1282 int i, ret;
1283
1284 chip = pci_get_drvdata(pdev);
1285 if (!chip)
1286 return 0;
1287
1288 for (i = 0; i < chip->num_slots; i++) {
1289 slot = chip->slots[i];
1290 if (!slot)
1291 continue;
1292
1293 ret = sdhci_runtime_suspend_host(slot->host);
1294
b678b91f
AL		 1295 if (ret)
1296 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1297 }
1298
1299 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1300 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1301 if (ret)
1302 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1303 }
1304
1305 return 0;
b678b91f
AL		 1306
1307err_pci_runtime_suspend:
1308 while (--i >= 0)
1309 sdhci_runtime_resume_host(chip->slots[i]->host);
1310 return ret;
66fd8ad5
AH		 1311}
1312
1313static int sdhci_pci_runtime_resume(struct device *dev)
1314{
1315 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1316 struct sdhci_pci_chip *chip;
1317 struct sdhci_pci_slot *slot;
1318 int i, ret;
1319
1320 chip = pci_get_drvdata(pdev);
1321 if (!chip)
1322 return 0;
1323
1324 if (chip->fixes && chip->fixes->resume) {
1325 ret = chip->fixes->resume(chip);
1326 if (ret)
1327 return ret;
1328 }
1329
1330 for (i = 0; i < chip->num_slots; i++) {
1331 slot = chip->slots[i];
1332 if (!slot)
1333 continue;
1334
1335 ret = sdhci_runtime_resume_host(slot->host);
1336 if (ret)
1337 return ret;
1338 }
1339
1340 return 0;
1341}
1342
1343static int sdhci_pci_runtime_idle(struct device *dev)
1344{
1345 return 0;
1346}
1347
66fd8ad5
AH		 1348#endif
1349
1350static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1351 .suspend = sdhci_pci_suspend,
1352 .resume = sdhci_pci_resume,
f3a92b1a
PG		 1353 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1354 sdhci_pci_runtime_resume, sdhci_pci_runtime_idle)
66fd8ad5
AH		 1355};
1356
b8c86fc5
PO		 1357/*****************************************************************************\
1358 * *
1359 * Device probing/removal *
1360 * *
1361\*****************************************************************************/
1362
c3be1efd 1363static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1364 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1365 int slotno)
b8c86fc5
PO		 1366{
1367 struct sdhci_pci_slot *slot;
1368 struct sdhci_host *host;
52c506f0 1369 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1370
1371 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1372 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1373 return ERR_PTR(-ENODEV);
1374 }
1375
90b3e6c5 1376 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1377 dev_err(&pdev->dev, "Invalid iomem size. You may "
1378 "experience problems.\n");
1379 }
1380
1381 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1382 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1383 return ERR_PTR(-ENODEV);
1384 }
1385
1386 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1387 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1388 return ERR_PTR(-ENODEV);
1389 }
1390
1391 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1392 if (IS_ERR(host)) {
c60a32cd 1393 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1394 return ERR_CAST(host);
b8c86fc5
PO		 1395 }
1396
1397 slot = sdhci_priv(host);
1398
1399 slot->chip = chip;
1400 slot->host = host;
1401 slot->pci_bar = bar;
0f201655 1402 slot->rst_n_gpio = -EINVAL;
c5e027a4 1403 slot->cd_gpio = -EINVAL;
ff59c520 1404 slot->cd_idx = -1;
b8c86fc5 1405
52c506f0
AH		 1406 /* Retrieve platform data if there is any */
1407 if (*sdhci_pci_get_data)
1408 slot->data = sdhci_pci_get_data(pdev, slotno);
1409
1410 if (slot->data) {
1411 if (slot->data->setup) {
1412 ret = slot->data->setup(slot->data);
1413 if (ret) {
1414 dev_err(&pdev->dev, "platform setup failed\n");
1415 goto free;
1416 }
1417 }
c5e027a4
AH		 1418 slot->rst_n_gpio = slot->data->rst_n_gpio;
1419 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1420 }
1421
b8c86fc5
PO		 1422 host->hw_name = "PCI";
1423 host->ops = &sdhci_pci_ops;
1424 host->quirks = chip->quirks;
f3c55a7b 1425 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1426
1427 host->irq = pdev->irq;
1428
1429 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1430 if (ret) {
1431 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1432 goto cleanup;
b8c86fc5
PO		 1433 }
1434
092f82ed 1435 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1436 if (!host->ioaddr) {
1437 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1438 ret = -ENOMEM;
b8c86fc5
PO		 1439 goto release;
1440 }
1441
4489428a
PO		 1442 if (chip->fixes && chip->fixes->probe_slot) {
1443 ret = chip->fixes->probe_slot(slot);
1444 if (ret)
1445 goto unmap;
1446 }
1447
c5e027a4
AH		 1448 if (gpio_is_valid(slot->rst_n_gpio)) {
1449 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1450 gpio_direction_output(slot->rst_n_gpio, 1);
1451 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1452 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1453 } else {
1454 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1455 slot->rst_n_gpio = -EINVAL;
1456 }
1457 }
1458
2f4cbb3d 1459 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1460 host->mmc->slotno = slotno;
a08b17be 1461 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1462
ff59c520
AH		 1463 if (slot->cd_idx >= 0 &&
1464 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1465 slot->cd_override_level, 0, NULL)) {
1466 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1467 slot->cd_idx = -1;
1468 }
1469
b8c86fc5
PO		 1470 ret = sdhci_add_host(host);
1471 if (ret)
4489428a 1472 goto remove;
b8c86fc5 1473
c5e027a4
AH		 1474 sdhci_pci_add_own_cd(slot);
1475
77a0122e
AH		 1476 /*
1477 * Check if the chip needs a separate GPIO for card detect to wake up
1478 * from runtime suspend. If it is not there, don't allow runtime PM.
1479 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1480 */
945be38c 1481 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1482 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1483 chip->allow_runtime_pm = false;
1484
b8c86fc5
PO		 1485 return slot;
1486
4489428a 1487remove:
c5e027a4
AH		 1488 if (gpio_is_valid(slot->rst_n_gpio))
1489 gpio_free(slot->rst_n_gpio);
1490
4489428a 1491 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1492 chip->fixes->remove_slot(slot, 0);
4489428a 1493
b8c86fc5
PO		 1494unmap:
1495 iounmap(host->ioaddr);
1496
1497release:
1498 pci_release_region(pdev, bar);
c60a32cd 1499
52c506f0
AH		 1500cleanup:
1501 if (slot->data && slot->data->cleanup)
1502 slot->data->cleanup(slot->data);
1503
c60a32cd 1504free:
b8c86fc5
PO		 1505 sdhci_free_host(host);
1506
1507 return ERR_PTR(ret);
1508}
1509
1510static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1511{
1e72859e
PO		 1512 int dead;
1513 u32 scratch;
1514
c5e027a4
AH		 1515 sdhci_pci_remove_own_cd(slot);
1516
1e72859e
PO		 1517 dead = 0;
1518 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1519 if (scratch == (u32)-1)
1520 dead = 1;
1521
1522 sdhci_remove_host(slot->host, dead);
4489428a 1523
c5e027a4
AH		 1524 if (gpio_is_valid(slot->rst_n_gpio))
1525 gpio_free(slot->rst_n_gpio);
1526
4489428a 1527 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1528 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1529
52c506f0
AH		 1530 if (slot->data && slot->data->cleanup)
1531 slot->data->cleanup(slot->data);
1532
b8c86fc5 1533 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1534
b8c86fc5
PO		 1535 sdhci_free_host(slot->host);
1536}
1537
c3be1efd 1538static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1539{
1540 pm_runtime_put_noidle(dev);
1541 pm_runtime_allow(dev);
1542 pm_runtime_set_autosuspend_delay(dev, 50);
1543 pm_runtime_use_autosuspend(dev);
1544 pm_suspend_ignore_children(dev, 1);
1545}
1546
6e0ee714 1547static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1548{
1549 pm_runtime_forbid(dev);
1550 pm_runtime_get_noresume(dev);
1551}
1552
c3be1efd 1553static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1554 const struct pci_device_id *ent)
1555{
1556 struct sdhci_pci_chip *chip;
1557 struct sdhci_pci_slot *slot;
1558
cf5e23e1 1559 u8 slots, first_bar;
b8c86fc5
PO		 1560 int ret, i;
1561
1562 BUG_ON(pdev == NULL);
1563 BUG_ON(ent == NULL);
1564
b8c86fc5 1565 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1566 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1567
1568 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1569 if (ret)
1570 return ret;
1571
1572 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1573 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1574 if (slots == 0)
1575 return -ENODEV;
1576
1577 BUG_ON(slots > MAX_SLOTS);
1578
1579 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1580 if (ret)
1581 return ret;
1582
1583 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1584
1585 if (first_bar > 5) {
1586 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1587 return -ENODEV;
1588 }
1589
1590 ret = pci_enable_device(pdev);
1591 if (ret)
1592 return ret;
1593
1594 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1595 if (!chip) {
1596 ret = -ENOMEM;
1597 goto err;
1598 }
1599
1600 chip->pdev = pdev;
b177bc91 1601 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1602 if (chip->fixes) {
22606405 1603 chip->quirks = chip->fixes->quirks;
f3c55a7b 1604 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1605 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1606 }
b8c86fc5
PO		 1607 chip->num_slots = slots;
1608
1609 pci_set_drvdata(pdev, chip);
1610
22606405
PO		 1611 if (chip->fixes && chip->fixes->probe) {
1612 ret = chip->fixes->probe(chip);
1613 if (ret)
1614 goto free;
1615 }
1616
225d85fe
AC		 1617 slots = chip->num_slots; /* Quirk may have changed this */
1618
b177bc91 1619 for (i = 0; i < slots; i++) {
52c506f0 1620 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1621 if (IS_ERR(slot)) {
b177bc91 1622 for (i--; i >= 0; i--)
b8c86fc5
PO		 1623 sdhci_pci_remove_slot(chip->slots[i]);
1624 ret = PTR_ERR(slot);
1625 goto free;
1626 }
1627
1628 chip->slots[i] = slot;
1629 }
1630
c43fd774
AH		 1631 if (chip->allow_runtime_pm)
1632 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1633
b8c86fc5
PO		 1634 return 0;
1635
1636free:
1637 pci_set_drvdata(pdev, NULL);
1638 kfree(chip);
1639
1640err:
1641 pci_disable_device(pdev);
1642 return ret;
1643}
1644
6e0ee714 1645static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1646{
1647 int i;
1648 struct sdhci_pci_chip *chip;
1649
1650 chip = pci_get_drvdata(pdev);
1651
1652 if (chip) {
c43fd774
AH		 1653 if (chip->allow_runtime_pm)
1654 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1655
b177bc91 1656 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1657 sdhci_pci_remove_slot(chip->slots[i]);
1658
1659 pci_set_drvdata(pdev, NULL);
1660 kfree(chip);
1661 }
1662
1663 pci_disable_device(pdev);
1664}
1665
1666static struct pci_driver sdhci_driver = {
b177bc91 1667 .name = "sdhci-pci",
b8c86fc5 1668 .id_table = pci_ids,
b177bc91 1669 .probe = sdhci_pci_probe,
0433c143 1670 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1671 .driver = {
1672 .pm = &sdhci_pci_pm_ops
1673 },
b8c86fc5
PO		 1674};
1675
acc69646 1676module_pci_driver(sdhci_driver);
b8c86fc5 1677
32710e8f 1678MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1679MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1680MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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