[deliverable/linux.git] / drivers / mmc / host / sdhci-tegra.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/gpio/consumer.h>

#include "sdhci-pltfm.h"

/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_MISC_CTRL		0x120
#define SDHCI_MISC_CTRL_ENABLE_SDR104		0x8
#define SDHCI_MISC_CTRL_ENABLE_SDR50		0x10
#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300	0x20
#define SDHCI_MISC_CTRL_ENABLE_DDR50		0x200

#define NVQUIRK_FORCE_SDHCI_SPEC_200	BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET	BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300	BIT(2)
#define NVQUIRK_DISABLE_SDR50		BIT(3)
#define NVQUIRK_DISABLE_SDR104		BIT(4)
#define NVQUIRK_DISABLE_DDR50		BIT(5)

struct sdhci_tegra_soc_data {
	const struct sdhci_pltfm_data *pdata;
	u32 nvquirks;
};

struct sdhci_tegra {
	const struct sdhci_tegra_soc_data *soc_data;
	struct gpio_desc *power_gpio;
};

static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
			(reg == SDHCI_HOST_VERSION))) {
		/* Erratum: Version register is invalid in HW. */
		return SDHCI_SPEC_200;
	}

	return readw(host->ioaddr + reg);
}

static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below.
		 */
		pltfm_host->xfer_mode_shadow = val;
		return;
	case SDHCI_COMMAND:
		writel((val << 16) | pltfm_host->xfer_mode_shadow,
			host->ioaddr + SDHCI_TRANSFER_MODE);
		return;
	}

	writew(val, host->ioaddr + reg);
}

static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	/* Seems like we're getting spurious timeout and crc errors, so
	 * disable signalling of them. In case of real errors software
	 * timers should take care of eventually detecting them.
	 */
	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
		val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);

	writel(val, host->ioaddr + reg);

	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
			(reg == SDHCI_INT_ENABLE))) {
		/* Erratum: Must enable block gap interrupt detection */
		u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
		if (val & SDHCI_INT_CARD_INT)
			gap_ctrl |= 0x8;
		else
			gap_ctrl &= ~0x8;
		writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	}
}

static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
{
	return mmc_gpio_get_ro(host->mmc);
}

static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	u32 misc_ctrl;

	sdhci_reset(host, mask);

	if (!(mask & SDHCI_RESET_ALL))
		return;

	misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	/* Erratum: Enable SDHCI spec v3.00 support */
	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
		misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
	/* Don't advertise UHS modes which aren't supported yet */
	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
	if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
	sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
}

static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
{
	u32 ctrl;

	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
	    (bus_width == MMC_BUS_WIDTH_8)) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (bus_width == MMC_BUS_WIDTH_4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

static const struct sdhci_ops tegra_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = sdhci_set_clock,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.set_uhs_signaling = sdhci_set_uhs_signaling,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra20 = {
	.pdata = &sdhci_tegra20_pdata,
	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
		    NVQUIRK_ENABLE_BLOCK_GAP_DET,
};

static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra30 = {
	.pdata = &sdhci_tegra30_pdata,
	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
		    NVQUIRK_DISABLE_SDR50 |
		    NVQUIRK_DISABLE_SDR104,
};

static const struct sdhci_ops tegra114_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_w    = tegra_sdhci_writew,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = sdhci_set_clock,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.set_uhs_signaling = sdhci_set_uhs_signaling,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra114_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra114 = {
	.pdata = &sdhci_tegra114_pdata,
	.nvquirks = NVQUIRK_DISABLE_SDR50 |
		    NVQUIRK_DISABLE_DDR50 |
		    NVQUIRK_DISABLE_SDR104,
};

static const struct of_device_id sdhci_tegra_dt_match[] = {
	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);

static int sdhci_tegra_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	const struct sdhci_tegra_soc_data *soc_data;
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_tegra *tegra_host;
	struct clk *clk;
	int rc;

	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);
	pltfm_host = sdhci_priv(host);

	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	if (!tegra_host) {
		dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
		rc = -ENOMEM;
		goto err_alloc_tegra_host;
	}
	tegra_host->soc_data = soc_data;
	pltfm_host->priv = tegra_host;

	rc = mmc_of_parse(host->mmc);
	if (rc)
		goto err_parse_dt;

	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
							 GPIOD_OUT_HIGH);
	if (IS_ERR(tegra_host->power_gpio)) {
		rc = PTR_ERR(tegra_host->power_gpio);
		goto err_power_req;
	}

	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		rc = PTR_ERR(clk);
		goto err_clk_get;
	}
	clk_prepare_enable(clk);
	pltfm_host->clk = clk;

	rc = sdhci_add_host(host);
	if (rc)
		goto err_add_host;

	return 0;

err_add_host:
	clk_disable_unprepare(pltfm_host->clk);
err_clk_get:
err_power_req:
err_parse_dt:
err_alloc_tegra_host:
	sdhci_pltfm_free(pdev);
	return rc;
}

static struct platform_driver sdhci_tegra_driver = {
	.driver		= {
		.name	= "sdhci-tegra",
		.of_match_table = sdhci_tegra_dt_match,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.probe		= sdhci_tegra_probe,
	.remove		= sdhci_pltfm_unregister,
};

module_platform_driver(sdhci_tegra_driver);

MODULE_DESCRIPTION("SDHCI driver for Tegra");
MODULE_AUTHOR("Google, Inc.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
03d2bfc8 OJ	1	/*
	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
	15	#include <linux/err.h>
96547f5d	16	#include <linux/module.h>
03d2bfc8 OJ	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/clk.h>
	20	#include <linux/io.h>
55cd65e4	21	#include <linux/of.h>
3e44a1a7	22	#include <linux/of_device.h>
03d2bfc8 OJ	23	#include <linux/mmc/card.h>
03d2bfc8 OJ	24	#include <linux/mmc/host.h>
0aacd23f	25	#include <linux/mmc/slot-gpio.h>
2391b340	26	#include <linux/gpio/consumer.h>
03d2bfc8	27
03d2bfc8 OJ	28	#include "sdhci-pltfm.h"
03d2bfc8 OJ	29
ca5879d3 PK	30	/* Tegra SDHOST controller vendor register definitions */
ca5879d3 PK	31	#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
3145351a AB	32	#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
3145351a AB	33	#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
ca5879d3	34	#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
3145351a	35	#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
ca5879d3	36
3e44a1a7 SW	37	#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
3e44a1a7 SW	38	#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
ca5879d3	39	#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
3145351a AB	40	#define NVQUIRK_DISABLE_SDR50 BIT(3)
	41	#define NVQUIRK_DISABLE_SDR104 BIT(4)
	42	#define NVQUIRK_DISABLE_DDR50 BIT(5)
3e44a1a7 SW	43
3e44a1a7 SW	44	struct sdhci_tegra_soc_data {
1db5eebf	45	const struct sdhci_pltfm_data *pdata;
3e44a1a7 SW	46	u32 nvquirks;
	47	};
	48
	49	struct sdhci_tegra {
3e44a1a7	50	const struct sdhci_tegra_soc_data *soc_data;
2391b340	51	struct gpio_desc *power_gpio;
3e44a1a7 SW	52	};
3e44a1a7 SW	53
03d2bfc8 OJ	54	static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
03d2bfc8 OJ	55	{
3e44a1a7 SW	56	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	57	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	58	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	59
	60	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
	61	(reg == SDHCI_HOST_VERSION))) {
03d2bfc8 OJ	62	/* Erratum: Version register is invalid in HW. */
	63	return SDHCI_SPEC_200;
	64	}
	65
	66	return readw(host->ioaddr + reg);
	67	}
	68
352ee868 PK	69	static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	70	{
	71	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
352ee868	72
01df7ecd RK	73	switch (reg) {
	74	case SDHCI_TRANSFER_MODE:
	75	/*
	76	* Postpone this write, we must do it together with a
	77	* command write that is down below.
	78	*/
	79	pltfm_host->xfer_mode_shadow = val;
	80	return;
	81	case SDHCI_COMMAND:
	82	writel((val << 16) \| pltfm_host->xfer_mode_shadow,
	83	host->ioaddr + SDHCI_TRANSFER_MODE);
	84	return;
352ee868 PK	85	}
	86
	87	writew(val, host->ioaddr + reg);
	88	}
	89
03d2bfc8 OJ	90	static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
03d2bfc8 OJ	91	{
3e44a1a7 SW	92	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	93	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	94	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	95
03d2bfc8 OJ	96	/* Seems like we're getting spurious timeout and crc errors, so
	97	* disable signalling of them. In case of real errors software
	98	* timers should take care of eventually detecting them.
	99	*/
	100	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
	101	val &= ~(SDHCI_INT_TIMEOUT\|SDHCI_INT_CRC);
	102
	103	writel(val, host->ioaddr + reg);
	104
3e44a1a7 SW	105	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
3e44a1a7 SW	106	(reg == SDHCI_INT_ENABLE))) {
03d2bfc8 OJ	107	/* Erratum: Must enable block gap interrupt detection */
	108	u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	109	if (val & SDHCI_INT_CARD_INT)
	110	gap_ctrl \|= 0x8;
	111	else
	112	gap_ctrl &= ~0x8;
	113	writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	114	}
	115	}
	116
3e44a1a7	117	static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
03d2bfc8	118	{
0aacd23f	119	return mmc_gpio_get_ro(host->mmc);
03d2bfc8 OJ	120	}
03d2bfc8 OJ	121
03231f9b	122	static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
ca5879d3 PK	123	{
	124	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	125	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	126	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
3145351a	127	u32 misc_ctrl;
ca5879d3	128
03231f9b RK	129	sdhci_reset(host, mask);
03231f9b RK	130
ca5879d3 PK	131	if (!(mask & SDHCI_RESET_ALL))
	132	return;
	133
3145351a	134	misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
ca5879d3	135	/* Erratum: Enable SDHCI spec v3.00 support */
3145351a	136	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
ca5879d3	137	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
3145351a AB	138	/* Don't advertise UHS modes which aren't supported yet */
	139	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
	140	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
	141	if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
	142	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
	143	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
	144	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
	145	sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
ca5879d3 PK	146	}
ca5879d3 PK	147
2317f56c	148	static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
03d2bfc8	149	{
03d2bfc8 OJ	150	u32 ctrl;
03d2bfc8 OJ	151
03d2bfc8	152	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
0aacd23f JL	153	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
0aacd23f JL	154	(bus_width == MMC_BUS_WIDTH_8)) {
03d2bfc8 OJ	155	ctrl &= ~SDHCI_CTRL_4BITBUS;
	156	ctrl \|= SDHCI_CTRL_8BITBUS;
	157	} else {
	158	ctrl &= ~SDHCI_CTRL_8BITBUS;
	159	if (bus_width == MMC_BUS_WIDTH_4)
	160	ctrl \|= SDHCI_CTRL_4BITBUS;
	161	else
	162	ctrl &= ~SDHCI_CTRL_4BITBUS;
	163	}
	164	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
03d2bfc8 OJ	165	}
03d2bfc8 OJ	166
c915568d	167	static const struct sdhci_ops tegra_sdhci_ops = {
85d6509d	168	.get_ro = tegra_sdhci_get_ro,
85d6509d SG	169	.read_w = tegra_sdhci_readw,
85d6509d SG	170	.write_l = tegra_sdhci_writel,
1771059c	171	.set_clock = sdhci_set_clock,
2317f56c	172	.set_bus_width = tegra_sdhci_set_bus_width,
03231f9b	173	.reset = tegra_sdhci_reset,
96d7b78c	174	.set_uhs_signaling = sdhci_set_uhs_signaling,
f9260355	175	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
85d6509d SG	176	};
85d6509d SG	177
1db5eebf	178	static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
3e44a1a7 SW	179	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	180	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	181	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	182	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	183	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
3e44a1a7 SW	184	.ops = &tegra_sdhci_ops,
	185	};
	186
	187	static struct sdhci_tegra_soc_data soc_data_tegra20 = {
	188	.pdata = &sdhci_tegra20_pdata,
	189	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 \|
	190	NVQUIRK_ENABLE_BLOCK_GAP_DET,
	191	};
3e44a1a7	192
1db5eebf	193	static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
85d6509d	194	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
3e44a1a7	195	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
85d6509d SG	196	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
85d6509d SG	197	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	198	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	199	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
85d6509d SG	200	.ops = &tegra_sdhci_ops,
85d6509d SG	201	};
03d2bfc8	202
3e44a1a7 SW	203	static struct sdhci_tegra_soc_data soc_data_tegra30 = {
3e44a1a7 SW	204	.pdata = &sdhci_tegra30_pdata,
3145351a AB	205	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 \|
	206	NVQUIRK_DISABLE_SDR50 \|
	207	NVQUIRK_DISABLE_SDR104,
3e44a1a7	208	};
3e44a1a7	209
01df7ecd RK	210	static const struct sdhci_ops tegra114_sdhci_ops = {
	211	.get_ro = tegra_sdhci_get_ro,
	212	.read_w = tegra_sdhci_readw,
	213	.write_w = tegra_sdhci_writew,
	214	.write_l = tegra_sdhci_writel,
	215	.set_clock = sdhci_set_clock,
	216	.set_bus_width = tegra_sdhci_set_bus_width,
	217	.reset = tegra_sdhci_reset,
	218	.set_uhs_signaling = sdhci_set_uhs_signaling,
	219	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	220	};
	221
1db5eebf	222	static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
5ebf2552 RK	223	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	224	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	225	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	226	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	227	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	228	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
01df7ecd	229	.ops = &tegra114_sdhci_ops,
5ebf2552 RK	230	};
	231
	232	static struct sdhci_tegra_soc_data soc_data_tegra114 = {
	233	.pdata = &sdhci_tegra114_pdata,
3145351a AB	234	.nvquirks = NVQUIRK_DISABLE_SDR50 \|
3145351a AB	235	NVQUIRK_DISABLE_DDR50 \|
01df7ecd	236	NVQUIRK_DISABLE_SDR104,
5ebf2552 RK	237	};
5ebf2552 RK	238
498d83e7	239	static const struct of_device_id sdhci_tegra_dt_match[] = {
67debea3	240	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
5ebf2552	241	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
3e44a1a7	242	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
3e44a1a7	243	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
275173b2 GL	244	{}
275173b2 GL	245	};
e4404fab	246	MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
275173b2	247
c3be1efd	248	static int sdhci_tegra_probe(struct platform_device *pdev)
03d2bfc8	249	{
3e44a1a7 SW	250	const struct of_device_id *match;
	251	const struct sdhci_tegra_soc_data *soc_data;
	252	struct sdhci_host *host;
85d6509d	253	struct sdhci_pltfm_host *pltfm_host;
3e44a1a7	254	struct sdhci_tegra *tegra_host;
03d2bfc8 OJ	255	struct clk *clk;
	256	int rc;
	257
3e44a1a7	258	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
b37f9d98 JL	259	if (!match)
	260	return -EINVAL;
	261	soc_data = match->data;
3e44a1a7	262
0e748234	263	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
85d6509d SG	264	if (IS_ERR(host))
85d6509d SG	265	return PTR_ERR(host);
85d6509d SG	266	pltfm_host = sdhci_priv(host);
85d6509d SG	267
3e44a1a7 SW	268	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	269	if (!tegra_host) {
	270	dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
	271	rc = -ENOMEM;
0e786102	272	goto err_alloc_tegra_host;
3e44a1a7	273	}
3e44a1a7	274	tegra_host->soc_data = soc_data;
3e44a1a7	275	pltfm_host->priv = tegra_host;
275173b2	276
2391b340	277	rc = mmc_of_parse(host->mmc);
47caa84f SB	278	if (rc)
47caa84f SB	279	goto err_parse_dt;
0e786102	280
2391b340 MJ	281	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
	282	GPIOD_OUT_HIGH);
	283	if (IS_ERR(tegra_host->power_gpio)) {
	284	rc = PTR_ERR(tegra_host->power_gpio);
	285	goto err_power_req;
03d2bfc8 OJ	286	}
03d2bfc8 OJ	287
e4f79d9c	288	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
03d2bfc8 OJ	289	if (IS_ERR(clk)) {
	290	dev_err(mmc_dev(host->mmc), "clk err\n");
	291	rc = PTR_ERR(clk);
85d6509d	292	goto err_clk_get;
03d2bfc8	293	}
1e674bc6	294	clk_prepare_enable(clk);
03d2bfc8 OJ	295	pltfm_host->clk = clk;
03d2bfc8 OJ	296
85d6509d SG	297	rc = sdhci_add_host(host);
	298	if (rc)
	299	goto err_add_host;
	300
03d2bfc8 OJ	301	return 0;
03d2bfc8 OJ	302
85d6509d	303	err_add_host:
1e674bc6	304	clk_disable_unprepare(pltfm_host->clk);
85d6509d	305	err_clk_get:
85d6509d	306	err_power_req:
47caa84f	307	err_parse_dt:
0e786102	308	err_alloc_tegra_host:
85d6509d	309	sdhci_pltfm_free(pdev);
03d2bfc8 OJ	310	return rc;
	311	}
	312
85d6509d SG	313	static struct platform_driver sdhci_tegra_driver = {
	314	.driver = {
	315	.name = "sdhci-tegra",
275173b2	316	.of_match_table = sdhci_tegra_dt_match,
29495aa0	317	.pm = SDHCI_PLTFM_PMOPS,
85d6509d SG	318	},
85d6509d SG	319	.probe = sdhci_tegra_probe,
caebcae9	320	.remove = sdhci_pltfm_unregister,
03d2bfc8 OJ	321	};
03d2bfc8 OJ	322
d1f81a64	323	module_platform_driver(sdhci_tegra_driver);
85d6509d SG	324
85d6509d SG	325	MODULE_DESCRIPTION("SDHCI driver for Tegra");
3e44a1a7	326	MODULE_AUTHOR("Google, Inc.");
85d6509d	327	MODULE_LICENSE("GPL v2");