[deliverable/linux.git] / drivers / mmc / host / sdhci-tegra.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>

#include <asm/gpio.h>

#include "sdhci-pltfm.h"

/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_MISC_CTRL		0x120
#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300	0x20

#define NVQUIRK_FORCE_SDHCI_SPEC_200	BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET	BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300	BIT(2)

struct sdhci_tegra_soc_data {
	const struct sdhci_pltfm_data *pdata;
	u32 nvquirks;
};

struct sdhci_tegra {
	const struct sdhci_tegra_soc_data *soc_data;
	int power_gpio;
};

static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
{
	u32 val;

	if (unlikely(reg == SDHCI_PRESENT_STATE)) {
		/* Use wp_gpio here instead? */
		val = readl(host->ioaddr + reg);
		return val | SDHCI_WRITE_PROTECT;
	}

	return readl(host->ioaddr + reg);
}

static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
			(reg == SDHCI_HOST_VERSION))) {
		/* Erratum: Version register is invalid in HW. */
		return SDHCI_SPEC_200;
	}

	return readw(host->ioaddr + reg);
}

static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	/* Seems like we're getting spurious timeout and crc errors, so
	 * disable signalling of them. In case of real errors software
	 * timers should take care of eventually detecting them.
	 */
	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
		val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);

	writel(val, host->ioaddr + reg);

	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
			(reg == SDHCI_INT_ENABLE))) {
		/* Erratum: Must enable block gap interrupt detection */
		u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
		if (val & SDHCI_INT_CARD_INT)
			gap_ctrl |= 0x8;
		else
			gap_ctrl &= ~0x8;
		writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	}
}

static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
{
	return mmc_gpio_get_ro(host->mmc);
}

static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	sdhci_reset(host, mask);

	if (!(mask & SDHCI_RESET_ALL))
		return;

	/* Erratum: Enable SDHCI spec v3.00 support */
	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) {
		u32 misc_ctrl;

		misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
		misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
		sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	}
}

static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
{
	u32 ctrl;

	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
	    (bus_width == MMC_BUS_WIDTH_8)) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (bus_width == MMC_BUS_WIDTH_4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

static const struct sdhci_ops tegra_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_l     = tegra_sdhci_readl,
	.read_w     = tegra_sdhci_readw,
	.write_l    = tegra_sdhci_writel,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
};

static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra20 = {
	.pdata = &sdhci_tegra20_pdata,
	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
		    NVQUIRK_ENABLE_BLOCK_GAP_DET,
};

static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra30 = {
	.pdata = &sdhci_tegra30_pdata,
	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300,
};

static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra114 = {
	.pdata = &sdhci_tegra114_pdata,
};

static const struct of_device_id sdhci_tegra_dt_match[] = {
	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);

static int sdhci_tegra_parse_dt(struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;

	tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
	return mmc_of_parse(host->mmc);
}

static int sdhci_tegra_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	const struct sdhci_tegra_soc_data *soc_data;
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_tegra *tegra_host;
	struct clk *clk;
	int rc;

	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);
	pltfm_host = sdhci_priv(host);

	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	if (!tegra_host) {
		dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
		rc = -ENOMEM;
		goto err_alloc_tegra_host;
	}
	tegra_host->soc_data = soc_data;
	pltfm_host->priv = tegra_host;

	rc = sdhci_tegra_parse_dt(&pdev->dev);
	if (rc)
		goto err_parse_dt;

	if (gpio_is_valid(tegra_host->power_gpio)) {
		rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
		if (rc) {
			dev_err(mmc_dev(host->mmc),
				"failed to allocate power gpio\n");
			goto err_power_req;
		}
		gpio_direction_output(tegra_host->power_gpio, 1);
	}

	clk = clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		rc = PTR_ERR(clk);
		goto err_clk_get;
	}
	clk_prepare_enable(clk);
	pltfm_host->clk = clk;

	rc = sdhci_add_host(host);
	if (rc)
		goto err_add_host;

	return 0;

err_add_host:
	clk_disable_unprepare(pltfm_host->clk);
	clk_put(pltfm_host->clk);
err_clk_get:
	if (gpio_is_valid(tegra_host->power_gpio))
		gpio_free(tegra_host->power_gpio);
err_power_req:
err_parse_dt:
err_alloc_tegra_host:
	sdhci_pltfm_free(pdev);
	return rc;
}

static int sdhci_tegra_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);

	sdhci_remove_host(host, dead);

	if (gpio_is_valid(tegra_host->power_gpio))
		gpio_free(tegra_host->power_gpio);

	clk_disable_unprepare(pltfm_host->clk);
	clk_put(pltfm_host->clk);

	sdhci_pltfm_free(pdev);

	return 0;
}

static struct platform_driver sdhci_tegra_driver = {
	.driver		= {
		.name	= "sdhci-tegra",
		.owner	= THIS_MODULE,
		.of_match_table = sdhci_tegra_dt_match,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.probe		= sdhci_tegra_probe,
	.remove		= sdhci_tegra_remove,
};

module_platform_driver(sdhci_tegra_driver);

MODULE_DESCRIPTION("SDHCI driver for Tegra");
MODULE_AUTHOR("Google, Inc.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
03d2bfc8 OJ	1	/*
	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
	15	#include <linux/err.h>
96547f5d	16	#include <linux/module.h>
03d2bfc8 OJ	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/clk.h>
	20	#include <linux/io.h>
55cd65e4	21	#include <linux/of.h>
3e44a1a7	22	#include <linux/of_device.h>
275173b2	23	#include <linux/of_gpio.h>
03d2bfc8 OJ	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
0aacd23f	27	#include <linux/mmc/slot-gpio.h>
03d2bfc8	28
e6b750d4	29	#include <asm/gpio.h>
ea5abbd2	30
03d2bfc8 OJ	31	#include "sdhci-pltfm.h"
03d2bfc8 OJ	32
ca5879d3 PK	33	/* Tegra SDHOST controller vendor register definitions */
	34	#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
	35	#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
	36
3e44a1a7 SW	37	#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
3e44a1a7 SW	38	#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
ca5879d3	39	#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
3e44a1a7 SW	40
3e44a1a7 SW	41	struct sdhci_tegra_soc_data {
1db5eebf	42	const struct sdhci_pltfm_data *pdata;
3e44a1a7 SW	43	u32 nvquirks;
	44	};
	45
	46	struct sdhci_tegra {
3e44a1a7	47	const struct sdhci_tegra_soc_data *soc_data;
0e786102	48	int power_gpio;
3e44a1a7 SW	49	};
3e44a1a7 SW	50
03d2bfc8 OJ	51	static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
	52	{
	53	u32 val;
	54
	55	if (unlikely(reg == SDHCI_PRESENT_STATE)) {
	56	/* Use wp_gpio here instead? */
	57	val = readl(host->ioaddr + reg);
	58	return val \| SDHCI_WRITE_PROTECT;
	59	}
	60
	61	return readl(host->ioaddr + reg);
	62	}
	63
	64	static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
	65	{
3e44a1a7 SW	66	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	67	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	68	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	69
	70	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
	71	(reg == SDHCI_HOST_VERSION))) {
03d2bfc8 OJ	72	/* Erratum: Version register is invalid in HW. */
	73	return SDHCI_SPEC_200;
	74	}
	75
	76	return readw(host->ioaddr + reg);
	77	}
	78
	79	static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	80	{
3e44a1a7 SW	81	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	82	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	83	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	84
03d2bfc8 OJ	85	/* Seems like we're getting spurious timeout and crc errors, so
	86	* disable signalling of them. In case of real errors software
	87	* timers should take care of eventually detecting them.
	88	*/
	89	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
	90	val &= ~(SDHCI_INT_TIMEOUT\|SDHCI_INT_CRC);
	91
	92	writel(val, host->ioaddr + reg);
	93
3e44a1a7 SW	94	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
3e44a1a7 SW	95	(reg == SDHCI_INT_ENABLE))) {
03d2bfc8 OJ	96	/* Erratum: Must enable block gap interrupt detection */
	97	u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	98	if (val & SDHCI_INT_CARD_INT)
	99	gap_ctrl \|= 0x8;
	100	else
	101	gap_ctrl &= ~0x8;
	102	writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	103	}
	104	}
	105
3e44a1a7	106	static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
03d2bfc8	107	{
0aacd23f	108	return mmc_gpio_get_ro(host->mmc);
03d2bfc8 OJ	109	}
03d2bfc8 OJ	110
03231f9b	111	static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
ca5879d3 PK	112	{
	113	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	114	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	115	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	116
03231f9b RK	117	sdhci_reset(host, mask);
03231f9b RK	118
ca5879d3 PK	119	if (!(mask & SDHCI_RESET_ALL))
	120	return;
	121
	122	/* Erratum: Enable SDHCI spec v3.00 support */
	123	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) {
	124	u32 misc_ctrl;
	125
	126	misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	127	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
	128	sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	129	}
	130	}
	131
2317f56c	132	static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
03d2bfc8	133	{
03d2bfc8 OJ	134	u32 ctrl;
03d2bfc8 OJ	135
03d2bfc8	136	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
0aacd23f JL	137	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
0aacd23f JL	138	(bus_width == MMC_BUS_WIDTH_8)) {
03d2bfc8 OJ	139	ctrl &= ~SDHCI_CTRL_4BITBUS;
	140	ctrl \|= SDHCI_CTRL_8BITBUS;
	141	} else {
	142	ctrl &= ~SDHCI_CTRL_8BITBUS;
	143	if (bus_width == MMC_BUS_WIDTH_4)
	144	ctrl \|= SDHCI_CTRL_4BITBUS;
	145	else
	146	ctrl &= ~SDHCI_CTRL_4BITBUS;
	147	}
	148	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
03d2bfc8 OJ	149	}
03d2bfc8 OJ	150
c915568d	151	static const struct sdhci_ops tegra_sdhci_ops = {
85d6509d SG	152	.get_ro = tegra_sdhci_get_ro,
	153	.read_l = tegra_sdhci_readl,
	154	.read_w = tegra_sdhci_readw,
	155	.write_l = tegra_sdhci_writel,
2317f56c	156	.set_bus_width = tegra_sdhci_set_bus_width,
03231f9b	157	.reset = tegra_sdhci_reset,
85d6509d SG	158	};
85d6509d SG	159
1db5eebf	160	static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
3e44a1a7 SW	161	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	162	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	163	SDHCI_QUIRK_NO_HISPD_BIT \|
	164	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
	165	.ops = &tegra_sdhci_ops,
	166	};
	167
	168	static struct sdhci_tegra_soc_data soc_data_tegra20 = {
	169	.pdata = &sdhci_tegra20_pdata,
	170	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 \|
	171	NVQUIRK_ENABLE_BLOCK_GAP_DET,
	172	};
3e44a1a7	173
1db5eebf	174	static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
85d6509d	175	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
3e44a1a7	176	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
85d6509d SG	177	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	178	SDHCI_QUIRK_NO_HISPD_BIT \|
	179	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
	180	.ops = &tegra_sdhci_ops,
	181	};
03d2bfc8	182
3e44a1a7 SW	183	static struct sdhci_tegra_soc_data soc_data_tegra30 = {
3e44a1a7 SW	184	.pdata = &sdhci_tegra30_pdata,
ca5879d3	185	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300,
3e44a1a7	186	};
3e44a1a7	187
1db5eebf	188	static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
5ebf2552 RK	189	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	190	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	191	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	192	SDHCI_QUIRK_NO_HISPD_BIT \|
	193	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
	194	.ops = &tegra_sdhci_ops,
	195	};
	196
	197	static struct sdhci_tegra_soc_data soc_data_tegra114 = {
	198	.pdata = &sdhci_tegra114_pdata,
	199	};
	200
498d83e7	201	static const struct of_device_id sdhci_tegra_dt_match[] = {
67debea3	202	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
5ebf2552	203	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
3e44a1a7	204	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
3e44a1a7	205	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
275173b2 GL	206	{}
275173b2 GL	207	};
e4404fab	208	MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
275173b2	209
47caa84f	210	static int sdhci_tegra_parse_dt(struct device *dev)
275173b2	211	{
0e786102	212	struct device_node *np = dev->of_node;
0aacd23f JL	213	struct sdhci_host *host = dev_get_drvdata(dev);
	214	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	215	struct sdhci_tegra *tegra_host = pltfm_host->priv;
275173b2	216
0e786102	217	tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
47caa84f	218	return mmc_of_parse(host->mmc);
275173b2 GL	219	}
275173b2 GL	220
c3be1efd	221	static int sdhci_tegra_probe(struct platform_device *pdev)
03d2bfc8	222	{
3e44a1a7 SW	223	const struct of_device_id *match;
	224	const struct sdhci_tegra_soc_data *soc_data;
	225	struct sdhci_host *host;
85d6509d	226	struct sdhci_pltfm_host *pltfm_host;
3e44a1a7	227	struct sdhci_tegra *tegra_host;
03d2bfc8 OJ	228	struct clk *clk;
	229	int rc;
	230
3e44a1a7	231	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
b37f9d98 JL	232	if (!match)
	233	return -EINVAL;
	234	soc_data = match->data;
3e44a1a7	235
0e748234	236	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
85d6509d SG	237	if (IS_ERR(host))
85d6509d SG	238	return PTR_ERR(host);
85d6509d SG	239	pltfm_host = sdhci_priv(host);
85d6509d SG	240
3e44a1a7 SW	241	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	242	if (!tegra_host) {
	243	dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
	244	rc = -ENOMEM;
0e786102	245	goto err_alloc_tegra_host;
3e44a1a7	246	}
3e44a1a7	247	tegra_host->soc_data = soc_data;
3e44a1a7	248	pltfm_host->priv = tegra_host;
275173b2	249
47caa84f SB	250	rc = sdhci_tegra_parse_dt(&pdev->dev);
	251	if (rc)
	252	goto err_parse_dt;
0e786102 SW	253
	254	if (gpio_is_valid(tegra_host->power_gpio)) {
	255	rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
03d2bfc8 OJ	256	if (rc) {
	257	dev_err(mmc_dev(host->mmc),
	258	"failed to allocate power gpio\n");
85d6509d	259	goto err_power_req;
03d2bfc8	260	}
0e786102	261	gpio_direction_output(tegra_host->power_gpio, 1);
03d2bfc8 OJ	262	}
03d2bfc8 OJ	263
03d2bfc8 OJ	264	clk = clk_get(mmc_dev(host->mmc), NULL);
	265	if (IS_ERR(clk)) {
	266	dev_err(mmc_dev(host->mmc), "clk err\n");
	267	rc = PTR_ERR(clk);
85d6509d	268	goto err_clk_get;
03d2bfc8	269	}
1e674bc6	270	clk_prepare_enable(clk);
03d2bfc8 OJ	271	pltfm_host->clk = clk;
03d2bfc8 OJ	272
85d6509d SG	273	rc = sdhci_add_host(host);
	274	if (rc)
	275	goto err_add_host;
	276
03d2bfc8 OJ	277	return 0;
03d2bfc8 OJ	278
85d6509d	279	err_add_host:
1e674bc6	280	clk_disable_unprepare(pltfm_host->clk);
85d6509d SG	281	clk_put(pltfm_host->clk);
85d6509d SG	282	err_clk_get:
0e786102 SW	283	if (gpio_is_valid(tegra_host->power_gpio))
0e786102 SW	284	gpio_free(tegra_host->power_gpio);
85d6509d	285	err_power_req:
47caa84f	286	err_parse_dt:
0e786102	287	err_alloc_tegra_host:
85d6509d	288	sdhci_pltfm_free(pdev);
03d2bfc8 OJ	289	return rc;
	290	}
	291
6e0ee714	292	static int sdhci_tegra_remove(struct platform_device *pdev)
03d2bfc8	293	{
85d6509d	294	struct sdhci_host *host = platform_get_drvdata(pdev);
03d2bfc8	295	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3e44a1a7	296	struct sdhci_tegra *tegra_host = pltfm_host->priv;
85d6509d SG	297	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
	298
	299	sdhci_remove_host(host, dead);
03d2bfc8	300
0e786102 SW	301	if (gpio_is_valid(tegra_host->power_gpio))
0e786102 SW	302	gpio_free(tegra_host->power_gpio);
03d2bfc8	303
1e674bc6	304	clk_disable_unprepare(pltfm_host->clk);
03d2bfc8	305	clk_put(pltfm_host->clk);
85d6509d SG	306
	307	sdhci_pltfm_free(pdev);
	308
	309	return 0;
03d2bfc8 OJ	310	}
03d2bfc8 OJ	311
85d6509d SG	312	static struct platform_driver sdhci_tegra_driver = {
	313	.driver = {
	314	.name = "sdhci-tegra",
	315	.owner = THIS_MODULE,
275173b2	316	.of_match_table = sdhci_tegra_dt_match,
29495aa0	317	.pm = SDHCI_PLTFM_PMOPS,
85d6509d SG	318	},
85d6509d SG	319	.probe = sdhci_tegra_probe,
0433c143	320	.remove = sdhci_tegra_remove,
03d2bfc8 OJ	321	};
03d2bfc8 OJ	322
d1f81a64	323	module_platform_driver(sdhci_tegra_driver);
85d6509d SG	324
85d6509d SG	325	MODULE_DESCRIPTION("SDHCI driver for Tegra");
3e44a1a7	326	MODULE_AUTHOR("Google, Inc.");
85d6509d	327	MODULE_LICENSE("GPL v2");