Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
d129bceb | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
11763609 | 21 | #include <linux/scatterlist.h> |
9bea3c85 | 22 | #include <linux/regulator/consumer.h> |
d129bceb | 23 | |
2f730fec PO |
24 | #include <linux/leds.h> |
25 | ||
22113efd | 26 | #include <linux/mmc/mmc.h> |
d129bceb | 27 | #include <linux/mmc/host.h> |
d129bceb | 28 | |
d129bceb PO |
29 | #include "sdhci.h" |
30 | ||
31 | #define DRIVER_NAME "sdhci" | |
d129bceb | 32 | |
d129bceb | 33 | #define DBG(f, x...) \ |
c6563178 | 34 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 35 | |
f9134319 PO |
36 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
37 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
38 | #define SDHCI_USE_LEDS_CLASS | |
39 | #endif | |
40 | ||
df673b22 | 41 | static unsigned int debug_quirks = 0; |
67435274 | 42 | |
d129bceb PO |
43 | static void sdhci_finish_data(struct sdhci_host *); |
44 | ||
45 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
46 | static void sdhci_finish_command(struct sdhci_host *); | |
47 | ||
48 | static void sdhci_dumpregs(struct sdhci_host *host) | |
49 | { | |
412ab659 PR |
50 | printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
51 | mmc_hostname(host->mmc)); | |
d129bceb PO |
52 | |
53 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
4e4141a5 AV |
54 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
55 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
d129bceb | 56 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
57 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
58 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
d129bceb | 59 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
60 | sdhci_readl(host, SDHCI_ARGUMENT), |
61 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
d129bceb | 62 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
63 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
64 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
d129bceb | 65 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
66 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
67 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
d129bceb | 68 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
69 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
70 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
d129bceb | 71 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
72 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
73 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
d129bceb | 74 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
75 | sdhci_readl(host, SDHCI_INT_ENABLE), |
76 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
d129bceb | 77 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
78 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
79 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
e8120ad1 | 80 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 81 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 PR |
82 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
83 | printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", | |
84 | sdhci_readw(host, SDHCI_COMMAND), | |
4e4141a5 | 85 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
f2119df6 AN |
86 | printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n", |
87 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); | |
d129bceb | 88 | |
be3f4ae0 BD |
89 | if (host->flags & SDHCI_USE_ADMA) |
90 | printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
91 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
92 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
93 | ||
d129bceb PO |
94 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); |
95 | } | |
96 | ||
97 | /*****************************************************************************\ | |
98 | * * | |
99 | * Low level functions * | |
100 | * * | |
101 | \*****************************************************************************/ | |
102 | ||
7260cf5e AV |
103 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
104 | { | |
105 | u32 ier; | |
106 | ||
107 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
108 | ier &= ~clear; | |
109 | ier |= set; | |
110 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | |
111 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | |
112 | } | |
113 | ||
114 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | |
115 | { | |
116 | sdhci_clear_set_irqs(host, 0, irqs); | |
117 | } | |
118 | ||
119 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | |
120 | { | |
121 | sdhci_clear_set_irqs(host, irqs, 0); | |
122 | } | |
123 | ||
124 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | |
125 | { | |
126 | u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; | |
127 | ||
68d1fb7e AV |
128 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
129 | return; | |
130 | ||
7260cf5e AV |
131 | if (enable) |
132 | sdhci_unmask_irqs(host, irqs); | |
133 | else | |
134 | sdhci_mask_irqs(host, irqs); | |
135 | } | |
136 | ||
137 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
138 | { | |
139 | sdhci_set_card_detection(host, true); | |
140 | } | |
141 | ||
142 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
143 | { | |
144 | sdhci_set_card_detection(host, false); | |
145 | } | |
146 | ||
d129bceb PO |
147 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
148 | { | |
e16514d8 | 149 | unsigned long timeout; |
063a9dbb | 150 | u32 uninitialized_var(ier); |
e16514d8 | 151 | |
b8c86fc5 | 152 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 153 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
154 | SDHCI_CARD_PRESENT)) |
155 | return; | |
156 | } | |
157 | ||
063a9dbb AV |
158 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
159 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
160 | ||
393c1a34 PR |
161 | if (host->ops->platform_reset_enter) |
162 | host->ops->platform_reset_enter(host, mask); | |
163 | ||
4e4141a5 | 164 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 165 | |
e16514d8 | 166 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
167 | host->clock = 0; |
168 | ||
e16514d8 PO |
169 | /* Wait max 100 ms */ |
170 | timeout = 100; | |
171 | ||
172 | /* hw clears the bit when it's done */ | |
4e4141a5 | 173 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 174 | if (timeout == 0) { |
acf1da45 | 175 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
176 | mmc_hostname(host->mmc), (int)mask); |
177 | sdhci_dumpregs(host); | |
178 | return; | |
179 | } | |
180 | timeout--; | |
181 | mdelay(1); | |
d129bceb | 182 | } |
063a9dbb | 183 | |
393c1a34 PR |
184 | if (host->ops->platform_reset_exit) |
185 | host->ops->platform_reset_exit(host, mask); | |
186 | ||
063a9dbb AV |
187 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
188 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | |
d129bceb PO |
189 | } |
190 | ||
2f4cbb3d NP |
191 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
192 | ||
193 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 194 | { |
2f4cbb3d NP |
195 | if (soft) |
196 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); | |
197 | else | |
198 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 199 | |
7260cf5e AV |
200 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
201 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | |
3192a28f PO |
202 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
203 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
6aa943ab | 204 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
2f4cbb3d NP |
205 | |
206 | if (soft) { | |
207 | /* force clock reconfiguration */ | |
208 | host->clock = 0; | |
209 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
210 | } | |
7260cf5e | 211 | } |
d129bceb | 212 | |
7260cf5e AV |
213 | static void sdhci_reinit(struct sdhci_host *host) |
214 | { | |
2f4cbb3d | 215 | sdhci_init(host, 0); |
7260cf5e | 216 | sdhci_enable_card_detection(host); |
d129bceb PO |
217 | } |
218 | ||
219 | static void sdhci_activate_led(struct sdhci_host *host) | |
220 | { | |
221 | u8 ctrl; | |
222 | ||
4e4141a5 | 223 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 224 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 225 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
226 | } |
227 | ||
228 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
229 | { | |
230 | u8 ctrl; | |
231 | ||
4e4141a5 | 232 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 233 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 234 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
235 | } |
236 | ||
f9134319 | 237 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
238 | static void sdhci_led_control(struct led_classdev *led, |
239 | enum led_brightness brightness) | |
240 | { | |
241 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
242 | unsigned long flags; | |
243 | ||
244 | spin_lock_irqsave(&host->lock, flags); | |
245 | ||
246 | if (brightness == LED_OFF) | |
247 | sdhci_deactivate_led(host); | |
248 | else | |
249 | sdhci_activate_led(host); | |
250 | ||
251 | spin_unlock_irqrestore(&host->lock, flags); | |
252 | } | |
253 | #endif | |
254 | ||
d129bceb PO |
255 | /*****************************************************************************\ |
256 | * * | |
257 | * Core functions * | |
258 | * * | |
259 | \*****************************************************************************/ | |
260 | ||
a406f5a3 | 261 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 262 | { |
7659150c PO |
263 | unsigned long flags; |
264 | size_t blksize, len, chunk; | |
7244b85b | 265 | u32 uninitialized_var(scratch); |
7659150c | 266 | u8 *buf; |
d129bceb | 267 | |
a406f5a3 | 268 | DBG("PIO reading\n"); |
d129bceb | 269 | |
a406f5a3 | 270 | blksize = host->data->blksz; |
7659150c | 271 | chunk = 0; |
d129bceb | 272 | |
7659150c | 273 | local_irq_save(flags); |
d129bceb | 274 | |
a406f5a3 | 275 | while (blksize) { |
7659150c PO |
276 | if (!sg_miter_next(&host->sg_miter)) |
277 | BUG(); | |
d129bceb | 278 | |
7659150c | 279 | len = min(host->sg_miter.length, blksize); |
d129bceb | 280 | |
7659150c PO |
281 | blksize -= len; |
282 | host->sg_miter.consumed = len; | |
14d836e7 | 283 | |
7659150c | 284 | buf = host->sg_miter.addr; |
d129bceb | 285 | |
7659150c PO |
286 | while (len) { |
287 | if (chunk == 0) { | |
4e4141a5 | 288 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 289 | chunk = 4; |
a406f5a3 | 290 | } |
7659150c PO |
291 | |
292 | *buf = scratch & 0xFF; | |
293 | ||
294 | buf++; | |
295 | scratch >>= 8; | |
296 | chunk--; | |
297 | len--; | |
d129bceb | 298 | } |
a406f5a3 | 299 | } |
7659150c PO |
300 | |
301 | sg_miter_stop(&host->sg_miter); | |
302 | ||
303 | local_irq_restore(flags); | |
a406f5a3 | 304 | } |
d129bceb | 305 | |
a406f5a3 PO |
306 | static void sdhci_write_block_pio(struct sdhci_host *host) |
307 | { | |
7659150c PO |
308 | unsigned long flags; |
309 | size_t blksize, len, chunk; | |
310 | u32 scratch; | |
311 | u8 *buf; | |
d129bceb | 312 | |
a406f5a3 PO |
313 | DBG("PIO writing\n"); |
314 | ||
315 | blksize = host->data->blksz; | |
7659150c PO |
316 | chunk = 0; |
317 | scratch = 0; | |
d129bceb | 318 | |
7659150c | 319 | local_irq_save(flags); |
d129bceb | 320 | |
a406f5a3 | 321 | while (blksize) { |
7659150c PO |
322 | if (!sg_miter_next(&host->sg_miter)) |
323 | BUG(); | |
a406f5a3 | 324 | |
7659150c PO |
325 | len = min(host->sg_miter.length, blksize); |
326 | ||
327 | blksize -= len; | |
328 | host->sg_miter.consumed = len; | |
329 | ||
330 | buf = host->sg_miter.addr; | |
d129bceb | 331 | |
7659150c PO |
332 | while (len) { |
333 | scratch |= (u32)*buf << (chunk * 8); | |
334 | ||
335 | buf++; | |
336 | chunk++; | |
337 | len--; | |
338 | ||
339 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 340 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
341 | chunk = 0; |
342 | scratch = 0; | |
d129bceb | 343 | } |
d129bceb PO |
344 | } |
345 | } | |
7659150c PO |
346 | |
347 | sg_miter_stop(&host->sg_miter); | |
348 | ||
349 | local_irq_restore(flags); | |
a406f5a3 PO |
350 | } |
351 | ||
352 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
353 | { | |
354 | u32 mask; | |
355 | ||
356 | BUG_ON(!host->data); | |
357 | ||
7659150c | 358 | if (host->blocks == 0) |
a406f5a3 PO |
359 | return; |
360 | ||
361 | if (host->data->flags & MMC_DATA_READ) | |
362 | mask = SDHCI_DATA_AVAILABLE; | |
363 | else | |
364 | mask = SDHCI_SPACE_AVAILABLE; | |
365 | ||
4a3cba32 PO |
366 | /* |
367 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
368 | * for transfers < 4 bytes. As long as it is just one block, | |
369 | * we can ignore the bits. | |
370 | */ | |
371 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
372 | (host->data->blocks == 1)) | |
373 | mask = ~0; | |
374 | ||
4e4141a5 | 375 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
376 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
377 | udelay(100); | |
378 | ||
a406f5a3 PO |
379 | if (host->data->flags & MMC_DATA_READ) |
380 | sdhci_read_block_pio(host); | |
381 | else | |
382 | sdhci_write_block_pio(host); | |
d129bceb | 383 | |
7659150c PO |
384 | host->blocks--; |
385 | if (host->blocks == 0) | |
a406f5a3 | 386 | break; |
a406f5a3 | 387 | } |
d129bceb | 388 | |
a406f5a3 | 389 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
390 | } |
391 | ||
2134a922 PO |
392 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
393 | { | |
394 | local_irq_save(*flags); | |
395 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
396 | } | |
397 | ||
398 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
399 | { | |
400 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
401 | local_irq_restore(*flags); | |
402 | } | |
403 | ||
118cd17d BD |
404 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
405 | { | |
9e506f35 BD |
406 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
407 | __le16 *cmdlen = (__le16 __force *)desc; | |
118cd17d | 408 | |
9e506f35 BD |
409 | /* SDHCI specification says ADMA descriptors should be 4 byte |
410 | * aligned, so using 16 or 32bit operations should be safe. */ | |
118cd17d | 411 | |
9e506f35 BD |
412 | cmdlen[0] = cpu_to_le16(cmd); |
413 | cmdlen[1] = cpu_to_le16(len); | |
414 | ||
415 | dataddr[0] = cpu_to_le32(addr); | |
118cd17d BD |
416 | } |
417 | ||
8f1934ce | 418 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
419 | struct mmc_data *data) |
420 | { | |
421 | int direction; | |
422 | ||
423 | u8 *desc; | |
424 | u8 *align; | |
425 | dma_addr_t addr; | |
426 | dma_addr_t align_addr; | |
427 | int len, offset; | |
428 | ||
429 | struct scatterlist *sg; | |
430 | int i; | |
431 | char *buffer; | |
432 | unsigned long flags; | |
433 | ||
434 | /* | |
435 | * The spec does not specify endianness of descriptor table. | |
436 | * We currently guess that it is LE. | |
437 | */ | |
438 | ||
439 | if (data->flags & MMC_DATA_READ) | |
440 | direction = DMA_FROM_DEVICE; | |
441 | else | |
442 | direction = DMA_TO_DEVICE; | |
443 | ||
444 | /* | |
445 | * The ADMA descriptor table is mapped further down as we | |
446 | * need to fill it with data first. | |
447 | */ | |
448 | ||
449 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
450 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 451 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 452 | goto fail; |
2134a922 PO |
453 | BUG_ON(host->align_addr & 0x3); |
454 | ||
455 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
456 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
457 | if (host->sg_count == 0) |
458 | goto unmap_align; | |
2134a922 PO |
459 | |
460 | desc = host->adma_desc; | |
461 | align = host->align_buffer; | |
462 | ||
463 | align_addr = host->align_addr; | |
464 | ||
465 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
466 | addr = sg_dma_address(sg); | |
467 | len = sg_dma_len(sg); | |
468 | ||
469 | /* | |
470 | * The SDHCI specification states that ADMA | |
471 | * addresses must be 32-bit aligned. If they | |
472 | * aren't, then we use a bounce buffer for | |
473 | * the (up to three) bytes that screw up the | |
474 | * alignment. | |
475 | */ | |
476 | offset = (4 - (addr & 0x3)) & 0x3; | |
477 | if (offset) { | |
478 | if (data->flags & MMC_DATA_WRITE) { | |
479 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 480 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
481 | memcpy(align, buffer, offset); |
482 | sdhci_kunmap_atomic(buffer, &flags); | |
483 | } | |
484 | ||
118cd17d BD |
485 | /* tran, valid */ |
486 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); | |
2134a922 PO |
487 | |
488 | BUG_ON(offset > 65536); | |
489 | ||
2134a922 PO |
490 | align += 4; |
491 | align_addr += 4; | |
492 | ||
493 | desc += 8; | |
494 | ||
495 | addr += offset; | |
496 | len -= offset; | |
497 | } | |
498 | ||
2134a922 PO |
499 | BUG_ON(len > 65536); |
500 | ||
118cd17d BD |
501 | /* tran, valid */ |
502 | sdhci_set_adma_desc(desc, addr, len, 0x21); | |
2134a922 PO |
503 | desc += 8; |
504 | ||
505 | /* | |
506 | * If this triggers then we have a calculation bug | |
507 | * somewhere. :/ | |
508 | */ | |
509 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
510 | } | |
511 | ||
70764a90 TA |
512 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
513 | /* | |
514 | * Mark the last descriptor as the terminating descriptor | |
515 | */ | |
516 | if (desc != host->adma_desc) { | |
517 | desc -= 8; | |
518 | desc[0] |= 0x2; /* end */ | |
519 | } | |
520 | } else { | |
521 | /* | |
522 | * Add a terminating entry. | |
523 | */ | |
2134a922 | 524 | |
70764a90 TA |
525 | /* nop, end, valid */ |
526 | sdhci_set_adma_desc(desc, 0, 0, 0x3); | |
527 | } | |
2134a922 PO |
528 | |
529 | /* | |
530 | * Resync align buffer as we might have changed it. | |
531 | */ | |
532 | if (data->flags & MMC_DATA_WRITE) { | |
533 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
534 | host->align_addr, 128 * 4, direction); | |
535 | } | |
536 | ||
537 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
538 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 539 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 540 | goto unmap_entries; |
2134a922 | 541 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
542 | |
543 | return 0; | |
544 | ||
545 | unmap_entries: | |
546 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
547 | data->sg_len, direction); | |
548 | unmap_align: | |
549 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
550 | 128 * 4, direction); | |
551 | fail: | |
552 | return -EINVAL; | |
2134a922 PO |
553 | } |
554 | ||
555 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
556 | struct mmc_data *data) | |
557 | { | |
558 | int direction; | |
559 | ||
560 | struct scatterlist *sg; | |
561 | int i, size; | |
562 | u8 *align; | |
563 | char *buffer; | |
564 | unsigned long flags; | |
565 | ||
566 | if (data->flags & MMC_DATA_READ) | |
567 | direction = DMA_FROM_DEVICE; | |
568 | else | |
569 | direction = DMA_TO_DEVICE; | |
570 | ||
571 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
572 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
573 | ||
574 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
575 | 128 * 4, direction); | |
576 | ||
577 | if (data->flags & MMC_DATA_READ) { | |
578 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
579 | data->sg_len, direction); | |
580 | ||
581 | align = host->align_buffer; | |
582 | ||
583 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
584 | if (sg_dma_address(sg) & 0x3) { | |
585 | size = 4 - (sg_dma_address(sg) & 0x3); | |
586 | ||
587 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 588 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
589 | memcpy(buffer, align, size); |
590 | sdhci_kunmap_atomic(buffer, &flags); | |
591 | ||
592 | align += 4; | |
593 | } | |
594 | } | |
595 | } | |
596 | ||
597 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
598 | data->sg_len, direction); | |
599 | } | |
600 | ||
a3c7778f | 601 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 602 | { |
1c8cde92 | 603 | u8 count; |
a3c7778f | 604 | struct mmc_data *data = cmd->data; |
1c8cde92 | 605 | unsigned target_timeout, current_timeout; |
d129bceb | 606 | |
ee53ab5d PO |
607 | /* |
608 | * If the host controller provides us with an incorrect timeout | |
609 | * value, just skip the check and use 0xE. The hardware may take | |
610 | * longer to time out, but that's much better than having a too-short | |
611 | * timeout value. | |
612 | */ | |
11a2f1b7 | 613 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 614 | return 0xE; |
e538fbe8 | 615 | |
a3c7778f AW |
616 | /* Unspecified timeout, assume max */ |
617 | if (!data && !cmd->cmd_timeout_ms) | |
618 | return 0xE; | |
d129bceb | 619 | |
a3c7778f AW |
620 | /* timeout in us */ |
621 | if (!data) | |
622 | target_timeout = cmd->cmd_timeout_ms * 1000; | |
623 | else | |
624 | target_timeout = data->timeout_ns / 1000 + | |
625 | data->timeout_clks / host->clock; | |
81b39802 | 626 | |
4b01681c MB |
627 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) |
628 | host->timeout_clk = host->clock / 1000; | |
629 | ||
1c8cde92 PO |
630 | /* |
631 | * Figure out needed cycles. | |
632 | * We do this in steps in order to fit inside a 32 bit int. | |
633 | * The first step is the minimum timeout, which will have a | |
634 | * minimum resolution of 6 bits: | |
635 | * (1) 2^13*1000 > 2^22, | |
636 | * (2) host->timeout_clk < 2^16 | |
637 | * => | |
638 | * (1) / (2) > 2^6 | |
639 | */ | |
4b01681c | 640 | BUG_ON(!host->timeout_clk); |
1c8cde92 PO |
641 | count = 0; |
642 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
643 | while (current_timeout < target_timeout) { | |
644 | count++; | |
645 | current_timeout <<= 1; | |
646 | if (count >= 0xF) | |
647 | break; | |
648 | } | |
649 | ||
650 | if (count >= 0xF) { | |
a3c7778f AW |
651 | printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n", |
652 | mmc_hostname(host->mmc), cmd->opcode); | |
1c8cde92 PO |
653 | count = 0xE; |
654 | } | |
655 | ||
ee53ab5d PO |
656 | return count; |
657 | } | |
658 | ||
6aa943ab AV |
659 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
660 | { | |
661 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
662 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
663 | ||
664 | if (host->flags & SDHCI_REQ_USE_DMA) | |
665 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | |
666 | else | |
667 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | |
668 | } | |
669 | ||
a3c7778f | 670 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
671 | { |
672 | u8 count; | |
2134a922 | 673 | u8 ctrl; |
a3c7778f | 674 | struct mmc_data *data = cmd->data; |
8f1934ce | 675 | int ret; |
ee53ab5d PO |
676 | |
677 | WARN_ON(host->data); | |
678 | ||
a3c7778f AW |
679 | if (data || (cmd->flags & MMC_RSP_BUSY)) { |
680 | count = sdhci_calc_timeout(host, cmd); | |
681 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
682 | } | |
683 | ||
684 | if (!data) | |
ee53ab5d PO |
685 | return; |
686 | ||
687 | /* Sanity checks */ | |
688 | BUG_ON(data->blksz * data->blocks > 524288); | |
689 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
690 | BUG_ON(data->blocks > 65535); | |
691 | ||
692 | host->data = data; | |
693 | host->data_early = 0; | |
f6a03cbf | 694 | host->data->bytes_xfered = 0; |
ee53ab5d | 695 | |
a13abc7b | 696 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
697 | host->flags |= SDHCI_REQ_USE_DMA; |
698 | ||
2134a922 PO |
699 | /* |
700 | * FIXME: This doesn't account for merging when mapping the | |
701 | * scatterlist. | |
702 | */ | |
703 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
704 | int broken, i; | |
705 | struct scatterlist *sg; | |
706 | ||
707 | broken = 0; | |
708 | if (host->flags & SDHCI_USE_ADMA) { | |
709 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
710 | broken = 1; | |
711 | } else { | |
712 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
713 | broken = 1; | |
714 | } | |
715 | ||
716 | if (unlikely(broken)) { | |
717 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
718 | if (sg->length & 0x3) { | |
719 | DBG("Reverting to PIO because of " | |
720 | "transfer size (%d)\n", | |
721 | sg->length); | |
722 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
723 | break; | |
724 | } | |
725 | } | |
726 | } | |
c9fddbc4 PO |
727 | } |
728 | ||
729 | /* | |
730 | * The assumption here being that alignment is the same after | |
731 | * translation to device address space. | |
732 | */ | |
2134a922 PO |
733 | if (host->flags & SDHCI_REQ_USE_DMA) { |
734 | int broken, i; | |
735 | struct scatterlist *sg; | |
736 | ||
737 | broken = 0; | |
738 | if (host->flags & SDHCI_USE_ADMA) { | |
739 | /* | |
740 | * As we use 3 byte chunks to work around | |
741 | * alignment problems, we need to check this | |
742 | * quirk. | |
743 | */ | |
744 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
745 | broken = 1; | |
746 | } else { | |
747 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
748 | broken = 1; | |
749 | } | |
750 | ||
751 | if (unlikely(broken)) { | |
752 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
753 | if (sg->offset & 0x3) { | |
754 | DBG("Reverting to PIO because of " | |
755 | "bad alignment\n"); | |
756 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
757 | break; | |
758 | } | |
759 | } | |
760 | } | |
761 | } | |
762 | ||
8f1934ce PO |
763 | if (host->flags & SDHCI_REQ_USE_DMA) { |
764 | if (host->flags & SDHCI_USE_ADMA) { | |
765 | ret = sdhci_adma_table_pre(host, data); | |
766 | if (ret) { | |
767 | /* | |
768 | * This only happens when someone fed | |
769 | * us an invalid request. | |
770 | */ | |
771 | WARN_ON(1); | |
ebd6d357 | 772 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 773 | } else { |
4e4141a5 AV |
774 | sdhci_writel(host, host->adma_addr, |
775 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
776 | } |
777 | } else { | |
c8b3e02e | 778 | int sg_cnt; |
8f1934ce | 779 | |
c8b3e02e | 780 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
781 | data->sg, data->sg_len, |
782 | (data->flags & MMC_DATA_READ) ? | |
783 | DMA_FROM_DEVICE : | |
784 | DMA_TO_DEVICE); | |
c8b3e02e | 785 | if (sg_cnt == 0) { |
8f1934ce PO |
786 | /* |
787 | * This only happens when someone fed | |
788 | * us an invalid request. | |
789 | */ | |
790 | WARN_ON(1); | |
ebd6d357 | 791 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 792 | } else { |
719a61b4 | 793 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
794 | sdhci_writel(host, sg_dma_address(data->sg), |
795 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
796 | } |
797 | } | |
798 | } | |
799 | ||
2134a922 PO |
800 | /* |
801 | * Always adjust the DMA selection as some controllers | |
802 | * (e.g. JMicron) can't do PIO properly when the selection | |
803 | * is ADMA. | |
804 | */ | |
805 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 806 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
807 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
808 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
809 | (host->flags & SDHCI_USE_ADMA)) | |
810 | ctrl |= SDHCI_CTRL_ADMA32; | |
811 | else | |
812 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 813 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
814 | } |
815 | ||
8f1934ce | 816 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
817 | int flags; |
818 | ||
819 | flags = SG_MITER_ATOMIC; | |
820 | if (host->data->flags & MMC_DATA_READ) | |
821 | flags |= SG_MITER_TO_SG; | |
822 | else | |
823 | flags |= SG_MITER_FROM_SG; | |
824 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 825 | host->blocks = data->blocks; |
d129bceb | 826 | } |
c7fa9963 | 827 | |
6aa943ab AV |
828 | sdhci_set_transfer_irqs(host); |
829 | ||
f6a03cbf MV |
830 | /* Set the DMA boundary value and block size */ |
831 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
832 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 833 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
834 | } |
835 | ||
836 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
837 | struct mmc_data *data) | |
838 | { | |
839 | u16 mode; | |
840 | ||
c7fa9963 PO |
841 | if (data == NULL) |
842 | return; | |
843 | ||
e538fbe8 PO |
844 | WARN_ON(!host->data); |
845 | ||
c7fa9963 | 846 | mode = SDHCI_TRNS_BLK_CNT_EN; |
c4512f79 JH |
847 | if (data->blocks > 1) { |
848 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
849 | mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12; | |
850 | else | |
851 | mode |= SDHCI_TRNS_MULTI; | |
852 | } | |
c7fa9963 PO |
853 | if (data->flags & MMC_DATA_READ) |
854 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 855 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
856 | mode |= SDHCI_TRNS_DMA; |
857 | ||
4e4141a5 | 858 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
859 | } |
860 | ||
861 | static void sdhci_finish_data(struct sdhci_host *host) | |
862 | { | |
863 | struct mmc_data *data; | |
d129bceb PO |
864 | |
865 | BUG_ON(!host->data); | |
866 | ||
867 | data = host->data; | |
868 | host->data = NULL; | |
869 | ||
c9fddbc4 | 870 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
871 | if (host->flags & SDHCI_USE_ADMA) |
872 | sdhci_adma_table_post(host, data); | |
873 | else { | |
874 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
875 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
876 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
877 | } | |
d129bceb PO |
878 | } |
879 | ||
880 | /* | |
c9b74c5b PO |
881 | * The specification states that the block count register must |
882 | * be updated, but it does not specify at what point in the | |
883 | * data flow. That makes the register entirely useless to read | |
884 | * back so we have to assume that nothing made it to the card | |
885 | * in the event of an error. | |
d129bceb | 886 | */ |
c9b74c5b PO |
887 | if (data->error) |
888 | data->bytes_xfered = 0; | |
d129bceb | 889 | else |
c9b74c5b | 890 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 891 | |
d129bceb PO |
892 | if (data->stop) { |
893 | /* | |
894 | * The controller needs a reset of internal state machines | |
895 | * upon error conditions. | |
896 | */ | |
17b0429d | 897 | if (data->error) { |
d129bceb PO |
898 | sdhci_reset(host, SDHCI_RESET_CMD); |
899 | sdhci_reset(host, SDHCI_RESET_DATA); | |
900 | } | |
901 | ||
902 | sdhci_send_command(host, data->stop); | |
903 | } else | |
904 | tasklet_schedule(&host->finish_tasklet); | |
905 | } | |
906 | ||
907 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
908 | { | |
909 | int flags; | |
fd2208d7 | 910 | u32 mask; |
7cb2c76f | 911 | unsigned long timeout; |
d129bceb PO |
912 | |
913 | WARN_ON(host->cmd); | |
914 | ||
d129bceb | 915 | /* Wait max 10 ms */ |
7cb2c76f | 916 | timeout = 10; |
fd2208d7 PO |
917 | |
918 | mask = SDHCI_CMD_INHIBIT; | |
919 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
920 | mask |= SDHCI_DATA_INHIBIT; | |
921 | ||
922 | /* We shouldn't wait for data inihibit for stop commands, even | |
923 | though they might use busy signaling */ | |
924 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
925 | mask &= ~SDHCI_DATA_INHIBIT; | |
926 | ||
4e4141a5 | 927 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 928 | if (timeout == 0) { |
d129bceb | 929 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 930 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 931 | sdhci_dumpregs(host); |
17b0429d | 932 | cmd->error = -EIO; |
d129bceb PO |
933 | tasklet_schedule(&host->finish_tasklet); |
934 | return; | |
935 | } | |
7cb2c76f PO |
936 | timeout--; |
937 | mdelay(1); | |
938 | } | |
d129bceb PO |
939 | |
940 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
941 | ||
942 | host->cmd = cmd; | |
943 | ||
a3c7778f | 944 | sdhci_prepare_data(host, cmd); |
d129bceb | 945 | |
4e4141a5 | 946 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 947 | |
c7fa9963 PO |
948 | sdhci_set_transfer_mode(host, cmd->data); |
949 | ||
d129bceb | 950 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 951 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 952 | mmc_hostname(host->mmc)); |
17b0429d | 953 | cmd->error = -EINVAL; |
d129bceb PO |
954 | tasklet_schedule(&host->finish_tasklet); |
955 | return; | |
956 | } | |
957 | ||
958 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
959 | flags = SDHCI_CMD_RESP_NONE; | |
960 | else if (cmd->flags & MMC_RSP_136) | |
961 | flags = SDHCI_CMD_RESP_LONG; | |
962 | else if (cmd->flags & MMC_RSP_BUSY) | |
963 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
964 | else | |
965 | flags = SDHCI_CMD_RESP_SHORT; | |
966 | ||
967 | if (cmd->flags & MMC_RSP_CRC) | |
968 | flags |= SDHCI_CMD_CRC; | |
969 | if (cmd->flags & MMC_RSP_OPCODE) | |
970 | flags |= SDHCI_CMD_INDEX; | |
971 | if (cmd->data) | |
972 | flags |= SDHCI_CMD_DATA; | |
973 | ||
4e4141a5 | 974 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb PO |
975 | } |
976 | ||
977 | static void sdhci_finish_command(struct sdhci_host *host) | |
978 | { | |
979 | int i; | |
980 | ||
981 | BUG_ON(host->cmd == NULL); | |
982 | ||
983 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
984 | if (host->cmd->flags & MMC_RSP_136) { | |
985 | /* CRC is stripped so we need to do some shifting. */ | |
986 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 987 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
988 | SDHCI_RESPONSE + (3-i)*4) << 8; |
989 | if (i != 3) | |
990 | host->cmd->resp[i] |= | |
4e4141a5 | 991 | sdhci_readb(host, |
d129bceb PO |
992 | SDHCI_RESPONSE + (3-i)*4-1); |
993 | } | |
994 | } else { | |
4e4141a5 | 995 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
996 | } |
997 | } | |
998 | ||
17b0429d | 999 | host->cmd->error = 0; |
d129bceb | 1000 | |
e538fbe8 PO |
1001 | if (host->data && host->data_early) |
1002 | sdhci_finish_data(host); | |
1003 | ||
1004 | if (!host->cmd->data) | |
d129bceb PO |
1005 | tasklet_schedule(&host->finish_tasklet); |
1006 | ||
1007 | host->cmd = NULL; | |
1008 | } | |
1009 | ||
1010 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
1011 | { | |
1012 | int div; | |
1013 | u16 clk; | |
7cb2c76f | 1014 | unsigned long timeout; |
d129bceb PO |
1015 | |
1016 | if (clock == host->clock) | |
1017 | return; | |
1018 | ||
8114634c AV |
1019 | if (host->ops->set_clock) { |
1020 | host->ops->set_clock(host, clock); | |
1021 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
1022 | return; | |
1023 | } | |
1024 | ||
4e4141a5 | 1025 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1026 | |
1027 | if (clock == 0) | |
1028 | goto out; | |
1029 | ||
85105c53 ZG |
1030 | if (host->version >= SDHCI_SPEC_300) { |
1031 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1032 | if (host->max_clk <= clock) | |
1033 | div = 1; | |
1034 | else { | |
0397526d | 1035 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { |
85105c53 ZG |
1036 | if ((host->max_clk / div) <= clock) |
1037 | break; | |
1038 | } | |
1039 | } | |
1040 | } else { | |
1041 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1042 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1043 | if ((host->max_clk / div) <= clock) |
1044 | break; | |
1045 | } | |
d129bceb PO |
1046 | } |
1047 | div >>= 1; | |
1048 | ||
85105c53 ZG |
1049 | clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
1050 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) | |
1051 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1052 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1053 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1054 | |
27f6cb16 CB |
1055 | /* Wait max 20 ms */ |
1056 | timeout = 20; | |
4e4141a5 | 1057 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1058 | & SDHCI_CLOCK_INT_STABLE)) { |
1059 | if (timeout == 0) { | |
acf1da45 PO |
1060 | printk(KERN_ERR "%s: Internal clock never " |
1061 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1062 | sdhci_dumpregs(host); |
1063 | return; | |
1064 | } | |
7cb2c76f PO |
1065 | timeout--; |
1066 | mdelay(1); | |
1067 | } | |
d129bceb PO |
1068 | |
1069 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1070 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1071 | |
1072 | out: | |
1073 | host->clock = clock; | |
1074 | } | |
1075 | ||
146ad66e PO |
1076 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
1077 | { | |
8364248a | 1078 | u8 pwr = 0; |
146ad66e | 1079 | |
8364248a | 1080 | if (power != (unsigned short)-1) { |
ae628903 PO |
1081 | switch (1 << power) { |
1082 | case MMC_VDD_165_195: | |
1083 | pwr = SDHCI_POWER_180; | |
1084 | break; | |
1085 | case MMC_VDD_29_30: | |
1086 | case MMC_VDD_30_31: | |
1087 | pwr = SDHCI_POWER_300; | |
1088 | break; | |
1089 | case MMC_VDD_32_33: | |
1090 | case MMC_VDD_33_34: | |
1091 | pwr = SDHCI_POWER_330; | |
1092 | break; | |
1093 | default: | |
1094 | BUG(); | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | if (host->pwr == pwr) | |
146ad66e PO |
1099 | return; |
1100 | ||
ae628903 PO |
1101 | host->pwr = pwr; |
1102 | ||
1103 | if (pwr == 0) { | |
4e4141a5 | 1104 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
ae628903 | 1105 | return; |
9e9dc5f2 DS |
1106 | } |
1107 | ||
1108 | /* | |
1109 | * Spec says that we should clear the power reg before setting | |
1110 | * a new value. Some controllers don't seem to like this though. | |
1111 | */ | |
b8c86fc5 | 1112 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1113 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1114 | |
e08c1694 | 1115 | /* |
c71f6512 | 1116 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1117 | * and set turn on power at the same time, so set the voltage first. |
1118 | */ | |
11a2f1b7 | 1119 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
ae628903 | 1120 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1121 | |
ae628903 | 1122 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1123 | |
ae628903 | 1124 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 HW |
1125 | |
1126 | /* | |
1127 | * Some controllers need an extra 10ms delay of 10ms before they | |
1128 | * can apply clock after applying power | |
1129 | */ | |
11a2f1b7 | 1130 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
557b0697 | 1131 | mdelay(10); |
146ad66e PO |
1132 | } |
1133 | ||
d129bceb PO |
1134 | /*****************************************************************************\ |
1135 | * * | |
1136 | * MMC callbacks * | |
1137 | * * | |
1138 | \*****************************************************************************/ | |
1139 | ||
1140 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1141 | { | |
1142 | struct sdhci_host *host; | |
68d1fb7e | 1143 | bool present; |
d129bceb PO |
1144 | unsigned long flags; |
1145 | ||
1146 | host = mmc_priv(mmc); | |
1147 | ||
1148 | spin_lock_irqsave(&host->lock, flags); | |
1149 | ||
1150 | WARN_ON(host->mrq != NULL); | |
1151 | ||
f9134319 | 1152 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1153 | sdhci_activate_led(host); |
2f730fec | 1154 | #endif |
c4512f79 JH |
1155 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) { |
1156 | if (mrq->stop) { | |
1157 | mrq->data->stop = NULL; | |
1158 | mrq->stop = NULL; | |
1159 | } | |
1160 | } | |
d129bceb PO |
1161 | |
1162 | host->mrq = mrq; | |
1163 | ||
68d1fb7e AV |
1164 | /* If polling, assume that the card is always present. */ |
1165 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1166 | present = true; | |
1167 | else | |
1168 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1169 | SDHCI_CARD_PRESENT; | |
1170 | ||
1171 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { | |
17b0429d | 1172 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1173 | tasklet_schedule(&host->finish_tasklet); |
1174 | } else | |
1175 | sdhci_send_command(host, mrq->cmd); | |
1176 | ||
5f25a66f | 1177 | mmiowb(); |
d129bceb PO |
1178 | spin_unlock_irqrestore(&host->lock, flags); |
1179 | } | |
1180 | ||
1181 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1182 | { | |
1183 | struct sdhci_host *host; | |
1184 | unsigned long flags; | |
1185 | u8 ctrl; | |
1186 | ||
1187 | host = mmc_priv(mmc); | |
1188 | ||
1189 | spin_lock_irqsave(&host->lock, flags); | |
1190 | ||
1e72859e PO |
1191 | if (host->flags & SDHCI_DEVICE_DEAD) |
1192 | goto out; | |
1193 | ||
d129bceb PO |
1194 | /* |
1195 | * Reset the chip on each power off. | |
1196 | * Should clear out any weird states. | |
1197 | */ | |
1198 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1199 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1200 | sdhci_reinit(host); |
d129bceb PO |
1201 | } |
1202 | ||
1203 | sdhci_set_clock(host, ios->clock); | |
1204 | ||
1205 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 1206 | sdhci_set_power(host, -1); |
d129bceb | 1207 | else |
146ad66e | 1208 | sdhci_set_power(host, ios->vdd); |
d129bceb | 1209 | |
643a81ff PR |
1210 | if (host->ops->platform_send_init_74_clocks) |
1211 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1212 | ||
15ec4461 PR |
1213 | /* |
1214 | * If your platform has 8-bit width support but is not a v3 controller, | |
1215 | * or if it requires special setup code, you should implement that in | |
1216 | * platform_8bit_width(). | |
1217 | */ | |
1218 | if (host->ops->platform_8bit_width) | |
1219 | host->ops->platform_8bit_width(host, ios->bus_width); | |
1220 | else { | |
1221 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1222 | if (ios->bus_width == MMC_BUS_WIDTH_8) { | |
1223 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1224 | if (host->version >= SDHCI_SPEC_300) | |
1225 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1226 | } else { | |
1227 | if (host->version >= SDHCI_SPEC_300) | |
1228 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1229 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1230 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1231 | else | |
1232 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1233 | } | |
1234 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1235 | } | |
ae6d6c92 | 1236 | |
15ec4461 | 1237 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1238 | |
3ab9c8da PR |
1239 | if ((ios->timing == MMC_TIMING_SD_HS || |
1240 | ios->timing == MMC_TIMING_MMC_HS) | |
1241 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1242 | ctrl |= SDHCI_CTRL_HISPD; |
1243 | else | |
1244 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1245 | ||
4e4141a5 | 1246 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb | 1247 | |
b8352260 LD |
1248 | /* |
1249 | * Some (ENE) controllers go apeshit on some ios operation, | |
1250 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1251 | * it on each ios seems to solve the problem. | |
1252 | */ | |
b8c86fc5 | 1253 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1254 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1255 | ||
1e72859e | 1256 | out: |
5f25a66f | 1257 | mmiowb(); |
d129bceb PO |
1258 | spin_unlock_irqrestore(&host->lock, flags); |
1259 | } | |
1260 | ||
82b0e23a | 1261 | static int check_ro(struct sdhci_host *host) |
d129bceb | 1262 | { |
d129bceb | 1263 | unsigned long flags; |
2dfb579c | 1264 | int is_readonly; |
d129bceb | 1265 | |
d129bceb PO |
1266 | spin_lock_irqsave(&host->lock, flags); |
1267 | ||
1e72859e | 1268 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1269 | is_readonly = 0; |
1270 | else if (host->ops->get_ro) | |
1271 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1272 | else |
2dfb579c WS |
1273 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1274 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1275 | |
1276 | spin_unlock_irqrestore(&host->lock, flags); | |
1277 | ||
2dfb579c WS |
1278 | /* This quirk needs to be replaced by a callback-function later */ |
1279 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1280 | !is_readonly : is_readonly; | |
d129bceb PO |
1281 | } |
1282 | ||
82b0e23a TI |
1283 | #define SAMPLE_COUNT 5 |
1284 | ||
1285 | static int sdhci_get_ro(struct mmc_host *mmc) | |
1286 | { | |
1287 | struct sdhci_host *host; | |
1288 | int i, ro_count; | |
1289 | ||
1290 | host = mmc_priv(mmc); | |
1291 | ||
1292 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) | |
1293 | return check_ro(host); | |
1294 | ||
1295 | ro_count = 0; | |
1296 | for (i = 0; i < SAMPLE_COUNT; i++) { | |
1297 | if (check_ro(host)) { | |
1298 | if (++ro_count > SAMPLE_COUNT / 2) | |
1299 | return 1; | |
1300 | } | |
1301 | msleep(30); | |
1302 | } | |
1303 | return 0; | |
1304 | } | |
1305 | ||
f75979b7 PO |
1306 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1307 | { | |
1308 | struct sdhci_host *host; | |
1309 | unsigned long flags; | |
f75979b7 PO |
1310 | |
1311 | host = mmc_priv(mmc); | |
1312 | ||
1313 | spin_lock_irqsave(&host->lock, flags); | |
1314 | ||
1e72859e PO |
1315 | if (host->flags & SDHCI_DEVICE_DEAD) |
1316 | goto out; | |
1317 | ||
f75979b7 | 1318 | if (enable) |
7260cf5e AV |
1319 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
1320 | else | |
1321 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | |
1e72859e | 1322 | out: |
f75979b7 PO |
1323 | mmiowb(); |
1324 | ||
1325 | spin_unlock_irqrestore(&host->lock, flags); | |
1326 | } | |
1327 | ||
f2119df6 AN |
1328 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
1329 | struct mmc_ios *ios) | |
1330 | { | |
1331 | struct sdhci_host *host; | |
1332 | u8 pwr; | |
1333 | u16 clk, ctrl; | |
1334 | u32 present_state; | |
1335 | ||
1336 | host = mmc_priv(mmc); | |
1337 | ||
1338 | /* | |
1339 | * Signal Voltage Switching is only applicable for Host Controllers | |
1340 | * v3.00 and above. | |
1341 | */ | |
1342 | if (host->version < SDHCI_SPEC_300) | |
1343 | return 0; | |
1344 | ||
1345 | /* | |
1346 | * We first check whether the request is to set signalling voltage | |
1347 | * to 3.3V. If so, we change the voltage to 3.3V and return quickly. | |
1348 | */ | |
1349 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1350 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { | |
1351 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
1352 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
1353 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1354 | ||
1355 | /* Wait for 5ms */ | |
1356 | usleep_range(5000, 5500); | |
1357 | ||
1358 | /* 3.3V regulator output should be stable within 5 ms */ | |
1359 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1360 | if (!(ctrl & SDHCI_CTRL_VDD_180)) | |
1361 | return 0; | |
1362 | else { | |
1363 | printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V " | |
1364 | "signalling voltage failed\n"); | |
1365 | return -EIO; | |
1366 | } | |
1367 | } else if (!(ctrl & SDHCI_CTRL_VDD_180) && | |
1368 | (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) { | |
1369 | /* Stop SDCLK */ | |
1370 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1371 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1372 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1373 | ||
1374 | /* Check whether DAT[3:0] is 0000 */ | |
1375 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1376 | if (!((present_state & SDHCI_DATA_LVL_MASK) >> | |
1377 | SDHCI_DATA_LVL_SHIFT)) { | |
1378 | /* | |
1379 | * Enable 1.8V Signal Enable in the Host Control2 | |
1380 | * register | |
1381 | */ | |
1382 | ctrl |= SDHCI_CTRL_VDD_180; | |
1383 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1384 | ||
1385 | /* Wait for 5ms */ | |
1386 | usleep_range(5000, 5500); | |
1387 | ||
1388 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1389 | if (ctrl & SDHCI_CTRL_VDD_180) { | |
1390 | /* Provide SDCLK again and wait for 1ms*/ | |
1391 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1392 | clk |= SDHCI_CLOCK_CARD_EN; | |
1393 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1394 | usleep_range(1000, 1500); | |
1395 | ||
1396 | /* | |
1397 | * If DAT[3:0] level is 1111b, then the card | |
1398 | * was successfully switched to 1.8V signaling. | |
1399 | */ | |
1400 | present_state = sdhci_readl(host, | |
1401 | SDHCI_PRESENT_STATE); | |
1402 | if ((present_state & SDHCI_DATA_LVL_MASK) == | |
1403 | SDHCI_DATA_LVL_MASK) | |
1404 | return 0; | |
1405 | } | |
1406 | } | |
1407 | ||
1408 | /* | |
1409 | * If we are here, that means the switch to 1.8V signaling | |
1410 | * failed. We power cycle the card, and retry initialization | |
1411 | * sequence by setting S18R to 0. | |
1412 | */ | |
1413 | pwr = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
1414 | pwr &= ~SDHCI_POWER_ON; | |
1415 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
1416 | ||
1417 | /* Wait for 1ms as per the spec */ | |
1418 | usleep_range(1000, 1500); | |
1419 | pwr |= SDHCI_POWER_ON; | |
1420 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
1421 | ||
1422 | printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling " | |
1423 | "voltage failed, retrying with S18R set to 0\n"); | |
1424 | return -EAGAIN; | |
1425 | } else | |
1426 | /* No signal voltage switch required */ | |
1427 | return 0; | |
1428 | } | |
1429 | ||
ab7aefd0 | 1430 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
1431 | .request = sdhci_request, |
1432 | .set_ios = sdhci_set_ios, | |
1433 | .get_ro = sdhci_get_ro, | |
f75979b7 | 1434 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
f2119df6 | 1435 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, |
d129bceb PO |
1436 | }; |
1437 | ||
1438 | /*****************************************************************************\ | |
1439 | * * | |
1440 | * Tasklets * | |
1441 | * * | |
1442 | \*****************************************************************************/ | |
1443 | ||
1444 | static void sdhci_tasklet_card(unsigned long param) | |
1445 | { | |
1446 | struct sdhci_host *host; | |
1447 | unsigned long flags; | |
1448 | ||
1449 | host = (struct sdhci_host*)param; | |
1450 | ||
1451 | spin_lock_irqsave(&host->lock, flags); | |
1452 | ||
4e4141a5 | 1453 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { |
d129bceb PO |
1454 | if (host->mrq) { |
1455 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
1456 | mmc_hostname(host->mmc)); | |
1457 | printk(KERN_ERR "%s: Resetting controller.\n", | |
1458 | mmc_hostname(host->mmc)); | |
1459 | ||
1460 | sdhci_reset(host, SDHCI_RESET_CMD); | |
1461 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1462 | ||
17b0429d | 1463 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1464 | tasklet_schedule(&host->finish_tasklet); |
1465 | } | |
1466 | } | |
1467 | ||
1468 | spin_unlock_irqrestore(&host->lock, flags); | |
1469 | ||
04cf585d | 1470 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
1471 | } |
1472 | ||
1473 | static void sdhci_tasklet_finish(unsigned long param) | |
1474 | { | |
1475 | struct sdhci_host *host; | |
1476 | unsigned long flags; | |
1477 | struct mmc_request *mrq; | |
1478 | ||
1479 | host = (struct sdhci_host*)param; | |
1480 | ||
0c9c99a7 CB |
1481 | /* |
1482 | * If this tasklet gets rescheduled while running, it will | |
1483 | * be run again afterwards but without any active request. | |
1484 | */ | |
1485 | if (!host->mrq) | |
1486 | return; | |
1487 | ||
d129bceb PO |
1488 | spin_lock_irqsave(&host->lock, flags); |
1489 | ||
1490 | del_timer(&host->timer); | |
1491 | ||
1492 | mrq = host->mrq; | |
1493 | ||
d129bceb PO |
1494 | /* |
1495 | * The controller needs a reset of internal state machines | |
1496 | * upon error conditions. | |
1497 | */ | |
1e72859e | 1498 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 1499 | ((mrq->cmd && mrq->cmd->error) || |
1e72859e PO |
1500 | (mrq->data && (mrq->data->error || |
1501 | (mrq->data->stop && mrq->data->stop->error))) || | |
1502 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
1503 | |
1504 | /* Some controllers need this kick or reset won't work here */ | |
b8c86fc5 | 1505 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
645289dc PO |
1506 | unsigned int clock; |
1507 | ||
1508 | /* This is to force an update */ | |
1509 | clock = host->clock; | |
1510 | host->clock = 0; | |
1511 | sdhci_set_clock(host, clock); | |
1512 | } | |
1513 | ||
1514 | /* Spec says we should do both at the same time, but Ricoh | |
1515 | controllers do not like that. */ | |
d129bceb PO |
1516 | sdhci_reset(host, SDHCI_RESET_CMD); |
1517 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1518 | } | |
1519 | ||
1520 | host->mrq = NULL; | |
1521 | host->cmd = NULL; | |
1522 | host->data = NULL; | |
1523 | ||
f9134319 | 1524 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1525 | sdhci_deactivate_led(host); |
2f730fec | 1526 | #endif |
d129bceb | 1527 | |
5f25a66f | 1528 | mmiowb(); |
d129bceb PO |
1529 | spin_unlock_irqrestore(&host->lock, flags); |
1530 | ||
1531 | mmc_request_done(host->mmc, mrq); | |
1532 | } | |
1533 | ||
1534 | static void sdhci_timeout_timer(unsigned long data) | |
1535 | { | |
1536 | struct sdhci_host *host; | |
1537 | unsigned long flags; | |
1538 | ||
1539 | host = (struct sdhci_host*)data; | |
1540 | ||
1541 | spin_lock_irqsave(&host->lock, flags); | |
1542 | ||
1543 | if (host->mrq) { | |
acf1da45 PO |
1544 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1545 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1546 | sdhci_dumpregs(host); |
1547 | ||
1548 | if (host->data) { | |
17b0429d | 1549 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1550 | sdhci_finish_data(host); |
1551 | } else { | |
1552 | if (host->cmd) | |
17b0429d | 1553 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1554 | else |
17b0429d | 1555 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1556 | |
1557 | tasklet_schedule(&host->finish_tasklet); | |
1558 | } | |
1559 | } | |
1560 | ||
5f25a66f | 1561 | mmiowb(); |
d129bceb PO |
1562 | spin_unlock_irqrestore(&host->lock, flags); |
1563 | } | |
1564 | ||
1565 | /*****************************************************************************\ | |
1566 | * * | |
1567 | * Interrupt handling * | |
1568 | * * | |
1569 | \*****************************************************************************/ | |
1570 | ||
1571 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1572 | { | |
1573 | BUG_ON(intmask == 0); | |
1574 | ||
1575 | if (!host->cmd) { | |
b67ac3f3 PO |
1576 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1577 | "though no command operation was in progress.\n", | |
1578 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1579 | sdhci_dumpregs(host); |
1580 | return; | |
1581 | } | |
1582 | ||
43b58b36 | 1583 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1584 | host->cmd->error = -ETIMEDOUT; |
1585 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1586 | SDHCI_INT_INDEX)) | |
1587 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1588 | |
e809517f | 1589 | if (host->cmd->error) { |
d129bceb | 1590 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
1591 | return; |
1592 | } | |
1593 | ||
1594 | /* | |
1595 | * The host can send and interrupt when the busy state has | |
1596 | * ended, allowing us to wait without wasting CPU cycles. | |
1597 | * Unfortunately this is overloaded on the "data complete" | |
1598 | * interrupt, so we need to take some care when handling | |
1599 | * it. | |
1600 | * | |
1601 | * Note: The 1.0 specification is a bit ambiguous about this | |
1602 | * feature so there might be some problems with older | |
1603 | * controllers. | |
1604 | */ | |
1605 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
1606 | if (host->cmd->data) | |
1607 | DBG("Cannot wait for busy signal when also " | |
1608 | "doing a data transfer"); | |
f945405c | 1609 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 1610 | return; |
f945405c BD |
1611 | |
1612 | /* The controller does not support the end-of-busy IRQ, | |
1613 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
1614 | } |
1615 | ||
1616 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 1617 | sdhci_finish_command(host); |
d129bceb PO |
1618 | } |
1619 | ||
0957c333 | 1620 | #ifdef CONFIG_MMC_DEBUG |
6882a8c0 BD |
1621 | static void sdhci_show_adma_error(struct sdhci_host *host) |
1622 | { | |
1623 | const char *name = mmc_hostname(host->mmc); | |
1624 | u8 *desc = host->adma_desc; | |
1625 | __le32 *dma; | |
1626 | __le16 *len; | |
1627 | u8 attr; | |
1628 | ||
1629 | sdhci_dumpregs(host); | |
1630 | ||
1631 | while (true) { | |
1632 | dma = (__le32 *)(desc + 4); | |
1633 | len = (__le16 *)(desc + 2); | |
1634 | attr = *desc; | |
1635 | ||
1636 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
1637 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
1638 | ||
1639 | desc += 8; | |
1640 | ||
1641 | if (attr & 2) | |
1642 | break; | |
1643 | } | |
1644 | } | |
1645 | #else | |
1646 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
1647 | #endif | |
1648 | ||
d129bceb PO |
1649 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
1650 | { | |
1651 | BUG_ON(intmask == 0); | |
1652 | ||
1653 | if (!host->data) { | |
1654 | /* | |
e809517f PO |
1655 | * The "data complete" interrupt is also used to |
1656 | * indicate that a busy state has ended. See comment | |
1657 | * above in sdhci_cmd_irq(). | |
d129bceb | 1658 | */ |
e809517f PO |
1659 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
1660 | if (intmask & SDHCI_INT_DATA_END) { | |
1661 | sdhci_finish_command(host); | |
1662 | return; | |
1663 | } | |
1664 | } | |
d129bceb | 1665 | |
b67ac3f3 PO |
1666 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1667 | "though no data operation was in progress.\n", | |
1668 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1669 | sdhci_dumpregs(host); |
1670 | ||
1671 | return; | |
1672 | } | |
1673 | ||
1674 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 1675 | host->data->error = -ETIMEDOUT; |
22113efd AL |
1676 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
1677 | host->data->error = -EILSEQ; | |
1678 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
1679 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
1680 | != MMC_BUS_TEST_R) | |
17b0429d | 1681 | host->data->error = -EILSEQ; |
6882a8c0 BD |
1682 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
1683 | printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc)); | |
1684 | sdhci_show_adma_error(host); | |
2134a922 | 1685 | host->data->error = -EIO; |
6882a8c0 | 1686 | } |
d129bceb | 1687 | |
17b0429d | 1688 | if (host->data->error) |
d129bceb PO |
1689 | sdhci_finish_data(host); |
1690 | else { | |
a406f5a3 | 1691 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1692 | sdhci_transfer_pio(host); |
1693 | ||
6ba736a1 PO |
1694 | /* |
1695 | * We currently don't do anything fancy with DMA | |
1696 | * boundaries, but as we can't disable the feature | |
1697 | * we need to at least restart the transfer. | |
f6a03cbf MV |
1698 | * |
1699 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
1700 | * should return a valid address to continue from, but as | |
1701 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 1702 | */ |
f6a03cbf MV |
1703 | if (intmask & SDHCI_INT_DMA_END) { |
1704 | u32 dmastart, dmanow; | |
1705 | dmastart = sg_dma_address(host->data->sg); | |
1706 | dmanow = dmastart + host->data->bytes_xfered; | |
1707 | /* | |
1708 | * Force update to the next DMA block boundary. | |
1709 | */ | |
1710 | dmanow = (dmanow & | |
1711 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
1712 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
1713 | host->data->bytes_xfered = dmanow - dmastart; | |
1714 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
1715 | " next 0x%08x\n", | |
1716 | mmc_hostname(host->mmc), dmastart, | |
1717 | host->data->bytes_xfered, dmanow); | |
1718 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
1719 | } | |
6ba736a1 | 1720 | |
e538fbe8 PO |
1721 | if (intmask & SDHCI_INT_DATA_END) { |
1722 | if (host->cmd) { | |
1723 | /* | |
1724 | * Data managed to finish before the | |
1725 | * command completed. Make sure we do | |
1726 | * things in the proper order. | |
1727 | */ | |
1728 | host->data_early = 1; | |
1729 | } else { | |
1730 | sdhci_finish_data(host); | |
1731 | } | |
1732 | } | |
d129bceb PO |
1733 | } |
1734 | } | |
1735 | ||
7d12e780 | 1736 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1737 | { |
1738 | irqreturn_t result; | |
1739 | struct sdhci_host* host = dev_id; | |
1740 | u32 intmask; | |
f75979b7 | 1741 | int cardint = 0; |
d129bceb PO |
1742 | |
1743 | spin_lock(&host->lock); | |
1744 | ||
4e4141a5 | 1745 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
d129bceb | 1746 | |
62df67a5 | 1747 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1748 | result = IRQ_NONE; |
1749 | goto out; | |
1750 | } | |
1751 | ||
b69c9058 PO |
1752 | DBG("*** %s got interrupt: 0x%08x\n", |
1753 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1754 | |
3192a28f | 1755 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
4e4141a5 AV |
1756 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
1757 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
d129bceb | 1758 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1759 | } |
d129bceb | 1760 | |
3192a28f | 1761 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1762 | |
3192a28f | 1763 | if (intmask & SDHCI_INT_CMD_MASK) { |
4e4141a5 AV |
1764 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
1765 | SDHCI_INT_STATUS); | |
3192a28f | 1766 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1767 | } |
1768 | ||
1769 | if (intmask & SDHCI_INT_DATA_MASK) { | |
4e4141a5 AV |
1770 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
1771 | SDHCI_INT_STATUS); | |
3192a28f | 1772 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1773 | } |
1774 | ||
1775 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1776 | ||
964f9ce2 PO |
1777 | intmask &= ~SDHCI_INT_ERROR; |
1778 | ||
d129bceb | 1779 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1780 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1781 | mmc_hostname(host->mmc)); |
4e4141a5 | 1782 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
d129bceb PO |
1783 | } |
1784 | ||
9d26a5d3 | 1785 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1786 | |
f75979b7 PO |
1787 | if (intmask & SDHCI_INT_CARD_INT) |
1788 | cardint = 1; | |
1789 | ||
1790 | intmask &= ~SDHCI_INT_CARD_INT; | |
1791 | ||
3192a28f | 1792 | if (intmask) { |
acf1da45 | 1793 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1794 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1795 | sdhci_dumpregs(host); |
1796 | ||
4e4141a5 | 1797 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
3192a28f | 1798 | } |
d129bceb PO |
1799 | |
1800 | result = IRQ_HANDLED; | |
1801 | ||
5f25a66f | 1802 | mmiowb(); |
d129bceb PO |
1803 | out: |
1804 | spin_unlock(&host->lock); | |
1805 | ||
f75979b7 PO |
1806 | /* |
1807 | * We have to delay this as it calls back into the driver. | |
1808 | */ | |
1809 | if (cardint) | |
1810 | mmc_signal_sdio_irq(host->mmc); | |
1811 | ||
d129bceb PO |
1812 | return result; |
1813 | } | |
1814 | ||
1815 | /*****************************************************************************\ | |
1816 | * * | |
1817 | * Suspend/resume * | |
1818 | * * | |
1819 | \*****************************************************************************/ | |
1820 | ||
1821 | #ifdef CONFIG_PM | |
1822 | ||
b8c86fc5 | 1823 | int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) |
d129bceb | 1824 | { |
b8c86fc5 | 1825 | int ret; |
a715dfc7 | 1826 | |
7260cf5e AV |
1827 | sdhci_disable_card_detection(host); |
1828 | ||
1a13f8fa | 1829 | ret = mmc_suspend_host(host->mmc); |
b8c86fc5 PO |
1830 | if (ret) |
1831 | return ret; | |
a715dfc7 | 1832 | |
b8c86fc5 | 1833 | free_irq(host->irq, host); |
d129bceb | 1834 | |
9bea3c85 MS |
1835 | if (host->vmmc) |
1836 | ret = regulator_disable(host->vmmc); | |
1837 | ||
1838 | return ret; | |
d129bceb PO |
1839 | } |
1840 | ||
b8c86fc5 | 1841 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 1842 | |
b8c86fc5 PO |
1843 | int sdhci_resume_host(struct sdhci_host *host) |
1844 | { | |
1845 | int ret; | |
d129bceb | 1846 | |
9bea3c85 MS |
1847 | if (host->vmmc) { |
1848 | int ret = regulator_enable(host->vmmc); | |
1849 | if (ret) | |
1850 | return ret; | |
1851 | } | |
1852 | ||
1853 | ||
a13abc7b | 1854 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1855 | if (host->ops->enable_dma) |
1856 | host->ops->enable_dma(host); | |
1857 | } | |
d129bceb | 1858 | |
b8c86fc5 PO |
1859 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
1860 | mmc_hostname(host->mmc), host); | |
df1c4b7b PO |
1861 | if (ret) |
1862 | return ret; | |
d129bceb | 1863 | |
2f4cbb3d | 1864 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
b8c86fc5 PO |
1865 | mmiowb(); |
1866 | ||
1867 | ret = mmc_resume_host(host->mmc); | |
7260cf5e AV |
1868 | sdhci_enable_card_detection(host); |
1869 | ||
2f4cbb3d | 1870 | return ret; |
d129bceb PO |
1871 | } |
1872 | ||
b8c86fc5 | 1873 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb | 1874 | |
5f619704 DD |
1875 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
1876 | { | |
1877 | u8 val; | |
1878 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
1879 | val |= SDHCI_WAKE_ON_INT; | |
1880 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
1881 | } | |
1882 | ||
1883 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
1884 | ||
d129bceb PO |
1885 | #endif /* CONFIG_PM */ |
1886 | ||
1887 | /*****************************************************************************\ | |
1888 | * * | |
b8c86fc5 | 1889 | * Device allocation/registration * |
d129bceb PO |
1890 | * * |
1891 | \*****************************************************************************/ | |
1892 | ||
b8c86fc5 PO |
1893 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
1894 | size_t priv_size) | |
d129bceb | 1895 | { |
d129bceb PO |
1896 | struct mmc_host *mmc; |
1897 | struct sdhci_host *host; | |
1898 | ||
b8c86fc5 | 1899 | WARN_ON(dev == NULL); |
d129bceb | 1900 | |
b8c86fc5 | 1901 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 1902 | if (!mmc) |
b8c86fc5 | 1903 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
1904 | |
1905 | host = mmc_priv(mmc); | |
1906 | host->mmc = mmc; | |
1907 | ||
b8c86fc5 PO |
1908 | return host; |
1909 | } | |
8a4da143 | 1910 | |
b8c86fc5 | 1911 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 1912 | |
b8c86fc5 PO |
1913 | int sdhci_add_host(struct sdhci_host *host) |
1914 | { | |
1915 | struct mmc_host *mmc; | |
f2119df6 AN |
1916 | u32 caps[2]; |
1917 | u32 max_current_caps; | |
1918 | unsigned int ocr_avail; | |
b8c86fc5 | 1919 | int ret; |
d129bceb | 1920 | |
b8c86fc5 PO |
1921 | WARN_ON(host == NULL); |
1922 | if (host == NULL) | |
1923 | return -EINVAL; | |
d129bceb | 1924 | |
b8c86fc5 | 1925 | mmc = host->mmc; |
d129bceb | 1926 | |
b8c86fc5 PO |
1927 | if (debug_quirks) |
1928 | host->quirks = debug_quirks; | |
d129bceb | 1929 | |
d96649ed PO |
1930 | sdhci_reset(host, SDHCI_RESET_ALL); |
1931 | ||
4e4141a5 | 1932 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
1933 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
1934 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 1935 | if (host->version > SDHCI_SPEC_300) { |
4a965505 | 1936 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1937 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 1938 | host->version); |
4a965505 PO |
1939 | } |
1940 | ||
f2119df6 | 1941 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
ccc92c23 | 1942 | sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 1943 | |
f2119df6 AN |
1944 | caps[1] = (host->version >= SDHCI_SPEC_300) ? |
1945 | sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0; | |
1946 | ||
b8c86fc5 | 1947 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b | 1948 | host->flags |= SDHCI_USE_SDMA; |
f2119df6 | 1949 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
a13abc7b | 1950 | DBG("Controller doesn't have SDMA capability\n"); |
67435274 | 1951 | else |
a13abc7b | 1952 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 1953 | |
b8c86fc5 | 1954 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 1955 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 1956 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 1957 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
1958 | } |
1959 | ||
f2119df6 AN |
1960 | if ((host->version >= SDHCI_SPEC_200) && |
1961 | (caps[0] & SDHCI_CAN_DO_ADMA2)) | |
a13abc7b | 1962 | host->flags |= SDHCI_USE_ADMA; |
2134a922 PO |
1963 | |
1964 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
1965 | (host->flags & SDHCI_USE_ADMA)) { | |
1966 | DBG("Disabling ADMA as it is marked broken\n"); | |
1967 | host->flags &= ~SDHCI_USE_ADMA; | |
1968 | } | |
1969 | ||
a13abc7b | 1970 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1971 | if (host->ops->enable_dma) { |
1972 | if (host->ops->enable_dma(host)) { | |
1973 | printk(KERN_WARNING "%s: No suitable DMA " | |
1974 | "available. Falling back to PIO.\n", | |
1975 | mmc_hostname(mmc)); | |
a13abc7b RR |
1976 | host->flags &= |
1977 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 1978 | } |
d129bceb PO |
1979 | } |
1980 | } | |
1981 | ||
2134a922 PO |
1982 | if (host->flags & SDHCI_USE_ADMA) { |
1983 | /* | |
1984 | * We need to allocate descriptors for all sg entries | |
1985 | * (128) and potentially one alignment transfer for | |
1986 | * each of those entries. | |
1987 | */ | |
1988 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
1989 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
1990 | if (!host->adma_desc || !host->align_buffer) { | |
1991 | kfree(host->adma_desc); | |
1992 | kfree(host->align_buffer); | |
1993 | printk(KERN_WARNING "%s: Unable to allocate ADMA " | |
1994 | "buffers. Falling back to standard DMA.\n", | |
1995 | mmc_hostname(mmc)); | |
1996 | host->flags &= ~SDHCI_USE_ADMA; | |
1997 | } | |
1998 | } | |
1999 | ||
7659150c PO |
2000 | /* |
2001 | * If we use DMA, then it's up to the caller to set the DMA | |
2002 | * mask, but PIO does not need the hw shim so we set a new | |
2003 | * mask here in that case. | |
2004 | */ | |
a13abc7b | 2005 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c PO |
2006 | host->dma_mask = DMA_BIT_MASK(64); |
2007 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
2008 | } | |
d129bceb | 2009 | |
c4687d5f | 2010 | if (host->version >= SDHCI_SPEC_300) |
f2119df6 | 2011 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
c4687d5f ZG |
2012 | >> SDHCI_CLOCK_BASE_SHIFT; |
2013 | else | |
f2119df6 | 2014 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
c4687d5f ZG |
2015 | >> SDHCI_CLOCK_BASE_SHIFT; |
2016 | ||
4240ff0a | 2017 | host->max_clk *= 1000000; |
f27f47ef AV |
2018 | if (host->max_clk == 0 || host->quirks & |
2019 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a BD |
2020 | if (!host->ops->get_max_clock) { |
2021 | printk(KERN_ERR | |
2022 | "%s: Hardware doesn't specify base clock " | |
2023 | "frequency.\n", mmc_hostname(mmc)); | |
2024 | return -ENODEV; | |
2025 | } | |
2026 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 2027 | } |
d129bceb | 2028 | |
1c8cde92 | 2029 | host->timeout_clk = |
f2119df6 | 2030 | (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; |
1c8cde92 | 2031 | if (host->timeout_clk == 0) { |
81b39802 AV |
2032 | if (host->ops->get_timeout_clock) { |
2033 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
2034 | } else if (!(host->quirks & | |
2035 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { | |
4240ff0a BD |
2036 | printk(KERN_ERR |
2037 | "%s: Hardware doesn't specify timeout clock " | |
2038 | "frequency.\n", mmc_hostname(mmc)); | |
2039 | return -ENODEV; | |
2040 | } | |
1c8cde92 | 2041 | } |
f2119df6 | 2042 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) |
1c8cde92 | 2043 | host->timeout_clk *= 1000; |
d129bceb PO |
2044 | |
2045 | /* | |
2046 | * Set host parameters. | |
2047 | */ | |
2048 | mmc->ops = &sdhci_ops; | |
ce5f036b | 2049 | if (host->ops->get_min_clock) |
a9e58f25 | 2050 | mmc->f_min = host->ops->get_min_clock(host); |
0397526d ZG |
2051 | else if (host->version >= SDHCI_SPEC_300) |
2052 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
a9e58f25 | 2053 | else |
0397526d | 2054 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 2055 | |
d129bceb | 2056 | mmc->f_max = host->max_clk; |
a3c7778f | 2057 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE; |
5fe23c7f | 2058 | |
15ec4461 PR |
2059 | /* |
2060 | * A controller may support 8-bit width, but the board itself | |
2061 | * might not have the pins brought out. Boards that support | |
2062 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
2063 | * their platform code before calling sdhci_add_host(), and we | |
2064 | * won't assume 8-bit width for hosts without that CAP. | |
2065 | */ | |
5fe23c7f | 2066 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 2067 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 2068 | |
f2119df6 | 2069 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 2070 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 2071 | |
176d1ed4 JC |
2072 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
2073 | mmc_card_is_removable(mmc)) | |
68d1fb7e AV |
2074 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
2075 | ||
f2119df6 AN |
2076 | /* UHS-I mode(s) supported by the host controller. */ |
2077 | if (host->version >= SDHCI_SPEC_300) | |
2078 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; | |
2079 | ||
2080 | /* SDR104 supports also implies SDR50 support */ | |
2081 | if (caps[1] & SDHCI_SUPPORT_SDR104) | |
2082 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; | |
2083 | else if (caps[1] & SDHCI_SUPPORT_SDR50) | |
2084 | mmc->caps |= MMC_CAP_UHS_SDR50; | |
2085 | ||
2086 | if (caps[1] & SDHCI_SUPPORT_DDR50) | |
2087 | mmc->caps |= MMC_CAP_UHS_DDR50; | |
2088 | ||
8f230f45 | 2089 | ocr_avail = 0; |
f2119df6 AN |
2090 | /* |
2091 | * According to SD Host Controller spec v3.00, if the Host System | |
2092 | * can afford more than 150mA, Host Driver should set XPC to 1. Also | |
2093 | * the value is meaningful only if Voltage Support in the Capabilities | |
2094 | * register is set. The actual current value is 4 times the register | |
2095 | * value. | |
2096 | */ | |
2097 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); | |
2098 | ||
2099 | if (caps[0] & SDHCI_CAN_VDD_330) { | |
2100 | int max_current_330; | |
2101 | ||
8f230f45 | 2102 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
f2119df6 AN |
2103 | |
2104 | max_current_330 = ((max_current_caps & | |
2105 | SDHCI_MAX_CURRENT_330_MASK) >> | |
2106 | SDHCI_MAX_CURRENT_330_SHIFT) * | |
2107 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
2108 | ||
2109 | if (max_current_330 > 150) | |
2110 | mmc->caps |= MMC_CAP_SET_XPC_330; | |
2111 | } | |
2112 | if (caps[0] & SDHCI_CAN_VDD_300) { | |
2113 | int max_current_300; | |
2114 | ||
8f230f45 | 2115 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
f2119df6 AN |
2116 | |
2117 | max_current_300 = ((max_current_caps & | |
2118 | SDHCI_MAX_CURRENT_300_MASK) >> | |
2119 | SDHCI_MAX_CURRENT_300_SHIFT) * | |
2120 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
2121 | ||
2122 | if (max_current_300 > 150) | |
2123 | mmc->caps |= MMC_CAP_SET_XPC_300; | |
2124 | } | |
2125 | if (caps[0] & SDHCI_CAN_VDD_180) { | |
2126 | int max_current_180; | |
2127 | ||
8f230f45 TI |
2128 | ocr_avail |= MMC_VDD_165_195; |
2129 | ||
f2119df6 AN |
2130 | max_current_180 = ((max_current_caps & |
2131 | SDHCI_MAX_CURRENT_180_MASK) >> | |
2132 | SDHCI_MAX_CURRENT_180_SHIFT) * | |
2133 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
2134 | ||
2135 | if (max_current_180 > 150) | |
2136 | mmc->caps |= MMC_CAP_SET_XPC_180; | |
2137 | } | |
2138 | ||
8f230f45 TI |
2139 | mmc->ocr_avail = ocr_avail; |
2140 | mmc->ocr_avail_sdio = ocr_avail; | |
2141 | if (host->ocr_avail_sdio) | |
2142 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
2143 | mmc->ocr_avail_sd = ocr_avail; | |
2144 | if (host->ocr_avail_sd) | |
2145 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
2146 | else /* normal SD controllers don't support 1.8V */ | |
2147 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
2148 | mmc->ocr_avail_mmc = ocr_avail; | |
2149 | if (host->ocr_avail_mmc) | |
2150 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
2151 | |
2152 | if (mmc->ocr_avail == 0) { | |
2153 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 2154 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 2155 | return -ENODEV; |
146ad66e PO |
2156 | } |
2157 | ||
d129bceb PO |
2158 | spin_lock_init(&host->lock); |
2159 | ||
2160 | /* | |
2134a922 PO |
2161 | * Maximum number of segments. Depends on if the hardware |
2162 | * can do scatter/gather or not. | |
d129bceb | 2163 | */ |
2134a922 | 2164 | if (host->flags & SDHCI_USE_ADMA) |
a36274e0 | 2165 | mmc->max_segs = 128; |
a13abc7b | 2166 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 2167 | mmc->max_segs = 1; |
2134a922 | 2168 | else /* PIO */ |
a36274e0 | 2169 | mmc->max_segs = 128; |
d129bceb PO |
2170 | |
2171 | /* | |
bab76961 | 2172 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 2173 | * size (512KiB). |
d129bceb | 2174 | */ |
55db890a | 2175 | mmc->max_req_size = 524288; |
d129bceb PO |
2176 | |
2177 | /* | |
2178 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
2179 | * of bytes. When doing hardware scatter/gather, each entry cannot |
2180 | * be larger than 64 KiB though. | |
d129bceb | 2181 | */ |
30652aa3 OJ |
2182 | if (host->flags & SDHCI_USE_ADMA) { |
2183 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
2184 | mmc->max_seg_size = 65535; | |
2185 | else | |
2186 | mmc->max_seg_size = 65536; | |
2187 | } else { | |
2134a922 | 2188 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 2189 | } |
d129bceb | 2190 | |
fe4a3c7a PO |
2191 | /* |
2192 | * Maximum block size. This varies from controller to controller and | |
2193 | * is specified in the capabilities register. | |
2194 | */ | |
0633f654 AV |
2195 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
2196 | mmc->max_blk_size = 2; | |
2197 | } else { | |
f2119df6 | 2198 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
0633f654 AV |
2199 | SDHCI_MAX_BLOCK_SHIFT; |
2200 | if (mmc->max_blk_size >= 3) { | |
2201 | printk(KERN_WARNING "%s: Invalid maximum block size, " | |
2202 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
2203 | mmc->max_blk_size = 0; | |
2204 | } | |
2205 | } | |
2206 | ||
2207 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 2208 | |
55db890a PO |
2209 | /* |
2210 | * Maximum block count. | |
2211 | */ | |
1388eefd | 2212 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 2213 | |
d129bceb PO |
2214 | /* |
2215 | * Init tasklets. | |
2216 | */ | |
2217 | tasklet_init(&host->card_tasklet, | |
2218 | sdhci_tasklet_card, (unsigned long)host); | |
2219 | tasklet_init(&host->finish_tasklet, | |
2220 | sdhci_tasklet_finish, (unsigned long)host); | |
2221 | ||
e4cad1b5 | 2222 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 2223 | |
dace1453 | 2224 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 2225 | mmc_hostname(mmc), host); |
d129bceb | 2226 | if (ret) |
8ef1a143 | 2227 | goto untasklet; |
d129bceb | 2228 | |
9bea3c85 MS |
2229 | host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); |
2230 | if (IS_ERR(host->vmmc)) { | |
2231 | printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc)); | |
2232 | host->vmmc = NULL; | |
2233 | } else { | |
2234 | regulator_enable(host->vmmc); | |
2235 | } | |
2236 | ||
2f4cbb3d | 2237 | sdhci_init(host, 0); |
d129bceb PO |
2238 | |
2239 | #ifdef CONFIG_MMC_DEBUG | |
2240 | sdhci_dumpregs(host); | |
2241 | #endif | |
2242 | ||
f9134319 | 2243 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
2244 | snprintf(host->led_name, sizeof(host->led_name), |
2245 | "%s::", mmc_hostname(mmc)); | |
2246 | host->led.name = host->led_name; | |
2f730fec PO |
2247 | host->led.brightness = LED_OFF; |
2248 | host->led.default_trigger = mmc_hostname(mmc); | |
2249 | host->led.brightness_set = sdhci_led_control; | |
2250 | ||
b8c86fc5 | 2251 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
2f730fec PO |
2252 | if (ret) |
2253 | goto reset; | |
2254 | #endif | |
2255 | ||
5f25a66f PO |
2256 | mmiowb(); |
2257 | ||
d129bceb PO |
2258 | mmc_add_host(mmc); |
2259 | ||
a13abc7b | 2260 | printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 2261 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
a13abc7b RR |
2262 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
2263 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); | |
d129bceb | 2264 | |
7260cf5e AV |
2265 | sdhci_enable_card_detection(host); |
2266 | ||
d129bceb PO |
2267 | return 0; |
2268 | ||
f9134319 | 2269 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
2270 | reset: |
2271 | sdhci_reset(host, SDHCI_RESET_ALL); | |
2272 | free_irq(host->irq, host); | |
2273 | #endif | |
8ef1a143 | 2274 | untasklet: |
d129bceb PO |
2275 | tasklet_kill(&host->card_tasklet); |
2276 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
2277 | |
2278 | return ret; | |
2279 | } | |
2280 | ||
b8c86fc5 | 2281 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 2282 | |
1e72859e | 2283 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 2284 | { |
1e72859e PO |
2285 | unsigned long flags; |
2286 | ||
2287 | if (dead) { | |
2288 | spin_lock_irqsave(&host->lock, flags); | |
2289 | ||
2290 | host->flags |= SDHCI_DEVICE_DEAD; | |
2291 | ||
2292 | if (host->mrq) { | |
2293 | printk(KERN_ERR "%s: Controller removed during " | |
2294 | " transfer!\n", mmc_hostname(host->mmc)); | |
2295 | ||
2296 | host->mrq->cmd->error = -ENOMEDIUM; | |
2297 | tasklet_schedule(&host->finish_tasklet); | |
2298 | } | |
2299 | ||
2300 | spin_unlock_irqrestore(&host->lock, flags); | |
2301 | } | |
2302 | ||
7260cf5e AV |
2303 | sdhci_disable_card_detection(host); |
2304 | ||
b8c86fc5 | 2305 | mmc_remove_host(host->mmc); |
d129bceb | 2306 | |
f9134319 | 2307 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
2308 | led_classdev_unregister(&host->led); |
2309 | #endif | |
2310 | ||
1e72859e PO |
2311 | if (!dead) |
2312 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb PO |
2313 | |
2314 | free_irq(host->irq, host); | |
2315 | ||
2316 | del_timer_sync(&host->timer); | |
2317 | ||
2318 | tasklet_kill(&host->card_tasklet); | |
2319 | tasklet_kill(&host->finish_tasklet); | |
2134a922 | 2320 | |
9bea3c85 MS |
2321 | if (host->vmmc) { |
2322 | regulator_disable(host->vmmc); | |
2323 | regulator_put(host->vmmc); | |
2324 | } | |
2325 | ||
2134a922 PO |
2326 | kfree(host->adma_desc); |
2327 | kfree(host->align_buffer); | |
2328 | ||
2329 | host->adma_desc = NULL; | |
2330 | host->align_buffer = NULL; | |
d129bceb PO |
2331 | } |
2332 | ||
b8c86fc5 | 2333 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 2334 | |
b8c86fc5 | 2335 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 2336 | { |
b8c86fc5 | 2337 | mmc_free_host(host->mmc); |
d129bceb PO |
2338 | } |
2339 | ||
b8c86fc5 | 2340 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
2341 | |
2342 | /*****************************************************************************\ | |
2343 | * * | |
2344 | * Driver init/exit * | |
2345 | * * | |
2346 | \*****************************************************************************/ | |
2347 | ||
2348 | static int __init sdhci_drv_init(void) | |
2349 | { | |
2350 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 2351 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
2352 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
2353 | ||
b8c86fc5 | 2354 | return 0; |
d129bceb PO |
2355 | } |
2356 | ||
2357 | static void __exit sdhci_drv_exit(void) | |
2358 | { | |
d129bceb PO |
2359 | } |
2360 | ||
2361 | module_init(sdhci_drv_init); | |
2362 | module_exit(sdhci_drv_exit); | |
2363 | ||
df673b22 | 2364 | module_param(debug_quirks, uint, 0444); |
67435274 | 2365 | |
32710e8f | 2366 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 2367 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 2368 | MODULE_LICENSE("GPL"); |
67435274 | 2369 | |
df673b22 | 2370 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |