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mmc: sdhci: Define ADMA descriptor structure
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
be3f4ae0 120 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
124
a3c76eb9 125 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 126}
127
128/*****************************************************************************\
129 * *
130 * Low level functions *
131 * *
132\*****************************************************************************/
133
7260cf5e
AV		 134static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
135{
5b4f1f6c 136 u32 present;
7260cf5e 137
c79396c1 138 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 139 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 140 return;
141
5b4f1f6c
RK		 142 if (enable) {
143 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
144 SDHCI_CARD_PRESENT;
d25928d1 145
5b4f1f6c
RK		 146 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
147 SDHCI_INT_CARD_INSERT;
148 } else {
149 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
150 }
b537f94c
RK		 151
152 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
153 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 154}
155
156static void sdhci_enable_card_detection(struct sdhci_host *host)
157{
158 sdhci_set_card_detection(host, true);
159}
160
161static void sdhci_disable_card_detection(struct sdhci_host *host)
162{
163 sdhci_set_card_detection(host, false);
164}
165
03231f9b 166void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 167{
e16514d8 168 unsigned long timeout;
393c1a34 169
4e4141a5 170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 171
f0710a55 172 if (mask & SDHCI_RESET_ALL) {
d129bceb 173 host->clock = 0;
f0710a55
AH		 174 /* Reset-all turns off SD Bus Power */
175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
176 sdhci_runtime_pm_bus_off(host);
177 }
d129bceb 178
e16514d8
PO		 179 /* Wait max 100 ms */
180 timeout = 100;
181
182 /* hw clears the bit when it's done */
4e4141a5 183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 184 if (timeout == 0) {
a3c76eb9 185 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 186 mmc_hostname(host->mmc), (int)mask);
187 sdhci_dumpregs(host);
188 return;
189 }
190 timeout--;
191 mdelay(1);
d129bceb 192 }
03231f9b
RK		 193}
194EXPORT_SYMBOL_GPL(sdhci_reset);
195
196static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
197{
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
199 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
200 SDHCI_CARD_PRESENT))
201 return;
202 }
063a9dbb 203
03231f9b 204 host->ops->reset(host, mask);
393c1a34 205
da91a8f9
RK		 206 if (mask & SDHCI_RESET_ALL) {
207 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
208 if (host->ops->enable_dma)
209 host->ops->enable_dma(host);
210 }
211
212 /* Resetting the controller clears many */
213 host->preset_enabled = false;
3abc1e80 214 }
d129bceb
PO		 215}
216
2f4cbb3d
NP		 217static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
218
219static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 220{
2f4cbb3d 221 if (soft)
03231f9b 222 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 223 else
03231f9b 224 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 225
b537f94c
RK		 226 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
227 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
228 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
229 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
230 SDHCI_INT_RESPONSE;
231
232 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
233 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 234
235 if (soft) {
236 /* force clock reconfiguration */
237 host->clock = 0;
238 sdhci_set_ios(host->mmc, &host->mmc->ios);
239 }
7260cf5e 240}
d129bceb 241
7260cf5e
AV		 242static void sdhci_reinit(struct sdhci_host *host)
243{
2f4cbb3d 244 sdhci_init(host, 0);
b67c6b41
AL		 245 /*
246 * Retuning stuffs are affected by different cards inserted and only
247 * applicable to UHS-I cards. So reset these fields to their initial
248 * value when card is removed.
249 */
973905fe
AL		 250 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
251 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
252
b67c6b41
AL		 253 del_timer_sync(&host->tuning_timer);
254 host->flags &= ~SDHCI_NEEDS_RETUNING;
255 host->mmc->max_blk_count =
256 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
257 }
7260cf5e 258 sdhci_enable_card_detection(host);
d129bceb
PO		 259}
260
261static void sdhci_activate_led(struct sdhci_host *host)
262{
263 u8 ctrl;
264
4e4141a5 265 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 266 ctrl |= SDHCI_CTRL_LED;
4e4141a5 267 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 268}
269
270static void sdhci_deactivate_led(struct sdhci_host *host)
271{
272 u8 ctrl;
273
4e4141a5 274 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 275 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 276 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 277}
278
f9134319 279#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 280static void sdhci_led_control(struct led_classdev *led,
281 enum led_brightness brightness)
282{
283 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
284 unsigned long flags;
285
286 spin_lock_irqsave(&host->lock, flags);
287
66fd8ad5
AH		 288 if (host->runtime_suspended)
289 goto out;
290
2f730fec
PO		 291 if (brightness == LED_OFF)
292 sdhci_deactivate_led(host);
293 else
294 sdhci_activate_led(host);
66fd8ad5 295out:
2f730fec
PO		 296 spin_unlock_irqrestore(&host->lock, flags);
297}
298#endif
299
d129bceb
PO		 300/*****************************************************************************\
301 * *
302 * Core functions *
303 * *
304\*****************************************************************************/
305
a406f5a3 306static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 307{
7659150c
PO		 308 unsigned long flags;
309 size_t blksize, len, chunk;
7244b85b 310 u32 uninitialized_var(scratch);
7659150c 311 u8 *buf;
d129bceb 312
a406f5a3 313 DBG("PIO reading\n");
d129bceb 314
a406f5a3 315 blksize = host->data->blksz;
7659150c 316 chunk = 0;
d129bceb 317
7659150c 318 local_irq_save(flags);
d129bceb 319
a406f5a3 320 while (blksize) {
7659150c
PO		 321 if (!sg_miter_next(&host->sg_miter))
322 BUG();
d129bceb 323
7659150c 324 len = min(host->sg_miter.length, blksize);
d129bceb 325
7659150c
PO		 326 blksize -= len;
327 host->sg_miter.consumed = len;
14d836e7 328
7659150c 329 buf = host->sg_miter.addr;
d129bceb 330
7659150c
PO		 331 while (len) {
332 if (chunk == 0) {
4e4141a5 333 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 334 chunk = 4;
a406f5a3 335 }
7659150c
PO		 336
337 *buf = scratch & 0xFF;
338
339 buf++;
340 scratch >>= 8;
341 chunk--;
342 len--;
d129bceb 343 }
a406f5a3 344 }
7659150c
PO		 345
346 sg_miter_stop(&host->sg_miter);
347
348 local_irq_restore(flags);
a406f5a3 349}
d129bceb 350
a406f5a3
PO		 351static void sdhci_write_block_pio(struct sdhci_host *host)
352{
7659150c
PO		 353 unsigned long flags;
354 size_t blksize, len, chunk;
355 u32 scratch;
356 u8 *buf;
d129bceb 357
a406f5a3
PO		 358 DBG("PIO writing\n");
359
360 blksize = host->data->blksz;
7659150c
PO		 361 chunk = 0;
362 scratch = 0;
d129bceb 363
7659150c 364 local_irq_save(flags);
d129bceb 365
a406f5a3 366 while (blksize) {
7659150c
PO		 367 if (!sg_miter_next(&host->sg_miter))
368 BUG();
a406f5a3 369
7659150c
PO		 370 len = min(host->sg_miter.length, blksize);
371
372 blksize -= len;
373 host->sg_miter.consumed = len;
374
375 buf = host->sg_miter.addr;
d129bceb 376
7659150c
PO		 377 while (len) {
378 scratch |= (u32)*buf << (chunk * 8);
379
380 buf++;
381 chunk++;
382 len--;
383
384 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 385 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 386 chunk = 0;
387 scratch = 0;
d129bceb 388 }
d129bceb
PO		 389 }
390 }
7659150c
PO		 391
392 sg_miter_stop(&host->sg_miter);
393
394 local_irq_restore(flags);
a406f5a3
PO		 395}
396
397static void sdhci_transfer_pio(struct sdhci_host *host)
398{
399 u32 mask;
400
401 BUG_ON(!host->data);
402
7659150c 403 if (host->blocks == 0)
a406f5a3
PO		 404 return;
405
406 if (host->data->flags & MMC_DATA_READ)
407 mask = SDHCI_DATA_AVAILABLE;
408 else
409 mask = SDHCI_SPACE_AVAILABLE;
410
4a3cba32
PO		 411 /*
412 * Some controllers (JMicron JMB38x) mess up the buffer bits
413 * for transfers < 4 bytes. As long as it is just one block,
414 * we can ignore the bits.
415 */
416 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
417 (host->data->blocks == 1))
418 mask = ~0;
419
4e4141a5 420 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 421 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
422 udelay(100);
423
a406f5a3
PO		 424 if (host->data->flags & MMC_DATA_READ)
425 sdhci_read_block_pio(host);
426 else
427 sdhci_write_block_pio(host);
d129bceb 428
7659150c
PO		 429 host->blocks--;
430 if (host->blocks == 0)
a406f5a3 431 break;
a406f5a3 432 }
d129bceb 433
a406f5a3 434 DBG("PIO transfer complete.\n");
d129bceb
PO		 435}
436
2134a922
PO		 437static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
438{
439 local_irq_save(*flags);
482fce99 440 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 441}
442
443static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
444{
482fce99 445 kunmap_atomic(buffer);
2134a922
PO		 446 local_irq_restore(*flags);
447}
448
1c3d5f6d 449static void sdhci_adma_write_desc(void *desc, u32 addr, int len, unsigned cmd)
118cd17d 450{
0545230f 451 struct sdhci_adma2_32_desc *dma_desc = desc;
118cd17d 452
0545230f
AH		 453 dma_desc->cmd = cpu_to_le16(cmd);
454 dma_desc->len = cpu_to_le16(len);
455 dma_desc->addr = cpu_to_le32(addr);
118cd17d
BD		 456}
457
b5ffa674
AH		 458static void sdhci_adma_mark_end(void *desc)
459{
0545230f 460 struct sdhci_adma2_32_desc *dma_desc = desc;
b5ffa674 461
0545230f 462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 463}
464
8f1934ce 465static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 466 struct mmc_data *data)
467{
468 int direction;
469
1c3d5f6d
AH		 470 void *desc;
471 void *align;
2134a922
PO		 472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
2134a922 491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 492 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 494 goto fail;
76fe379a 495 BUG_ON(host->align_addr & host->align_mask);
2134a922
PO		 496
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
8f1934ce
PO		 499 if (host->sg_count == 0)
500 goto unmap_align;
2134a922 501
4efaa6fb 502 desc = host->adma_table;
2134a922
PO		 503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
76fe379a
AH		 518 offset = (host->align_sz - (addr & host->align_mask)) &
519 host->align_mask;
2134a922
PO		 520 if (offset) {
521 if (data->flags & MMC_DATA_WRITE) {
522 buffer = sdhci_kmap_atomic(sg, &flags);
8be78c6a
AH		 523 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
524 (PAGE_SIZE - offset));
2134a922
PO		 525 memcpy(align, buffer, offset);
526 sdhci_kunmap_atomic(buffer, &flags);
527 }
528
118cd17d 529 /* tran, valid */
739d46dc
AH		 530 sdhci_adma_write_desc(desc, align_addr, offset,
531 ADMA2_TRAN_VALID);
2134a922
PO		 532
533 BUG_ON(offset > 65536);
534
76fe379a
AH		 535 align += host->align_sz;
536 align_addr += host->align_sz;
2134a922 537
76fe379a 538 desc += host->desc_sz;
2134a922
PO		 539
540 addr += offset;
541 len -= offset;
542 }
543
2134a922
PO		 544 BUG_ON(len > 65536);
545
118cd17d 546 /* tran, valid */
739d46dc 547 sdhci_adma_write_desc(desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 548 desc += host->desc_sz;
2134a922
PO		 549
550 /*
551 * If this triggers then we have a calculation bug
552 * somewhere. :/
553 */
76fe379a 554 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 555 }
556
70764a90
TA		 557 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
558 /*
559 * Mark the last descriptor as the terminating descriptor
560 */
4efaa6fb 561 if (desc != host->adma_table) {
76fe379a 562 desc -= host->desc_sz;
b5ffa674 563 sdhci_adma_mark_end(desc);
70764a90
TA		 564 }
565 } else {
566 /*
567 * Add a terminating entry.
568 */
2134a922 569
70764a90 570 /* nop, end, valid */
739d46dc 571 sdhci_adma_write_desc(desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 572 }
2134a922
PO		 573
574 /*
575 * Resync align buffer as we might have changed it.
576 */
577 if (data->flags & MMC_DATA_WRITE) {
578 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 579 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 580 }
581
8f1934ce
PO		 582 return 0;
583
8f1934ce
PO		 584unmap_align:
585 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 586 host->align_buffer_sz, direction);
8f1934ce
PO		 587fail:
588 return -EINVAL;
2134a922
PO		 589}
590
591static void sdhci_adma_table_post(struct sdhci_host *host,
592 struct mmc_data *data)
593{
594 int direction;
595
596 struct scatterlist *sg;
597 int i, size;
1c3d5f6d 598 void *align;
2134a922
PO		 599 char *buffer;
600 unsigned long flags;
de0b65a7 601 bool has_unaligned;
2134a922
PO		 602
603 if (data->flags & MMC_DATA_READ)
604 direction = DMA_FROM_DEVICE;
605 else
606 direction = DMA_TO_DEVICE;
607
2134a922 608 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 609 host->align_buffer_sz, direction);
2134a922 610
de0b65a7
RK		 611 /* Do a quick scan of the SG list for any unaligned mappings */
612 has_unaligned = false;
613 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 614 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 615 has_unaligned = true;
616 break;
617 }
618
619 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 620 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
621 data->sg_len, direction);
622
623 align = host->align_buffer;
624
625 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 626 if (sg_dma_address(sg) & host->align_mask) {
627 size = host->align_sz -
628 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 629
630 buffer = sdhci_kmap_atomic(sg, &flags);
8be78c6a
AH		 631 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
632 (PAGE_SIZE - size));
2134a922
PO		 633 memcpy(buffer, align, size);
634 sdhci_kunmap_atomic(buffer, &flags);
635
76fe379a 636 align += host->align_sz;
2134a922
PO		 637 }
638 }
639 }
640
641 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
642 data->sg_len, direction);
643}
644
a3c7778f 645static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 646{
1c8cde92 647 u8 count;
a3c7778f 648 struct mmc_data *data = cmd->data;
1c8cde92 649 unsigned target_timeout, current_timeout;
d129bceb 650
ee53ab5d
PO		 651 /*
652 * If the host controller provides us with an incorrect timeout
653 * value, just skip the check and use 0xE. The hardware may take
654 * longer to time out, but that's much better than having a too-short
655 * timeout value.
656 */
11a2f1b7 657 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 658 return 0xE;
e538fbe8 659
a3c7778f 660 /* Unspecified timeout, assume max */
1d4d7744 661 if (!data && !cmd->busy_timeout)
a3c7778f 662 return 0xE;
d129bceb 663
a3c7778f
AW		 664 /* timeout in us */
665 if (!data)
1d4d7744 666 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 667 else {
668 target_timeout = data->timeout_ns / 1000;
669 if (host->clock)
670 target_timeout += data->timeout_clks / host->clock;
671 }
81b39802 672
1c8cde92
PO		 673 /*
674 * Figure out needed cycles.
675 * We do this in steps in order to fit inside a 32 bit int.
676 * The first step is the minimum timeout, which will have a
677 * minimum resolution of 6 bits:
678 * (1) 2^13*1000 > 2^22,
679 * (2) host->timeout_clk < 2^16
680 * =>
681 * (1) / (2) > 2^6
682 */
683 count = 0;
684 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
685 while (current_timeout < target_timeout) {
686 count++;
687 current_timeout <<= 1;
688 if (count >= 0xF)
689 break;
690 }
691
692 if (count >= 0xF) {
09eeff52
CB		 693 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
694 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 695 count = 0xE;
696 }
697
ee53ab5d
PO		 698 return count;
699}
700
6aa943ab
AV		 701static void sdhci_set_transfer_irqs(struct sdhci_host *host)
702{
703 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
704 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
705
706 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 707 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 708 else
b537f94c
RK		 709 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
710
711 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
712 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 713}
714
b45e668a 715static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 716{
717 u8 count;
b45e668a
AD		 718
719 if (host->ops->set_timeout) {
720 host->ops->set_timeout(host, cmd);
721 } else {
722 count = sdhci_calc_timeout(host, cmd);
723 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
724 }
725}
726
727static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
728{
2134a922 729 u8 ctrl;
a3c7778f 730 struct mmc_data *data = cmd->data;
8f1934ce 731 int ret;
ee53ab5d
PO		 732
733 WARN_ON(host->data);
734
b45e668a
AD		 735 if (data || (cmd->flags & MMC_RSP_BUSY))
736 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 737
738 if (!data)
ee53ab5d
PO		 739 return;
740
741 /* Sanity checks */
742 BUG_ON(data->blksz * data->blocks > 524288);
743 BUG_ON(data->blksz > host->mmc->max_blk_size);
744 BUG_ON(data->blocks > 65535);
745
746 host->data = data;
747 host->data_early = 0;
f6a03cbf 748 host->data->bytes_xfered = 0;
ee53ab5d 749
a13abc7b 750 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 751 host->flags |= SDHCI_REQ_USE_DMA;
752
2134a922
PO		 753 /*
754 * FIXME: This doesn't account for merging when mapping the
755 * scatterlist.
756 */
757 if (host->flags & SDHCI_REQ_USE_DMA) {
758 int broken, i;
759 struct scatterlist *sg;
760
761 broken = 0;
762 if (host->flags & SDHCI_USE_ADMA) {
763 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
764 broken = 1;
765 } else {
766 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
767 broken = 1;
768 }
769
770 if (unlikely(broken)) {
771 for_each_sg(data->sg, sg, data->sg_len, i) {
772 if (sg->length & 0x3) {
773 DBG("Reverting to PIO because of "
774 "transfer size (%d)\n",
775 sg->length);
776 host->flags &= ~SDHCI_REQ_USE_DMA;
777 break;
778 }
779 }
780 }
c9fddbc4
PO		 781 }
782
783 /*
784 * The assumption here being that alignment is the same after
785 * translation to device address space.
786 */
2134a922
PO		 787 if (host->flags & SDHCI_REQ_USE_DMA) {
788 int broken, i;
789 struct scatterlist *sg;
790
791 broken = 0;
792 if (host->flags & SDHCI_USE_ADMA) {
793 /*
794 * As we use 3 byte chunks to work around
795 * alignment problems, we need to check this
796 * quirk.
797 */
798 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
799 broken = 1;
800 } else {
801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
802 broken = 1;
803 }
804
805 if (unlikely(broken)) {
806 for_each_sg(data->sg, sg, data->sg_len, i) {
807 if (sg->offset & 0x3) {
808 DBG("Reverting to PIO because of "
809 "bad alignment\n");
810 host->flags &= ~SDHCI_REQ_USE_DMA;
811 break;
812 }
813 }
814 }
815 }
816
8f1934ce
PO		 817 if (host->flags & SDHCI_REQ_USE_DMA) {
818 if (host->flags & SDHCI_USE_ADMA) {
819 ret = sdhci_adma_table_pre(host, data);
820 if (ret) {
821 /*
822 * This only happens when someone fed
823 * us an invalid request.
824 */
825 WARN_ON(1);
ebd6d357 826 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 827 } else {
4e4141a5
AV		 828 sdhci_writel(host, host->adma_addr,
829 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 830 }
831 } else {
c8b3e02e 832 int sg_cnt;
8f1934ce 833
c8b3e02e 834 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 835 data->sg, data->sg_len,
836 (data->flags & MMC_DATA_READ) ?
837 DMA_FROM_DEVICE :
838 DMA_TO_DEVICE);
c8b3e02e 839 if (sg_cnt == 0) {
8f1934ce
PO		 840 /*
841 * This only happens when someone fed
842 * us an invalid request.
843 */
844 WARN_ON(1);
ebd6d357 845 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 846 } else {
719a61b4 847 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 848 sdhci_writel(host, sg_dma_address(data->sg),
849 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 850 }
851 }
852 }
853
2134a922
PO		 854 /*
855 * Always adjust the DMA selection as some controllers
856 * (e.g. JMicron) can't do PIO properly when the selection
857 * is ADMA.
858 */
859 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 860 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 861 ctrl &= ~SDHCI_CTRL_DMA_MASK;
862 if ((host->flags & SDHCI_REQ_USE_DMA) &&
863 (host->flags & SDHCI_USE_ADMA))
864 ctrl |= SDHCI_CTRL_ADMA32;
865 else
866 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 867 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 868 }
869
8f1934ce 870 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 871 int flags;
872
873 flags = SG_MITER_ATOMIC;
874 if (host->data->flags & MMC_DATA_READ)
875 flags |= SG_MITER_TO_SG;
876 else
877 flags |= SG_MITER_FROM_SG;
878 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 879 host->blocks = data->blocks;
d129bceb 880 }
c7fa9963 881
6aa943ab
AV		 882 sdhci_set_transfer_irqs(host);
883
f6a03cbf
MV		 884 /* Set the DMA boundary value and block size */
885 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
886 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 887 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 888}
889
890static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 891 struct mmc_command *cmd)
c7fa9963
PO		 892{
893 u16 mode;
e89d456f 894 struct mmc_data *data = cmd->data;
c7fa9963 895
2b558c13
DA		 896 if (data == NULL) {
897 /* clear Auto CMD settings for no data CMDs */
898 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
899 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
900 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 901 return;
2b558c13 902 }
c7fa9963 903
e538fbe8
PO		 904 WARN_ON(!host->data);
905
c7fa9963 906 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 907 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
908 mode |= SDHCI_TRNS_MULTI;
909 /*
910 * If we are sending CMD23, CMD12 never gets sent
911 * on successful completion (so no Auto-CMD12).
912 */
913 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
914 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 915 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
916 mode |= SDHCI_TRNS_AUTO_CMD23;
917 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
918 }
c4512f79 919 }
8edf6371 920
c7fa9963
PO		 921 if (data->flags & MMC_DATA_READ)
922 mode |= SDHCI_TRNS_READ;
c9fddbc4 923 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 924 mode |= SDHCI_TRNS_DMA;
925
4e4141a5 926 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 927}
928
929static void sdhci_finish_data(struct sdhci_host *host)
930{
931 struct mmc_data *data;
d129bceb
PO		 932
933 BUG_ON(!host->data);
934
935 data = host->data;
936 host->data = NULL;
937
c9fddbc4 938 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 939 if (host->flags & SDHCI_USE_ADMA)
940 sdhci_adma_table_post(host, data);
941 else {
942 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
943 data->sg_len, (data->flags & MMC_DATA_READ) ?
944 DMA_FROM_DEVICE : DMA_TO_DEVICE);
945 }
d129bceb
PO		 946 }
947
948 /*
c9b74c5b
PO		 949 * The specification states that the block count register must
950 * be updated, but it does not specify at what point in the
951 * data flow. That makes the register entirely useless to read
952 * back so we have to assume that nothing made it to the card
953 * in the event of an error.
d129bceb 954 */
c9b74c5b
PO		 955 if (data->error)
956 data->bytes_xfered = 0;
d129bceb 957 else
c9b74c5b 958 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 959
e89d456f
AW		 960 /*
961 * Need to send CMD12 if -
962 * a) open-ended multiblock transfer (no CMD23)
963 * b) error in multiblock transfer
964 */
965 if (data->stop &&
966 (data->error ||
967 !host->mrq->sbc)) {
968
d129bceb
PO		 969 /*
970 * The controller needs a reset of internal state machines
971 * upon error conditions.
972 */
17b0429d 973 if (data->error) {
03231f9b
RK		 974 sdhci_do_reset(host, SDHCI_RESET_CMD);
975 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 976 }
977
978 sdhci_send_command(host, data->stop);
979 } else
980 tasklet_schedule(&host->finish_tasklet);
981}
982
c0e55129 983void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 984{
985 int flags;
fd2208d7 986 u32 mask;
7cb2c76f 987 unsigned long timeout;
d129bceb
PO		 988
989 WARN_ON(host->cmd);
990
d129bceb 991 /* Wait max 10 ms */
7cb2c76f 992 timeout = 10;
fd2208d7
PO		 993
994 mask = SDHCI_CMD_INHIBIT;
995 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
996 mask |= SDHCI_DATA_INHIBIT;
997
998 /* We shouldn't wait for data inihibit for stop commands, even
999 though they might use busy signaling */
1000 if (host->mrq->data && (cmd == host->mrq->data->stop))
1001 mask &= ~SDHCI_DATA_INHIBIT;
1002
4e4141a5 1003 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1004 if (timeout == 0) {
a3c76eb9 1005 pr_err("%s: Controller never released "
acf1da45 1006 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1007 sdhci_dumpregs(host);
17b0429d 1008 cmd->error = -EIO;
d129bceb
PO		 1009 tasklet_schedule(&host->finish_tasklet);
1010 return;
1011 }
7cb2c76f
PO		 1012 timeout--;
1013 mdelay(1);
1014 }
d129bceb 1015
3e1a6892 1016 timeout = jiffies;
1d4d7744
UH		 1017 if (!cmd->data && cmd->busy_timeout > 9000)
1018 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1019 else
1020 timeout += 10 * HZ;
1021 mod_timer(&host->timer, timeout);
d129bceb
PO		 1022
1023 host->cmd = cmd;
e99783a4 1024 host->busy_handle = 0;
d129bceb 1025
a3c7778f 1026 sdhci_prepare_data(host, cmd);
d129bceb 1027
4e4141a5 1028 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1029
e89d456f 1030 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1031
d129bceb 1032 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1033 pr_err("%s: Unsupported response type!\n",
d129bceb 1034 mmc_hostname(host->mmc));
17b0429d 1035 cmd->error = -EINVAL;
d129bceb
PO		 1036 tasklet_schedule(&host->finish_tasklet);
1037 return;
1038 }
1039
1040 if (!(cmd->flags & MMC_RSP_PRESENT))
1041 flags = SDHCI_CMD_RESP_NONE;
1042 else if (cmd->flags & MMC_RSP_136)
1043 flags = SDHCI_CMD_RESP_LONG;
1044 else if (cmd->flags & MMC_RSP_BUSY)
1045 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1046 else
1047 flags = SDHCI_CMD_RESP_SHORT;
1048
1049 if (cmd->flags & MMC_RSP_CRC)
1050 flags |= SDHCI_CMD_CRC;
1051 if (cmd->flags & MMC_RSP_OPCODE)
1052 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1053
1054 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1055 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1056 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1057 flags |= SDHCI_CMD_DATA;
1058
4e4141a5 1059 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1060}
c0e55129 1061EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1062
1063static void sdhci_finish_command(struct sdhci_host *host)
1064{
1065 int i;
1066
1067 BUG_ON(host->cmd == NULL);
1068
1069 if (host->cmd->flags & MMC_RSP_PRESENT) {
1070 if (host->cmd->flags & MMC_RSP_136) {
1071 /* CRC is stripped so we need to do some shifting. */
1072 for (i = 0;i < 4;i++) {
4e4141a5 1073 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1074 SDHCI_RESPONSE + (3-i)*4) << 8;
1075 if (i != 3)
1076 host->cmd->resp[i] |=
4e4141a5 1077 sdhci_readb(host,
d129bceb
PO		 1078 SDHCI_RESPONSE + (3-i)*4-1);
1079 }
1080 } else {
4e4141a5 1081 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1082 }
1083 }
1084
17b0429d 1085 host->cmd->error = 0;
d129bceb 1086
e89d456f
AW		 1087 /* Finished CMD23, now send actual command. */
1088 if (host->cmd == host->mrq->sbc) {
1089 host->cmd = NULL;
1090 sdhci_send_command(host, host->mrq->cmd);
1091 } else {
e538fbe8 1092
e89d456f
AW		 1093 /* Processed actual command. */
1094 if (host->data && host->data_early)
1095 sdhci_finish_data(host);
d129bceb 1096
e89d456f
AW		 1097 if (!host->cmd->data)
1098 tasklet_schedule(&host->finish_tasklet);
1099
1100 host->cmd = NULL;
1101 }
d129bceb
PO		 1102}
1103
52983382
KL		 1104static u16 sdhci_get_preset_value(struct sdhci_host *host)
1105{
d975f121 1106 u16 preset = 0;
52983382 1107
d975f121
RK		 1108 switch (host->timing) {
1109 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1110 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1111 break;
d975f121 1112 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1114 break;
d975f121 1115 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1116 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1117 break;
d975f121
RK		 1118 case MMC_TIMING_UHS_SDR104:
1119 case MMC_TIMING_MMC_HS200:
52983382
KL		 1120 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1121 break;
d975f121 1122 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1124 break;
1125 default:
1126 pr_warn("%s: Invalid UHS-I mode selected\n",
1127 mmc_hostname(host->mmc));
1128 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1129 break;
1130 }
1131 return preset;
1132}
1133
1771059c 1134void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1135{
c3ed3877 1136 int div = 0; /* Initialized for compiler warning */
df16219f 1137 int real_div = div, clk_mul = 1;
c3ed3877 1138 u16 clk = 0;
7cb2c76f 1139 unsigned long timeout;
d129bceb 1140
1650d0c7
RK		 1141 host->mmc->actual_clock = 0;
1142
4e4141a5 1143 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1144
1145 if (clock == 0)
373073ef 1146 return;
d129bceb 1147
85105c53 1148 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1149 if (host->preset_enabled) {
52983382
KL		 1150 u16 pre_val;
1151
1152 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1153 pre_val = sdhci_get_preset_value(host);
1154 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1155 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1156 if (host->clk_mul &&
1157 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1158 clk = SDHCI_PROG_CLOCK_MODE;
1159 real_div = div + 1;
1160 clk_mul = host->clk_mul;
1161 } else {
1162 real_div = max_t(int, 1, div << 1);
1163 }
1164 goto clock_set;
1165 }
1166
c3ed3877
AN		 1167 /*
1168 * Check if the Host Controller supports Programmable Clock
1169 * Mode.
1170 */
1171 if (host->clk_mul) {
52983382
KL		 1172 for (div = 1; div <= 1024; div++) {
1173 if ((host->max_clk * host->clk_mul / div)
1174 <= clock)
1175 break;
1176 }
c3ed3877 1177 /*
52983382
KL		 1178 * Set Programmable Clock Mode in the Clock
1179 * Control register.
c3ed3877 1180 */
52983382
KL		 1181 clk = SDHCI_PROG_CLOCK_MODE;
1182 real_div = div;
1183 clk_mul = host->clk_mul;
1184 div--;
c3ed3877
AN		 1185 } else {
1186 /* Version 3.00 divisors must be a multiple of 2. */
1187 if (host->max_clk <= clock)
1188 div = 1;
1189 else {
1190 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1191 div += 2) {
1192 if ((host->max_clk / div) <= clock)
1193 break;
1194 }
85105c53 1195 }
df16219f 1196 real_div = div;
c3ed3877 1197 div >>= 1;
85105c53
ZG		 1198 }
1199 } else {
1200 /* Version 2.00 divisors must be a power of 2. */
0397526d 1201 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1202 if ((host->max_clk / div) <= clock)
1203 break;
1204 }
df16219f 1205 real_div = div;
c3ed3877 1206 div >>= 1;
d129bceb 1207 }
d129bceb 1208
52983382 1209clock_set:
03d6f5ff 1210 if (real_div)
df16219f 1211 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1212 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1213 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1214 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1215 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1216 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1217
27f6cb16
CB		 1218 /* Wait max 20 ms */
1219 timeout = 20;
4e4141a5 1220 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1221 & SDHCI_CLOCK_INT_STABLE)) {
1222 if (timeout == 0) {
a3c76eb9 1223 pr_err("%s: Internal clock never "
acf1da45 1224 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1225 sdhci_dumpregs(host);
1226 return;
1227 }
7cb2c76f
PO		 1228 timeout--;
1229 mdelay(1);
1230 }
d129bceb
PO		 1231
1232 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1233 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1234}
1771059c 1235EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1236
24fbb3ca
RK		 1237static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1238 unsigned short vdd)
146ad66e 1239{
3a48edc4 1240 struct mmc_host *mmc = host->mmc;
8364248a 1241 u8 pwr = 0;
146ad66e 1242
52221610
TK		 1243 if (!IS_ERR(mmc->supply.vmmc)) {
1244 spin_unlock_irq(&host->lock);
4e743f1f 1245 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610
TK		 1246 spin_lock_irq(&host->lock);
1247 return;
1248 }
1249
24fbb3ca
RK		 1250 if (mode != MMC_POWER_OFF) {
1251 switch (1 << vdd) {
ae628903
PO		 1252 case MMC_VDD_165_195:
1253 pwr = SDHCI_POWER_180;
1254 break;
1255 case MMC_VDD_29_30:
1256 case MMC_VDD_30_31:
1257 pwr = SDHCI_POWER_300;
1258 break;
1259 case MMC_VDD_32_33:
1260 case MMC_VDD_33_34:
1261 pwr = SDHCI_POWER_330;
1262 break;
1263 default:
1264 BUG();
1265 }
1266 }
1267
1268 if (host->pwr == pwr)
e921a8b6 1269 return;
146ad66e 1270
ae628903
PO		 1271 host->pwr = pwr;
1272
1273 if (pwr == 0) {
4e4141a5 1274 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1275 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1276 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1277 vdd = 0;
e921a8b6
RK		 1278 } else {
1279 /*
1280 * Spec says that we should clear the power reg before setting
1281 * a new value. Some controllers don't seem to like this though.
1282 */
1283 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1284 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1285
e921a8b6
RK		 1286 /*
1287 * At least the Marvell CaFe chip gets confused if we set the
1288 * voltage and set turn on power at the same time, so set the
1289 * voltage first.
1290 */
1291 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1292 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1293
e921a8b6 1294 pwr |= SDHCI_POWER_ON;
146ad66e 1295
e921a8b6 1296 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1297
e921a8b6
RK		 1298 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1299 sdhci_runtime_pm_bus_on(host);
f0710a55 1300
e921a8b6
RK		 1301 /*
1302 * Some controllers need an extra 10ms delay of 10ms before
1303 * they can apply clock after applying power
1304 */
1305 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1306 mdelay(10);
1307 }
146ad66e
PO		 1308}
1309
d129bceb
PO		 1310/*****************************************************************************\
1311 * *
1312 * MMC callbacks *
1313 * *
1314\*****************************************************************************/
1315
1316static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1317{
1318 struct sdhci_host *host;
505a8680 1319 int present;
d129bceb 1320 unsigned long flags;
473b095a 1321 u32 tuning_opcode;
d129bceb
PO		 1322
1323 host = mmc_priv(mmc);
1324
66fd8ad5
AH		 1325 sdhci_runtime_pm_get(host);
1326
d129bceb
PO		 1327 spin_lock_irqsave(&host->lock, flags);
1328
1329 WARN_ON(host->mrq != NULL);
1330
f9134319 1331#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1332 sdhci_activate_led(host);
2f730fec 1333#endif
e89d456f
AW		 1334
1335 /*
1336 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1337 * requests if Auto-CMD12 is enabled.
1338 */
1339 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1340 if (mrq->stop) {
1341 mrq->data->stop = NULL;
1342 mrq->stop = NULL;
1343 }
1344 }
d129bceb
PO		 1345
1346 host->mrq = mrq;
1347
505a8680
SG		 1348 /*
1349 * Firstly check card presence from cd-gpio. The return could
1350 * be one of the following possibilities:
1351 * negative: cd-gpio is not available
1352 * zero: cd-gpio is used, and card is removed
1353 * one: cd-gpio is used, and card is present
1354 */
1355 present = mmc_gpio_get_cd(host->mmc);
1356 if (present < 0) {
1357 /* If polling, assume that the card is always present. */
1358 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1359 present = 1;
1360 else
1361 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1362 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1363 }
1364
68d1fb7e 1365 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1366 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1367 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1368 } else {
1369 u32 present_state;
1370
1371 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1372 /*
1373 * Check if the re-tuning timer has already expired and there
7756a96d
YS		 1374 * is no on-going data transfer and DAT0 is not busy. If so,
1375 * we need to execute tuning procedure before sending command.
cf2b5eea
AN		 1376 */
1377 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
7756a96d
YS		 1378 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1379 (present_state & SDHCI_DATA_0_LVL_MASK)) {
14efd957
CB		 1380 if (mmc->card) {
1381 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1382 tuning_opcode =
1383 mmc->card->type == MMC_TYPE_MMC ?
1384 MMC_SEND_TUNING_BLOCK_HS200 :
1385 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1386
1387 /* Here we need to set the host->mrq to NULL,
1388 * in case the pending finish_tasklet
1389 * finishes it incorrectly.
1390 */
1391 host->mrq = NULL;
1392
14efd957
CB		 1393 spin_unlock_irqrestore(&host->lock, flags);
1394 sdhci_execute_tuning(mmc, tuning_opcode);
1395 spin_lock_irqsave(&host->lock, flags);
1396
1397 /* Restore original mmc_request structure */
1398 host->mrq = mrq;
1399 }
cf2b5eea
AN		 1400 }
1401
8edf6371 1402 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1403 sdhci_send_command(host, mrq->sbc);
1404 else
1405 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1406 }
d129bceb 1407
5f25a66f 1408 mmiowb();
d129bceb
PO		 1409 spin_unlock_irqrestore(&host->lock, flags);
1410}
1411
2317f56c
RK		 1412void sdhci_set_bus_width(struct sdhci_host *host, int width)
1413{
1414 u8 ctrl;
1415
1416 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1417 if (width == MMC_BUS_WIDTH_8) {
1418 ctrl &= ~SDHCI_CTRL_4BITBUS;
1419 if (host->version >= SDHCI_SPEC_300)
1420 ctrl |= SDHCI_CTRL_8BITBUS;
1421 } else {
1422 if (host->version >= SDHCI_SPEC_300)
1423 ctrl &= ~SDHCI_CTRL_8BITBUS;
1424 if (width == MMC_BUS_WIDTH_4)
1425 ctrl |= SDHCI_CTRL_4BITBUS;
1426 else
1427 ctrl &= ~SDHCI_CTRL_4BITBUS;
1428 }
1429 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1430}
1431EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1432
96d7b78c
RK		 1433void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1434{
1435 u16 ctrl_2;
1436
1437 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1438 /* Select Bus Speed Mode for host */
1439 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1440 if ((timing == MMC_TIMING_MMC_HS200) ||
1441 (timing == MMC_TIMING_UHS_SDR104))
1442 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1443 else if (timing == MMC_TIMING_UHS_SDR12)
1444 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1445 else if (timing == MMC_TIMING_UHS_SDR25)
1446 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1447 else if (timing == MMC_TIMING_UHS_SDR50)
1448 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1449 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1450 (timing == MMC_TIMING_MMC_DDR52))
1451 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1452 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1453}
1454EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1455
66fd8ad5 1456static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1457{
d129bceb
PO		 1458 unsigned long flags;
1459 u8 ctrl;
3a48edc4 1460 struct mmc_host *mmc = host->mmc;
d129bceb 1461
d129bceb
PO		 1462 spin_lock_irqsave(&host->lock, flags);
1463
ceb6143b
AH		 1464 if (host->flags & SDHCI_DEVICE_DEAD) {
1465 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1466 if (!IS_ERR(mmc->supply.vmmc) &&
1467 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1468 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1469 return;
1470 }
1e72859e 1471
d129bceb
PO		 1472 /*
1473 * Reset the chip on each power off.
1474 * Should clear out any weird states.
1475 */
1476 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1477 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1478 sdhci_reinit(host);
d129bceb
PO		 1479 }
1480
52983382 1481 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1482 (ios->power_mode == MMC_POWER_UP) &&
1483 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1484 sdhci_enable_preset_value(host, false);
1485
373073ef 1486 if (!ios->clock || ios->clock != host->clock) {
1771059c 1487 host->ops->set_clock(host, ios->clock);
373073ef 1488 host->clock = ios->clock;
03d6f5ff
AD		 1489
1490 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1491 host->clock) {
1492 host->timeout_clk = host->mmc->actual_clock ?
1493 host->mmc->actual_clock / 1000 :
1494 host->clock / 1000;
1495 host->mmc->max_busy_timeout =
1496 host->ops->get_max_timeout_count ?
1497 host->ops->get_max_timeout_count(host) :
1498 1 << 27;
1499 host->mmc->max_busy_timeout /= host->timeout_clk;
1500 }
373073ef 1501 }
d129bceb 1502
24fbb3ca 1503 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1504
643a81ff
PR		 1505 if (host->ops->platform_send_init_74_clocks)
1506 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1507
2317f56c 1508 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1509
15ec4461 1510 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1511
3ab9c8da
PR		 1512 if ((ios->timing == MMC_TIMING_SD_HS ||
1513 ios->timing == MMC_TIMING_MMC_HS)
1514 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1515 ctrl |= SDHCI_CTRL_HISPD;
1516 else
1517 ctrl &= ~SDHCI_CTRL_HISPD;
1518
d6d50a15 1519 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1520 u16 clk, ctrl_2;
49c468fc
AN		 1521
1522 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1523 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1524 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1525 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1526 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1527 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1528 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1529 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1530
da91a8f9 1531 if (!host->preset_enabled) {
758535c4 1532 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1533 /*
1534 * We only need to set Driver Strength if the
1535 * preset value enable is not set.
1536 */
da91a8f9 1537 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1538 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1539 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1540 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1541 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1542 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1543
1544 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1545 } else {
1546 /*
1547 * According to SDHC Spec v3.00, if the Preset Value
1548 * Enable in the Host Control 2 register is set, we
1549 * need to reset SD Clock Enable before changing High
1550 * Speed Enable to avoid generating clock gliches.
1551 */
758535c4
AN		 1552
1553 /* Reset SD Clock Enable */
1554 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1555 clk &= ~SDHCI_CLOCK_CARD_EN;
1556 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1557
1558 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1559
1560 /* Re-enable SD Clock */
1771059c 1561 host->ops->set_clock(host, host->clock);
d6d50a15 1562 }
49c468fc 1563
49c468fc
AN		 1564 /* Reset SD Clock Enable */
1565 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1566 clk &= ~SDHCI_CLOCK_CARD_EN;
1567 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1568
96d7b78c 1569 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1570 host->timing = ios->timing;
49c468fc 1571
52983382
KL		 1572 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1573 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1574 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1575 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1576 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1577 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1578 u16 preset;
1579
1580 sdhci_enable_preset_value(host, true);
1581 preset = sdhci_get_preset_value(host);
1582 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1583 >> SDHCI_PRESET_DRV_SHIFT;
1584 }
1585
49c468fc 1586 /* Re-enable SD Clock */
1771059c 1587 host->ops->set_clock(host, host->clock);
758535c4
AN		 1588 } else
1589 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1590
b8352260
LD		 1591 /*
1592 * Some (ENE) controllers go apeshit on some ios operation,
1593 * signalling timeout and CRC errors even on CMD0. Resetting
1594 * it on each ios seems to solve the problem.
1595 */
b8c86fc5 1596 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1597 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1598
5f25a66f 1599 mmiowb();
d129bceb
PO		 1600 spin_unlock_irqrestore(&host->lock, flags);
1601}
1602
66fd8ad5
AH		 1603static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1604{
1605 struct sdhci_host *host = mmc_priv(mmc);
1606
1607 sdhci_runtime_pm_get(host);
1608 sdhci_do_set_ios(host, ios);
1609 sdhci_runtime_pm_put(host);
1610}
1611
94144a46
KL		 1612static int sdhci_do_get_cd(struct sdhci_host *host)
1613{
1614 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1615
1616 if (host->flags & SDHCI_DEVICE_DEAD)
1617 return 0;
1618
1619 /* If polling/nonremovable, assume that the card is always present. */
1620 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1621 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1622 return 1;
1623
1624 /* Try slot gpio detect */
1625 if (!IS_ERR_VALUE(gpio_cd))
1626 return !!gpio_cd;
1627
1628 /* Host native card detect */
1629 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1630}
1631
1632static int sdhci_get_cd(struct mmc_host *mmc)
1633{
1634 struct sdhci_host *host = mmc_priv(mmc);
1635 int ret;
1636
1637 sdhci_runtime_pm_get(host);
1638 ret = sdhci_do_get_cd(host);
1639 sdhci_runtime_pm_put(host);
1640 return ret;
1641}
1642
66fd8ad5 1643static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1644{
d129bceb 1645 unsigned long flags;
2dfb579c 1646 int is_readonly;
d129bceb 1647
d129bceb
PO		 1648 spin_lock_irqsave(&host->lock, flags);
1649
1e72859e 1650 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1651 is_readonly = 0;
1652 else if (host->ops->get_ro)
1653 is_readonly = host->ops->get_ro(host);
1e72859e 1654 else
2dfb579c
WS		 1655 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1656 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1657
1658 spin_unlock_irqrestore(&host->lock, flags);
1659
2dfb579c
WS		 1660 /* This quirk needs to be replaced by a callback-function later */
1661 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1662 !is_readonly : is_readonly;
d129bceb
PO		 1663}
1664
82b0e23a
TI		 1665#define SAMPLE_COUNT 5
1666
66fd8ad5 1667static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1668{
82b0e23a
TI		 1669 int i, ro_count;
1670
82b0e23a 1671 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1672 return sdhci_check_ro(host);
82b0e23a
TI		 1673
1674 ro_count = 0;
1675 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1676 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1677 if (++ro_count > SAMPLE_COUNT / 2)
1678 return 1;
1679 }
1680 msleep(30);
1681 }
1682 return 0;
1683}
1684
20758b66
AH		 1685static void sdhci_hw_reset(struct mmc_host *mmc)
1686{
1687 struct sdhci_host *host = mmc_priv(mmc);
1688
1689 if (host->ops && host->ops->hw_reset)
1690 host->ops->hw_reset(host);
1691}
1692
66fd8ad5 1693static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1694{
66fd8ad5
AH		 1695 struct sdhci_host *host = mmc_priv(mmc);
1696 int ret;
f75979b7 1697
66fd8ad5
AH		 1698 sdhci_runtime_pm_get(host);
1699 ret = sdhci_do_get_ro(host);
1700 sdhci_runtime_pm_put(host);
1701 return ret;
1702}
f75979b7 1703
66fd8ad5
AH		 1704static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1705{
be138554 1706 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1707 if (enable)
b537f94c 1708 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1709 else
b537f94c
RK		 1710 host->ier &= ~SDHCI_INT_CARD_INT;
1711
1712 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1713 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1714 mmiowb();
1715 }
66fd8ad5
AH		 1716}
1717
1718static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1719{
1720 struct sdhci_host *host = mmc_priv(mmc);
1721 unsigned long flags;
f75979b7 1722
ef104333
RK		 1723 sdhci_runtime_pm_get(host);
1724
66fd8ad5 1725 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1726 if (enable)
1727 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1728 else
1729 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1730
66fd8ad5 1731 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1732 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1733
1734 sdhci_runtime_pm_put(host);
f75979b7
PO		 1735}
1736
20b92a30 1737static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1738 struct mmc_ios *ios)
f2119df6 1739{
3a48edc4 1740 struct mmc_host *mmc = host->mmc;
20b92a30 1741 u16 ctrl;
6231f3de 1742 int ret;
f2119df6 1743
20b92a30
KL		 1744 /*
1745 * Signal Voltage Switching is only applicable for Host Controllers
1746 * v3.00 and above.
1747 */
1748 if (host->version < SDHCI_SPEC_300)
1749 return 0;
6231f3de 1750
f2119df6 1751 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1752
21f5998f 1753 switch (ios->signal_voltage) {
20b92a30
KL		 1754 case MMC_SIGNAL_VOLTAGE_330:
1755 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1756 ctrl &= ~SDHCI_CTRL_VDD_180;
1757 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1758
3a48edc4
TK		 1759 if (!IS_ERR(mmc->supply.vqmmc)) {
1760 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1761 3600000);
20b92a30 1762 if (ret) {
6606110d
JP		 1763 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1764 mmc_hostname(mmc));
20b92a30
KL		 1765 return -EIO;
1766 }
1767 }
1768 /* Wait for 5ms */
1769 usleep_range(5000, 5500);
f2119df6 1770
20b92a30
KL		 1771 /* 3.3V regulator output should be stable within 5 ms */
1772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1773 if (!(ctrl & SDHCI_CTRL_VDD_180))
1774 return 0;
6231f3de 1775
6606110d
JP		 1776 pr_warn("%s: 3.3V regulator output did not became stable\n",
1777 mmc_hostname(mmc));
20b92a30
KL		 1778
1779 return -EAGAIN;
1780 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1781 if (!IS_ERR(mmc->supply.vqmmc)) {
1782 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1783 1700000, 1950000);
1784 if (ret) {
6606110d
JP		 1785 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1786 mmc_hostname(mmc));
20b92a30
KL		 1787 return -EIO;
1788 }
1789 }
6231f3de 1790
6231f3de
PR		 1791 /*
1792 * Enable 1.8V Signal Enable in the Host Control2
1793 * register
1794 */
20b92a30
KL		 1795 ctrl |= SDHCI_CTRL_VDD_180;
1796 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1797
20b92a30
KL		 1798 /* 1.8V regulator output should be stable within 5 ms */
1799 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1800 if (ctrl & SDHCI_CTRL_VDD_180)
1801 return 0;
f2119df6 1802
6606110d
JP		 1803 pr_warn("%s: 1.8V regulator output did not became stable\n",
1804 mmc_hostname(mmc));
f2119df6 1805
20b92a30
KL		 1806 return -EAGAIN;
1807 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1808 if (!IS_ERR(mmc->supply.vqmmc)) {
1809 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1810 1300000);
20b92a30 1811 if (ret) {
6606110d
JP		 1812 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1813 mmc_hostname(mmc));
20b92a30 1814 return -EIO;
f2119df6
AN		 1815 }
1816 }
6231f3de 1817 return 0;
20b92a30 1818 default:
f2119df6
AN		 1819 /* No signal voltage switch required */
1820 return 0;
20b92a30 1821 }
f2119df6
AN		 1822}
1823
66fd8ad5 1824static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1825 struct mmc_ios *ios)
66fd8ad5
AH		 1826{
1827 struct sdhci_host *host = mmc_priv(mmc);
1828 int err;
1829
1830 if (host->version < SDHCI_SPEC_300)
1831 return 0;
1832 sdhci_runtime_pm_get(host);
21f5998f 1833 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1834 sdhci_runtime_pm_put(host);
1835 return err;
1836}
1837
20b92a30
KL		 1838static int sdhci_card_busy(struct mmc_host *mmc)
1839{
1840 struct sdhci_host *host = mmc_priv(mmc);
1841 u32 present_state;
1842
1843 sdhci_runtime_pm_get(host);
1844 /* Check whether DAT[3:0] is 0000 */
1845 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1846 sdhci_runtime_pm_put(host);
1847
1848 return !(present_state & SDHCI_DATA_LVL_MASK);
1849}
1850
069c9f14 1851static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1852{
4b6f37d3 1853 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1854 u16 ctrl;
b513ea25 1855 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1856 int err = 0;
2b35bd83 1857 unsigned long flags;
b513ea25 1858
66fd8ad5 1859 sdhci_runtime_pm_get(host);
2b35bd83 1860 spin_lock_irqsave(&host->lock, flags);
b513ea25 1861
b513ea25 1862 /*
069c9f14
G		 1863 * The Host Controller needs tuning only in case of SDR104 mode
1864 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1865 * Capabilities register.
069c9f14
G		 1866 * If the Host Controller supports the HS200 mode then the
1867 * tuning function has to be executed.
b513ea25 1868 */
4b6f37d3
RK		 1869 switch (host->timing) {
1870 case MMC_TIMING_MMC_HS200:
1871 case MMC_TIMING_UHS_SDR104:
1872 break;
1873
1874 case MMC_TIMING_UHS_SDR50:
1875 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1876 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1877 break;
1878 /* FALLTHROUGH */
1879
1880 default:
2b35bd83 1881 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1882 sdhci_runtime_pm_put(host);
b513ea25
AN		 1883 return 0;
1884 }
1885
45251812 1886 if (host->ops->platform_execute_tuning) {
2b35bd83 1887 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1888 err = host->ops->platform_execute_tuning(host, opcode);
1889 sdhci_runtime_pm_put(host);
1890 return err;
1891 }
1892
4b6f37d3
RK		 1893 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1894 ctrl |= SDHCI_CTRL_EXEC_TUNING;
b513ea25
AN		 1895 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1896
1897 /*
1898 * As per the Host Controller spec v3.00, tuning command
1899 * generates Buffer Read Ready interrupt, so enable that.
1900 *
1901 * Note: The spec clearly says that when tuning sequence
1902 * is being performed, the controller does not generate
1903 * interrupts other than Buffer Read Ready interrupt. But
1904 * to make sure we don't hit a controller bug, we _only_
1905 * enable Buffer Read Ready interrupt here.
1906 */
b537f94c
RK		 1907 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1908 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1909
1910 /*
1911 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1912 * of loops reaches 40 times or a timeout of 150ms occurs.
1913 */
b513ea25
AN		 1914 do {
1915 struct mmc_command cmd = {0};
66fd8ad5 1916 struct mmc_request mrq = {NULL};
b513ea25 1917
069c9f14 1918 cmd.opcode = opcode;
b513ea25
AN		 1919 cmd.arg = 0;
1920 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1921 cmd.retries = 0;
1922 cmd.data = NULL;
1923 cmd.error = 0;
1924
7ce45e95
AC		 1925 if (tuning_loop_counter-- == 0)
1926 break;
1927
b513ea25
AN		 1928 mrq.cmd = &cmd;
1929 host->mrq = &mrq;
1930
1931 /*
1932 * In response to CMD19, the card sends 64 bytes of tuning
1933 * block to the Host Controller. So we set the block size
1934 * to 64 here.
1935 */
069c9f14
G		 1936 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1937 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1938 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1939 SDHCI_BLOCK_SIZE);
1940 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1941 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1942 SDHCI_BLOCK_SIZE);
1943 } else {
1944 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1945 SDHCI_BLOCK_SIZE);
1946 }
b513ea25
AN		 1947
1948 /*
1949 * The tuning block is sent by the card to the host controller.
1950 * So we set the TRNS_READ bit in the Transfer Mode register.
1951 * This also takes care of setting DMA Enable and Multi Block
1952 * Select in the same register to 0.
1953 */
1954 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1955
1956 sdhci_send_command(host, &cmd);
1957
1958 host->cmd = NULL;
1959 host->mrq = NULL;
1960
2b35bd83 1961 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1962 /* Wait for Buffer Read Ready interrupt */
1963 wait_event_interruptible_timeout(host->buf_ready_int,
1964 (host->tuning_done == 1),
1965 msecs_to_jiffies(50));
2b35bd83 1966 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1967
1968 if (!host->tuning_done) {
a3c76eb9 1969 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1970 "Buffer Read Ready interrupt during tuning "
1971 "procedure, falling back to fixed sampling "
1972 "clock\n");
1973 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1974 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1975 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1976 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1977
1978 err = -EIO;
1979 goto out;
1980 }
1981
1982 host->tuning_done = 0;
1983
1984 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1985
1986 /* eMMC spec does not require a delay between tuning cycles */
1987 if (opcode == MMC_SEND_TUNING_BLOCK)
1988 mdelay(1);
b513ea25
AN		 1989 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1990
1991 /*
1992 * The Host Driver has exhausted the maximum number of loops allowed,
1993 * so use fixed sampling frequency.
1994 */
7ce45e95 1995 if (tuning_loop_counter < 0) {
b513ea25
AN		 1996 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1997 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 1998 }
1999 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2000 pr_info(DRIVER_NAME ": Tuning procedure"
2001 " failed, falling back to fixed sampling"
2002 " clock\n");
114f2bf6 2003 err = -EIO;
b513ea25
AN		 2004 }
2005
2006out:
cf2b5eea
AN		 2007 /*
2008 * If this is the very first time we are here, we start the retuning
2009 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2010 * flag won't be set, we check this condition before actually starting
2011 * the timer.
2012 */
2013 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2014 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2015 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2016 mod_timer(&host->tuning_timer, jiffies +
2017 host->tuning_count * HZ);
2018 /* Tuning mode 1 limits the maximum data length to 4MB */
2019 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2020 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2021 host->flags &= ~SDHCI_NEEDS_RETUNING;
2022 /* Reload the new initial value for timer */
2bc02485
AS		 2023 mod_timer(&host->tuning_timer, jiffies +
2024 host->tuning_count * HZ);
cf2b5eea
AN		 2025 }
2026
2027 /*
2028 * In case tuning fails, host controllers which support re-tuning can
2029 * try tuning again at a later time, when the re-tuning timer expires.
2030 * So for these controllers, we return 0. Since there might be other
2031 * controllers who do not have this capability, we return error for
973905fe
AL		 2032 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2033 * a retuning timer to do the retuning for the card.
cf2b5eea 2034 */
973905fe 2035 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2036 err = 0;
2037
b537f94c
RK		 2038 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2039 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2040 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2041 sdhci_runtime_pm_put(host);
b513ea25
AN		 2042
2043 return err;
2044}
2045
52983382
KL		 2046
2047static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2048{
4d55c5a1
AN		 2049 /* Host Controller v3.00 defines preset value registers */
2050 if (host->version < SDHCI_SPEC_300)
2051 return;
2052
4d55c5a1
AN		 2053 /*
2054 * We only enable or disable Preset Value if they are not already
2055 * enabled or disabled respectively. Otherwise, we bail out.
2056 */
da91a8f9
RK		 2057 if (host->preset_enabled != enable) {
2058 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2059
2060 if (enable)
2061 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2062 else
2063 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2064
4d55c5a1 2065 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2066
2067 if (enable)
2068 host->flags |= SDHCI_PV_ENABLED;
2069 else
2070 host->flags &= ~SDHCI_PV_ENABLED;
2071
2072 host->preset_enabled = enable;
4d55c5a1 2073 }
66fd8ad5
AH		 2074}
2075
71e69211 2076static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2077{
71e69211 2078 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2079 unsigned long flags;
2080
722e1280
CD		 2081 /* First check if client has provided their own card event */
2082 if (host->ops->card_event)
2083 host->ops->card_event(host);
2084
d129bceb
PO		 2085 spin_lock_irqsave(&host->lock, flags);
2086
66fd8ad5 2087 /* Check host->mrq first in case we are runtime suspended */
9668d765 2088 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2089 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2090 mmc_hostname(host->mmc));
a3c76eb9 2091 pr_err("%s: Resetting controller.\n",
66fd8ad5 2092 mmc_hostname(host->mmc));
d129bceb 2093
03231f9b
RK		 2094 sdhci_do_reset(host, SDHCI_RESET_CMD);
2095 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2096
66fd8ad5
AH		 2097 host->mrq->cmd->error = -ENOMEDIUM;
2098 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2099 }
2100
2101 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2102}
2103
2104static const struct mmc_host_ops sdhci_ops = {
2105 .request = sdhci_request,
2106 .set_ios = sdhci_set_ios,
94144a46 2107 .get_cd = sdhci_get_cd,
71e69211
GL		 2108 .get_ro = sdhci_get_ro,
2109 .hw_reset = sdhci_hw_reset,
2110 .enable_sdio_irq = sdhci_enable_sdio_irq,
2111 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2112 .execute_tuning = sdhci_execute_tuning,
71e69211 2113 .card_event = sdhci_card_event,
20b92a30 2114 .card_busy = sdhci_card_busy,
71e69211
GL		 2115};
2116
2117/*****************************************************************************\
2118 * *
2119 * Tasklets *
2120 * *
2121\*****************************************************************************/
2122
d129bceb
PO		 2123static void sdhci_tasklet_finish(unsigned long param)
2124{
2125 struct sdhci_host *host;
2126 unsigned long flags;
2127 struct mmc_request *mrq;
2128
2129 host = (struct sdhci_host*)param;
2130
66fd8ad5
AH		 2131 spin_lock_irqsave(&host->lock, flags);
2132
0c9c99a7
CB		 2133 /*
2134 * If this tasklet gets rescheduled while running, it will
2135 * be run again afterwards but without any active request.
2136 */
66fd8ad5
AH		 2137 if (!host->mrq) {
2138 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2139 return;
66fd8ad5 2140 }
d129bceb
PO		 2141
2142 del_timer(&host->timer);
2143
2144 mrq = host->mrq;
2145
d129bceb
PO		 2146 /*
2147 * The controller needs a reset of internal state machines
2148 * upon error conditions.
2149 */
1e72859e 2150 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2151 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2152 (mrq->sbc && mrq->sbc->error) ||
2153 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2154 (mrq->data->stop && mrq->data->stop->error))) ||
2155 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2156
2157 /* Some controllers need this kick or reset won't work here */
8213af3b 2158 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2159 /* This is to force an update */
1771059c 2160 host->ops->set_clock(host, host->clock);
645289dc
PO		 2161
2162 /* Spec says we should do both at the same time, but Ricoh
2163 controllers do not like that. */
03231f9b
RK		 2164 sdhci_do_reset(host, SDHCI_RESET_CMD);
2165 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2166 }
2167
2168 host->mrq = NULL;
2169 host->cmd = NULL;
2170 host->data = NULL;
2171
f9134319 2172#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2173 sdhci_deactivate_led(host);
2f730fec 2174#endif
d129bceb 2175
5f25a66f 2176 mmiowb();
d129bceb
PO		 2177 spin_unlock_irqrestore(&host->lock, flags);
2178
2179 mmc_request_done(host->mmc, mrq);
66fd8ad5 2180 sdhci_runtime_pm_put(host);
d129bceb
PO		 2181}
2182
2183static void sdhci_timeout_timer(unsigned long data)
2184{
2185 struct sdhci_host *host;
2186 unsigned long flags;
2187
2188 host = (struct sdhci_host*)data;
2189
2190 spin_lock_irqsave(&host->lock, flags);
2191
2192 if (host->mrq) {
a3c76eb9 2193 pr_err("%s: Timeout waiting for hardware "
acf1da45 2194 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2195 sdhci_dumpregs(host);
2196
2197 if (host->data) {
17b0429d 2198 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2199 sdhci_finish_data(host);
2200 } else {
2201 if (host->cmd)
17b0429d 2202 host->cmd->error = -ETIMEDOUT;
d129bceb 2203 else
17b0429d 2204 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2205
2206 tasklet_schedule(&host->finish_tasklet);
2207 }
2208 }
2209
5f25a66f 2210 mmiowb();
d129bceb
PO		 2211 spin_unlock_irqrestore(&host->lock, flags);
2212}
2213
cf2b5eea
AN		 2214static void sdhci_tuning_timer(unsigned long data)
2215{
2216 struct sdhci_host *host;
2217 unsigned long flags;
2218
2219 host = (struct sdhci_host *)data;
2220
2221 spin_lock_irqsave(&host->lock, flags);
2222
2223 host->flags |= SDHCI_NEEDS_RETUNING;
2224
2225 spin_unlock_irqrestore(&host->lock, flags);
2226}
2227
d129bceb
PO		 2228/*****************************************************************************\
2229 * *
2230 * Interrupt handling *
2231 * *
2232\*****************************************************************************/
2233
61541397 2234static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2235{
2236 BUG_ON(intmask == 0);
2237
2238 if (!host->cmd) {
a3c76eb9 2239 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2240 "though no command operation was in progress.\n",
2241 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2242 sdhci_dumpregs(host);
2243 return;
2244 }
2245
43b58b36 2246 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2247 host->cmd->error = -ETIMEDOUT;
2248 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2249 SDHCI_INT_INDEX))
2250 host->cmd->error = -EILSEQ;
43b58b36 2251
e809517f 2252 if (host->cmd->error) {
d129bceb 2253 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2254 return;
2255 }
2256
2257 /*
2258 * The host can send and interrupt when the busy state has
2259 * ended, allowing us to wait without wasting CPU cycles.
2260 * Unfortunately this is overloaded on the "data complete"
2261 * interrupt, so we need to take some care when handling
2262 * it.
2263 *
2264 * Note: The 1.0 specification is a bit ambiguous about this
2265 * feature so there might be some problems with older
2266 * controllers.
2267 */
2268 if (host->cmd->flags & MMC_RSP_BUSY) {
2269 if (host->cmd->data)
2270 DBG("Cannot wait for busy signal when also "
2271 "doing a data transfer");
e99783a4
CM		 2272 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2273 && !host->busy_handle) {
2274 /* Mark that command complete before busy is ended */
2275 host->busy_handle = 1;
e809517f 2276 return;
e99783a4 2277 }
f945405c
BD		 2278
2279 /* The controller does not support the end-of-busy IRQ,
2280 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2281 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2282 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2283 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2284 }
2285
2286 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2287 sdhci_finish_command(host);
d129bceb
PO		 2288}
2289
0957c333 2290#ifdef CONFIG_MMC_DEBUG
08621b18 2291static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2292{
2293 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2294 void *desc = host->adma_table;
6882a8c0
BD		 2295
2296 sdhci_dumpregs(host);
2297
2298 while (true) {
0545230f 2299 struct sdhci_adma2_32_desc *dma_desc = desc;
6882a8c0
BD		 2300
2301 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
0545230f
AH		 2302 name, desc, le32_to_cpu(dma_desc->addr),
2303 le16_to_cpu(dma_desc->len),
2304 le16_to_cpu(dma_desc->cmd));
6882a8c0 2305
76fe379a 2306 desc += host->desc_sz;
6882a8c0 2307
0545230f 2308 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2309 break;
2310 }
2311}
2312#else
08621b18 2313static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2314#endif
2315
d129bceb
PO		 2316static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2317{
069c9f14 2318 u32 command;
d129bceb
PO		 2319 BUG_ON(intmask == 0);
2320
b513ea25
AN		 2321 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2322 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2323 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2324 if (command == MMC_SEND_TUNING_BLOCK ||
2325 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2326 host->tuning_done = 1;
2327 wake_up(&host->buf_ready_int);
2328 return;
2329 }
2330 }
2331
d129bceb
PO		 2332 if (!host->data) {
2333 /*
e809517f
PO		 2334 * The "data complete" interrupt is also used to
2335 * indicate that a busy state has ended. See comment
2336 * above in sdhci_cmd_irq().
d129bceb 2337 */
e809517f 2338 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2339 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2340 host->cmd->error = -ETIMEDOUT;
2341 tasklet_schedule(&host->finish_tasklet);
2342 return;
2343 }
e809517f 2344 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2345 /*
2346 * Some cards handle busy-end interrupt
2347 * before the command completed, so make
2348 * sure we do things in the proper order.
2349 */
2350 if (host->busy_handle)
2351 sdhci_finish_command(host);
2352 else
2353 host->busy_handle = 1;
e809517f
PO		 2354 return;
2355 }
2356 }
d129bceb 2357
a3c76eb9 2358 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2359 "though no data operation was in progress.\n",
2360 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2361 sdhci_dumpregs(host);
2362
2363 return;
2364 }
2365
2366 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2367 host->data->error = -ETIMEDOUT;
22113efd
AL		 2368 else if (intmask & SDHCI_INT_DATA_END_BIT)
2369 host->data->error = -EILSEQ;
2370 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2371 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2372 != MMC_BUS_TEST_R)
17b0429d 2373 host->data->error = -EILSEQ;
6882a8c0 2374 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2375 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2376 sdhci_adma_show_error(host);
2134a922 2377 host->data->error = -EIO;
a4071fbb
HZ		 2378 if (host->ops->adma_workaround)
2379 host->ops->adma_workaround(host, intmask);
6882a8c0 2380 }
d129bceb 2381
17b0429d 2382 if (host->data->error)
d129bceb
PO		 2383 sdhci_finish_data(host);
2384 else {
a406f5a3 2385 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2386 sdhci_transfer_pio(host);
2387
6ba736a1
PO		 2388 /*
2389 * We currently don't do anything fancy with DMA
2390 * boundaries, but as we can't disable the feature
2391 * we need to at least restart the transfer.
f6a03cbf
MV		 2392 *
2393 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2394 * should return a valid address to continue from, but as
2395 * some controllers are faulty, don't trust them.
6ba736a1 2396 */
f6a03cbf
MV		 2397 if (intmask & SDHCI_INT_DMA_END) {
2398 u32 dmastart, dmanow;
2399 dmastart = sg_dma_address(host->data->sg);
2400 dmanow = dmastart + host->data->bytes_xfered;
2401 /*
2402 * Force update to the next DMA block boundary.
2403 */
2404 dmanow = (dmanow &
2405 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2406 SDHCI_DEFAULT_BOUNDARY_SIZE;
2407 host->data->bytes_xfered = dmanow - dmastart;
2408 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2409 " next 0x%08x\n",
2410 mmc_hostname(host->mmc), dmastart,
2411 host->data->bytes_xfered, dmanow);
2412 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2413 }
6ba736a1 2414
e538fbe8
PO		 2415 if (intmask & SDHCI_INT_DATA_END) {
2416 if (host->cmd) {
2417 /*
2418 * Data managed to finish before the
2419 * command completed. Make sure we do
2420 * things in the proper order.
2421 */
2422 host->data_early = 1;
2423 } else {
2424 sdhci_finish_data(host);
2425 }
2426 }
d129bceb
PO		 2427 }
2428}
2429
7d12e780 2430static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2431{
781e989c 2432 irqreturn_t result = IRQ_NONE;
66fd8ad5 2433 struct sdhci_host *host = dev_id;
41005003 2434 u32 intmask, mask, unexpected = 0;
781e989c 2435 int max_loops = 16;
d129bceb
PO		 2436
2437 spin_lock(&host->lock);
2438
be138554 2439 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2440 spin_unlock(&host->lock);
655bca76 2441 return IRQ_NONE;
66fd8ad5
AH		 2442 }
2443
4e4141a5 2444 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2445 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2446 result = IRQ_NONE;
2447 goto out;
2448 }
2449
41005003
RK		 2450 do {
2451 /* Clear selected interrupts. */
2452 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2453 SDHCI_INT_BUS_POWER);
2454 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2455
41005003
RK		 2456 DBG("*** %s got interrupt: 0x%08x\n",
2457 mmc_hostname(host->mmc), intmask);
d129bceb 2458
41005003
RK		 2459 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2460 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2461 SDHCI_CARD_PRESENT;
d129bceb 2462
41005003
RK		 2463 /*
2464 * There is a observation on i.mx esdhc. INSERT
2465 * bit will be immediately set again when it gets
2466 * cleared, if a card is inserted. We have to mask
2467 * the irq to prevent interrupt storm which will
2468 * freeze the system. And the REMOVE gets the
2469 * same situation.
2470 *
2471 * More testing are needed here to ensure it works
2472 * for other platforms though.
2473 */
b537f94c
RK		 2474 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2475 SDHCI_INT_CARD_REMOVE);
2476 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2477 SDHCI_INT_CARD_INSERT;
2478 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2479 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2480
2481 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2482 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2483
2484 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2485 SDHCI_INT_CARD_REMOVE);
2486 result = IRQ_WAKE_THREAD;
41005003 2487 }
d129bceb 2488
41005003 2489 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2490 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2491 &intmask);
964f9ce2 2492
41005003
RK		 2493 if (intmask & SDHCI_INT_DATA_MASK)
2494 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2495
41005003
RK		 2496 if (intmask & SDHCI_INT_BUS_POWER)
2497 pr_err("%s: Card is consuming too much power!\n",
2498 mmc_hostname(host->mmc));
3192a28f 2499
781e989c
RK		 2500 if (intmask & SDHCI_INT_CARD_INT) {
2501 sdhci_enable_sdio_irq_nolock(host, false);
2502 host->thread_isr |= SDHCI_INT_CARD_INT;
2503 result = IRQ_WAKE_THREAD;
2504 }
f75979b7 2505
41005003
RK		 2506 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2507 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2508 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2509 SDHCI_INT_CARD_INT);
f75979b7 2510
41005003
RK		 2511 if (intmask) {
2512 unexpected |= intmask;
2513 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2514 }
d129bceb 2515
781e989c
RK		 2516 if (result == IRQ_NONE)
2517 result = IRQ_HANDLED;
d129bceb 2518
41005003 2519 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2520 } while (intmask && --max_loops);
d129bceb
PO		 2521out:
2522 spin_unlock(&host->lock);
2523
6379b237
AS		 2524 if (unexpected) {
2525 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2526 mmc_hostname(host->mmc), unexpected);
2527 sdhci_dumpregs(host);
2528 }
f75979b7 2529
d129bceb
PO		 2530 return result;
2531}
2532
781e989c
RK		 2533static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2534{
2535 struct sdhci_host *host = dev_id;
2536 unsigned long flags;
2537 u32 isr;
2538
2539 spin_lock_irqsave(&host->lock, flags);
2540 isr = host->thread_isr;
2541 host->thread_isr = 0;
2542 spin_unlock_irqrestore(&host->lock, flags);
2543
3560db8e
RK		 2544 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2545 sdhci_card_event(host->mmc);
2546 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2547 }
2548
781e989c
RK		 2549 if (isr & SDHCI_INT_CARD_INT) {
2550 sdio_run_irqs(host->mmc);
2551
2552 spin_lock_irqsave(&host->lock, flags);
2553 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2554 sdhci_enable_sdio_irq_nolock(host, true);
2555 spin_unlock_irqrestore(&host->lock, flags);
2556 }
2557
2558 return isr ? IRQ_HANDLED : IRQ_NONE;
2559}
2560
d129bceb
PO		 2561/*****************************************************************************\
2562 * *
2563 * Suspend/resume *
2564 * *
2565\*****************************************************************************/
2566
2567#ifdef CONFIG_PM
ad080d79
KL		 2568void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2569{
2570 u8 val;
2571 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2572 | SDHCI_WAKE_ON_INT;
2573
2574 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2575 val |= mask ;
2576 /* Avoid fake wake up */
2577 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2578 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2579 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2580}
2581EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2582
0b10f478 2583static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2584{
2585 u8 val;
2586 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2587 | SDHCI_WAKE_ON_INT;
2588
2589 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2590 val &= ~mask;
2591 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2592}
d129bceb 2593
29495aa0 2594int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2595{
7260cf5e
AV		 2596 sdhci_disable_card_detection(host);
2597
cf2b5eea 2598 /* Disable tuning since we are suspending */
973905fe 2599 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2600 del_timer_sync(&host->tuning_timer);
cf2b5eea 2601 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2602 }
2603
ad080d79 2604 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2605 host->ier = 0;
2606 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2607 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2608 free_irq(host->irq, host);
2609 } else {
2610 sdhci_enable_irq_wakeups(host);
2611 enable_irq_wake(host->irq);
2612 }
4ee14ec6 2613 return 0;
d129bceb
PO		 2614}
2615
b8c86fc5 2616EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2617
b8c86fc5
PO		 2618int sdhci_resume_host(struct sdhci_host *host)
2619{
4ee14ec6 2620 int ret = 0;
d129bceb 2621
a13abc7b 2622 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2623 if (host->ops->enable_dma)
2624 host->ops->enable_dma(host);
2625 }
d129bceb 2626
ad080d79 2627 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2628 ret = request_threaded_irq(host->irq, sdhci_irq,
2629 sdhci_thread_irq, IRQF_SHARED,
2630 mmc_hostname(host->mmc), host);
ad080d79
KL		 2631 if (ret)
2632 return ret;
2633 } else {
2634 sdhci_disable_irq_wakeups(host);
2635 disable_irq_wake(host->irq);
2636 }
d129bceb 2637
6308d290
AH		 2638 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2639 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2640 /* Card keeps power but host controller does not */
2641 sdhci_init(host, 0);
2642 host->pwr = 0;
2643 host->clock = 0;
2644 sdhci_do_set_ios(host, &host->mmc->ios);
2645 } else {
2646 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2647 mmiowb();
2648 }
b8c86fc5 2649
7260cf5e
AV		 2650 sdhci_enable_card_detection(host);
2651
cf2b5eea 2652 /* Set the re-tuning expiration flag */
973905fe 2653 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2654 host->flags |= SDHCI_NEEDS_RETUNING;
2655
2f4cbb3d 2656 return ret;
d129bceb
PO		 2657}
2658
b8c86fc5 2659EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2660#endif /* CONFIG_PM */
2661
66fd8ad5
AH		 2662#ifdef CONFIG_PM_RUNTIME
2663
2664static int sdhci_runtime_pm_get(struct sdhci_host *host)
2665{
2666 return pm_runtime_get_sync(host->mmc->parent);
2667}
2668
2669static int sdhci_runtime_pm_put(struct sdhci_host *host)
2670{
2671 pm_runtime_mark_last_busy(host->mmc->parent);
2672 return pm_runtime_put_autosuspend(host->mmc->parent);
2673}
2674
f0710a55
AH		 2675static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2676{
2677 if (host->runtime_suspended || host->bus_on)
2678 return;
2679 host->bus_on = true;
2680 pm_runtime_get_noresume(host->mmc->parent);
2681}
2682
2683static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2684{
2685 if (host->runtime_suspended || !host->bus_on)
2686 return;
2687 host->bus_on = false;
2688 pm_runtime_put_noidle(host->mmc->parent);
2689}
2690
66fd8ad5
AH		 2691int sdhci_runtime_suspend_host(struct sdhci_host *host)
2692{
2693 unsigned long flags;
66fd8ad5
AH		 2694
2695 /* Disable tuning since we are suspending */
973905fe 2696 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2697 del_timer_sync(&host->tuning_timer);
2698 host->flags &= ~SDHCI_NEEDS_RETUNING;
2699 }
2700
2701 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2702 host->ier &= SDHCI_INT_CARD_INT;
2703 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2704 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2705 spin_unlock_irqrestore(&host->lock, flags);
2706
781e989c 2707 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2708
2709 spin_lock_irqsave(&host->lock, flags);
2710 host->runtime_suspended = true;
2711 spin_unlock_irqrestore(&host->lock, flags);
2712
8a125bad 2713 return 0;
66fd8ad5
AH		 2714}
2715EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2716
2717int sdhci_runtime_resume_host(struct sdhci_host *host)
2718{
2719 unsigned long flags;
8a125bad 2720 int host_flags = host->flags;
66fd8ad5
AH		 2721
2722 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2723 if (host->ops->enable_dma)
2724 host->ops->enable_dma(host);
2725 }
2726
2727 sdhci_init(host, 0);
2728
2729 /* Force clock and power re-program */
2730 host->pwr = 0;
2731 host->clock = 0;
2732 sdhci_do_set_ios(host, &host->mmc->ios);
2733
2734 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2735 if ((host_flags & SDHCI_PV_ENABLED) &&
2736 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2737 spin_lock_irqsave(&host->lock, flags);
2738 sdhci_enable_preset_value(host, true);
2739 spin_unlock_irqrestore(&host->lock, flags);
2740 }
66fd8ad5
AH		 2741
2742 /* Set the re-tuning expiration flag */
973905fe 2743 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2744 host->flags |= SDHCI_NEEDS_RETUNING;
2745
2746 spin_lock_irqsave(&host->lock, flags);
2747
2748 host->runtime_suspended = false;
2749
2750 /* Enable SDIO IRQ */
ef104333 2751 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2752 sdhci_enable_sdio_irq_nolock(host, true);
2753
2754 /* Enable Card Detection */
2755 sdhci_enable_card_detection(host);
2756
2757 spin_unlock_irqrestore(&host->lock, flags);
2758
8a125bad 2759 return 0;
66fd8ad5
AH		 2760}
2761EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2762
2763#endif
2764
d129bceb
PO		 2765/*****************************************************************************\
2766 * *
b8c86fc5 2767 * Device allocation/registration *
d129bceb
PO		 2768 * *
2769\*****************************************************************************/
2770
b8c86fc5
PO		 2771struct sdhci_host *sdhci_alloc_host(struct device *dev,
2772 size_t priv_size)
d129bceb 2773{
d129bceb
PO		 2774 struct mmc_host *mmc;
2775 struct sdhci_host *host;
2776
b8c86fc5 2777 WARN_ON(dev == NULL);
d129bceb 2778
b8c86fc5 2779 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2780 if (!mmc)
b8c86fc5 2781 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2782
2783 host = mmc_priv(mmc);
2784 host->mmc = mmc;
2785
b8c86fc5
PO		 2786 return host;
2787}
8a4da143 2788
b8c86fc5 2789EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2790
b8c86fc5
PO		 2791int sdhci_add_host(struct sdhci_host *host)
2792{
2793 struct mmc_host *mmc;
bd6a8c30 2794 u32 caps[2] = {0, 0};
f2119df6
AN		 2795 u32 max_current_caps;
2796 unsigned int ocr_avail;
f5fa92e5 2797 unsigned int override_timeout_clk;
b8c86fc5 2798 int ret;
d129bceb 2799
b8c86fc5
PO		 2800 WARN_ON(host == NULL);
2801 if (host == NULL)
2802 return -EINVAL;
d129bceb 2803
b8c86fc5 2804 mmc = host->mmc;
d129bceb 2805
b8c86fc5
PO		 2806 if (debug_quirks)
2807 host->quirks = debug_quirks;
66fd8ad5
AH		 2808 if (debug_quirks2)
2809 host->quirks2 = debug_quirks2;
d129bceb 2810
f5fa92e5
AH		 2811 override_timeout_clk = host->timeout_clk;
2812
03231f9b 2813 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2814
4e4141a5 2815 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2816 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2817 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2818 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2819 pr_err("%s: Unknown controller version (%d). "
b69c9058 2820 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2821 host->version);
4a965505
PO		 2822 }
2823
f2119df6 2824 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2825 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2826
bd6a8c30
PR		 2827 if (host->version >= SDHCI_SPEC_300)
2828 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2829 host->caps1 :
2830 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2831
b8c86fc5 2832 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2833 host->flags |= SDHCI_USE_SDMA;
f2119df6 2834 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2835 DBG("Controller doesn't have SDMA capability\n");
67435274 2836 else
a13abc7b 2837 host->flags |= SDHCI_USE_SDMA;
d129bceb 2838
b8c86fc5 2839 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2840 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2841 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2842 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2843 }
2844
f2119df6
AN		 2845 if ((host->version >= SDHCI_SPEC_200) &&
2846 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2847 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2848
2849 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2850 (host->flags & SDHCI_USE_ADMA)) {
2851 DBG("Disabling ADMA as it is marked broken\n");
2852 host->flags &= ~SDHCI_USE_ADMA;
2853 }
2854
a13abc7b 2855 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2856 if (host->ops->enable_dma) {
2857 if (host->ops->enable_dma(host)) {
6606110d 2858 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2859 mmc_hostname(mmc));
a13abc7b
RR		 2860 host->flags &=
2861 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2862 }
d129bceb
PO		 2863 }
2864 }
2865
2134a922
PO		 2866 if (host->flags & SDHCI_USE_ADMA) {
2867 /*
76fe379a
AH		 2868 * The DMA descriptor table size is calculated as the maximum
2869 * number of segments times 2, to allow for an alignment
2870 * descriptor for each segment, plus 1 for a nop end descriptor,
2871 * all multipled by the descriptor size.
2134a922 2872 */
739d46dc
AH		 2873 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2874 SDHCI_ADMA2_32_DESC_SZ;
2875 host->align_buffer_sz = SDHCI_MAX_SEGS *
2876 SDHCI_ADMA2_32_ALIGN;
2877 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2878 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2879 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
4efaa6fb 2880 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2881 host->adma_table_sz,
4efaa6fb
AH		 2882 &host->adma_addr,
2883 GFP_KERNEL);
76fe379a 2884 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 2885 if (!host->adma_table || !host->align_buffer) {
76fe379a 2886 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2887 host->adma_table, host->adma_addr);
2134a922 2888 kfree(host->align_buffer);
6606110d 2889 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2890 mmc_hostname(mmc));
2891 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2892 host->adma_table = NULL;
d1e49f77 2893 host->align_buffer = NULL;
76fe379a 2894 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 2895 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2896 mmc_hostname(mmc));
d1e49f77 2897 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 2898 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2899 host->adma_table, host->adma_addr);
d1e49f77 2900 kfree(host->align_buffer);
4efaa6fb 2901 host->adma_table = NULL;
d1e49f77 2902 host->align_buffer = NULL;
2134a922
PO		 2903 }
2904 }
2905
7659150c
PO		 2906 /*
2907 * If we use DMA, then it's up to the caller to set the DMA
2908 * mask, but PIO does not need the hw shim so we set a new
2909 * mask here in that case.
2910 */
a13abc7b 2911 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2912 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2913 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2914 }
d129bceb 2915
c4687d5f 2916 if (host->version >= SDHCI_SPEC_300)
f2119df6 2917 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2918 >> SDHCI_CLOCK_BASE_SHIFT;
2919 else
f2119df6 2920 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2921 >> SDHCI_CLOCK_BASE_SHIFT;
2922
4240ff0a 2923 host->max_clk *= 1000000;
f27f47ef
AV		 2924 if (host->max_clk == 0 || host->quirks &
2925 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2926 if (!host->ops->get_max_clock) {
a3c76eb9 2927 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2928 "frequency.\n", mmc_hostname(mmc));
2929 return -ENODEV;
2930 }
2931 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2932 }
d129bceb 2933
c3ed3877
AN		 2934 /*
2935 * In case of Host Controller v3.00, find out whether clock
2936 * multiplier is supported.
2937 */
2938 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2939 SDHCI_CLOCK_MUL_SHIFT;
2940
2941 /*
2942 * In case the value in Clock Multiplier is 0, then programmable
2943 * clock mode is not supported, otherwise the actual clock
2944 * multiplier is one more than the value of Clock Multiplier
2945 * in the Capabilities Register.
2946 */
2947 if (host->clk_mul)
2948 host->clk_mul += 1;
2949
d129bceb
PO		 2950 /*
2951 * Set host parameters.
2952 */
2953 mmc->ops = &sdhci_ops;
c3ed3877 2954 mmc->f_max = host->max_clk;
ce5f036b 2955 if (host->ops->get_min_clock)
a9e58f25 2956 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2957 else if (host->version >= SDHCI_SPEC_300) {
2958 if (host->clk_mul) {
2959 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2960 mmc->f_max = host->max_clk * host->clk_mul;
2961 } else
2962 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2963 } else
0397526d 2964 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2965
28aab053
AD		 2966 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2967 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2968 SDHCI_TIMEOUT_CLK_SHIFT;
2969 if (host->timeout_clk == 0) {
2970 if (host->ops->get_timeout_clock) {
2971 host->timeout_clk =
2972 host->ops->get_timeout_clock(host);
2973 } else {
2974 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2975 mmc_hostname(mmc));
2976 return -ENODEV;
2977 }
272308ca 2978 }
272308ca 2979
28aab053
AD		 2980 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2981 host->timeout_clk *= 1000;
272308ca 2982
28aab053 2983 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 2984 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 2985 mmc->max_busy_timeout /= host->timeout_clk;
2986 }
58d1246d 2987
f5fa92e5
AH		 2988 if (override_timeout_clk)
2989 host->timeout_clk = override_timeout_clk;
2990
e89d456f 2991 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2992 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2993
2994 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2995 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2996
8edf6371 2997 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2998 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2999 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 3000 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 3001 host->flags |= SDHCI_AUTO_CMD23;
3002 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3003 } else {
3004 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3005 }
3006
15ec4461
PR		 3007 /*
3008 * A controller may support 8-bit width, but the board itself
3009 * might not have the pins brought out. Boards that support
3010 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3011 * their platform code before calling sdhci_add_host(), and we
3012 * won't assume 8-bit width for hosts without that CAP.
3013 */
5fe23c7f 3014 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3015 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3016
63ef5d8c
JH		 3017 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3018 mmc->caps &= ~MMC_CAP_CMD23;
3019
f2119df6 3020 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3021 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3022
176d1ed4 3023 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 3024 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 3025 mmc->caps |= MMC_CAP_NEEDS_POLL;
3026
3a48edc4
TK		 3027 /* If there are external regulators, get them */
3028 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3029 return -EPROBE_DEFER;
3030
6231f3de 3031 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3032 if (!IS_ERR(mmc->supply.vqmmc)) {
3033 ret = regulator_enable(mmc->supply.vqmmc);
3034 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3035 1950000))
8363c374
KL		 3036 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3037 SDHCI_SUPPORT_SDR50 |
3038 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3039 if (ret) {
3040 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3041 mmc_hostname(mmc), ret);
3a48edc4 3042 mmc->supply.vqmmc = NULL;
a3361aba 3043 }
8363c374 3044 }
6231f3de 3045
6a66180a
DD		 3046 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3047 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3048 SDHCI_SUPPORT_DDR50);
3049
4188bba0
AC		 3050 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3051 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3052 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3053 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3054
3055 /* SDR104 supports also implies SDR50 support */
156e14b1 3056 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3057 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3058 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3059 * field can be promoted to support HS200.
3060 */
adc82855 3061 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
13868bf2 3062 mmc->caps2 |= MMC_CAP2_HS200;
adc82855
CD		 3063 if (IS_ERR(mmc->supply.vqmmc) ||
3064 !regulator_is_supported_voltage
3065 (mmc->supply.vqmmc, 1100000, 1300000))
3066 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3067 }
156e14b1 3068 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3069 mmc->caps |= MMC_CAP_UHS_SDR50;
3070
9107ebbf
MC		 3071 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3072 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3073 mmc->caps |= MMC_CAP_UHS_DDR50;
3074
069c9f14 3075 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3076 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3077 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3078
156e14b1 3079 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3080 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3081 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3082
d6d50a15
AN		 3083 /* Driver Type(s) (A, C, D) supported by the host */
3084 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3085 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3086 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3087 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3088 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3089 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3090
cf2b5eea
AN		 3091 /* Initial value for re-tuning timer count */
3092 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3093 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3094
3095 /*
3096 * In case Re-tuning Timer is not disabled, the actual value of
3097 * re-tuning timer will be 2 ^ (n - 1).
3098 */
3099 if (host->tuning_count)
3100 host->tuning_count = 1 << (host->tuning_count - 1);
3101
3102 /* Re-tuning mode supported by the Host Controller */
3103 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3104 SDHCI_RETUNING_MODE_SHIFT;
3105
8f230f45 3106 ocr_avail = 0;
bad37e1a 3107
f2119df6
AN		 3108 /*
3109 * According to SD Host Controller spec v3.00, if the Host System
3110 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3111 * the value is meaningful only if Voltage Support in the Capabilities
3112 * register is set. The actual current value is 4 times the register
3113 * value.
3114 */
3115 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3116 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3117 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3118 if (curr > 0) {
3119
3120 /* convert to SDHCI_MAX_CURRENT format */
3121 curr = curr/1000; /* convert to mA */
3122 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3123
3124 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3125 max_current_caps =
3126 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3127 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3128 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3129 }
3130 }
f2119df6
AN		 3131
3132 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3133 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3134
55c4665e 3135 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3136 SDHCI_MAX_CURRENT_330_MASK) >>
3137 SDHCI_MAX_CURRENT_330_SHIFT) *
3138 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3139 }
3140 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3141 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3142
55c4665e 3143 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3144 SDHCI_MAX_CURRENT_300_MASK) >>
3145 SDHCI_MAX_CURRENT_300_SHIFT) *
3146 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3147 }
3148 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3149 ocr_avail |= MMC_VDD_165_195;
3150
55c4665e 3151 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3152 SDHCI_MAX_CURRENT_180_MASK) >>
3153 SDHCI_MAX_CURRENT_180_SHIFT) *
3154 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3155 }
3156
52221610 3157 /* If OCR set by external regulators, use it instead */
3a48edc4 3158 if (mmc->ocr_avail)
52221610 3159 ocr_avail = mmc->ocr_avail;
3a48edc4 3160
c0b887b6 3161 if (host->ocr_mask)
3a48edc4 3162 ocr_avail &= host->ocr_mask;
c0b887b6 3163
8f230f45
TI		 3164 mmc->ocr_avail = ocr_avail;
3165 mmc->ocr_avail_sdio = ocr_avail;
3166 if (host->ocr_avail_sdio)
3167 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3168 mmc->ocr_avail_sd = ocr_avail;
3169 if (host->ocr_avail_sd)
3170 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3171 else /* normal SD controllers don't support 1.8V */
3172 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3173 mmc->ocr_avail_mmc = ocr_avail;
3174 if (host->ocr_avail_mmc)
3175 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3176
3177 if (mmc->ocr_avail == 0) {
a3c76eb9 3178 pr_err("%s: Hardware doesn't report any "
b69c9058 3179 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3180 return -ENODEV;
146ad66e
PO		 3181 }
3182
d129bceb
PO		 3183 spin_lock_init(&host->lock);
3184
3185 /*
2134a922
PO		 3186 * Maximum number of segments. Depends on if the hardware
3187 * can do scatter/gather or not.
d129bceb 3188 */
2134a922 3189 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3190 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3191 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3192 mmc->max_segs = 1;
2134a922 3193 else /* PIO */
4fb213f8 3194 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3195
3196 /*
bab76961 3197 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3198 * size (512KiB).
d129bceb 3199 */
55db890a 3200 mmc->max_req_size = 524288;
d129bceb
PO		 3201
3202 /*
3203 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3204 * of bytes. When doing hardware scatter/gather, each entry cannot
3205 * be larger than 64 KiB though.
d129bceb 3206 */
30652aa3
OJ		 3207 if (host->flags & SDHCI_USE_ADMA) {
3208 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3209 mmc->max_seg_size = 65535;
3210 else
3211 mmc->max_seg_size = 65536;
3212 } else {
2134a922 3213 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3214 }
d129bceb 3215
fe4a3c7a
PO		 3216 /*
3217 * Maximum block size. This varies from controller to controller and
3218 * is specified in the capabilities register.
3219 */
0633f654
AV		 3220 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3221 mmc->max_blk_size = 2;
3222 } else {
f2119df6 3223 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3224 SDHCI_MAX_BLOCK_SHIFT;
3225 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3226 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3227 mmc_hostname(mmc));
0633f654
AV		 3228 mmc->max_blk_size = 0;
3229 }
3230 }
3231
3232 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3233
55db890a
PO		 3234 /*
3235 * Maximum block count.
3236 */
1388eefd 3237 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3238
d129bceb
PO		 3239 /*
3240 * Init tasklets.
3241 */
d129bceb
PO		 3242 tasklet_init(&host->finish_tasklet,
3243 sdhci_tasklet_finish, (unsigned long)host);
3244
e4cad1b5 3245 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3246
cf2b5eea 3247 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3248 init_waitqueue_head(&host->buf_ready_int);
3249
cf2b5eea
AN		 3250 /* Initialize re-tuning timer */
3251 init_timer(&host->tuning_timer);
3252 host->tuning_timer.data = (unsigned long)host;
3253 host->tuning_timer.function = sdhci_tuning_timer;
3254 }
3255
2af502ca
SG		 3256 sdhci_init(host, 0);
3257
781e989c
RK		 3258 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3259 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3260 if (ret) {
3261 pr_err("%s: Failed to request IRQ %d: %d\n",
3262 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3263 goto untasklet;
0fc81ee3 3264 }
d129bceb 3265
d129bceb
PO		 3266#ifdef CONFIG_MMC_DEBUG
3267 sdhci_dumpregs(host);
3268#endif
3269
f9134319 3270#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3271 snprintf(host->led_name, sizeof(host->led_name),
3272 "%s::", mmc_hostname(mmc));
3273 host->led.name = host->led_name;
2f730fec
PO		 3274 host->led.brightness = LED_OFF;
3275 host->led.default_trigger = mmc_hostname(mmc);
3276 host->led.brightness_set = sdhci_led_control;
3277
b8c86fc5 3278 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3279 if (ret) {
3280 pr_err("%s: Failed to register LED device: %d\n",
3281 mmc_hostname(mmc), ret);
2f730fec 3282 goto reset;
0fc81ee3 3283 }
2f730fec
PO		 3284#endif
3285
5f25a66f
PO		 3286 mmiowb();
3287
d129bceb
PO		 3288 mmc_add_host(mmc);
3289
a3c76eb9 3290 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3291 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3292 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3293 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3294
7260cf5e
AV		 3295 sdhci_enable_card_detection(host);
3296
d129bceb
PO		 3297 return 0;
3298
f9134319 3299#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3300reset:
03231f9b 3301 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3302 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3303 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3304 free_irq(host->irq, host);
3305#endif
8ef1a143 3306untasklet:
d129bceb 3307 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3308
3309 return ret;
3310}
3311
b8c86fc5 3312EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3313
1e72859e 3314void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3315{
3a48edc4 3316 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3317 unsigned long flags;
3318
3319 if (dead) {
3320 spin_lock_irqsave(&host->lock, flags);
3321
3322 host->flags |= SDHCI_DEVICE_DEAD;
3323
3324 if (host->mrq) {
a3c76eb9 3325 pr_err("%s: Controller removed during "
4e743f1f 3326 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3327
3328 host->mrq->cmd->error = -ENOMEDIUM;
3329 tasklet_schedule(&host->finish_tasklet);
3330 }
3331
3332 spin_unlock_irqrestore(&host->lock, flags);
3333 }
3334
7260cf5e
AV		 3335 sdhci_disable_card_detection(host);
3336
4e743f1f 3337 mmc_remove_host(mmc);
d129bceb 3338
f9134319 3339#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3340 led_classdev_unregister(&host->led);
3341#endif
3342
1e72859e 3343 if (!dead)
03231f9b 3344 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3345
b537f94c
RK		 3346 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3347 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3348 free_irq(host->irq, host);
3349
3350 del_timer_sync(&host->timer);
3351
d129bceb 3352 tasklet_kill(&host->finish_tasklet);
2134a922 3353
3a48edc4
TK		 3354 if (!IS_ERR(mmc->supply.vqmmc))
3355 regulator_disable(mmc->supply.vqmmc);
6231f3de 3356
4efaa6fb 3357 if (host->adma_table)
76fe379a 3358 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3359 host->adma_table, host->adma_addr);
2134a922
PO		 3360 kfree(host->align_buffer);
3361
4efaa6fb 3362 host->adma_table = NULL;
2134a922 3363 host->align_buffer = NULL;
d129bceb
PO		 3364}
3365
b8c86fc5 3366EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3367
b8c86fc5 3368void sdhci_free_host(struct sdhci_host *host)
d129bceb 3369{
b8c86fc5 3370 mmc_free_host(host->mmc);
d129bceb
PO		 3371}
3372
b8c86fc5 3373EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3374
3375/*****************************************************************************\
3376 * *
3377 * Driver init/exit *
3378 * *
3379\*****************************************************************************/
3380
3381static int __init sdhci_drv_init(void)
3382{
a3c76eb9 3383 pr_info(DRIVER_NAME
52fbf9c9 3384 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3385 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3386
b8c86fc5 3387 return 0;
d129bceb
PO		 3388}
3389
3390static void __exit sdhci_drv_exit(void)
3391{
d129bceb
PO		 3392}
3393
3394module_init(sdhci_drv_init);
3395module_exit(sdhci_drv_exit);
3396
df673b22 3397module_param(debug_quirks, uint, 0444);
66fd8ad5 3398module_param(debug_quirks2, uint, 0444);
67435274 3399
32710e8f 3400MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3401MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3402MODULE_LICENSE("GPL");
67435274 3403
df673b22 3404MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3405MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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