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mmc: dw_mmc: add quirk for broken data transfer over scheme
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
348487cb
HC		 56static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data,
58 struct sdhci_host_next *next);
04e079cf 59static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 60
162d6f98 61#ifdef CONFIG_PM
66fd8ad5
AH		 62static int sdhci_runtime_pm_get(struct sdhci_host *host);
63static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 64static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
65static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 66#else
67static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
68{
69 return 0;
70}
71static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
72{
73 return 0;
74}
f0710a55
AH		 75static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76{
77}
78static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79{
80}
66fd8ad5
AH		 81#endif
82
d129bceb
PO		 83static void sdhci_dumpregs(struct sdhci_host *host)
84{
a3c76eb9 85 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 86 mmc_hostname(host->mmc));
d129bceb 87
a3c76eb9 88 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readl(host, SDHCI_DMA_ADDRESS),
90 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readw(host, SDHCI_BLOCK_SIZE),
93 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_ARGUMENT),
96 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readl(host, SDHCI_PRESENT_STATE),
99 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_POWER_CONTROL),
102 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
105 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
108 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 109 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readl(host, SDHCI_INT_ENABLE),
111 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 112 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 113 sdhci_readw(host, SDHCI_ACMD12_ERR),
114 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 116 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 117 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 119 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 120 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 121 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 122 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 123
e57a5f61
AH		 124 if (host->flags & SDHCI_USE_ADMA) {
125 if (host->flags & SDHCI_USE_64_BIT_DMA)
126 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
127 readl(host->ioaddr + SDHCI_ADMA_ERROR),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 else
131 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_ADMA_ERROR),
133 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
134 }
be3f4ae0 135
a3c76eb9 136 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 137}
138
139/*****************************************************************************\
140 * *
141 * Low level functions *
142 * *
143\*****************************************************************************/
144
7260cf5e
AV		 145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
5b4f1f6c 147 u32 present;
7260cf5e 148
c79396c1 149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 150 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 151 return;
152
5b4f1f6c
RK		 153 if (enable) {
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
d25928d1 156
5b4f1f6c
RK		 157 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
158 SDHCI_INT_CARD_INSERT;
159 } else {
160 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
161 }
b537f94c
RK		 162
163 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
164 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 165}
166
167static void sdhci_enable_card_detection(struct sdhci_host *host)
168{
169 sdhci_set_card_detection(host, true);
170}
171
172static void sdhci_disable_card_detection(struct sdhci_host *host)
173{
174 sdhci_set_card_detection(host, false);
175}
176
03231f9b 177void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 178{
e16514d8 179 unsigned long timeout;
393c1a34 180
4e4141a5 181 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 182
f0710a55 183 if (mask & SDHCI_RESET_ALL) {
d129bceb 184 host->clock = 0;
f0710a55
AH		 185 /* Reset-all turns off SD Bus Power */
186 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
187 sdhci_runtime_pm_bus_off(host);
188 }
d129bceb 189
e16514d8
PO		 190 /* Wait max 100 ms */
191 timeout = 100;
192
193 /* hw clears the bit when it's done */
4e4141a5 194 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 195 if (timeout == 0) {
a3c76eb9 196 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 197 mmc_hostname(host->mmc), (int)mask);
198 sdhci_dumpregs(host);
199 return;
200 }
201 timeout--;
202 mdelay(1);
d129bceb 203 }
03231f9b
RK		 204}
205EXPORT_SYMBOL_GPL(sdhci_reset);
206
207static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208{
209 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 210 if (!sdhci_do_get_cd(host))
03231f9b
RK		 211 return;
212 }
063a9dbb 213
03231f9b 214 host->ops->reset(host, mask);
393c1a34 215
da91a8f9
RK		 216 if (mask & SDHCI_RESET_ALL) {
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if (host->ops->enable_dma)
219 host->ops->enable_dma(host);
220 }
221
222 /* Resetting the controller clears many */
223 host->preset_enabled = false;
3abc1e80 224 }
d129bceb
PO		 225}
226
2f4cbb3d
NP		 227static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
228
229static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 230{
2f4cbb3d 231 if (soft)
03231f9b 232 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 233 else
03231f9b 234 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 235
b537f94c
RK		 236 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
238 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
239 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
240 SDHCI_INT_RESPONSE;
241
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 244
245 if (soft) {
246 /* force clock reconfiguration */
247 host->clock = 0;
248 sdhci_set_ios(host->mmc, &host->mmc->ios);
249 }
7260cf5e 250}
d129bceb 251
7260cf5e
AV		 252static void sdhci_reinit(struct sdhci_host *host)
253{
2f4cbb3d 254 sdhci_init(host, 0);
7260cf5e 255 sdhci_enable_card_detection(host);
d129bceb
PO		 256}
257
258static void sdhci_activate_led(struct sdhci_host *host)
259{
260 u8 ctrl;
261
4e4141a5 262 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 263 ctrl |= SDHCI_CTRL_LED;
4e4141a5 264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 265}
266
267static void sdhci_deactivate_led(struct sdhci_host *host)
268{
269 u8 ctrl;
270
4e4141a5 271 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 272 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 274}
275
f9134319 276#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 277static void sdhci_led_control(struct led_classdev *led,
278 enum led_brightness brightness)
279{
280 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
281 unsigned long flags;
282
283 spin_lock_irqsave(&host->lock, flags);
284
66fd8ad5
AH		 285 if (host->runtime_suspended)
286 goto out;
287
2f730fec
PO		 288 if (brightness == LED_OFF)
289 sdhci_deactivate_led(host);
290 else
291 sdhci_activate_led(host);
66fd8ad5 292out:
2f730fec
PO		 293 spin_unlock_irqrestore(&host->lock, flags);
294}
295#endif
296
d129bceb
PO		 297/*****************************************************************************\
298 * *
299 * Core functions *
300 * *
301\*****************************************************************************/
302
a406f5a3 303static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 304{
7659150c
PO		 305 unsigned long flags;
306 size_t blksize, len, chunk;
7244b85b 307 u32 uninitialized_var(scratch);
7659150c 308 u8 *buf;
d129bceb 309
a406f5a3 310 DBG("PIO reading\n");
d129bceb 311
a406f5a3 312 blksize = host->data->blksz;
7659150c 313 chunk = 0;
d129bceb 314
7659150c 315 local_irq_save(flags);
d129bceb 316
a406f5a3 317 while (blksize) {
bf3a35ac 318 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 319
7659150c 320 len = min(host->sg_miter.length, blksize);
d129bceb 321
7659150c
PO		 322 blksize -= len;
323 host->sg_miter.consumed = len;
14d836e7 324
7659150c 325 buf = host->sg_miter.addr;
d129bceb 326
7659150c
PO		 327 while (len) {
328 if (chunk == 0) {
4e4141a5 329 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 330 chunk = 4;
a406f5a3 331 }
7659150c
PO		 332
333 *buf = scratch & 0xFF;
334
335 buf++;
336 scratch >>= 8;
337 chunk--;
338 len--;
d129bceb 339 }
a406f5a3 340 }
7659150c
PO		 341
342 sg_miter_stop(&host->sg_miter);
343
344 local_irq_restore(flags);
a406f5a3 345}
d129bceb 346
a406f5a3
PO		 347static void sdhci_write_block_pio(struct sdhci_host *host)
348{
7659150c
PO		 349 unsigned long flags;
350 size_t blksize, len, chunk;
351 u32 scratch;
352 u8 *buf;
d129bceb 353
a406f5a3
PO		 354 DBG("PIO writing\n");
355
356 blksize = host->data->blksz;
7659150c
PO		 357 chunk = 0;
358 scratch = 0;
d129bceb 359
7659150c 360 local_irq_save(flags);
d129bceb 361
a406f5a3 362 while (blksize) {
bf3a35ac 363 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 364
7659150c
PO		 365 len = min(host->sg_miter.length, blksize);
366
367 blksize -= len;
368 host->sg_miter.consumed = len;
369
370 buf = host->sg_miter.addr;
d129bceb 371
7659150c
PO		 372 while (len) {
373 scratch |= (u32)*buf << (chunk * 8);
374
375 buf++;
376 chunk++;
377 len--;
378
379 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 380 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 381 chunk = 0;
382 scratch = 0;
d129bceb 383 }
d129bceb
PO		 384 }
385 }
7659150c
PO		 386
387 sg_miter_stop(&host->sg_miter);
388
389 local_irq_restore(flags);
a406f5a3
PO		 390}
391
392static void sdhci_transfer_pio(struct sdhci_host *host)
393{
394 u32 mask;
395
396 BUG_ON(!host->data);
397
7659150c 398 if (host->blocks == 0)
a406f5a3
PO		 399 return;
400
401 if (host->data->flags & MMC_DATA_READ)
402 mask = SDHCI_DATA_AVAILABLE;
403 else
404 mask = SDHCI_SPACE_AVAILABLE;
405
4a3cba32
PO		 406 /*
407 * Some controllers (JMicron JMB38x) mess up the buffer bits
408 * for transfers < 4 bytes. As long as it is just one block,
409 * we can ignore the bits.
410 */
411 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
412 (host->data->blocks == 1))
413 mask = ~0;
414
4e4141a5 415 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 416 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
417 udelay(100);
418
a406f5a3
PO		 419 if (host->data->flags & MMC_DATA_READ)
420 sdhci_read_block_pio(host);
421 else
422 sdhci_write_block_pio(host);
d129bceb 423
7659150c
PO		 424 host->blocks--;
425 if (host->blocks == 0)
a406f5a3 426 break;
a406f5a3 427 }
d129bceb 428
a406f5a3 429 DBG("PIO transfer complete.\n");
d129bceb
PO		 430}
431
2134a922
PO		 432static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
433{
434 local_irq_save(*flags);
482fce99 435 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 436}
437
438static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
439{
482fce99 440 kunmap_atomic(buffer);
2134a922
PO		 441 local_irq_restore(*flags);
442}
443
e57a5f61
AH		 444static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
445 dma_addr_t addr, int len, unsigned cmd)
118cd17d 446{
e57a5f61 447 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 448
e57a5f61 449 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 450 dma_desc->cmd = cpu_to_le16(cmd);
451 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 452 dma_desc->addr_lo = cpu_to_le32((u32)addr);
453
454 if (host->flags & SDHCI_USE_64_BIT_DMA)
455 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 456}
457
b5ffa674
AH		 458static void sdhci_adma_mark_end(void *desc)
459{
e57a5f61 460 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 461
e57a5f61 462 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 463 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 464}
465
8f1934ce 466static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 467 struct mmc_data *data)
468{
469 int direction;
470
1c3d5f6d
AH		 471 void *desc;
472 void *align;
2134a922
PO		 473 dma_addr_t addr;
474 dma_addr_t align_addr;
475 int len, offset;
476
477 struct scatterlist *sg;
478 int i;
479 char *buffer;
480 unsigned long flags;
481
482 /*
483 * The spec does not specify endianness of descriptor table.
484 * We currently guess that it is LE.
485 */
486
487 if (data->flags & MMC_DATA_READ)
488 direction = DMA_FROM_DEVICE;
489 else
490 direction = DMA_TO_DEVICE;
491
2134a922 492 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 493 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 494 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 495 goto fail;
76fe379a 496 BUG_ON(host->align_addr & host->align_mask);
2134a922 497
348487cb
HC		 498 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
499 if (host->sg_count < 0)
8f1934ce 500 goto unmap_align;
2134a922 501
4efaa6fb 502 desc = host->adma_table;
2134a922
PO		 503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
76fe379a
AH		 518 offset = (host->align_sz - (addr & host->align_mask)) &
519 host->align_mask;
2134a922
PO		 520 if (offset) {
521 if (data->flags & MMC_DATA_WRITE) {
522 buffer = sdhci_kmap_atomic(sg, &flags);
523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
525 }
526
118cd17d 527 /* tran, valid */
e57a5f61 528 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 529 ADMA2_TRAN_VALID);
2134a922
PO		 530
531 BUG_ON(offset > 65536);
532
76fe379a
AH		 533 align += host->align_sz;
534 align_addr += host->align_sz;
2134a922 535
76fe379a 536 desc += host->desc_sz;
2134a922
PO		 537
538 addr += offset;
539 len -= offset;
540 }
541
2134a922
PO		 542 BUG_ON(len > 65536);
543
118cd17d 544 /* tran, valid */
e57a5f61 545 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 546 desc += host->desc_sz;
2134a922
PO		 547
548 /*
549 * If this triggers then we have a calculation bug
550 * somewhere. :/
551 */
76fe379a 552 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 553 }
554
70764a90
TA		 555 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
556 /*
557 * Mark the last descriptor as the terminating descriptor
558 */
4efaa6fb 559 if (desc != host->adma_table) {
76fe379a 560 desc -= host->desc_sz;
b5ffa674 561 sdhci_adma_mark_end(desc);
70764a90
TA		 562 }
563 } else {
564 /*
565 * Add a terminating entry.
566 */
2134a922 567
70764a90 568 /* nop, end, valid */
e57a5f61 569 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 570 }
2134a922
PO		 571
572 /*
573 * Resync align buffer as we might have changed it.
574 */
575 if (data->flags & MMC_DATA_WRITE) {
576 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 577 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 578 }
579
8f1934ce
PO		 580 return 0;
581
8f1934ce
PO		 582unmap_align:
583 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 584 host->align_buffer_sz, direction);
8f1934ce
PO		 585fail:
586 return -EINVAL;
2134a922
PO		 587}
588
589static void sdhci_adma_table_post(struct sdhci_host *host,
590 struct mmc_data *data)
591{
592 int direction;
593
594 struct scatterlist *sg;
595 int i, size;
1c3d5f6d 596 void *align;
2134a922
PO		 597 char *buffer;
598 unsigned long flags;
de0b65a7 599 bool has_unaligned;
2134a922
PO		 600
601 if (data->flags & MMC_DATA_READ)
602 direction = DMA_FROM_DEVICE;
603 else
604 direction = DMA_TO_DEVICE;
605
2134a922 606 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 607 host->align_buffer_sz, direction);
2134a922 608
de0b65a7
RK		 609 /* Do a quick scan of the SG list for any unaligned mappings */
610 has_unaligned = false;
611 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 612 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 613 has_unaligned = true;
614 break;
615 }
616
617 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 618 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
619 data->sg_len, direction);
620
621 align = host->align_buffer;
622
623 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 624 if (sg_dma_address(sg) & host->align_mask) {
625 size = host->align_sz -
626 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 627
628 buffer = sdhci_kmap_atomic(sg, &flags);
629 memcpy(buffer, align, size);
630 sdhci_kunmap_atomic(buffer, &flags);
631
76fe379a 632 align += host->align_sz;
2134a922
PO		 633 }
634 }
635 }
636
348487cb
HC		 637 if (!data->host_cookie)
638 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
639 data->sg_len, direction);
2134a922
PO		 640}
641
a3c7778f 642static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 643{
1c8cde92 644 u8 count;
a3c7778f 645 struct mmc_data *data = cmd->data;
1c8cde92 646 unsigned target_timeout, current_timeout;
d129bceb 647
ee53ab5d
PO		 648 /*
649 * If the host controller provides us with an incorrect timeout
650 * value, just skip the check and use 0xE. The hardware may take
651 * longer to time out, but that's much better than having a too-short
652 * timeout value.
653 */
11a2f1b7 654 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 655 return 0xE;
e538fbe8 656
a3c7778f 657 /* Unspecified timeout, assume max */
1d4d7744 658 if (!data && !cmd->busy_timeout)
a3c7778f 659 return 0xE;
d129bceb 660
a3c7778f
AW		 661 /* timeout in us */
662 if (!data)
1d4d7744 663 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 664 else {
665 target_timeout = data->timeout_ns / 1000;
666 if (host->clock)
667 target_timeout += data->timeout_clks / host->clock;
668 }
81b39802 669
1c8cde92
PO		 670 /*
671 * Figure out needed cycles.
672 * We do this in steps in order to fit inside a 32 bit int.
673 * The first step is the minimum timeout, which will have a
674 * minimum resolution of 6 bits:
675 * (1) 2^13*1000 > 2^22,
676 * (2) host->timeout_clk < 2^16
677 * =>
678 * (1) / (2) > 2^6
679 */
680 count = 0;
681 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
682 while (current_timeout < target_timeout) {
683 count++;
684 current_timeout <<= 1;
685 if (count >= 0xF)
686 break;
687 }
688
689 if (count >= 0xF) {
09eeff52
CB		 690 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
691 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 692 count = 0xE;
693 }
694
ee53ab5d
PO		 695 return count;
696}
697
6aa943ab
AV		 698static void sdhci_set_transfer_irqs(struct sdhci_host *host)
699{
700 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
701 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
702
703 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 704 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 705 else
b537f94c
RK		 706 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
707
708 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
709 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 710}
711
b45e668a 712static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 713{
714 u8 count;
b45e668a
AD		 715
716 if (host->ops->set_timeout) {
717 host->ops->set_timeout(host, cmd);
718 } else {
719 count = sdhci_calc_timeout(host, cmd);
720 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
721 }
722}
723
724static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
725{
2134a922 726 u8 ctrl;
a3c7778f 727 struct mmc_data *data = cmd->data;
8f1934ce 728 int ret;
ee53ab5d
PO		 729
730 WARN_ON(host->data);
731
b45e668a
AD		 732 if (data || (cmd->flags & MMC_RSP_BUSY))
733 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 734
735 if (!data)
ee53ab5d
PO		 736 return;
737
738 /* Sanity checks */
739 BUG_ON(data->blksz * data->blocks > 524288);
740 BUG_ON(data->blksz > host->mmc->max_blk_size);
741 BUG_ON(data->blocks > 65535);
742
743 host->data = data;
744 host->data_early = 0;
f6a03cbf 745 host->data->bytes_xfered = 0;
ee53ab5d 746
a13abc7b 747 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 748 host->flags |= SDHCI_REQ_USE_DMA;
749
2134a922
PO		 750 /*
751 * FIXME: This doesn't account for merging when mapping the
752 * scatterlist.
753 */
754 if (host->flags & SDHCI_REQ_USE_DMA) {
755 int broken, i;
756 struct scatterlist *sg;
757
758 broken = 0;
759 if (host->flags & SDHCI_USE_ADMA) {
760 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
761 broken = 1;
762 } else {
763 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
764 broken = 1;
765 }
766
767 if (unlikely(broken)) {
768 for_each_sg(data->sg, sg, data->sg_len, i) {
769 if (sg->length & 0x3) {
770 DBG("Reverting to PIO because of "
771 "transfer size (%d)\n",
772 sg->length);
773 host->flags &= ~SDHCI_REQ_USE_DMA;
774 break;
775 }
776 }
777 }
c9fddbc4
PO		 778 }
779
780 /*
781 * The assumption here being that alignment is the same after
782 * translation to device address space.
783 */
2134a922
PO		 784 if (host->flags & SDHCI_REQ_USE_DMA) {
785 int broken, i;
786 struct scatterlist *sg;
787
788 broken = 0;
789 if (host->flags & SDHCI_USE_ADMA) {
790 /*
791 * As we use 3 byte chunks to work around
792 * alignment problems, we need to check this
793 * quirk.
794 */
795 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
796 broken = 1;
797 } else {
798 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
799 broken = 1;
800 }
801
802 if (unlikely(broken)) {
803 for_each_sg(data->sg, sg, data->sg_len, i) {
804 if (sg->offset & 0x3) {
805 DBG("Reverting to PIO because of "
806 "bad alignment\n");
807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 }
811 }
812 }
813
8f1934ce
PO		 814 if (host->flags & SDHCI_REQ_USE_DMA) {
815 if (host->flags & SDHCI_USE_ADMA) {
816 ret = sdhci_adma_table_pre(host, data);
817 if (ret) {
818 /*
819 * This only happens when someone fed
820 * us an invalid request.
821 */
822 WARN_ON(1);
ebd6d357 823 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 824 } else {
4e4141a5
AV		 825 sdhci_writel(host, host->adma_addr,
826 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 827 if (host->flags & SDHCI_USE_64_BIT_DMA)
828 sdhci_writel(host,
829 (u64)host->adma_addr >> 32,
830 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 831 }
832 } else {
c8b3e02e 833 int sg_cnt;
8f1934ce 834
348487cb 835 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
62a7f368 836 if (sg_cnt <= 0) {
8f1934ce
PO		 837 /*
838 * This only happens when someone fed
839 * us an invalid request.
840 */
841 WARN_ON(1);
ebd6d357 842 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 843 } else {
719a61b4 844 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 845 sdhci_writel(host, sg_dma_address(data->sg),
846 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 847 }
848 }
849 }
850
2134a922
PO		 851 /*
852 * Always adjust the DMA selection as some controllers
853 * (e.g. JMicron) can't do PIO properly when the selection
854 * is ADMA.
855 */
856 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 857 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 858 ctrl &= ~SDHCI_CTRL_DMA_MASK;
859 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 860 (host->flags & SDHCI_USE_ADMA)) {
861 if (host->flags & SDHCI_USE_64_BIT_DMA)
862 ctrl |= SDHCI_CTRL_ADMA64;
863 else
864 ctrl |= SDHCI_CTRL_ADMA32;
865 } else {
2134a922 866 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 867 }
4e4141a5 868 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 869 }
870
8f1934ce 871 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 872 int flags;
873
874 flags = SG_MITER_ATOMIC;
875 if (host->data->flags & MMC_DATA_READ)
876 flags |= SG_MITER_TO_SG;
877 else
878 flags |= SG_MITER_FROM_SG;
879 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 880 host->blocks = data->blocks;
d129bceb 881 }
c7fa9963 882
6aa943ab
AV		 883 sdhci_set_transfer_irqs(host);
884
f6a03cbf
MV		 885 /* Set the DMA boundary value and block size */
886 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
887 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 888 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 889}
890
891static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 892 struct mmc_command *cmd)
c7fa9963 893{
d3fc5d71 894 u16 mode = 0;
e89d456f 895 struct mmc_data *data = cmd->data;
c7fa9963 896
2b558c13 897 if (data == NULL) {
9b8ffea6
VW		 898 if (host->quirks2 &
899 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
900 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
901 } else {
2b558c13 902 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 903 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
904 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 905 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 906 }
c7fa9963 907 return;
2b558c13 908 }
c7fa9963 909
e538fbe8
PO		 910 WARN_ON(!host->data);
911
d3fc5d71
VY		 912 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
913 mode = SDHCI_TRNS_BLK_CNT_EN;
914
e89d456f 915 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 916 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 917 /*
918 * If we are sending CMD23, CMD12 never gets sent
919 * on successful completion (so no Auto-CMD12).
920 */
85cc1c33
CD		 921 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
922 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 923 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 924 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
925 mode |= SDHCI_TRNS_AUTO_CMD23;
926 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
927 }
c4512f79 928 }
8edf6371 929
c7fa9963
PO		 930 if (data->flags & MMC_DATA_READ)
931 mode |= SDHCI_TRNS_READ;
c9fddbc4 932 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 933 mode |= SDHCI_TRNS_DMA;
934
4e4141a5 935 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 936}
937
938static void sdhci_finish_data(struct sdhci_host *host)
939{
940 struct mmc_data *data;
d129bceb
PO		 941
942 BUG_ON(!host->data);
943
944 data = host->data;
945 host->data = NULL;
946
c9fddbc4 947 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 948 if (host->flags & SDHCI_USE_ADMA)
949 sdhci_adma_table_post(host, data);
950 else {
348487cb
HC		 951 if (!data->host_cookie)
952 dma_unmap_sg(mmc_dev(host->mmc),
953 data->sg, data->sg_len,
954 (data->flags & MMC_DATA_READ) ?
2134a922
PO		 955 DMA_FROM_DEVICE : DMA_TO_DEVICE);
956 }
d129bceb
PO		 957 }
958
959 /*
c9b74c5b
PO		 960 * The specification states that the block count register must
961 * be updated, but it does not specify at what point in the
962 * data flow. That makes the register entirely useless to read
963 * back so we have to assume that nothing made it to the card
964 * in the event of an error.
d129bceb 965 */
c9b74c5b
PO		 966 if (data->error)
967 data->bytes_xfered = 0;
d129bceb 968 else
c9b74c5b 969 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 970
e89d456f
AW		 971 /*
972 * Need to send CMD12 if -
973 * a) open-ended multiblock transfer (no CMD23)
974 * b) error in multiblock transfer
975 */
976 if (data->stop &&
977 (data->error ||
978 !host->mrq->sbc)) {
979
d129bceb
PO		 980 /*
981 * The controller needs a reset of internal state machines
982 * upon error conditions.
983 */
17b0429d 984 if (data->error) {
03231f9b
RK		 985 sdhci_do_reset(host, SDHCI_RESET_CMD);
986 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 987 }
988
989 sdhci_send_command(host, data->stop);
990 } else
991 tasklet_schedule(&host->finish_tasklet);
992}
993
c0e55129 994void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 995{
996 int flags;
fd2208d7 997 u32 mask;
7cb2c76f 998 unsigned long timeout;
d129bceb
PO		 999
1000 WARN_ON(host->cmd);
1001
d129bceb 1002 /* Wait max 10 ms */
7cb2c76f 1003 timeout = 10;
fd2208d7
PO		 1004
1005 mask = SDHCI_CMD_INHIBIT;
1006 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1007 mask |= SDHCI_DATA_INHIBIT;
1008
1009 /* We shouldn't wait for data inihibit for stop commands, even
1010 though they might use busy signaling */
1011 if (host->mrq->data && (cmd == host->mrq->data->stop))
1012 mask &= ~SDHCI_DATA_INHIBIT;
1013
4e4141a5 1014 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1015 if (timeout == 0) {
a3c76eb9 1016 pr_err("%s: Controller never released "
acf1da45 1017 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1018 sdhci_dumpregs(host);
17b0429d 1019 cmd->error = -EIO;
d129bceb
PO		 1020 tasklet_schedule(&host->finish_tasklet);
1021 return;
1022 }
7cb2c76f
PO		 1023 timeout--;
1024 mdelay(1);
1025 }
d129bceb 1026
3e1a6892 1027 timeout = jiffies;
1d4d7744
UH		 1028 if (!cmd->data && cmd->busy_timeout > 9000)
1029 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1030 else
1031 timeout += 10 * HZ;
1032 mod_timer(&host->timer, timeout);
d129bceb
PO		 1033
1034 host->cmd = cmd;
e99783a4 1035 host->busy_handle = 0;
d129bceb 1036
a3c7778f 1037 sdhci_prepare_data(host, cmd);
d129bceb 1038
4e4141a5 1039 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1040
e89d456f 1041 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1042
d129bceb 1043 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1044 pr_err("%s: Unsupported response type!\n",
d129bceb 1045 mmc_hostname(host->mmc));
17b0429d 1046 cmd->error = -EINVAL;
d129bceb
PO		 1047 tasklet_schedule(&host->finish_tasklet);
1048 return;
1049 }
1050
1051 if (!(cmd->flags & MMC_RSP_PRESENT))
1052 flags = SDHCI_CMD_RESP_NONE;
1053 else if (cmd->flags & MMC_RSP_136)
1054 flags = SDHCI_CMD_RESP_LONG;
1055 else if (cmd->flags & MMC_RSP_BUSY)
1056 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1057 else
1058 flags = SDHCI_CMD_RESP_SHORT;
1059
1060 if (cmd->flags & MMC_RSP_CRC)
1061 flags |= SDHCI_CMD_CRC;
1062 if (cmd->flags & MMC_RSP_OPCODE)
1063 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1064
1065 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1066 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1067 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1068 flags |= SDHCI_CMD_DATA;
1069
4e4141a5 1070 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1071}
c0e55129 1072EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1073
1074static void sdhci_finish_command(struct sdhci_host *host)
1075{
1076 int i;
1077
1078 BUG_ON(host->cmd == NULL);
1079
1080 if (host->cmd->flags & MMC_RSP_PRESENT) {
1081 if (host->cmd->flags & MMC_RSP_136) {
1082 /* CRC is stripped so we need to do some shifting. */
1083 for (i = 0;i < 4;i++) {
4e4141a5 1084 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1085 SDHCI_RESPONSE + (3-i)*4) << 8;
1086 if (i != 3)
1087 host->cmd->resp[i] |=
4e4141a5 1088 sdhci_readb(host,
d129bceb
PO		 1089 SDHCI_RESPONSE + (3-i)*4-1);
1090 }
1091 } else {
4e4141a5 1092 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1093 }
1094 }
1095
17b0429d 1096 host->cmd->error = 0;
d129bceb 1097
e89d456f
AW		 1098 /* Finished CMD23, now send actual command. */
1099 if (host->cmd == host->mrq->sbc) {
1100 host->cmd = NULL;
1101 sdhci_send_command(host, host->mrq->cmd);
1102 } else {
e538fbe8 1103
e89d456f
AW		 1104 /* Processed actual command. */
1105 if (host->data && host->data_early)
1106 sdhci_finish_data(host);
d129bceb 1107
e89d456f
AW		 1108 if (!host->cmd->data)
1109 tasklet_schedule(&host->finish_tasklet);
1110
1111 host->cmd = NULL;
1112 }
d129bceb
PO		 1113}
1114
52983382
KL		 1115static u16 sdhci_get_preset_value(struct sdhci_host *host)
1116{
d975f121 1117 u16 preset = 0;
52983382 1118
d975f121
RK		 1119 switch (host->timing) {
1120 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1121 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1122 break;
d975f121 1123 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1125 break;
d975f121 1126 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1128 break;
d975f121
RK		 1129 case MMC_TIMING_UHS_SDR104:
1130 case MMC_TIMING_MMC_HS200:
52983382
KL		 1131 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1132 break;
d975f121 1133 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1135 break;
e9fb05d5
AH		 1136 case MMC_TIMING_MMC_HS400:
1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1138 break;
52983382
KL		 1139 default:
1140 pr_warn("%s: Invalid UHS-I mode selected\n",
1141 mmc_hostname(host->mmc));
1142 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1143 break;
1144 }
1145 return preset;
1146}
1147
1771059c 1148void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1149{
c3ed3877 1150 int div = 0; /* Initialized for compiler warning */
df16219f 1151 int real_div = div, clk_mul = 1;
c3ed3877 1152 u16 clk = 0;
7cb2c76f 1153 unsigned long timeout;
d129bceb 1154
1650d0c7
RK		 1155 host->mmc->actual_clock = 0;
1156
4e4141a5 1157 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1158
1159 if (clock == 0)
373073ef 1160 return;
d129bceb 1161
85105c53 1162 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1163 if (host->preset_enabled) {
52983382
KL		 1164 u16 pre_val;
1165
1166 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1167 pre_val = sdhci_get_preset_value(host);
1168 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1169 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1170 if (host->clk_mul &&
1171 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1172 clk = SDHCI_PROG_CLOCK_MODE;
1173 real_div = div + 1;
1174 clk_mul = host->clk_mul;
1175 } else {
1176 real_div = max_t(int, 1, div << 1);
1177 }
1178 goto clock_set;
1179 }
1180
c3ed3877
AN		 1181 /*
1182 * Check if the Host Controller supports Programmable Clock
1183 * Mode.
1184 */
1185 if (host->clk_mul) {
52983382
KL		 1186 for (div = 1; div <= 1024; div++) {
1187 if ((host->max_clk * host->clk_mul / div)
1188 <= clock)
1189 break;
1190 }
c3ed3877 1191 /*
52983382
KL		 1192 * Set Programmable Clock Mode in the Clock
1193 * Control register.
c3ed3877 1194 */
52983382
KL		 1195 clk = SDHCI_PROG_CLOCK_MODE;
1196 real_div = div;
1197 clk_mul = host->clk_mul;
1198 div--;
c3ed3877
AN		 1199 } else {
1200 /* Version 3.00 divisors must be a multiple of 2. */
1201 if (host->max_clk <= clock)
1202 div = 1;
1203 else {
1204 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1205 div += 2) {
1206 if ((host->max_clk / div) <= clock)
1207 break;
1208 }
85105c53 1209 }
df16219f 1210 real_div = div;
c3ed3877 1211 div >>= 1;
d1955c3a
SG		 1212 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1213 && !div && host->max_clk <= 25000000)
1214 div = 1;
85105c53
ZG		 1215 }
1216 } else {
1217 /* Version 2.00 divisors must be a power of 2. */
0397526d 1218 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1219 if ((host->max_clk / div) <= clock)
1220 break;
1221 }
df16219f 1222 real_div = div;
c3ed3877 1223 div >>= 1;
d129bceb 1224 }
d129bceb 1225
52983382 1226clock_set:
03d6f5ff 1227 if (real_div)
df16219f 1228 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1229 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1230 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1231 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1232 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1233 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1234
27f6cb16
CB		 1235 /* Wait max 20 ms */
1236 timeout = 20;
4e4141a5 1237 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1238 & SDHCI_CLOCK_INT_STABLE)) {
1239 if (timeout == 0) {
a3c76eb9 1240 pr_err("%s: Internal clock never "
acf1da45 1241 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1242 sdhci_dumpregs(host);
1243 return;
1244 }
7cb2c76f
PO		 1245 timeout--;
1246 mdelay(1);
1247 }
d129bceb
PO		 1248
1249 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1250 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1251}
1771059c 1252EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1253
24fbb3ca
RK		 1254static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1255 unsigned short vdd)
146ad66e 1256{
3a48edc4 1257 struct mmc_host *mmc = host->mmc;
8364248a 1258 u8 pwr = 0;
146ad66e 1259
52221610
TK		 1260 if (!IS_ERR(mmc->supply.vmmc)) {
1261 spin_unlock_irq(&host->lock);
4e743f1f 1262 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610 1263 spin_lock_irq(&host->lock);
3cbc6123
TK		 1264
1265 if (mode != MMC_POWER_OFF)
1266 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1267 else
1268 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1269
52221610
TK		 1270 return;
1271 }
1272
24fbb3ca
RK		 1273 if (mode != MMC_POWER_OFF) {
1274 switch (1 << vdd) {
ae628903
PO		 1275 case MMC_VDD_165_195:
1276 pwr = SDHCI_POWER_180;
1277 break;
1278 case MMC_VDD_29_30:
1279 case MMC_VDD_30_31:
1280 pwr = SDHCI_POWER_300;
1281 break;
1282 case MMC_VDD_32_33:
1283 case MMC_VDD_33_34:
1284 pwr = SDHCI_POWER_330;
1285 break;
1286 default:
1287 BUG();
1288 }
1289 }
1290
1291 if (host->pwr == pwr)
e921a8b6 1292 return;
146ad66e 1293
ae628903
PO		 1294 host->pwr = pwr;
1295
1296 if (pwr == 0) {
4e4141a5 1297 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1298 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1299 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1300 vdd = 0;
e921a8b6
RK		 1301 } else {
1302 /*
1303 * Spec says that we should clear the power reg before setting
1304 * a new value. Some controllers don't seem to like this though.
1305 */
1306 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1307 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1308
e921a8b6
RK		 1309 /*
1310 * At least the Marvell CaFe chip gets confused if we set the
1311 * voltage and set turn on power at the same time, so set the
1312 * voltage first.
1313 */
1314 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1315 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1316
e921a8b6 1317 pwr |= SDHCI_POWER_ON;
146ad66e 1318
e921a8b6 1319 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1320
e921a8b6
RK		 1321 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1322 sdhci_runtime_pm_bus_on(host);
f0710a55 1323
e921a8b6
RK		 1324 /*
1325 * Some controllers need an extra 10ms delay of 10ms before
1326 * they can apply clock after applying power
1327 */
1328 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1329 mdelay(10);
1330 }
146ad66e
PO		 1331}
1332
d129bceb
PO		 1333/*****************************************************************************\
1334 * *
1335 * MMC callbacks *
1336 * *
1337\*****************************************************************************/
1338
1339static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1340{
1341 struct sdhci_host *host;
505a8680 1342 int present;
d129bceb
PO		 1343 unsigned long flags;
1344
1345 host = mmc_priv(mmc);
1346
66fd8ad5
AH		 1347 sdhci_runtime_pm_get(host);
1348
04e079cf
SB		 1349 /* Firstly check card presence */
1350 present = sdhci_do_get_cd(host);
2836766a 1351
d129bceb
PO		 1352 spin_lock_irqsave(&host->lock, flags);
1353
1354 WARN_ON(host->mrq != NULL);
1355
f9134319 1356#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1357 sdhci_activate_led(host);
2f730fec 1358#endif
e89d456f
AW		 1359
1360 /*
1361 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1362 * requests if Auto-CMD12 is enabled.
1363 */
1364 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1365 if (mrq->stop) {
1366 mrq->data->stop = NULL;
1367 mrq->stop = NULL;
1368 }
1369 }
d129bceb
PO		 1370
1371 host->mrq = mrq;
1372
68d1fb7e 1373 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1374 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1375 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1376 } else {
8edf6371 1377 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1378 sdhci_send_command(host, mrq->sbc);
1379 else
1380 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1381 }
d129bceb 1382
5f25a66f 1383 mmiowb();
d129bceb
PO		 1384 spin_unlock_irqrestore(&host->lock, flags);
1385}
1386
2317f56c
RK		 1387void sdhci_set_bus_width(struct sdhci_host *host, int width)
1388{
1389 u8 ctrl;
1390
1391 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1392 if (width == MMC_BUS_WIDTH_8) {
1393 ctrl &= ~SDHCI_CTRL_4BITBUS;
1394 if (host->version >= SDHCI_SPEC_300)
1395 ctrl |= SDHCI_CTRL_8BITBUS;
1396 } else {
1397 if (host->version >= SDHCI_SPEC_300)
1398 ctrl &= ~SDHCI_CTRL_8BITBUS;
1399 if (width == MMC_BUS_WIDTH_4)
1400 ctrl |= SDHCI_CTRL_4BITBUS;
1401 else
1402 ctrl &= ~SDHCI_CTRL_4BITBUS;
1403 }
1404 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1405}
1406EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1407
96d7b78c
RK		 1408void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1409{
1410 u16 ctrl_2;
1411
1412 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1413 /* Select Bus Speed Mode for host */
1414 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1415 if ((timing == MMC_TIMING_MMC_HS200) ||
1416 (timing == MMC_TIMING_UHS_SDR104))
1417 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1418 else if (timing == MMC_TIMING_UHS_SDR12)
1419 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1420 else if (timing == MMC_TIMING_UHS_SDR25)
1421 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1422 else if (timing == MMC_TIMING_UHS_SDR50)
1423 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1424 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1425 (timing == MMC_TIMING_MMC_DDR52))
1426 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1427 else if (timing == MMC_TIMING_MMC_HS400)
1428 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1429 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1430}
1431EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1432
66fd8ad5 1433static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1434{
d129bceb
PO		 1435 unsigned long flags;
1436 u8 ctrl;
3a48edc4 1437 struct mmc_host *mmc = host->mmc;
d129bceb 1438
d129bceb
PO		 1439 spin_lock_irqsave(&host->lock, flags);
1440
ceb6143b
AH		 1441 if (host->flags & SDHCI_DEVICE_DEAD) {
1442 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1443 if (!IS_ERR(mmc->supply.vmmc) &&
1444 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1445 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1446 return;
1447 }
1e72859e 1448
d129bceb
PO		 1449 /*
1450 * Reset the chip on each power off.
1451 * Should clear out any weird states.
1452 */
1453 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1454 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1455 sdhci_reinit(host);
d129bceb
PO		 1456 }
1457
52983382 1458 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1459 (ios->power_mode == MMC_POWER_UP) &&
1460 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1461 sdhci_enable_preset_value(host, false);
1462
373073ef 1463 if (!ios->clock || ios->clock != host->clock) {
1771059c 1464 host->ops->set_clock(host, ios->clock);
373073ef 1465 host->clock = ios->clock;
03d6f5ff
AD		 1466
1467 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1468 host->clock) {
1469 host->timeout_clk = host->mmc->actual_clock ?
1470 host->mmc->actual_clock / 1000 :
1471 host->clock / 1000;
1472 host->mmc->max_busy_timeout =
1473 host->ops->get_max_timeout_count ?
1474 host->ops->get_max_timeout_count(host) :
1475 1 << 27;
1476 host->mmc->max_busy_timeout /= host->timeout_clk;
1477 }
373073ef 1478 }
d129bceb 1479
24fbb3ca 1480 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1481
643a81ff
PR		 1482 if (host->ops->platform_send_init_74_clocks)
1483 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1484
2317f56c 1485 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1486
15ec4461 1487 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1488
3ab9c8da
PR		 1489 if ((ios->timing == MMC_TIMING_SD_HS ||
1490 ios->timing == MMC_TIMING_MMC_HS)
1491 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1492 ctrl |= SDHCI_CTRL_HISPD;
1493 else
1494 ctrl &= ~SDHCI_CTRL_HISPD;
1495
d6d50a15 1496 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1497 u16 clk, ctrl_2;
49c468fc
AN		 1498
1499 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1500 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1501 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1502 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1503 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1504 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1505 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1506 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1507 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1508
da91a8f9 1509 if (!host->preset_enabled) {
758535c4 1510 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1511 /*
1512 * We only need to set Driver Strength if the
1513 * preset value enable is not set.
1514 */
da91a8f9 1515 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1516 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1517 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1518 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1519 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1520 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1521 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1522 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1523 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1524 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1525 else {
1526 pr_warn("%s: invalid driver type, default to "
1527 "driver type B\n", mmc_hostname(mmc));
1528 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1529 }
d6d50a15
AN		 1530
1531 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1532 } else {
1533 /*
1534 * According to SDHC Spec v3.00, if the Preset Value
1535 * Enable in the Host Control 2 register is set, we
1536 * need to reset SD Clock Enable before changing High
1537 * Speed Enable to avoid generating clock gliches.
1538 */
758535c4
AN		 1539
1540 /* Reset SD Clock Enable */
1541 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1542 clk &= ~SDHCI_CLOCK_CARD_EN;
1543 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1544
1545 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1546
1547 /* Re-enable SD Clock */
1771059c 1548 host->ops->set_clock(host, host->clock);
d6d50a15 1549 }
49c468fc 1550
49c468fc
AN		 1551 /* Reset SD Clock Enable */
1552 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1553 clk &= ~SDHCI_CLOCK_CARD_EN;
1554 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1555
96d7b78c 1556 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1557 host->timing = ios->timing;
49c468fc 1558
52983382
KL		 1559 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1560 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1561 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1562 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1563 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1564 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1565 u16 preset;
1566
1567 sdhci_enable_preset_value(host, true);
1568 preset = sdhci_get_preset_value(host);
1569 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1570 >> SDHCI_PRESET_DRV_SHIFT;
1571 }
1572
49c468fc 1573 /* Re-enable SD Clock */
1771059c 1574 host->ops->set_clock(host, host->clock);
758535c4
AN		 1575 } else
1576 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1577
b8352260
LD		 1578 /*
1579 * Some (ENE) controllers go apeshit on some ios operation,
1580 * signalling timeout and CRC errors even on CMD0. Resetting
1581 * it on each ios seems to solve the problem.
1582 */
c63705e1 1583 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1584 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1585
5f25a66f 1586 mmiowb();
d129bceb
PO		 1587 spin_unlock_irqrestore(&host->lock, flags);
1588}
1589
66fd8ad5
AH		 1590static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1591{
1592 struct sdhci_host *host = mmc_priv(mmc);
1593
1594 sdhci_runtime_pm_get(host);
1595 sdhci_do_set_ios(host, ios);
1596 sdhci_runtime_pm_put(host);
1597}
1598
94144a46
KL		 1599static int sdhci_do_get_cd(struct sdhci_host *host)
1600{
1601 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1602
1603 if (host->flags & SDHCI_DEVICE_DEAD)
1604 return 0;
1605
88af5655
II		 1606 /* If nonremovable, assume that the card is always present. */
1607 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1608 return 1;
1609
88af5655
II		 1610 /*
1611 * Try slot gpio detect, if defined it take precedence
1612 * over build in controller functionality
1613 */
94144a46
KL		 1614 if (!IS_ERR_VALUE(gpio_cd))
1615 return !!gpio_cd;
1616
88af5655
II		 1617 /* If polling, assume that the card is always present. */
1618 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1619 return 1;
1620
94144a46
KL		 1621 /* Host native card detect */
1622 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1623}
1624
1625static int sdhci_get_cd(struct mmc_host *mmc)
1626{
1627 struct sdhci_host *host = mmc_priv(mmc);
1628 int ret;
1629
1630 sdhci_runtime_pm_get(host);
1631 ret = sdhci_do_get_cd(host);
1632 sdhci_runtime_pm_put(host);
1633 return ret;
1634}
1635
66fd8ad5 1636static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1637{
d129bceb 1638 unsigned long flags;
2dfb579c 1639 int is_readonly;
d129bceb 1640
d129bceb
PO		 1641 spin_lock_irqsave(&host->lock, flags);
1642
1e72859e 1643 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1644 is_readonly = 0;
1645 else if (host->ops->get_ro)
1646 is_readonly = host->ops->get_ro(host);
1e72859e 1647 else
2dfb579c
WS		 1648 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1649 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1650
1651 spin_unlock_irqrestore(&host->lock, flags);
1652
2dfb579c
WS		 1653 /* This quirk needs to be replaced by a callback-function later */
1654 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1655 !is_readonly : is_readonly;
d129bceb
PO		 1656}
1657
82b0e23a
TI		 1658#define SAMPLE_COUNT 5
1659
66fd8ad5 1660static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1661{
82b0e23a
TI		 1662 int i, ro_count;
1663
82b0e23a 1664 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1665 return sdhci_check_ro(host);
82b0e23a
TI		 1666
1667 ro_count = 0;
1668 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1669 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1670 if (++ro_count > SAMPLE_COUNT / 2)
1671 return 1;
1672 }
1673 msleep(30);
1674 }
1675 return 0;
1676}
1677
20758b66
AH		 1678static void sdhci_hw_reset(struct mmc_host *mmc)
1679{
1680 struct sdhci_host *host = mmc_priv(mmc);
1681
1682 if (host->ops && host->ops->hw_reset)
1683 host->ops->hw_reset(host);
1684}
1685
66fd8ad5 1686static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1687{
66fd8ad5
AH		 1688 struct sdhci_host *host = mmc_priv(mmc);
1689 int ret;
f75979b7 1690
66fd8ad5
AH		 1691 sdhci_runtime_pm_get(host);
1692 ret = sdhci_do_get_ro(host);
1693 sdhci_runtime_pm_put(host);
1694 return ret;
1695}
f75979b7 1696
66fd8ad5
AH		 1697static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1698{
be138554 1699 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1700 if (enable)
b537f94c 1701 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1702 else
b537f94c
RK		 1703 host->ier &= ~SDHCI_INT_CARD_INT;
1704
1705 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1706 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1707 mmiowb();
1708 }
66fd8ad5
AH		 1709}
1710
1711static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1712{
1713 struct sdhci_host *host = mmc_priv(mmc);
1714 unsigned long flags;
f75979b7 1715
ef104333
RK		 1716 sdhci_runtime_pm_get(host);
1717
66fd8ad5 1718 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1719 if (enable)
1720 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1721 else
1722 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1723
66fd8ad5 1724 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1725 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1726
1727 sdhci_runtime_pm_put(host);
f75979b7
PO		 1728}
1729
20b92a30 1730static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1731 struct mmc_ios *ios)
f2119df6 1732{
3a48edc4 1733 struct mmc_host *mmc = host->mmc;
20b92a30 1734 u16 ctrl;
6231f3de 1735 int ret;
f2119df6 1736
20b92a30
KL		 1737 /*
1738 * Signal Voltage Switching is only applicable for Host Controllers
1739 * v3.00 and above.
1740 */
1741 if (host->version < SDHCI_SPEC_300)
1742 return 0;
6231f3de 1743
f2119df6 1744 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1745
21f5998f 1746 switch (ios->signal_voltage) {
20b92a30
KL		 1747 case MMC_SIGNAL_VOLTAGE_330:
1748 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1749 ctrl &= ~SDHCI_CTRL_VDD_180;
1750 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1751
3a48edc4
TK		 1752 if (!IS_ERR(mmc->supply.vqmmc)) {
1753 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1754 3600000);
20b92a30 1755 if (ret) {
6606110d
JP		 1756 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1757 mmc_hostname(mmc));
20b92a30
KL		 1758 return -EIO;
1759 }
1760 }
1761 /* Wait for 5ms */
1762 usleep_range(5000, 5500);
f2119df6 1763
20b92a30
KL		 1764 /* 3.3V regulator output should be stable within 5 ms */
1765 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1766 if (!(ctrl & SDHCI_CTRL_VDD_180))
1767 return 0;
6231f3de 1768
6606110d
JP		 1769 pr_warn("%s: 3.3V regulator output did not became stable\n",
1770 mmc_hostname(mmc));
20b92a30
KL		 1771
1772 return -EAGAIN;
1773 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1774 if (!IS_ERR(mmc->supply.vqmmc)) {
1775 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1776 1700000, 1950000);
1777 if (ret) {
6606110d
JP		 1778 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1779 mmc_hostname(mmc));
20b92a30
KL		 1780 return -EIO;
1781 }
1782 }
6231f3de 1783
6231f3de
PR		 1784 /*
1785 * Enable 1.8V Signal Enable in the Host Control2
1786 * register
1787 */
20b92a30
KL		 1788 ctrl |= SDHCI_CTRL_VDD_180;
1789 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1790
9d967a61
VY		 1791 /* Some controller need to do more when switching */
1792 if (host->ops->voltage_switch)
1793 host->ops->voltage_switch(host);
1794
20b92a30
KL		 1795 /* 1.8V regulator output should be stable within 5 ms */
1796 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1797 if (ctrl & SDHCI_CTRL_VDD_180)
1798 return 0;
f2119df6 1799
6606110d
JP		 1800 pr_warn("%s: 1.8V regulator output did not became stable\n",
1801 mmc_hostname(mmc));
f2119df6 1802
20b92a30
KL		 1803 return -EAGAIN;
1804 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1805 if (!IS_ERR(mmc->supply.vqmmc)) {
1806 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1807 1300000);
20b92a30 1808 if (ret) {
6606110d
JP		 1809 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1810 mmc_hostname(mmc));
20b92a30 1811 return -EIO;
f2119df6
AN		 1812 }
1813 }
6231f3de 1814 return 0;
20b92a30 1815 default:
f2119df6
AN		 1816 /* No signal voltage switch required */
1817 return 0;
20b92a30 1818 }
f2119df6
AN		 1819}
1820
66fd8ad5 1821static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1822 struct mmc_ios *ios)
66fd8ad5
AH		 1823{
1824 struct sdhci_host *host = mmc_priv(mmc);
1825 int err;
1826
1827 if (host->version < SDHCI_SPEC_300)
1828 return 0;
1829 sdhci_runtime_pm_get(host);
21f5998f 1830 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1831 sdhci_runtime_pm_put(host);
1832 return err;
1833}
1834
20b92a30
KL		 1835static int sdhci_card_busy(struct mmc_host *mmc)
1836{
1837 struct sdhci_host *host = mmc_priv(mmc);
1838 u32 present_state;
1839
1840 sdhci_runtime_pm_get(host);
1841 /* Check whether DAT[3:0] is 0000 */
1842 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1843 sdhci_runtime_pm_put(host);
1844
1845 return !(present_state & SDHCI_DATA_LVL_MASK);
1846}
1847
b5540ce1
AH		 1848static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1849{
1850 struct sdhci_host *host = mmc_priv(mmc);
1851 unsigned long flags;
1852
1853 spin_lock_irqsave(&host->lock, flags);
1854 host->flags |= SDHCI_HS400_TUNING;
1855 spin_unlock_irqrestore(&host->lock, flags);
1856
1857 return 0;
1858}
1859
069c9f14 1860static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1861{
4b6f37d3 1862 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1863 u16 ctrl;
b513ea25 1864 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1865 int err = 0;
2b35bd83 1866 unsigned long flags;
38e40bf5 1867 unsigned int tuning_count = 0;
b5540ce1 1868 bool hs400_tuning;
b513ea25 1869
66fd8ad5 1870 sdhci_runtime_pm_get(host);
2b35bd83 1871 spin_lock_irqsave(&host->lock, flags);
b513ea25 1872
b5540ce1
AH		 1873 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1874 host->flags &= ~SDHCI_HS400_TUNING;
1875
38e40bf5
AH		 1876 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1877 tuning_count = host->tuning_count;
1878
b513ea25 1879 /*
069c9f14
G		 1880 * The Host Controller needs tuning only in case of SDR104 mode
1881 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1882 * Capabilities register.
069c9f14
G		 1883 * If the Host Controller supports the HS200 mode then the
1884 * tuning function has to be executed.
b513ea25 1885 */
4b6f37d3 1886 switch (host->timing) {
b5540ce1 1887 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1888 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1889 err = -EINVAL;
1890 goto out_unlock;
1891
4b6f37d3 1892 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1893 /*
1894 * Periodic re-tuning for HS400 is not expected to be needed, so
1895 * disable it here.
1896 */
1897 if (hs400_tuning)
1898 tuning_count = 0;
1899 break;
1900
4b6f37d3
RK		 1901 case MMC_TIMING_UHS_SDR104:
1902 break;
1903
1904 case MMC_TIMING_UHS_SDR50:
1905 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1906 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1907 break;
1908 /* FALLTHROUGH */
1909
1910 default:
d519c863 1911 goto out_unlock;
b513ea25
AN		 1912 }
1913
45251812 1914 if (host->ops->platform_execute_tuning) {
2b35bd83 1915 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1916 err = host->ops->platform_execute_tuning(host, opcode);
1917 sdhci_runtime_pm_put(host);
1918 return err;
1919 }
1920
4b6f37d3
RK		 1921 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1922 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1923 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1924 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1925 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1926
1927 /*
1928 * As per the Host Controller spec v3.00, tuning command
1929 * generates Buffer Read Ready interrupt, so enable that.
1930 *
1931 * Note: The spec clearly says that when tuning sequence
1932 * is being performed, the controller does not generate
1933 * interrupts other than Buffer Read Ready interrupt. But
1934 * to make sure we don't hit a controller bug, we _only_
1935 * enable Buffer Read Ready interrupt here.
1936 */
b537f94c
RK		 1937 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1938 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1939
1940 /*
1941 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1942 * of loops reaches 40 times or a timeout of 150ms occurs.
1943 */
b513ea25
AN		 1944 do {
1945 struct mmc_command cmd = {0};
66fd8ad5 1946 struct mmc_request mrq = {NULL};
b513ea25 1947
069c9f14 1948 cmd.opcode = opcode;
b513ea25
AN		 1949 cmd.arg = 0;
1950 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1951 cmd.retries = 0;
1952 cmd.data = NULL;
1953 cmd.error = 0;
1954
7ce45e95
AC		 1955 if (tuning_loop_counter-- == 0)
1956 break;
1957
b513ea25
AN		 1958 mrq.cmd = &cmd;
1959 host->mrq = &mrq;
1960
1961 /*
1962 * In response to CMD19, the card sends 64 bytes of tuning
1963 * block to the Host Controller. So we set the block size
1964 * to 64 here.
1965 */
069c9f14
G		 1966 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1967 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1968 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1969 SDHCI_BLOCK_SIZE);
1970 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1971 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1972 SDHCI_BLOCK_SIZE);
1973 } else {
1974 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1975 SDHCI_BLOCK_SIZE);
1976 }
b513ea25
AN		 1977
1978 /*
1979 * The tuning block is sent by the card to the host controller.
1980 * So we set the TRNS_READ bit in the Transfer Mode register.
1981 * This also takes care of setting DMA Enable and Multi Block
1982 * Select in the same register to 0.
1983 */
1984 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1985
1986 sdhci_send_command(host, &cmd);
1987
1988 host->cmd = NULL;
1989 host->mrq = NULL;
1990
2b35bd83 1991 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1992 /* Wait for Buffer Read Ready interrupt */
1993 wait_event_interruptible_timeout(host->buf_ready_int,
1994 (host->tuning_done == 1),
1995 msecs_to_jiffies(50));
2b35bd83 1996 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1997
1998 if (!host->tuning_done) {
a3c76eb9 1999 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 2000 "Buffer Read Ready interrupt during tuning "
2001 "procedure, falling back to fixed sampling "
2002 "clock\n");
2003 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2004 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2005 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2006 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2007
2008 err = -EIO;
2009 goto out;
2010 }
2011
2012 host->tuning_done = 0;
2013
2014 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2015
2016 /* eMMC spec does not require a delay between tuning cycles */
2017 if (opcode == MMC_SEND_TUNING_BLOCK)
2018 mdelay(1);
b513ea25
AN		 2019 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2020
2021 /*
2022 * The Host Driver has exhausted the maximum number of loops allowed,
2023 * so use fixed sampling frequency.
2024 */
7ce45e95 2025 if (tuning_loop_counter < 0) {
b513ea25
AN		 2026 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2027 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2028 }
2029 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2030 pr_info(DRIVER_NAME ": Tuning procedure"
2031 " failed, falling back to fixed sampling"
2032 " clock\n");
114f2bf6 2033 err = -EIO;
b513ea25
AN		 2034 }
2035
2036out:
38e40bf5 2037 if (tuning_count) {
66c39dfc
AH		 2038 /*
2039 * In case tuning fails, host controllers which support
2040 * re-tuning can try tuning again at a later time, when the
2041 * re-tuning timer expires. So for these controllers, we
2042 * return 0. Since there might be other controllers who do not
2043 * have this capability, we return error for them.
2044 */
2045 err = 0;
cf2b5eea
AN		 2046 }
2047
66c39dfc 2048 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2049
b537f94c
RK		 2050 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2051 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2052out_unlock:
2b35bd83 2053 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2054 sdhci_runtime_pm_put(host);
b513ea25
AN		 2055
2056 return err;
2057}
2058
cb849648
AH		 2059static int sdhci_select_drive_strength(struct mmc_card *card,
2060 unsigned int max_dtr, int host_drv,
2061 int card_drv, int *drv_type)
2062{
2063 struct sdhci_host *host = mmc_priv(card->host);
2064
2065 if (!host->ops->select_drive_strength)
2066 return 0;
2067
2068 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2069 card_drv, drv_type);
2070}
52983382
KL		 2071
2072static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2073{
4d55c5a1
AN		 2074 /* Host Controller v3.00 defines preset value registers */
2075 if (host->version < SDHCI_SPEC_300)
2076 return;
2077
4d55c5a1
AN		 2078 /*
2079 * We only enable or disable Preset Value if they are not already
2080 * enabled or disabled respectively. Otherwise, we bail out.
2081 */
da91a8f9
RK		 2082 if (host->preset_enabled != enable) {
2083 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2084
2085 if (enable)
2086 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2087 else
2088 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2089
4d55c5a1 2090 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2091
2092 if (enable)
2093 host->flags |= SDHCI_PV_ENABLED;
2094 else
2095 host->flags &= ~SDHCI_PV_ENABLED;
2096
2097 host->preset_enabled = enable;
4d55c5a1 2098 }
66fd8ad5
AH		 2099}
2100
348487cb
HC		 2101static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2102 int err)
2103{
2104 struct sdhci_host *host = mmc_priv(mmc);
2105 struct mmc_data *data = mrq->data;
2106
2107 if (host->flags & SDHCI_REQ_USE_DMA) {
2108 if (data->host_cookie)
2109 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2110 data->flags & MMC_DATA_WRITE ?
2111 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2112 mrq->data->host_cookie = 0;
2113 }
2114}
2115
2116static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2117 struct mmc_data *data,
2118 struct sdhci_host_next *next)
2119{
2120 int sg_count;
2121
2122 if (!next && data->host_cookie &&
2123 data->host_cookie != host->next_data.cookie) {
2124 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2125 __func__, data->host_cookie, host->next_data.cookie);
2126 data->host_cookie = 0;
2127 }
2128
2129 /* Check if next job is already prepared */
2130 if (next ||
2131 (!next && data->host_cookie != host->next_data.cookie)) {
2132 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2133 data->sg_len,
2134 data->flags & MMC_DATA_WRITE ?
2135 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2136
2137 } else {
2138 sg_count = host->next_data.sg_count;
2139 host->next_data.sg_count = 0;
2140 }
2141
2142
2143 if (sg_count == 0)
2144 return -EINVAL;
2145
2146 if (next) {
2147 next->sg_count = sg_count;
2148 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2149 } else
2150 host->sg_count = sg_count;
2151
2152 return sg_count;
2153}
2154
2155static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2156 bool is_first_req)
2157{
2158 struct sdhci_host *host = mmc_priv(mmc);
2159
2160 if (mrq->data->host_cookie) {
2161 mrq->data->host_cookie = 0;
2162 return;
2163 }
2164
2165 if (host->flags & SDHCI_REQ_USE_DMA)
2166 if (sdhci_pre_dma_transfer(host,
2167 mrq->data,
2168 &host->next_data) < 0)
2169 mrq->data->host_cookie = 0;
2170}
2171
71e69211 2172static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2173{
71e69211 2174 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2175 unsigned long flags;
2836766a 2176 int present;
d129bceb 2177
722e1280
CD		 2178 /* First check if client has provided their own card event */
2179 if (host->ops->card_event)
2180 host->ops->card_event(host);
2181
2836766a
KK		 2182 present = sdhci_do_get_cd(host);
2183
d129bceb
PO		 2184 spin_lock_irqsave(&host->lock, flags);
2185
66fd8ad5 2186 /* Check host->mrq first in case we are runtime suspended */
2836766a 2187 if (host->mrq && !present) {
a3c76eb9 2188 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2189 mmc_hostname(host->mmc));
a3c76eb9 2190 pr_err("%s: Resetting controller.\n",
66fd8ad5 2191 mmc_hostname(host->mmc));
d129bceb 2192
03231f9b
RK		 2193 sdhci_do_reset(host, SDHCI_RESET_CMD);
2194 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2195
66fd8ad5
AH		 2196 host->mrq->cmd->error = -ENOMEDIUM;
2197 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2198 }
2199
2200 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2201}
2202
2203static const struct mmc_host_ops sdhci_ops = {
2204 .request = sdhci_request,
348487cb
HC		 2205 .post_req = sdhci_post_req,
2206 .pre_req = sdhci_pre_req,
71e69211 2207 .set_ios = sdhci_set_ios,
94144a46 2208 .get_cd = sdhci_get_cd,
71e69211
GL		 2209 .get_ro = sdhci_get_ro,
2210 .hw_reset = sdhci_hw_reset,
2211 .enable_sdio_irq = sdhci_enable_sdio_irq,
2212 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2213 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2214 .execute_tuning = sdhci_execute_tuning,
cb849648 2215 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2216 .card_event = sdhci_card_event,
20b92a30 2217 .card_busy = sdhci_card_busy,
71e69211
GL		 2218};
2219
2220/*****************************************************************************\
2221 * *
2222 * Tasklets *
2223 * *
2224\*****************************************************************************/
2225
d129bceb
PO		 2226static void sdhci_tasklet_finish(unsigned long param)
2227{
2228 struct sdhci_host *host;
2229 unsigned long flags;
2230 struct mmc_request *mrq;
2231
2232 host = (struct sdhci_host*)param;
2233
66fd8ad5
AH		 2234 spin_lock_irqsave(&host->lock, flags);
2235
0c9c99a7
CB		 2236 /*
2237 * If this tasklet gets rescheduled while running, it will
2238 * be run again afterwards but without any active request.
2239 */
66fd8ad5
AH		 2240 if (!host->mrq) {
2241 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2242 return;
66fd8ad5 2243 }
d129bceb
PO		 2244
2245 del_timer(&host->timer);
2246
2247 mrq = host->mrq;
2248
d129bceb
PO		 2249 /*
2250 * The controller needs a reset of internal state machines
2251 * upon error conditions.
2252 */
1e72859e 2253 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2254 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2255 (mrq->sbc && mrq->sbc->error) ||
2256 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2257 (mrq->data->stop && mrq->data->stop->error))) ||
2258 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2259
2260 /* Some controllers need this kick or reset won't work here */
8213af3b 2261 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2262 /* This is to force an update */
1771059c 2263 host->ops->set_clock(host, host->clock);
645289dc
PO		 2264
2265 /* Spec says we should do both at the same time, but Ricoh
2266 controllers do not like that. */
03231f9b
RK		 2267 sdhci_do_reset(host, SDHCI_RESET_CMD);
2268 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2269 }
2270
2271 host->mrq = NULL;
2272 host->cmd = NULL;
2273 host->data = NULL;
2274
f9134319 2275#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2276 sdhci_deactivate_led(host);
2f730fec 2277#endif
d129bceb 2278
5f25a66f 2279 mmiowb();
d129bceb
PO		 2280 spin_unlock_irqrestore(&host->lock, flags);
2281
2282 mmc_request_done(host->mmc, mrq);
66fd8ad5 2283 sdhci_runtime_pm_put(host);
d129bceb
PO		 2284}
2285
2286static void sdhci_timeout_timer(unsigned long data)
2287{
2288 struct sdhci_host *host;
2289 unsigned long flags;
2290
2291 host = (struct sdhci_host*)data;
2292
2293 spin_lock_irqsave(&host->lock, flags);
2294
2295 if (host->mrq) {
a3c76eb9 2296 pr_err("%s: Timeout waiting for hardware "
acf1da45 2297 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2298 sdhci_dumpregs(host);
2299
2300 if (host->data) {
17b0429d 2301 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2302 sdhci_finish_data(host);
2303 } else {
2304 if (host->cmd)
17b0429d 2305 host->cmd->error = -ETIMEDOUT;
d129bceb 2306 else
17b0429d 2307 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2308
2309 tasklet_schedule(&host->finish_tasklet);
2310 }
2311 }
2312
5f25a66f 2313 mmiowb();
d129bceb
PO		 2314 spin_unlock_irqrestore(&host->lock, flags);
2315}
2316
2317/*****************************************************************************\
2318 * *
2319 * Interrupt handling *
2320 * *
2321\*****************************************************************************/
2322
61541397 2323static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2324{
2325 BUG_ON(intmask == 0);
2326
2327 if (!host->cmd) {
a3c76eb9 2328 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2329 "though no command operation was in progress.\n",
2330 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2331 sdhci_dumpregs(host);
2332 return;
2333 }
2334
43b58b36 2335 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2336 host->cmd->error = -ETIMEDOUT;
2337 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2338 SDHCI_INT_INDEX))
2339 host->cmd->error = -EILSEQ;
43b58b36 2340
e809517f 2341 if (host->cmd->error) {
d129bceb 2342 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2343 return;
2344 }
2345
2346 /*
2347 * The host can send and interrupt when the busy state has
2348 * ended, allowing us to wait without wasting CPU cycles.
2349 * Unfortunately this is overloaded on the "data complete"
2350 * interrupt, so we need to take some care when handling
2351 * it.
2352 *
2353 * Note: The 1.0 specification is a bit ambiguous about this
2354 * feature so there might be some problems with older
2355 * controllers.
2356 */
2357 if (host->cmd->flags & MMC_RSP_BUSY) {
2358 if (host->cmd->data)
2359 DBG("Cannot wait for busy signal when also "
2360 "doing a data transfer");
e99783a4
CM		 2361 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2362 && !host->busy_handle) {
2363 /* Mark that command complete before busy is ended */
2364 host->busy_handle = 1;
e809517f 2365 return;
e99783a4 2366 }
f945405c
BD		 2367
2368 /* The controller does not support the end-of-busy IRQ,
2369 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2370 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2371 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2372 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2373 }
2374
2375 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2376 sdhci_finish_command(host);
d129bceb
PO		 2377}
2378
0957c333 2379#ifdef CONFIG_MMC_DEBUG
08621b18 2380static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2381{
2382 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2383 void *desc = host->adma_table;
6882a8c0
BD		 2384
2385 sdhci_dumpregs(host);
2386
2387 while (true) {
e57a5f61
AH		 2388 struct sdhci_adma2_64_desc *dma_desc = desc;
2389
2390 if (host->flags & SDHCI_USE_64_BIT_DMA)
2391 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2392 name, desc, le32_to_cpu(dma_desc->addr_hi),
2393 le32_to_cpu(dma_desc->addr_lo),
2394 le16_to_cpu(dma_desc->len),
2395 le16_to_cpu(dma_desc->cmd));
2396 else
2397 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2398 name, desc, le32_to_cpu(dma_desc->addr_lo),
2399 le16_to_cpu(dma_desc->len),
2400 le16_to_cpu(dma_desc->cmd));
6882a8c0 2401
76fe379a 2402 desc += host->desc_sz;
6882a8c0 2403
0545230f 2404 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2405 break;
2406 }
2407}
2408#else
08621b18 2409static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2410#endif
2411
d129bceb
PO		 2412static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2413{
069c9f14 2414 u32 command;
d129bceb
PO		 2415 BUG_ON(intmask == 0);
2416
b513ea25
AN		 2417 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2418 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2419 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2420 if (command == MMC_SEND_TUNING_BLOCK ||
2421 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2422 host->tuning_done = 1;
2423 wake_up(&host->buf_ready_int);
2424 return;
2425 }
2426 }
2427
d129bceb
PO		 2428 if (!host->data) {
2429 /*
e809517f
PO		 2430 * The "data complete" interrupt is also used to
2431 * indicate that a busy state has ended. See comment
2432 * above in sdhci_cmd_irq().
d129bceb 2433 */
e809517f 2434 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2435 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2436 host->cmd->error = -ETIMEDOUT;
2437 tasklet_schedule(&host->finish_tasklet);
2438 return;
2439 }
e809517f 2440 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2441 /*
2442 * Some cards handle busy-end interrupt
2443 * before the command completed, so make
2444 * sure we do things in the proper order.
2445 */
2446 if (host->busy_handle)
2447 sdhci_finish_command(host);
2448 else
2449 host->busy_handle = 1;
e809517f
PO		 2450 return;
2451 }
2452 }
d129bceb 2453
a3c76eb9 2454 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2455 "though no data operation was in progress.\n",
2456 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2457 sdhci_dumpregs(host);
2458
2459 return;
2460 }
2461
2462 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2463 host->data->error = -ETIMEDOUT;
22113efd
AL		 2464 else if (intmask & SDHCI_INT_DATA_END_BIT)
2465 host->data->error = -EILSEQ;
2466 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2467 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2468 != MMC_BUS_TEST_R)
17b0429d 2469 host->data->error = -EILSEQ;
6882a8c0 2470 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2471 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2472 sdhci_adma_show_error(host);
2134a922 2473 host->data->error = -EIO;
a4071fbb
HZ		 2474 if (host->ops->adma_workaround)
2475 host->ops->adma_workaround(host, intmask);
6882a8c0 2476 }
d129bceb 2477
17b0429d 2478 if (host->data->error)
d129bceb
PO		 2479 sdhci_finish_data(host);
2480 else {
a406f5a3 2481 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2482 sdhci_transfer_pio(host);
2483
6ba736a1
PO		 2484 /*
2485 * We currently don't do anything fancy with DMA
2486 * boundaries, but as we can't disable the feature
2487 * we need to at least restart the transfer.
f6a03cbf
MV		 2488 *
2489 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2490 * should return a valid address to continue from, but as
2491 * some controllers are faulty, don't trust them.
6ba736a1 2492 */
f6a03cbf
MV		 2493 if (intmask & SDHCI_INT_DMA_END) {
2494 u32 dmastart, dmanow;
2495 dmastart = sg_dma_address(host->data->sg);
2496 dmanow = dmastart + host->data->bytes_xfered;
2497 /*
2498 * Force update to the next DMA block boundary.
2499 */
2500 dmanow = (dmanow &
2501 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2502 SDHCI_DEFAULT_BOUNDARY_SIZE;
2503 host->data->bytes_xfered = dmanow - dmastart;
2504 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2505 " next 0x%08x\n",
2506 mmc_hostname(host->mmc), dmastart,
2507 host->data->bytes_xfered, dmanow);
2508 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2509 }
6ba736a1 2510
e538fbe8
PO		 2511 if (intmask & SDHCI_INT_DATA_END) {
2512 if (host->cmd) {
2513 /*
2514 * Data managed to finish before the
2515 * command completed. Make sure we do
2516 * things in the proper order.
2517 */
2518 host->data_early = 1;
2519 } else {
2520 sdhci_finish_data(host);
2521 }
2522 }
d129bceb
PO		 2523 }
2524}
2525
7d12e780 2526static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2527{
781e989c 2528 irqreturn_t result = IRQ_NONE;
66fd8ad5 2529 struct sdhci_host *host = dev_id;
41005003 2530 u32 intmask, mask, unexpected = 0;
781e989c 2531 int max_loops = 16;
d129bceb
PO		 2532
2533 spin_lock(&host->lock);
2534
be138554 2535 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2536 spin_unlock(&host->lock);
655bca76 2537 return IRQ_NONE;
66fd8ad5
AH		 2538 }
2539
4e4141a5 2540 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2541 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2542 result = IRQ_NONE;
2543 goto out;
2544 }
2545
41005003
RK		 2546 do {
2547 /* Clear selected interrupts. */
2548 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2549 SDHCI_INT_BUS_POWER);
2550 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2551
41005003
RK		 2552 DBG("*** %s got interrupt: 0x%08x\n",
2553 mmc_hostname(host->mmc), intmask);
d129bceb 2554
41005003
RK		 2555 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2556 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2557 SDHCI_CARD_PRESENT;
d129bceb 2558
41005003
RK		 2559 /*
2560 * There is a observation on i.mx esdhc. INSERT
2561 * bit will be immediately set again when it gets
2562 * cleared, if a card is inserted. We have to mask
2563 * the irq to prevent interrupt storm which will
2564 * freeze the system. And the REMOVE gets the
2565 * same situation.
2566 *
2567 * More testing are needed here to ensure it works
2568 * for other platforms though.
2569 */
b537f94c
RK		 2570 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2571 SDHCI_INT_CARD_REMOVE);
2572 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2573 SDHCI_INT_CARD_INSERT;
2574 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2575 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2576
2577 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2578 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2579
2580 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2581 SDHCI_INT_CARD_REMOVE);
2582 result = IRQ_WAKE_THREAD;
41005003 2583 }
d129bceb 2584
41005003 2585 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2586 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2587 &intmask);
964f9ce2 2588
41005003
RK		 2589 if (intmask & SDHCI_INT_DATA_MASK)
2590 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2591
41005003
RK		 2592 if (intmask & SDHCI_INT_BUS_POWER)
2593 pr_err("%s: Card is consuming too much power!\n",
2594 mmc_hostname(host->mmc));
3192a28f 2595
781e989c
RK		 2596 if (intmask & SDHCI_INT_CARD_INT) {
2597 sdhci_enable_sdio_irq_nolock(host, false);
2598 host->thread_isr |= SDHCI_INT_CARD_INT;
2599 result = IRQ_WAKE_THREAD;
2600 }
f75979b7 2601
41005003
RK		 2602 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2603 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2604 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2605 SDHCI_INT_CARD_INT);
f75979b7 2606
41005003
RK		 2607 if (intmask) {
2608 unexpected |= intmask;
2609 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2610 }
d129bceb 2611
781e989c
RK		 2612 if (result == IRQ_NONE)
2613 result = IRQ_HANDLED;
d129bceb 2614
41005003 2615 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2616 } while (intmask && --max_loops);
d129bceb
PO		 2617out:
2618 spin_unlock(&host->lock);
2619
6379b237
AS		 2620 if (unexpected) {
2621 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2622 mmc_hostname(host->mmc), unexpected);
2623 sdhci_dumpregs(host);
2624 }
f75979b7 2625
d129bceb
PO		 2626 return result;
2627}
2628
781e989c
RK		 2629static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2630{
2631 struct sdhci_host *host = dev_id;
2632 unsigned long flags;
2633 u32 isr;
2634
2635 spin_lock_irqsave(&host->lock, flags);
2636 isr = host->thread_isr;
2637 host->thread_isr = 0;
2638 spin_unlock_irqrestore(&host->lock, flags);
2639
3560db8e
RK		 2640 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2641 sdhci_card_event(host->mmc);
2642 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2643 }
2644
781e989c
RK		 2645 if (isr & SDHCI_INT_CARD_INT) {
2646 sdio_run_irqs(host->mmc);
2647
2648 spin_lock_irqsave(&host->lock, flags);
2649 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2650 sdhci_enable_sdio_irq_nolock(host, true);
2651 spin_unlock_irqrestore(&host->lock, flags);
2652 }
2653
2654 return isr ? IRQ_HANDLED : IRQ_NONE;
2655}
2656
d129bceb
PO		 2657/*****************************************************************************\
2658 * *
2659 * Suspend/resume *
2660 * *
2661\*****************************************************************************/
2662
2663#ifdef CONFIG_PM
ad080d79
KL		 2664void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2665{
2666 u8 val;
2667 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2668 | SDHCI_WAKE_ON_INT;
2669
2670 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2671 val |= mask ;
2672 /* Avoid fake wake up */
2673 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2674 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2675 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2676}
2677EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2678
0b10f478 2679static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2680{
2681 u8 val;
2682 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2683 | SDHCI_WAKE_ON_INT;
2684
2685 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2686 val &= ~mask;
2687 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2688}
d129bceb 2689
29495aa0 2690int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2691{
7260cf5e
AV		 2692 sdhci_disable_card_detection(host);
2693
66c39dfc
AH		 2694 mmc_retune_timer_stop(host->mmc);
2695 mmc_retune_needed(host->mmc);
cf2b5eea 2696
ad080d79 2697 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2698 host->ier = 0;
2699 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2700 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2701 free_irq(host->irq, host);
2702 } else {
2703 sdhci_enable_irq_wakeups(host);
2704 enable_irq_wake(host->irq);
2705 }
4ee14ec6 2706 return 0;
d129bceb
PO		 2707}
2708
b8c86fc5 2709EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2710
b8c86fc5
PO		 2711int sdhci_resume_host(struct sdhci_host *host)
2712{
4ee14ec6 2713 int ret = 0;
d129bceb 2714
a13abc7b 2715 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2716 if (host->ops->enable_dma)
2717 host->ops->enable_dma(host);
2718 }
d129bceb 2719
ad080d79 2720 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2721 ret = request_threaded_irq(host->irq, sdhci_irq,
2722 sdhci_thread_irq, IRQF_SHARED,
2723 mmc_hostname(host->mmc), host);
ad080d79
KL		 2724 if (ret)
2725 return ret;
2726 } else {
2727 sdhci_disable_irq_wakeups(host);
2728 disable_irq_wake(host->irq);
2729 }
d129bceb 2730
6308d290
AH		 2731 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2732 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2733 /* Card keeps power but host controller does not */
2734 sdhci_init(host, 0);
2735 host->pwr = 0;
2736 host->clock = 0;
2737 sdhci_do_set_ios(host, &host->mmc->ios);
2738 } else {
2739 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2740 mmiowb();
2741 }
b8c86fc5 2742
7260cf5e
AV		 2743 sdhci_enable_card_detection(host);
2744
2f4cbb3d 2745 return ret;
d129bceb
PO		 2746}
2747
b8c86fc5 2748EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2749
2750static int sdhci_runtime_pm_get(struct sdhci_host *host)
2751{
2752 return pm_runtime_get_sync(host->mmc->parent);
2753}
2754
2755static int sdhci_runtime_pm_put(struct sdhci_host *host)
2756{
2757 pm_runtime_mark_last_busy(host->mmc->parent);
2758 return pm_runtime_put_autosuspend(host->mmc->parent);
2759}
2760
f0710a55
AH		 2761static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2762{
2763 if (host->runtime_suspended || host->bus_on)
2764 return;
2765 host->bus_on = true;
2766 pm_runtime_get_noresume(host->mmc->parent);
2767}
2768
2769static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2770{
2771 if (host->runtime_suspended || !host->bus_on)
2772 return;
2773 host->bus_on = false;
2774 pm_runtime_put_noidle(host->mmc->parent);
2775}
2776
66fd8ad5
AH		 2777int sdhci_runtime_suspend_host(struct sdhci_host *host)
2778{
2779 unsigned long flags;
66fd8ad5 2780
66c39dfc
AH		 2781 mmc_retune_timer_stop(host->mmc);
2782 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2783
2784 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2785 host->ier &= SDHCI_INT_CARD_INT;
2786 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2787 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2788 spin_unlock_irqrestore(&host->lock, flags);
2789
781e989c 2790 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2791
2792 spin_lock_irqsave(&host->lock, flags);
2793 host->runtime_suspended = true;
2794 spin_unlock_irqrestore(&host->lock, flags);
2795
8a125bad 2796 return 0;
66fd8ad5
AH		 2797}
2798EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2799
2800int sdhci_runtime_resume_host(struct sdhci_host *host)
2801{
2802 unsigned long flags;
8a125bad 2803 int host_flags = host->flags;
66fd8ad5
AH		 2804
2805 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2806 if (host->ops->enable_dma)
2807 host->ops->enable_dma(host);
2808 }
2809
2810 sdhci_init(host, 0);
2811
2812 /* Force clock and power re-program */
2813 host->pwr = 0;
2814 host->clock = 0;
3396e736 2815 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2816 sdhci_do_set_ios(host, &host->mmc->ios);
2817
52983382
KL		 2818 if ((host_flags & SDHCI_PV_ENABLED) &&
2819 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2820 spin_lock_irqsave(&host->lock, flags);
2821 sdhci_enable_preset_value(host, true);
2822 spin_unlock_irqrestore(&host->lock, flags);
2823 }
66fd8ad5 2824
66fd8ad5
AH		 2825 spin_lock_irqsave(&host->lock, flags);
2826
2827 host->runtime_suspended = false;
2828
2829 /* Enable SDIO IRQ */
ef104333 2830 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2831 sdhci_enable_sdio_irq_nolock(host, true);
2832
2833 /* Enable Card Detection */
2834 sdhci_enable_card_detection(host);
2835
2836 spin_unlock_irqrestore(&host->lock, flags);
2837
8a125bad 2838 return 0;
66fd8ad5
AH		 2839}
2840EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2841
162d6f98 2842#endif /* CONFIG_PM */
66fd8ad5 2843
d129bceb
PO		 2844/*****************************************************************************\
2845 * *
b8c86fc5 2846 * Device allocation/registration *
d129bceb
PO		 2847 * *
2848\*****************************************************************************/
2849
b8c86fc5
PO		 2850struct sdhci_host *sdhci_alloc_host(struct device *dev,
2851 size_t priv_size)
d129bceb 2852{
d129bceb
PO		 2853 struct mmc_host *mmc;
2854 struct sdhci_host *host;
2855
b8c86fc5 2856 WARN_ON(dev == NULL);
d129bceb 2857
b8c86fc5 2858 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2859 if (!mmc)
b8c86fc5 2860 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2861
2862 host = mmc_priv(mmc);
2863 host->mmc = mmc;
2864
b8c86fc5
PO		 2865 return host;
2866}
8a4da143 2867
b8c86fc5 2868EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2869
b8c86fc5
PO		 2870int sdhci_add_host(struct sdhci_host *host)
2871{
2872 struct mmc_host *mmc;
bd6a8c30 2873 u32 caps[2] = {0, 0};
f2119df6
AN		 2874 u32 max_current_caps;
2875 unsigned int ocr_avail;
f5fa92e5 2876 unsigned int override_timeout_clk;
59241757 2877 u32 max_clk;
b8c86fc5 2878 int ret;
d129bceb 2879
b8c86fc5
PO		 2880 WARN_ON(host == NULL);
2881 if (host == NULL)
2882 return -EINVAL;
d129bceb 2883
b8c86fc5 2884 mmc = host->mmc;
d129bceb 2885
b8c86fc5
PO		 2886 if (debug_quirks)
2887 host->quirks = debug_quirks;
66fd8ad5
AH		 2888 if (debug_quirks2)
2889 host->quirks2 = debug_quirks2;
d129bceb 2890
f5fa92e5
AH		 2891 override_timeout_clk = host->timeout_clk;
2892
03231f9b 2893 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2894
4e4141a5 2895 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2896 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2897 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2898 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2899 pr_err("%s: Unknown controller version (%d). "
b69c9058 2900 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2901 host->version);
4a965505
PO		 2902 }
2903
f2119df6 2904 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2905 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2906
bd6a8c30
PR		 2907 if (host->version >= SDHCI_SPEC_300)
2908 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2909 host->caps1 :
2910 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2911
b8c86fc5 2912 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2913 host->flags |= SDHCI_USE_SDMA;
f2119df6 2914 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2915 DBG("Controller doesn't have SDMA capability\n");
67435274 2916 else
a13abc7b 2917 host->flags |= SDHCI_USE_SDMA;
d129bceb 2918
b8c86fc5 2919 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2920 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2921 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2922 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2923 }
2924
f2119df6
AN		 2925 if ((host->version >= SDHCI_SPEC_200) &&
2926 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2927 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2928
2929 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2930 (host->flags & SDHCI_USE_ADMA)) {
2931 DBG("Disabling ADMA as it is marked broken\n");
2932 host->flags &= ~SDHCI_USE_ADMA;
2933 }
2934
e57a5f61
AH		 2935 /*
2936 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2937 * and *must* do 64-bit DMA. A driver has the opportunity to change
2938 * that during the first call to ->enable_dma(). Similarly
2939 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2940 * implement.
2941 */
2942 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2943 host->flags |= SDHCI_USE_64_BIT_DMA;
2944
a13abc7b 2945 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2946 if (host->ops->enable_dma) {
2947 if (host->ops->enable_dma(host)) {
6606110d 2948 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2949 mmc_hostname(mmc));
a13abc7b
RR		 2950 host->flags &=
2951 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2952 }
d129bceb
PO		 2953 }
2954 }
2955
e57a5f61
AH		 2956 /* SDMA does not support 64-bit DMA */
2957 if (host->flags & SDHCI_USE_64_BIT_DMA)
2958 host->flags &= ~SDHCI_USE_SDMA;
2959
2134a922
PO		 2960 if (host->flags & SDHCI_USE_ADMA) {
2961 /*
76fe379a
AH		 2962 * The DMA descriptor table size is calculated as the maximum
2963 * number of segments times 2, to allow for an alignment
2964 * descriptor for each segment, plus 1 for a nop end descriptor,
2965 * all multipled by the descriptor size.
2134a922 2966 */
e57a5f61
AH		 2967 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2968 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2969 SDHCI_ADMA2_64_DESC_SZ;
2970 host->align_buffer_sz = SDHCI_MAX_SEGS *
2971 SDHCI_ADMA2_64_ALIGN;
2972 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2973 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2974 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2975 } else {
2976 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2977 SDHCI_ADMA2_32_DESC_SZ;
2978 host->align_buffer_sz = SDHCI_MAX_SEGS *
2979 SDHCI_ADMA2_32_ALIGN;
2980 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2981 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2982 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2983 }
4efaa6fb 2984 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2985 host->adma_table_sz,
4efaa6fb
AH		 2986 &host->adma_addr,
2987 GFP_KERNEL);
76fe379a 2988 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 2989 if (!host->adma_table || !host->align_buffer) {
7ac02036
PF		 2990 if (host->adma_table)
2991 dma_free_coherent(mmc_dev(mmc),
2992 host->adma_table_sz,
2993 host->adma_table,
2994 host->adma_addr);
2134a922 2995 kfree(host->align_buffer);
6606110d 2996 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2997 mmc_hostname(mmc));
2998 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2999 host->adma_table = NULL;
d1e49f77 3000 host->align_buffer = NULL;
76fe379a 3001 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 3002 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3003 mmc_hostname(mmc));
d1e49f77 3004 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 3005 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3006 host->adma_table, host->adma_addr);
d1e49f77 3007 kfree(host->align_buffer);
4efaa6fb 3008 host->adma_table = NULL;
d1e49f77 3009 host->align_buffer = NULL;
2134a922
PO		 3010 }
3011 }
3012
7659150c
PO		 3013 /*
3014 * If we use DMA, then it's up to the caller to set the DMA
3015 * mask, but PIO does not need the hw shim so we set a new
3016 * mask here in that case.
3017 */
a13abc7b 3018 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3019 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3020 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3021 }
d129bceb 3022
c4687d5f 3023 if (host->version >= SDHCI_SPEC_300)
f2119df6 3024 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3025 >> SDHCI_CLOCK_BASE_SHIFT;
3026 else
f2119df6 3027 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3028 >> SDHCI_CLOCK_BASE_SHIFT;
3029
4240ff0a 3030 host->max_clk *= 1000000;
f27f47ef
AV		 3031 if (host->max_clk == 0 || host->quirks &
3032 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3033 if (!host->ops->get_max_clock) {
a3c76eb9 3034 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 3035 "frequency.\n", mmc_hostname(mmc));
3036 return -ENODEV;
3037 }
3038 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3039 }
d129bceb 3040
348487cb 3041 host->next_data.cookie = 1;
c3ed3877
AN		 3042 /*
3043 * In case of Host Controller v3.00, find out whether clock
3044 * multiplier is supported.
3045 */
3046 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3047 SDHCI_CLOCK_MUL_SHIFT;
3048
3049 /*
3050 * In case the value in Clock Multiplier is 0, then programmable
3051 * clock mode is not supported, otherwise the actual clock
3052 * multiplier is one more than the value of Clock Multiplier
3053 * in the Capabilities Register.
3054 */
3055 if (host->clk_mul)
3056 host->clk_mul += 1;
3057
d129bceb
PO		 3058 /*
3059 * Set host parameters.
3060 */
3061 mmc->ops = &sdhci_ops;
59241757
DA		 3062 max_clk = host->max_clk;
3063
ce5f036b 3064 if (host->ops->get_min_clock)
a9e58f25 3065 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3066 else if (host->version >= SDHCI_SPEC_300) {
3067 if (host->clk_mul) {
3068 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3069 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3070 } else
3071 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3072 } else
0397526d 3073 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3074
59241757
DA		 3075 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3076 mmc->f_max = max_clk;
3077
28aab053
AD		 3078 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3079 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3080 SDHCI_TIMEOUT_CLK_SHIFT;
3081 if (host->timeout_clk == 0) {
3082 if (host->ops->get_timeout_clock) {
3083 host->timeout_clk =
3084 host->ops->get_timeout_clock(host);
3085 } else {
3086 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3087 mmc_hostname(mmc));
3088 return -ENODEV;
3089 }
272308ca 3090 }
272308ca 3091
28aab053
AD		 3092 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3093 host->timeout_clk *= 1000;
272308ca 3094
28aab053 3095 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3096 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3097 mmc->max_busy_timeout /= host->timeout_clk;
3098 }
58d1246d 3099
f5fa92e5
AH		 3100 if (override_timeout_clk)
3101 host->timeout_clk = override_timeout_clk;
3102
e89d456f 3103 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3104 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3105
3106 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3107 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3108
8edf6371 3109 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3110 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3111 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3112 !(host->flags & SDHCI_USE_SDMA)) &&
3113 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3114 host->flags |= SDHCI_AUTO_CMD23;
3115 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3116 } else {
3117 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3118 }
3119
15ec4461
PR		 3120 /*
3121 * A controller may support 8-bit width, but the board itself
3122 * might not have the pins brought out. Boards that support
3123 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3124 * their platform code before calling sdhci_add_host(), and we
3125 * won't assume 8-bit width for hosts without that CAP.
3126 */
5fe23c7f 3127 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3128 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3129
63ef5d8c
JH		 3130 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3131 mmc->caps &= ~MMC_CAP_CMD23;
3132
f2119df6 3133 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3134 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3135
176d1ed4 3136 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3137 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3138 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3139 mmc->caps |= MMC_CAP_NEEDS_POLL;
3140
3a48edc4
TK		 3141 /* If there are external regulators, get them */
3142 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3143 return -EPROBE_DEFER;
3144
6231f3de 3145 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3146 if (!IS_ERR(mmc->supply.vqmmc)) {
3147 ret = regulator_enable(mmc->supply.vqmmc);
3148 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3149 1950000))
8363c374
KL		 3150 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3151 SDHCI_SUPPORT_SDR50 |
3152 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3153 if (ret) {
3154 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3155 mmc_hostname(mmc), ret);
4bb74313 3156 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3157 }
8363c374 3158 }
6231f3de 3159
6a66180a
DD		 3160 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3161 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3162 SDHCI_SUPPORT_DDR50);
3163
4188bba0
AC		 3164 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3165 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3166 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3167 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3168
3169 /* SDR104 supports also implies SDR50 support */
156e14b1 3170 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3171 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3172 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3173 * field can be promoted to support HS200.
3174 */
549c0b18 3175 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3176 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3177 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3178 mmc->caps |= MMC_CAP_UHS_SDR50;
3179
e9fb05d5
AH		 3180 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3181 (caps[1] & SDHCI_SUPPORT_HS400))
3182 mmc->caps2 |= MMC_CAP2_HS400;
3183
549c0b18
AH		 3184 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3185 (IS_ERR(mmc->supply.vqmmc) ||
3186 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3187 1300000)))
3188 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3189
9107ebbf
MC		 3190 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3191 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3192 mmc->caps |= MMC_CAP_UHS_DDR50;
3193
069c9f14 3194 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3195 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3196 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3197
156e14b1 3198 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3199 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3200 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3201
d6d50a15
AN		 3202 /* Driver Type(s) (A, C, D) supported by the host */
3203 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3204 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3205 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3206 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3207 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3208 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3209
cf2b5eea
AN		 3210 /* Initial value for re-tuning timer count */
3211 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3212 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3213
3214 /*
3215 * In case Re-tuning Timer is not disabled, the actual value of
3216 * re-tuning timer will be 2 ^ (n - 1).
3217 */
3218 if (host->tuning_count)
3219 host->tuning_count = 1 << (host->tuning_count - 1);
3220
3221 /* Re-tuning mode supported by the Host Controller */
3222 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3223 SDHCI_RETUNING_MODE_SHIFT;
3224
8f230f45 3225 ocr_avail = 0;
bad37e1a 3226
f2119df6
AN		 3227 /*
3228 * According to SD Host Controller spec v3.00, if the Host System
3229 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3230 * the value is meaningful only if Voltage Support in the Capabilities
3231 * register is set. The actual current value is 4 times the register
3232 * value.
3233 */
3234 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3235 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3236 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3237 if (curr > 0) {
3238
3239 /* convert to SDHCI_MAX_CURRENT format */
3240 curr = curr/1000; /* convert to mA */
3241 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3242
3243 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3244 max_current_caps =
3245 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3246 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3247 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3248 }
3249 }
f2119df6
AN		 3250
3251 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3252 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3253
55c4665e 3254 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3255 SDHCI_MAX_CURRENT_330_MASK) >>
3256 SDHCI_MAX_CURRENT_330_SHIFT) *
3257 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3258 }
3259 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3260 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3261
55c4665e 3262 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3263 SDHCI_MAX_CURRENT_300_MASK) >>
3264 SDHCI_MAX_CURRENT_300_SHIFT) *
3265 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3266 }
3267 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3268 ocr_avail |= MMC_VDD_165_195;
3269
55c4665e 3270 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3271 SDHCI_MAX_CURRENT_180_MASK) >>
3272 SDHCI_MAX_CURRENT_180_SHIFT) *
3273 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3274 }
3275
5fd26c7e
UH		 3276 /* If OCR set by host, use it instead. */
3277 if (host->ocr_mask)
3278 ocr_avail = host->ocr_mask;
3279
3280 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3281 if (mmc->ocr_avail)
52221610 3282 ocr_avail = mmc->ocr_avail;
3a48edc4 3283
8f230f45
TI		 3284 mmc->ocr_avail = ocr_avail;
3285 mmc->ocr_avail_sdio = ocr_avail;
3286 if (host->ocr_avail_sdio)
3287 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3288 mmc->ocr_avail_sd = ocr_avail;
3289 if (host->ocr_avail_sd)
3290 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3291 else /* normal SD controllers don't support 1.8V */
3292 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3293 mmc->ocr_avail_mmc = ocr_avail;
3294 if (host->ocr_avail_mmc)
3295 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3296
3297 if (mmc->ocr_avail == 0) {
a3c76eb9 3298 pr_err("%s: Hardware doesn't report any "
b69c9058 3299 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3300 return -ENODEV;
146ad66e
PO		 3301 }
3302
d129bceb
PO		 3303 spin_lock_init(&host->lock);
3304
3305 /*
2134a922
PO		 3306 * Maximum number of segments. Depends on if the hardware
3307 * can do scatter/gather or not.
d129bceb 3308 */
2134a922 3309 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3310 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3311 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3312 mmc->max_segs = 1;
2134a922 3313 else /* PIO */
4fb213f8 3314 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3315
3316 /*
ac00531d
AH		 3317 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3318 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3319 * is less anyway.
d129bceb 3320 */
55db890a 3321 mmc->max_req_size = 524288;
d129bceb
PO		 3322
3323 /*
3324 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3325 * of bytes. When doing hardware scatter/gather, each entry cannot
3326 * be larger than 64 KiB though.
d129bceb 3327 */
30652aa3
OJ		 3328 if (host->flags & SDHCI_USE_ADMA) {
3329 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3330 mmc->max_seg_size = 65535;
3331 else
3332 mmc->max_seg_size = 65536;
3333 } else {
2134a922 3334 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3335 }
d129bceb 3336
fe4a3c7a
PO		 3337 /*
3338 * Maximum block size. This varies from controller to controller and
3339 * is specified in the capabilities register.
3340 */
0633f654
AV		 3341 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3342 mmc->max_blk_size = 2;
3343 } else {
f2119df6 3344 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3345 SDHCI_MAX_BLOCK_SHIFT;
3346 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3347 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3348 mmc_hostname(mmc));
0633f654
AV		 3349 mmc->max_blk_size = 0;
3350 }
3351 }
3352
3353 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3354
55db890a
PO		 3355 /*
3356 * Maximum block count.
3357 */
1388eefd 3358 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3359
d129bceb
PO		 3360 /*
3361 * Init tasklets.
3362 */
d129bceb
PO		 3363 tasklet_init(&host->finish_tasklet,
3364 sdhci_tasklet_finish, (unsigned long)host);
3365
e4cad1b5 3366 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3367
250fb7b4 3368 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3369
2af502ca
SG		 3370 sdhci_init(host, 0);
3371
781e989c
RK		 3372 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3373 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3374 if (ret) {
3375 pr_err("%s: Failed to request IRQ %d: %d\n",
3376 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3377 goto untasklet;
0fc81ee3 3378 }
d129bceb 3379
d129bceb
PO		 3380#ifdef CONFIG_MMC_DEBUG
3381 sdhci_dumpregs(host);
3382#endif
3383
f9134319 3384#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3385 snprintf(host->led_name, sizeof(host->led_name),
3386 "%s::", mmc_hostname(mmc));
3387 host->led.name = host->led_name;
2f730fec
PO		 3388 host->led.brightness = LED_OFF;
3389 host->led.default_trigger = mmc_hostname(mmc);
3390 host->led.brightness_set = sdhci_led_control;
3391
b8c86fc5 3392 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3393 if (ret) {
3394 pr_err("%s: Failed to register LED device: %d\n",
3395 mmc_hostname(mmc), ret);
2f730fec 3396 goto reset;
0fc81ee3 3397 }
2f730fec
PO		 3398#endif
3399
5f25a66f
PO		 3400 mmiowb();
3401
d129bceb
PO		 3402 mmc_add_host(mmc);
3403
a3c76eb9 3404 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3405 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3406 (host->flags & SDHCI_USE_ADMA) ?
3407 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3408 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3409
7260cf5e
AV		 3410 sdhci_enable_card_detection(host);
3411
d129bceb
PO		 3412 return 0;
3413
f9134319 3414#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3415reset:
03231f9b 3416 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3417 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3418 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3419 free_irq(host->irq, host);
3420#endif
8ef1a143 3421untasklet:
d129bceb 3422 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3423
3424 return ret;
3425}
3426
b8c86fc5 3427EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3428
1e72859e 3429void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3430{
3a48edc4 3431 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3432 unsigned long flags;
3433
3434 if (dead) {
3435 spin_lock_irqsave(&host->lock, flags);
3436
3437 host->flags |= SDHCI_DEVICE_DEAD;
3438
3439 if (host->mrq) {
a3c76eb9 3440 pr_err("%s: Controller removed during "
4e743f1f 3441 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3442
3443 host->mrq->cmd->error = -ENOMEDIUM;
3444 tasklet_schedule(&host->finish_tasklet);
3445 }
3446
3447 spin_unlock_irqrestore(&host->lock, flags);
3448 }
3449
7260cf5e
AV		 3450 sdhci_disable_card_detection(host);
3451
4e743f1f 3452 mmc_remove_host(mmc);
d129bceb 3453
f9134319 3454#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3455 led_classdev_unregister(&host->led);
3456#endif
3457
1e72859e 3458 if (!dead)
03231f9b 3459 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3460
b537f94c
RK		 3461 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3462 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3463 free_irq(host->irq, host);
3464
3465 del_timer_sync(&host->timer);
3466
d129bceb 3467 tasklet_kill(&host->finish_tasklet);
2134a922 3468
3a48edc4
TK		 3469 if (!IS_ERR(mmc->supply.vqmmc))
3470 regulator_disable(mmc->supply.vqmmc);
6231f3de 3471
4efaa6fb 3472 if (host->adma_table)
76fe379a 3473 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3474 host->adma_table, host->adma_addr);
2134a922
PO		 3475 kfree(host->align_buffer);
3476
4efaa6fb 3477 host->adma_table = NULL;
2134a922 3478 host->align_buffer = NULL;
d129bceb
PO		 3479}
3480
b8c86fc5 3481EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3482
b8c86fc5 3483void sdhci_free_host(struct sdhci_host *host)
d129bceb 3484{
b8c86fc5 3485 mmc_free_host(host->mmc);
d129bceb
PO		 3486}
3487
b8c86fc5 3488EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3489
3490/*****************************************************************************\
3491 * *
3492 * Driver init/exit *
3493 * *
3494\*****************************************************************************/
3495
3496static int __init sdhci_drv_init(void)
3497{
a3c76eb9 3498 pr_info(DRIVER_NAME
52fbf9c9 3499 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3500 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3501
b8c86fc5 3502 return 0;
d129bceb
PO		 3503}
3504
3505static void __exit sdhci_drv_exit(void)
3506{
d129bceb
PO		 3507}
3508
3509module_init(sdhci_drv_init);
3510module_exit(sdhci_drv_exit);
3511
df673b22 3512module_param(debug_quirks, uint, 0444);
66fd8ad5 3513module_param(debug_quirks2, uint, 0444);
67435274 3514
32710e8f 3515MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3516MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3517MODULE_LICENSE("GPL");
67435274 3518
df673b22 3519MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3520MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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