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mmc: sdhci: Record what command is using the data lines
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
66fd8ad5 44static unsigned int debug_quirks2;
67435274 45
d129bceb
PO		 46static void sdhci_finish_data(struct sdhci_host *);
47
52983382 48static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
a7c53671
CD		 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb 54
a7c53671
CD		 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
e57a5f61
AH		 91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 97 else
a7c53671
CD		 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 101 }
be3f4ae0 102
a7c53671 103 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 104}
105
106/*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110\*****************************************************************************/
111
7260cf5e
AV		 112static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
113{
5b4f1f6c 114 u32 present;
7260cf5e 115
c79396c1 116 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 117 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 118 return;
119
5b4f1f6c
RK		 120 if (enable) {
121 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
122 SDHCI_CARD_PRESENT;
d25928d1 123
5b4f1f6c
RK		 124 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
125 SDHCI_INT_CARD_INSERT;
126 } else {
127 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
128 }
b537f94c
RK		 129
130 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
131 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 132}
133
134static void sdhci_enable_card_detection(struct sdhci_host *host)
135{
136 sdhci_set_card_detection(host, true);
137}
138
139static void sdhci_disable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, false);
142}
143
02d0b685
UH		 144static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
145{
146 if (host->bus_on)
147 return;
148 host->bus_on = true;
149 pm_runtime_get_noresume(host->mmc->parent);
150}
151
152static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
153{
154 if (!host->bus_on)
155 return;
156 host->bus_on = false;
157 pm_runtime_put_noidle(host->mmc->parent);
158}
159
03231f9b 160void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 161{
e16514d8 162 unsigned long timeout;
393c1a34 163
4e4141a5 164 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 165
f0710a55 166 if (mask & SDHCI_RESET_ALL) {
d129bceb 167 host->clock = 0;
f0710a55
AH		 168 /* Reset-all turns off SD Bus Power */
169 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
170 sdhci_runtime_pm_bus_off(host);
171 }
d129bceb 172
e16514d8
PO		 173 /* Wait max 100 ms */
174 timeout = 100;
175
176 /* hw clears the bit when it's done */
4e4141a5 177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 178 if (timeout == 0) {
a3c76eb9 179 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 180 mmc_hostname(host->mmc), (int)mask);
181 sdhci_dumpregs(host);
182 return;
183 }
184 timeout--;
185 mdelay(1);
d129bceb 186 }
03231f9b
RK		 187}
188EXPORT_SYMBOL_GPL(sdhci_reset);
189
190static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
191{
192 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 193 struct mmc_host *mmc = host->mmc;
194
195 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 196 return;
197 }
063a9dbb 198
03231f9b 199 host->ops->reset(host, mask);
393c1a34 200
da91a8f9
RK		 201 if (mask & SDHCI_RESET_ALL) {
202 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
203 if (host->ops->enable_dma)
204 host->ops->enable_dma(host);
205 }
206
207 /* Resetting the controller clears many */
208 host->preset_enabled = false;
3abc1e80 209 }
d129bceb
PO		 210}
211
2f4cbb3d 212static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 213{
d3940f27
AH		 214 struct mmc_host *mmc = host->mmc;
215
2f4cbb3d 216 if (soft)
03231f9b 217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 218 else
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 220
b537f94c
RK		 221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
225 SDHCI_INT_RESPONSE;
226
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 229
230 if (soft) {
231 /* force clock reconfiguration */
232 host->clock = 0;
d3940f27 233 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 234 }
7260cf5e 235}
d129bceb 236
7260cf5e
AV		 237static void sdhci_reinit(struct sdhci_host *host)
238{
2f4cbb3d 239 sdhci_init(host, 0);
7260cf5e 240 sdhci_enable_card_detection(host);
d129bceb
PO		 241}
242
061d17a6 243static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 244{
245 u8 ctrl;
246
4e4141a5 247 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 248 ctrl |= SDHCI_CTRL_LED;
4e4141a5 249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 250}
251
061d17a6 252static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 253{
254 u8 ctrl;
255
4e4141a5 256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 257 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 259}
260
4f78230f 261#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 262static void sdhci_led_control(struct led_classdev *led,
061d17a6 263 enum led_brightness brightness)
2f730fec
PO		 264{
265 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
266 unsigned long flags;
267
268 spin_lock_irqsave(&host->lock, flags);
269
66fd8ad5
AH		 270 if (host->runtime_suspended)
271 goto out;
272
2f730fec 273 if (brightness == LED_OFF)
061d17a6 274 __sdhci_led_deactivate(host);
2f730fec 275 else
061d17a6 276 __sdhci_led_activate(host);
66fd8ad5 277out:
2f730fec
PO		 278 spin_unlock_irqrestore(&host->lock, flags);
279}
061d17a6
AH		 280
281static int sdhci_led_register(struct sdhci_host *host)
282{
283 struct mmc_host *mmc = host->mmc;
284
285 snprintf(host->led_name, sizeof(host->led_name),
286 "%s::", mmc_hostname(mmc));
287
288 host->led.name = host->led_name;
289 host->led.brightness = LED_OFF;
290 host->led.default_trigger = mmc_hostname(mmc);
291 host->led.brightness_set = sdhci_led_control;
292
293 return led_classdev_register(mmc_dev(mmc), &host->led);
294}
295
296static void sdhci_led_unregister(struct sdhci_host *host)
297{
298 led_classdev_unregister(&host->led);
299}
300
301static inline void sdhci_led_activate(struct sdhci_host *host)
302{
303}
304
305static inline void sdhci_led_deactivate(struct sdhci_host *host)
306{
307}
308
309#else
310
311static inline int sdhci_led_register(struct sdhci_host *host)
312{
313 return 0;
314}
315
316static inline void sdhci_led_unregister(struct sdhci_host *host)
317{
318}
319
320static inline void sdhci_led_activate(struct sdhci_host *host)
321{
322 __sdhci_led_activate(host);
323}
324
325static inline void sdhci_led_deactivate(struct sdhci_host *host)
326{
327 __sdhci_led_deactivate(host);
328}
329
2f730fec
PO		 330#endif
331
d129bceb
PO		 332/*****************************************************************************\
333 * *
334 * Core functions *
335 * *
336\*****************************************************************************/
337
a406f5a3 338static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 339{
7659150c
PO		 340 unsigned long flags;
341 size_t blksize, len, chunk;
7244b85b 342 u32 uninitialized_var(scratch);
7659150c 343 u8 *buf;
d129bceb 344
a406f5a3 345 DBG("PIO reading\n");
d129bceb 346
a406f5a3 347 blksize = host->data->blksz;
7659150c 348 chunk = 0;
d129bceb 349
7659150c 350 local_irq_save(flags);
d129bceb 351
a406f5a3 352 while (blksize) {
bf3a35ac 353 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 354
7659150c 355 len = min(host->sg_miter.length, blksize);
d129bceb 356
7659150c
PO		 357 blksize -= len;
358 host->sg_miter.consumed = len;
14d836e7 359
7659150c 360 buf = host->sg_miter.addr;
d129bceb 361
7659150c
PO		 362 while (len) {
363 if (chunk == 0) {
4e4141a5 364 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 365 chunk = 4;
a406f5a3 366 }
7659150c
PO		 367
368 *buf = scratch & 0xFF;
369
370 buf++;
371 scratch >>= 8;
372 chunk--;
373 len--;
d129bceb 374 }
a406f5a3 375 }
7659150c
PO		 376
377 sg_miter_stop(&host->sg_miter);
378
379 local_irq_restore(flags);
a406f5a3 380}
d129bceb 381
a406f5a3
PO		 382static void sdhci_write_block_pio(struct sdhci_host *host)
383{
7659150c
PO		 384 unsigned long flags;
385 size_t blksize, len, chunk;
386 u32 scratch;
387 u8 *buf;
d129bceb 388
a406f5a3
PO		 389 DBG("PIO writing\n");
390
391 blksize = host->data->blksz;
7659150c
PO		 392 chunk = 0;
393 scratch = 0;
d129bceb 394
7659150c 395 local_irq_save(flags);
d129bceb 396
a406f5a3 397 while (blksize) {
bf3a35ac 398 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 399
7659150c
PO		 400 len = min(host->sg_miter.length, blksize);
401
402 blksize -= len;
403 host->sg_miter.consumed = len;
404
405 buf = host->sg_miter.addr;
d129bceb 406
7659150c
PO		 407 while (len) {
408 scratch |= (u32)*buf << (chunk * 8);
409
410 buf++;
411 chunk++;
412 len--;
413
414 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 415 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 416 chunk = 0;
417 scratch = 0;
d129bceb 418 }
d129bceb
PO		 419 }
420 }
7659150c
PO		 421
422 sg_miter_stop(&host->sg_miter);
423
424 local_irq_restore(flags);
a406f5a3
PO		 425}
426
427static void sdhci_transfer_pio(struct sdhci_host *host)
428{
429 u32 mask;
430
7659150c 431 if (host->blocks == 0)
a406f5a3
PO		 432 return;
433
434 if (host->data->flags & MMC_DATA_READ)
435 mask = SDHCI_DATA_AVAILABLE;
436 else
437 mask = SDHCI_SPACE_AVAILABLE;
438
4a3cba32
PO		 439 /*
440 * Some controllers (JMicron JMB38x) mess up the buffer bits
441 * for transfers < 4 bytes. As long as it is just one block,
442 * we can ignore the bits.
443 */
444 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
445 (host->data->blocks == 1))
446 mask = ~0;
447
4e4141a5 448 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 449 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
450 udelay(100);
451
a406f5a3
PO		 452 if (host->data->flags & MMC_DATA_READ)
453 sdhci_read_block_pio(host);
454 else
455 sdhci_write_block_pio(host);
d129bceb 456
7659150c
PO		 457 host->blocks--;
458 if (host->blocks == 0)
a406f5a3 459 break;
a406f5a3 460 }
d129bceb 461
a406f5a3 462 DBG("PIO transfer complete.\n");
d129bceb
PO		 463}
464
48857d9b 465static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 466 struct mmc_data *data, int cookie)
48857d9b
RK		 467{
468 int sg_count;
469
94538e51
RK		 470 /*
471 * If the data buffers are already mapped, return the previous
472 * dma_map_sg() result.
473 */
474 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 475 return data->sg_count;
48857d9b
RK		 476
477 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
478 data->flags & MMC_DATA_WRITE ?
479 DMA_TO_DEVICE : DMA_FROM_DEVICE);
480
481 if (sg_count == 0)
482 return -ENOSPC;
483
484 data->sg_count = sg_count;
c0999b72 485 data->host_cookie = cookie;
48857d9b
RK		 486
487 return sg_count;
488}
489
2134a922
PO		 490static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
491{
492 local_irq_save(*flags);
482fce99 493 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 494}
495
496static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
497{
482fce99 498 kunmap_atomic(buffer);
2134a922
PO		 499 local_irq_restore(*flags);
500}
501
e57a5f61
AH		 502static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
503 dma_addr_t addr, int len, unsigned cmd)
118cd17d 504{
e57a5f61 505 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 506
e57a5f61 507 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 508 dma_desc->cmd = cpu_to_le16(cmd);
509 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 510 dma_desc->addr_lo = cpu_to_le32((u32)addr);
511
512 if (host->flags & SDHCI_USE_64_BIT_DMA)
513 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 514}
515
b5ffa674
AH		 516static void sdhci_adma_mark_end(void *desc)
517{
e57a5f61 518 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 519
e57a5f61 520 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 521 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 522}
523
60c64762
RK		 524static void sdhci_adma_table_pre(struct sdhci_host *host,
525 struct mmc_data *data, int sg_count)
2134a922 526{
2134a922 527 struct scatterlist *sg;
2134a922 528 unsigned long flags;
acc3ad13
RK		 529 dma_addr_t addr, align_addr;
530 void *desc, *align;
531 char *buffer;
532 int len, offset, i;
2134a922
PO		 533
534 /*
535 * The spec does not specify endianness of descriptor table.
536 * We currently guess that it is LE.
537 */
538
60c64762 539 host->sg_count = sg_count;
2134a922 540
4efaa6fb 541 desc = host->adma_table;
2134a922
PO		 542 align = host->align_buffer;
543
544 align_addr = host->align_addr;
545
546 for_each_sg(data->sg, sg, host->sg_count, i) {
547 addr = sg_dma_address(sg);
548 len = sg_dma_len(sg);
549
550 /*
acc3ad13
RK		 551 * The SDHCI specification states that ADMA addresses must
552 * be 32-bit aligned. If they aren't, then we use a bounce
553 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 554 * alignment.
555 */
04a5ae6f
AH		 556 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
557 SDHCI_ADMA2_MASK;
2134a922
PO		 558 if (offset) {
559 if (data->flags & MMC_DATA_WRITE) {
560 buffer = sdhci_kmap_atomic(sg, &flags);
561 memcpy(align, buffer, offset);
562 sdhci_kunmap_atomic(buffer, &flags);
563 }
564
118cd17d 565 /* tran, valid */
e57a5f61 566 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 567 ADMA2_TRAN_VALID);
2134a922
PO		 568
569 BUG_ON(offset > 65536);
570
04a5ae6f
AH		 571 align += SDHCI_ADMA2_ALIGN;
572 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 573
76fe379a 574 desc += host->desc_sz;
2134a922
PO		 575
576 addr += offset;
577 len -= offset;
578 }
579
2134a922
PO		 580 BUG_ON(len > 65536);
581
347ea32d
AH		 582 if (len) {
583 /* tran, valid */
584 sdhci_adma_write_desc(host, desc, addr, len,
585 ADMA2_TRAN_VALID);
586 desc += host->desc_sz;
587 }
2134a922
PO		 588
589 /*
590 * If this triggers then we have a calculation bug
591 * somewhere. :/
592 */
76fe379a 593 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 594 }
595
70764a90 596 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 597 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 598 if (desc != host->adma_table) {
76fe379a 599 desc -= host->desc_sz;
b5ffa674 600 sdhci_adma_mark_end(desc);
70764a90
TA		 601 }
602 } else {
acc3ad13 603 /* Add a terminating entry - nop, end, valid */
e57a5f61 604 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 605 }
2134a922
PO		 606}
607
608static void sdhci_adma_table_post(struct sdhci_host *host,
609 struct mmc_data *data)
610{
2134a922
PO		 611 struct scatterlist *sg;
612 int i, size;
1c3d5f6d 613 void *align;
2134a922
PO		 614 char *buffer;
615 unsigned long flags;
616
47fa9613
RK		 617 if (data->flags & MMC_DATA_READ) {
618 bool has_unaligned = false;
de0b65a7 619
47fa9613
RK		 620 /* Do a quick scan of the SG list for any unaligned mappings */
621 for_each_sg(data->sg, sg, host->sg_count, i)
622 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
623 has_unaligned = true;
624 break;
625 }
2134a922 626
47fa9613
RK		 627 if (has_unaligned) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 629 data->sg_len, DMA_FROM_DEVICE);
2134a922 630
47fa9613 631 align = host->align_buffer;
2134a922 632
47fa9613
RK		 633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
635 size = SDHCI_ADMA2_ALIGN -
636 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
637
638 buffer = sdhci_kmap_atomic(sg, &flags);
639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
2134a922 641
47fa9613
RK		 642 align += SDHCI_ADMA2_ALIGN;
643 }
2134a922
PO		 644 }
645 }
646 }
2134a922
PO		 647}
648
a3c7778f 649static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 650{
1c8cde92 651 u8 count;
a3c7778f 652 struct mmc_data *data = cmd->data;
1c8cde92 653 unsigned target_timeout, current_timeout;
d129bceb 654
ee53ab5d
PO		 655 /*
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
659 * timeout value.
660 */
11a2f1b7 661 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 662 return 0xE;
e538fbe8 663
a3c7778f 664 /* Unspecified timeout, assume max */
1d4d7744 665 if (!data && !cmd->busy_timeout)
a3c7778f 666 return 0xE;
d129bceb 667
a3c7778f
AW		 668 /* timeout in us */
669 if (!data)
1d4d7744 670 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 671 else {
fafcfda9 672 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 673 if (host->clock && data->timeout_clks) {
674 unsigned long long val;
675
676 /*
677 * data->timeout_clks is in units of clock cycles.
678 * host->clock is in Hz. target_timeout is in us.
679 * Hence, us = 1000000 * cycles / Hz. Round up.
680 */
681 val = 1000000 * data->timeout_clks;
682 if (do_div(val, host->clock))
683 target_timeout++;
684 target_timeout += val;
685 }
78a2ca27 686 }
81b39802 687
1c8cde92
PO		 688 /*
689 * Figure out needed cycles.
690 * We do this in steps in order to fit inside a 32 bit int.
691 * The first step is the minimum timeout, which will have a
692 * minimum resolution of 6 bits:
693 * (1) 2^13*1000 > 2^22,
694 * (2) host->timeout_clk < 2^16
695 * =>
696 * (1) / (2) > 2^6
697 */
698 count = 0;
699 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
700 while (current_timeout < target_timeout) {
701 count++;
702 current_timeout <<= 1;
703 if (count >= 0xF)
704 break;
705 }
706
707 if (count >= 0xF) {
09eeff52
CB		 708 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
709 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 710 count = 0xE;
711 }
712
ee53ab5d
PO		 713 return count;
714}
715
6aa943ab
AV		 716static void sdhci_set_transfer_irqs(struct sdhci_host *host)
717{
718 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
719 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
720
721 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 722 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 723 else
b537f94c
RK		 724 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
725
726 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
727 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 728}
729
b45e668a 730static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 731{
732 u8 count;
b45e668a
AD		 733
734 if (host->ops->set_timeout) {
735 host->ops->set_timeout(host, cmd);
736 } else {
737 count = sdhci_calc_timeout(host, cmd);
738 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
739 }
740}
741
742static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
743{
2134a922 744 u8 ctrl;
a3c7778f 745 struct mmc_data *data = cmd->data;
ee53ab5d
PO		 746
747 WARN_ON(host->data);
748
b45e668a
AD		 749 if (data || (cmd->flags & MMC_RSP_BUSY))
750 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 751
752 if (!data)
ee53ab5d
PO		 753 return;
754
755 /* Sanity checks */
756 BUG_ON(data->blksz * data->blocks > 524288);
757 BUG_ON(data->blksz > host->mmc->max_blk_size);
758 BUG_ON(data->blocks > 65535);
759
760 host->data = data;
761 host->data_early = 0;
f6a03cbf 762 host->data->bytes_xfered = 0;
ee53ab5d 763
fce14421 764 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 765 struct scatterlist *sg;
df953925 766 unsigned int length_mask, offset_mask;
a0eaf0f9 767 int i;
2134a922 768
fce14421
RK		 769 host->flags |= SDHCI_REQ_USE_DMA;
770
771 /*
772 * FIXME: This doesn't account for merging when mapping the
773 * scatterlist.
774 *
775 * The assumption here being that alignment and lengths are
776 * the same after DMA mapping to device address space.
777 */
a0eaf0f9 778 length_mask = 0;
df953925 779 offset_mask = 0;
2134a922 780 if (host->flags & SDHCI_USE_ADMA) {
df953925 781 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 782 length_mask = 3;
df953925
RK		 783 /*
784 * As we use up to 3 byte chunks to work
785 * around alignment problems, we need to
786 * check the offset as well.
787 */
788 offset_mask = 3;
789 }
2134a922
PO		 790 } else {
791 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 792 length_mask = 3;
df953925
RK		 793 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
794 offset_mask = 3;
2134a922
PO		 795 }
796
df953925 797 if (unlikely(length_mask | offset_mask)) {
2134a922 798 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 799 if (sg->length & length_mask) {
2e4456f0 800 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 801 sg->length);
2134a922
PO		 802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 break;
804 }
a0eaf0f9 805 if (sg->offset & offset_mask) {
2e4456f0 806 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 }
811 }
812 }
813
8f1934ce 814 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 815 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 816
817 if (sg_cnt <= 0) {
818 /*
819 * This only happens when someone fed
820 * us an invalid request.
821 */
822 WARN_ON(1);
823 host->flags &= ~SDHCI_REQ_USE_DMA;
824 } else if (host->flags & SDHCI_USE_ADMA) {
825 sdhci_adma_table_pre(host, data, sg_cnt);
826
827 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 832 } else {
60c64762
RK		 833 WARN_ON(sg_cnt != 1);
834 sdhci_writel(host, sg_dma_address(data->sg),
835 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 836 }
837 }
838
2134a922
PO		 839 /*
840 * Always adjust the DMA selection as some controllers
841 * (e.g. JMicron) can't do PIO properly when the selection
842 * is ADMA.
843 */
844 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 845 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 846 ctrl &= ~SDHCI_CTRL_DMA_MASK;
847 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 848 (host->flags & SDHCI_USE_ADMA)) {
849 if (host->flags & SDHCI_USE_64_BIT_DMA)
850 ctrl |= SDHCI_CTRL_ADMA64;
851 else
852 ctrl |= SDHCI_CTRL_ADMA32;
853 } else {
2134a922 854 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 855 }
4e4141a5 856 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 857 }
858
8f1934ce 859 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 860 int flags;
861
862 flags = SG_MITER_ATOMIC;
863 if (host->data->flags & MMC_DATA_READ)
864 flags |= SG_MITER_TO_SG;
865 else
866 flags |= SG_MITER_FROM_SG;
867 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 868 host->blocks = data->blocks;
d129bceb 869 }
c7fa9963 870
6aa943ab
AV		 871 sdhci_set_transfer_irqs(host);
872
f6a03cbf
MV		 873 /* Set the DMA boundary value and block size */
874 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
875 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 876 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 877}
878
879static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 880 struct mmc_command *cmd)
c7fa9963 881{
d3fc5d71 882 u16 mode = 0;
e89d456f 883 struct mmc_data *data = cmd->data;
c7fa9963 884
2b558c13 885 if (data == NULL) {
9b8ffea6
VW		 886 if (host->quirks2 &
887 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
888 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
889 } else {
2b558c13 890 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 891 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
892 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 893 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 894 }
c7fa9963 895 return;
2b558c13 896 }
c7fa9963 897
e538fbe8
PO		 898 WARN_ON(!host->data);
899
d3fc5d71
VY		 900 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902
e89d456f 903 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 904 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 905 /*
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
908 */
85cc1c33
CD		 909 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
910 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 911 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 912 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
913 mode |= SDHCI_TRNS_AUTO_CMD23;
914 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
915 }
c4512f79 916 }
8edf6371 917
c7fa9963
PO		 918 if (data->flags & MMC_DATA_READ)
919 mode |= SDHCI_TRNS_READ;
c9fddbc4 920 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 921 mode |= SDHCI_TRNS_DMA;
922
4e4141a5 923 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 924}
925
926static void sdhci_finish_data(struct sdhci_host *host)
927{
928 struct mmc_data *data;
d129bceb 929
d129bceb
PO		 930 data = host->data;
931 host->data = NULL;
7c89a3d9 932 host->data_cmd = NULL;
d129bceb 933
add8913d
RK		 934 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
935 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
936 sdhci_adma_table_post(host, data);
d129bceb
PO		 937
938 /*
c9b74c5b
PO		 939 * The specification states that the block count register must
940 * be updated, but it does not specify at what point in the
941 * data flow. That makes the register entirely useless to read
942 * back so we have to assume that nothing made it to the card
943 * in the event of an error.
d129bceb 944 */
c9b74c5b
PO		 945 if (data->error)
946 data->bytes_xfered = 0;
d129bceb 947 else
c9b74c5b 948 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 949
e89d456f
AW		 950 /*
951 * Need to send CMD12 if -
952 * a) open-ended multiblock transfer (no CMD23)
953 * b) error in multiblock transfer
954 */
955 if (data->stop &&
956 (data->error ||
957 !host->mrq->sbc)) {
958
d129bceb
PO		 959 /*
960 * The controller needs a reset of internal state machines
961 * upon error conditions.
962 */
17b0429d 963 if (data->error) {
03231f9b
RK		 964 sdhci_do_reset(host, SDHCI_RESET_CMD);
965 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 966 }
967
968 sdhci_send_command(host, data->stop);
969 } else
970 tasklet_schedule(&host->finish_tasklet);
971}
972
c0e55129 973void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 974{
975 int flags;
fd2208d7 976 u32 mask;
7cb2c76f 977 unsigned long timeout;
d129bceb
PO		 978
979 WARN_ON(host->cmd);
980
96776200
RK		 981 /* Initially, a command has no error */
982 cmd->error = 0;
983
d129bceb 984 /* Wait max 10 ms */
7cb2c76f 985 timeout = 10;
fd2208d7
PO		 986
987 mask = SDHCI_CMD_INHIBIT;
988 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
989 mask |= SDHCI_DATA_INHIBIT;
990
991 /* We shouldn't wait for data inihibit for stop commands, even
992 though they might use busy signaling */
993 if (host->mrq->data && (cmd == host->mrq->data->stop))
994 mask &= ~SDHCI_DATA_INHIBIT;
995
4e4141a5 996 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 997 if (timeout == 0) {
2e4456f0
MV		 998 pr_err("%s: Controller never released inhibit bit(s).\n",
999 mmc_hostname(host->mmc));
d129bceb 1000 sdhci_dumpregs(host);
17b0429d 1001 cmd->error = -EIO;
d129bceb
PO		 1002 tasklet_schedule(&host->finish_tasklet);
1003 return;
1004 }
7cb2c76f
PO		 1005 timeout--;
1006 mdelay(1);
1007 }
d129bceb 1008
3e1a6892 1009 timeout = jiffies;
1d4d7744
UH		 1010 if (!cmd->data && cmd->busy_timeout > 9000)
1011 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1012 else
1013 timeout += 10 * HZ;
1014 mod_timer(&host->timer, timeout);
d129bceb
PO		 1015
1016 host->cmd = cmd;
e99783a4 1017 host->busy_handle = 0;
7c89a3d9
AH		 1018 if (cmd->data || cmd->flags & MMC_RSP_BUSY) {
1019 WARN_ON(host->data_cmd);
1020 host->data_cmd = cmd;
1021 }
d129bceb 1022
a3c7778f 1023 sdhci_prepare_data(host, cmd);
d129bceb 1024
4e4141a5 1025 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1026
e89d456f 1027 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1028
d129bceb 1029 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1030 pr_err("%s: Unsupported response type!\n",
d129bceb 1031 mmc_hostname(host->mmc));
17b0429d 1032 cmd->error = -EINVAL;
d129bceb
PO		 1033 tasklet_schedule(&host->finish_tasklet);
1034 return;
1035 }
1036
1037 if (!(cmd->flags & MMC_RSP_PRESENT))
1038 flags = SDHCI_CMD_RESP_NONE;
1039 else if (cmd->flags & MMC_RSP_136)
1040 flags = SDHCI_CMD_RESP_LONG;
1041 else if (cmd->flags & MMC_RSP_BUSY)
1042 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1043 else
1044 flags = SDHCI_CMD_RESP_SHORT;
1045
1046 if (cmd->flags & MMC_RSP_CRC)
1047 flags |= SDHCI_CMD_CRC;
1048 if (cmd->flags & MMC_RSP_OPCODE)
1049 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1050
1051 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1052 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1053 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1054 flags |= SDHCI_CMD_DATA;
1055
4e4141a5 1056 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1057}
c0e55129 1058EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1059
1060static void sdhci_finish_command(struct sdhci_host *host)
1061{
e0a5640a 1062 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1063 int i;
1064
e0a5640a
AH		 1065 host->cmd = NULL;
1066
1067 if (cmd->flags & MMC_RSP_PRESENT) {
1068 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1069 /* CRC is stripped so we need to do some shifting. */
1070 for (i = 0;i < 4;i++) {
e0a5640a 1071 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1072 SDHCI_RESPONSE + (3-i)*4) << 8;
1073 if (i != 3)
e0a5640a 1074 cmd->resp[i] |=
4e4141a5 1075 sdhci_readb(host,
d129bceb
PO		 1076 SDHCI_RESPONSE + (3-i)*4-1);
1077 }
1078 } else {
e0a5640a 1079 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1080 }
1081 }
1082
6bde8681
AH		 1083 /*
1084 * The host can send and interrupt when the busy state has
1085 * ended, allowing us to wait without wasting CPU cycles.
1086 * The busy signal uses DAT0 so this is similar to waiting
1087 * for data to complete.
1088 *
1089 * Note: The 1.0 specification is a bit ambiguous about this
1090 * feature so there might be some problems with older
1091 * controllers.
1092 */
e0a5640a
AH		 1093 if (cmd->flags & MMC_RSP_BUSY) {
1094 if (cmd->data) {
6bde8681
AH		 1095 DBG("Cannot wait for busy signal when also doing a data transfer");
1096 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1097 !host->busy_handle) {
1098 /* Mark that command complete before busy is ended */
1099 host->busy_handle = 1;
6bde8681
AH		 1100 return;
1101 }
1102 }
1103
e89d456f 1104 /* Finished CMD23, now send actual command. */
e0a5640a 1105 if (cmd == host->mrq->sbc) {
e89d456f
AW		 1106 sdhci_send_command(host, host->mrq->cmd);
1107 } else {
e538fbe8 1108
e89d456f
AW		 1109 /* Processed actual command. */
1110 if (host->data && host->data_early)
1111 sdhci_finish_data(host);
d129bceb 1112
e0a5640a 1113 if (!cmd->data)
e89d456f 1114 tasklet_schedule(&host->finish_tasklet);
e89d456f 1115 }
d129bceb
PO		 1116}
1117
52983382
KL		 1118static u16 sdhci_get_preset_value(struct sdhci_host *host)
1119{
d975f121 1120 u16 preset = 0;
52983382 1121
d975f121
RK		 1122 switch (host->timing) {
1123 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1125 break;
d975f121 1126 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1128 break;
d975f121 1129 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1130 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1131 break;
d975f121
RK		 1132 case MMC_TIMING_UHS_SDR104:
1133 case MMC_TIMING_MMC_HS200:
52983382
KL		 1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1135 break;
d975f121 1136 case MMC_TIMING_UHS_DDR50:
0dafa60e 1137 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1138 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1139 break;
e9fb05d5
AH		 1140 case MMC_TIMING_MMC_HS400:
1141 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1142 break;
52983382
KL		 1143 default:
1144 pr_warn("%s: Invalid UHS-I mode selected\n",
1145 mmc_hostname(host->mmc));
1146 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1147 break;
1148 }
1149 return preset;
1150}
1151
fb9ee047
LD		 1152u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1153 unsigned int *actual_clock)
d129bceb 1154{
c3ed3877 1155 int div = 0; /* Initialized for compiler warning */
df16219f 1156 int real_div = div, clk_mul = 1;
c3ed3877 1157 u16 clk = 0;
5497159c 1158 bool switch_base_clk = false;
d129bceb 1159
85105c53 1160 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1161 if (host->preset_enabled) {
52983382
KL		 1162 u16 pre_val;
1163
1164 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1165 pre_val = sdhci_get_preset_value(host);
1166 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1167 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1168 if (host->clk_mul &&
1169 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1170 clk = SDHCI_PROG_CLOCK_MODE;
1171 real_div = div + 1;
1172 clk_mul = host->clk_mul;
1173 } else {
1174 real_div = max_t(int, 1, div << 1);
1175 }
1176 goto clock_set;
1177 }
1178
c3ed3877
AN		 1179 /*
1180 * Check if the Host Controller supports Programmable Clock
1181 * Mode.
1182 */
1183 if (host->clk_mul) {
52983382
KL		 1184 for (div = 1; div <= 1024; div++) {
1185 if ((host->max_clk * host->clk_mul / div)
1186 <= clock)
1187 break;
1188 }
5497159c 1189 if ((host->max_clk * host->clk_mul / div) <= clock) {
1190 /*
1191 * Set Programmable Clock Mode in the Clock
1192 * Control register.
1193 */
1194 clk = SDHCI_PROG_CLOCK_MODE;
1195 real_div = div;
1196 clk_mul = host->clk_mul;
1197 div--;
1198 } else {
1199 /*
1200 * Divisor can be too small to reach clock
1201 * speed requirement. Then use the base clock.
1202 */
1203 switch_base_clk = true;
1204 }
1205 }
1206
1207 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1208 /* Version 3.00 divisors must be a multiple of 2. */
1209 if (host->max_clk <= clock)
1210 div = 1;
1211 else {
1212 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1213 div += 2) {
1214 if ((host->max_clk / div) <= clock)
1215 break;
1216 }
85105c53 1217 }
df16219f 1218 real_div = div;
c3ed3877 1219 div >>= 1;
d1955c3a
SG		 1220 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1221 && !div && host->max_clk <= 25000000)
1222 div = 1;
85105c53
ZG		 1223 }
1224 } else {
1225 /* Version 2.00 divisors must be a power of 2. */
0397526d 1226 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1227 if ((host->max_clk / div) <= clock)
1228 break;
1229 }
df16219f 1230 real_div = div;
c3ed3877 1231 div >>= 1;
d129bceb 1232 }
d129bceb 1233
52983382 1234clock_set:
03d6f5ff 1235 if (real_div)
fb9ee047 1236 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1237 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1238 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1239 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1240
1241 return clk;
1242}
1243EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1244
1245void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1246{
1247 u16 clk;
1248 unsigned long timeout;
1249
1250 host->mmc->actual_clock = 0;
1251
1252 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fb9ee047
LD		 1253
1254 if (clock == 0)
1255 return;
1256
1257 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1258
d129bceb 1259 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1260 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1261
27f6cb16
CB		 1262 /* Wait max 20 ms */
1263 timeout = 20;
4e4141a5 1264 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1265 & SDHCI_CLOCK_INT_STABLE)) {
1266 if (timeout == 0) {
2e4456f0
MV		 1267 pr_err("%s: Internal clock never stabilised.\n",
1268 mmc_hostname(host->mmc));
d129bceb
PO		 1269 sdhci_dumpregs(host);
1270 return;
1271 }
7cb2c76f
PO		 1272 timeout--;
1273 mdelay(1);
1274 }
d129bceb
PO		 1275
1276 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1277 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1278}
1771059c 1279EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1280
1dceb041
AH		 1281static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1282 unsigned short vdd)
146ad66e 1283{
3a48edc4 1284 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1285
1286 spin_unlock_irq(&host->lock);
1287 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1288 spin_lock_irq(&host->lock);
1289
1290 if (mode != MMC_POWER_OFF)
1291 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1292 else
1293 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1294}
1295
1296void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1297 unsigned short vdd)
1298{
8364248a 1299 u8 pwr = 0;
146ad66e 1300
24fbb3ca
RK		 1301 if (mode != MMC_POWER_OFF) {
1302 switch (1 << vdd) {
ae628903
PO		 1303 case MMC_VDD_165_195:
1304 pwr = SDHCI_POWER_180;
1305 break;
1306 case MMC_VDD_29_30:
1307 case MMC_VDD_30_31:
1308 pwr = SDHCI_POWER_300;
1309 break;
1310 case MMC_VDD_32_33:
1311 case MMC_VDD_33_34:
1312 pwr = SDHCI_POWER_330;
1313 break;
1314 default:
9d5de93f
AH		 1315 WARN(1, "%s: Invalid vdd %#x\n",
1316 mmc_hostname(host->mmc), vdd);
1317 break;
ae628903
PO		 1318 }
1319 }
1320
1321 if (host->pwr == pwr)
e921a8b6 1322 return;
146ad66e 1323
ae628903
PO		 1324 host->pwr = pwr;
1325
1326 if (pwr == 0) {
4e4141a5 1327 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1328 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1329 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1330 } else {
1331 /*
1332 * Spec says that we should clear the power reg before setting
1333 * a new value. Some controllers don't seem to like this though.
1334 */
1335 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1336 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1337
e921a8b6
RK		 1338 /*
1339 * At least the Marvell CaFe chip gets confused if we set the
1340 * voltage and set turn on power at the same time, so set the
1341 * voltage first.
1342 */
1343 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1344 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1345
e921a8b6 1346 pwr |= SDHCI_POWER_ON;
146ad66e 1347
e921a8b6 1348 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1349
e921a8b6
RK		 1350 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1351 sdhci_runtime_pm_bus_on(host);
f0710a55 1352
e921a8b6
RK		 1353 /*
1354 * Some controllers need an extra 10ms delay of 10ms before
1355 * they can apply clock after applying power
1356 */
1357 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1358 mdelay(10);
1359 }
1dceb041
AH		 1360}
1361EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1362
1dceb041
AH		 1363static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1364 unsigned short vdd)
1365{
1366 struct mmc_host *mmc = host->mmc;
1367
1368 if (host->ops->set_power)
1369 host->ops->set_power(host, mode, vdd);
1370 else if (!IS_ERR(mmc->supply.vmmc))
1371 sdhci_set_power_reg(host, mode, vdd);
1372 else
1373 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1374}
1375
d129bceb
PO		 1376/*****************************************************************************\
1377 * *
1378 * MMC callbacks *
1379 * *
1380\*****************************************************************************/
1381
1382static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1383{
1384 struct sdhci_host *host;
505a8680 1385 int present;
d129bceb
PO		 1386 unsigned long flags;
1387
1388 host = mmc_priv(mmc);
1389
04e079cf 1390 /* Firstly check card presence */
8d28b7a7 1391 present = mmc->ops->get_cd(mmc);
2836766a 1392
d129bceb
PO		 1393 spin_lock_irqsave(&host->lock, flags);
1394
1395 WARN_ON(host->mrq != NULL);
1396
061d17a6 1397 sdhci_led_activate(host);
e89d456f
AW		 1398
1399 /*
1400 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1401 * requests if Auto-CMD12 is enabled.
1402 */
1403 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1404 if (mrq->stop) {
1405 mrq->data->stop = NULL;
1406 mrq->stop = NULL;
1407 }
1408 }
d129bceb
PO		 1409
1410 host->mrq = mrq;
1411
68d1fb7e 1412 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1413 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1414 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1415 } else {
8edf6371 1416 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1417 sdhci_send_command(host, mrq->sbc);
1418 else
1419 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1420 }
d129bceb 1421
5f25a66f 1422 mmiowb();
d129bceb
PO		 1423 spin_unlock_irqrestore(&host->lock, flags);
1424}
1425
2317f56c
RK		 1426void sdhci_set_bus_width(struct sdhci_host *host, int width)
1427{
1428 u8 ctrl;
1429
1430 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1431 if (width == MMC_BUS_WIDTH_8) {
1432 ctrl &= ~SDHCI_CTRL_4BITBUS;
1433 if (host->version >= SDHCI_SPEC_300)
1434 ctrl |= SDHCI_CTRL_8BITBUS;
1435 } else {
1436 if (host->version >= SDHCI_SPEC_300)
1437 ctrl &= ~SDHCI_CTRL_8BITBUS;
1438 if (width == MMC_BUS_WIDTH_4)
1439 ctrl |= SDHCI_CTRL_4BITBUS;
1440 else
1441 ctrl &= ~SDHCI_CTRL_4BITBUS;
1442 }
1443 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1444}
1445EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1446
96d7b78c
RK		 1447void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1448{
1449 u16 ctrl_2;
1450
1451 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1452 /* Select Bus Speed Mode for host */
1453 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1454 if ((timing == MMC_TIMING_MMC_HS200) ||
1455 (timing == MMC_TIMING_UHS_SDR104))
1456 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1457 else if (timing == MMC_TIMING_UHS_SDR12)
1458 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1459 else if (timing == MMC_TIMING_UHS_SDR25)
1460 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1461 else if (timing == MMC_TIMING_UHS_SDR50)
1462 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1463 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1464 (timing == MMC_TIMING_MMC_DDR52))
1465 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1466 else if (timing == MMC_TIMING_MMC_HS400)
1467 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1468 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1469}
1470EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1471
ded97e0b 1472static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1473{
ded97e0b 1474 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1475 unsigned long flags;
1476 u8 ctrl;
1477
d129bceb
PO		 1478 spin_lock_irqsave(&host->lock, flags);
1479
ceb6143b
AH		 1480 if (host->flags & SDHCI_DEVICE_DEAD) {
1481 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1482 if (!IS_ERR(mmc->supply.vmmc) &&
1483 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1484 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1485 return;
1486 }
1e72859e 1487
d129bceb
PO		 1488 /*
1489 * Reset the chip on each power off.
1490 * Should clear out any weird states.
1491 */
1492 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1493 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1494 sdhci_reinit(host);
d129bceb
PO		 1495 }
1496
52983382 1497 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1498 (ios->power_mode == MMC_POWER_UP) &&
1499 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1500 sdhci_enable_preset_value(host, false);
1501
373073ef 1502 if (!ios->clock || ios->clock != host->clock) {
1771059c 1503 host->ops->set_clock(host, ios->clock);
373073ef 1504 host->clock = ios->clock;
03d6f5ff
AD		 1505
1506 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1507 host->clock) {
1508 host->timeout_clk = host->mmc->actual_clock ?
1509 host->mmc->actual_clock / 1000 :
1510 host->clock / 1000;
1511 host->mmc->max_busy_timeout =
1512 host->ops->get_max_timeout_count ?
1513 host->ops->get_max_timeout_count(host) :
1514 1 << 27;
1515 host->mmc->max_busy_timeout /= host->timeout_clk;
1516 }
373073ef 1517 }
d129bceb 1518
1dceb041 1519 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1520
643a81ff
PR		 1521 if (host->ops->platform_send_init_74_clocks)
1522 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1523
2317f56c 1524 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1525
15ec4461 1526 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1527
3ab9c8da
PR		 1528 if ((ios->timing == MMC_TIMING_SD_HS ||
1529 ios->timing == MMC_TIMING_MMC_HS)
1530 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1531 ctrl |= SDHCI_CTRL_HISPD;
1532 else
1533 ctrl &= ~SDHCI_CTRL_HISPD;
1534
d6d50a15 1535 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1536 u16 clk, ctrl_2;
49c468fc
AN		 1537
1538 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1539 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1540 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1541 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1542 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1543 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1544 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1545 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1546 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1547
da91a8f9 1548 if (!host->preset_enabled) {
758535c4 1549 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1550 /*
1551 * We only need to set Driver Strength if the
1552 * preset value enable is not set.
1553 */
da91a8f9 1554 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1555 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1556 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1557 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1558 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1559 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1560 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1561 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1562 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1563 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1564 else {
2e4456f0
MV		 1565 pr_warn("%s: invalid driver type, default to driver type B\n",
1566 mmc_hostname(mmc));
43e943a0
PG		 1567 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1568 }
d6d50a15
AN		 1569
1570 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1571 } else {
1572 /*
1573 * According to SDHC Spec v3.00, if the Preset Value
1574 * Enable in the Host Control 2 register is set, we
1575 * need to reset SD Clock Enable before changing High
1576 * Speed Enable to avoid generating clock gliches.
1577 */
758535c4
AN		 1578
1579 /* Reset SD Clock Enable */
1580 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1581 clk &= ~SDHCI_CLOCK_CARD_EN;
1582 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1583
1584 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1585
1586 /* Re-enable SD Clock */
1771059c 1587 host->ops->set_clock(host, host->clock);
d6d50a15 1588 }
49c468fc 1589
49c468fc
AN		 1590 /* Reset SD Clock Enable */
1591 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1592 clk &= ~SDHCI_CLOCK_CARD_EN;
1593 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1594
96d7b78c 1595 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1596 host->timing = ios->timing;
49c468fc 1597
52983382
KL		 1598 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1599 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1600 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1601 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1602 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1603 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1604 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1605 u16 preset;
1606
1607 sdhci_enable_preset_value(host, true);
1608 preset = sdhci_get_preset_value(host);
1609 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1610 >> SDHCI_PRESET_DRV_SHIFT;
1611 }
1612
49c468fc 1613 /* Re-enable SD Clock */
1771059c 1614 host->ops->set_clock(host, host->clock);
758535c4
AN		 1615 } else
1616 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1617
b8352260
LD		 1618 /*
1619 * Some (ENE) controllers go apeshit on some ios operation,
1620 * signalling timeout and CRC errors even on CMD0. Resetting
1621 * it on each ios seems to solve the problem.
1622 */
c63705e1 1623 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1624 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1625
5f25a66f 1626 mmiowb();
d129bceb
PO		 1627 spin_unlock_irqrestore(&host->lock, flags);
1628}
1629
ded97e0b 1630static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1631{
1632 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1633 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1634
1635 if (host->flags & SDHCI_DEVICE_DEAD)
1636 return 0;
1637
88af5655 1638 /* If nonremovable, assume that the card is always present. */
860951c5 1639 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1640 return 1;
1641
88af5655
II		 1642 /*
1643 * Try slot gpio detect, if defined it take precedence
1644 * over build in controller functionality
1645 */
287980e4 1646 if (gpio_cd >= 0)
94144a46
KL		 1647 return !!gpio_cd;
1648
88af5655
II		 1649 /* If polling, assume that the card is always present. */
1650 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1651 return 1;
1652
94144a46
KL		 1653 /* Host native card detect */
1654 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1655}
1656
66fd8ad5 1657static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1658{
d129bceb 1659 unsigned long flags;
2dfb579c 1660 int is_readonly;
d129bceb 1661
d129bceb
PO		 1662 spin_lock_irqsave(&host->lock, flags);
1663
1e72859e 1664 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1665 is_readonly = 0;
1666 else if (host->ops->get_ro)
1667 is_readonly = host->ops->get_ro(host);
1e72859e 1668 else
2dfb579c
WS		 1669 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1670 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1671
1672 spin_unlock_irqrestore(&host->lock, flags);
1673
2dfb579c
WS		 1674 /* This quirk needs to be replaced by a callback-function later */
1675 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1676 !is_readonly : is_readonly;
d129bceb
PO		 1677}
1678
82b0e23a
TI		 1679#define SAMPLE_COUNT 5
1680
ded97e0b 1681static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1682{
ded97e0b 1683 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1684 int i, ro_count;
1685
82b0e23a 1686 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1687 return sdhci_check_ro(host);
82b0e23a
TI		 1688
1689 ro_count = 0;
1690 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1691 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1692 if (++ro_count > SAMPLE_COUNT / 2)
1693 return 1;
1694 }
1695 msleep(30);
1696 }
1697 return 0;
1698}
1699
20758b66
AH		 1700static void sdhci_hw_reset(struct mmc_host *mmc)
1701{
1702 struct sdhci_host *host = mmc_priv(mmc);
1703
1704 if (host->ops && host->ops->hw_reset)
1705 host->ops->hw_reset(host);
1706}
1707
66fd8ad5
AH		 1708static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1709{
be138554 1710 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1711 if (enable)
b537f94c 1712 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1713 else
b537f94c
RK		 1714 host->ier &= ~SDHCI_INT_CARD_INT;
1715
1716 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1717 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1718 mmiowb();
1719 }
66fd8ad5
AH		 1720}
1721
1722static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1723{
1724 struct sdhci_host *host = mmc_priv(mmc);
1725 unsigned long flags;
f75979b7 1726
66fd8ad5 1727 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1728 if (enable)
1729 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1730 else
1731 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1732
66fd8ad5 1733 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1734 spin_unlock_irqrestore(&host->lock, flags);
1735}
1736
ded97e0b
DA		 1737static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1738 struct mmc_ios *ios)
f2119df6 1739{
ded97e0b 1740 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1741 u16 ctrl;
6231f3de 1742 int ret;
f2119df6 1743
20b92a30
KL		 1744 /*
1745 * Signal Voltage Switching is only applicable for Host Controllers
1746 * v3.00 and above.
1747 */
1748 if (host->version < SDHCI_SPEC_300)
1749 return 0;
6231f3de 1750
f2119df6 1751 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1752
21f5998f 1753 switch (ios->signal_voltage) {
20b92a30 1754 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1755 if (!(host->flags & SDHCI_SIGNALING_330))
1756 return -EINVAL;
20b92a30
KL		 1757 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1758 ctrl &= ~SDHCI_CTRL_VDD_180;
1759 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1760
3a48edc4
TK		 1761 if (!IS_ERR(mmc->supply.vqmmc)) {
1762 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1763 3600000);
20b92a30 1764 if (ret) {
6606110d
JP		 1765 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1766 mmc_hostname(mmc));
20b92a30
KL		 1767 return -EIO;
1768 }
1769 }
1770 /* Wait for 5ms */
1771 usleep_range(5000, 5500);
f2119df6 1772
20b92a30
KL		 1773 /* 3.3V regulator output should be stable within 5 ms */
1774 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1775 if (!(ctrl & SDHCI_CTRL_VDD_180))
1776 return 0;
6231f3de 1777
6606110d
JP		 1778 pr_warn("%s: 3.3V regulator output did not became stable\n",
1779 mmc_hostname(mmc));
20b92a30
KL		 1780
1781 return -EAGAIN;
1782 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1783 if (!(host->flags & SDHCI_SIGNALING_180))
1784 return -EINVAL;
3a48edc4
TK		 1785 if (!IS_ERR(mmc->supply.vqmmc)) {
1786 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1787 1700000, 1950000);
1788 if (ret) {
6606110d
JP		 1789 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1790 mmc_hostname(mmc));
20b92a30
KL		 1791 return -EIO;
1792 }
1793 }
6231f3de 1794
6231f3de
PR		 1795 /*
1796 * Enable 1.8V Signal Enable in the Host Control2
1797 * register
1798 */
20b92a30
KL		 1799 ctrl |= SDHCI_CTRL_VDD_180;
1800 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1801
9d967a61
VY		 1802 /* Some controller need to do more when switching */
1803 if (host->ops->voltage_switch)
1804 host->ops->voltage_switch(host);
1805
20b92a30
KL		 1806 /* 1.8V regulator output should be stable within 5 ms */
1807 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1808 if (ctrl & SDHCI_CTRL_VDD_180)
1809 return 0;
f2119df6 1810
6606110d
JP		 1811 pr_warn("%s: 1.8V regulator output did not became stable\n",
1812 mmc_hostname(mmc));
f2119df6 1813
20b92a30
KL		 1814 return -EAGAIN;
1815 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1816 if (!(host->flags & SDHCI_SIGNALING_120))
1817 return -EINVAL;
3a48edc4
TK		 1818 if (!IS_ERR(mmc->supply.vqmmc)) {
1819 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1820 1300000);
20b92a30 1821 if (ret) {
6606110d
JP		 1822 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1823 mmc_hostname(mmc));
20b92a30 1824 return -EIO;
f2119df6
AN		 1825 }
1826 }
6231f3de 1827 return 0;
20b92a30 1828 default:
f2119df6
AN		 1829 /* No signal voltage switch required */
1830 return 0;
20b92a30 1831 }
f2119df6
AN		 1832}
1833
20b92a30
KL		 1834static int sdhci_card_busy(struct mmc_host *mmc)
1835{
1836 struct sdhci_host *host = mmc_priv(mmc);
1837 u32 present_state;
1838
e613cc47 1839 /* Check whether DAT[0] is 0 */
20b92a30 1840 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1841
e613cc47 1842 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1843}
1844
b5540ce1
AH		 1845static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1846{
1847 struct sdhci_host *host = mmc_priv(mmc);
1848 unsigned long flags;
1849
1850 spin_lock_irqsave(&host->lock, flags);
1851 host->flags |= SDHCI_HS400_TUNING;
1852 spin_unlock_irqrestore(&host->lock, flags);
1853
1854 return 0;
1855}
1856
069c9f14 1857static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1858{
4b6f37d3 1859 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1860 u16 ctrl;
b513ea25 1861 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1862 int err = 0;
2b35bd83 1863 unsigned long flags;
38e40bf5 1864 unsigned int tuning_count = 0;
b5540ce1 1865 bool hs400_tuning;
b513ea25 1866
2b35bd83 1867 spin_lock_irqsave(&host->lock, flags);
b513ea25 1868
b5540ce1
AH		 1869 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1870 host->flags &= ~SDHCI_HS400_TUNING;
1871
38e40bf5
AH		 1872 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1873 tuning_count = host->tuning_count;
1874
b513ea25 1875 /*
9faac7b9
WY		 1876 * The Host Controller needs tuning in case of SDR104 and DDR50
1877 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1878 * the Capabilities register.
069c9f14
G		 1879 * If the Host Controller supports the HS200 mode then the
1880 * tuning function has to be executed.
b513ea25 1881 */
4b6f37d3 1882 switch (host->timing) {
b5540ce1 1883 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1884 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1885 err = -EINVAL;
1886 goto out_unlock;
1887
4b6f37d3 1888 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1889 /*
1890 * Periodic re-tuning for HS400 is not expected to be needed, so
1891 * disable it here.
1892 */
1893 if (hs400_tuning)
1894 tuning_count = 0;
1895 break;
1896
4b6f37d3 1897 case MMC_TIMING_UHS_SDR104:
9faac7b9 1898 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1899 break;
1900
1901 case MMC_TIMING_UHS_SDR50:
4228b213 1902 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 1903 break;
1904 /* FALLTHROUGH */
1905
1906 default:
d519c863 1907 goto out_unlock;
b513ea25
AN		 1908 }
1909
45251812 1910 if (host->ops->platform_execute_tuning) {
2b35bd83 1911 spin_unlock_irqrestore(&host->lock, flags);
45251812 1912 err = host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 1913 return err;
1914 }
1915
4b6f37d3
RK		 1916 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1917 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1918 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1919 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1920 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1921
1922 /*
1923 * As per the Host Controller spec v3.00, tuning command
1924 * generates Buffer Read Ready interrupt, so enable that.
1925 *
1926 * Note: The spec clearly says that when tuning sequence
1927 * is being performed, the controller does not generate
1928 * interrupts other than Buffer Read Ready interrupt. But
1929 * to make sure we don't hit a controller bug, we _only_
1930 * enable Buffer Read Ready interrupt here.
1931 */
b537f94c
RK		 1932 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1933 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1934
1935 /*
1936 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1473bdd5 1937 * of loops reaches 40 times.
b513ea25 1938 */
b513ea25
AN		 1939 do {
1940 struct mmc_command cmd = {0};
66fd8ad5 1941 struct mmc_request mrq = {NULL};
b513ea25 1942
069c9f14 1943 cmd.opcode = opcode;
b513ea25
AN		 1944 cmd.arg = 0;
1945 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1946 cmd.retries = 0;
1947 cmd.data = NULL;
1948 cmd.error = 0;
1949
7ce45e95
AC		 1950 if (tuning_loop_counter-- == 0)
1951 break;
1952
b513ea25
AN		 1953 mrq.cmd = &cmd;
1954 host->mrq = &mrq;
1955
1956 /*
1957 * In response to CMD19, the card sends 64 bytes of tuning
1958 * block to the Host Controller. So we set the block size
1959 * to 64 here.
1960 */
069c9f14
G		 1961 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1962 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1963 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1964 SDHCI_BLOCK_SIZE);
1965 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1966 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1967 SDHCI_BLOCK_SIZE);
1968 } else {
1969 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1970 SDHCI_BLOCK_SIZE);
1971 }
b513ea25
AN		 1972
1973 /*
1974 * The tuning block is sent by the card to the host controller.
1975 * So we set the TRNS_READ bit in the Transfer Mode register.
1976 * This also takes care of setting DMA Enable and Multi Block
1977 * Select in the same register to 0.
1978 */
1979 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1980
1981 sdhci_send_command(host, &cmd);
1982
1983 host->cmd = NULL;
1984 host->mrq = NULL;
1985
2b35bd83 1986 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1987 /* Wait for Buffer Read Ready interrupt */
1988 wait_event_interruptible_timeout(host->buf_ready_int,
1989 (host->tuning_done == 1),
1990 msecs_to_jiffies(50));
2b35bd83 1991 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1992
1993 if (!host->tuning_done) {
2e4456f0 1994 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1995 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1996 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1997 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1998 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1999
2000 err = -EIO;
2001 goto out;
2002 }
2003
2004 host->tuning_done = 0;
2005
2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2007
2008 /* eMMC spec does not require a delay between tuning cycles */
2009 if (opcode == MMC_SEND_TUNING_BLOCK)
2010 mdelay(1);
b513ea25
AN		 2011 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2012
2013 /*
2014 * The Host Driver has exhausted the maximum number of loops allowed,
2015 * so use fixed sampling frequency.
2016 */
7ce45e95 2017 if (tuning_loop_counter < 0) {
b513ea25
AN		 2018 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2019 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2020 }
2021 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2022 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2023 err = -EIO;
b513ea25
AN		 2024 }
2025
2026out:
38e40bf5 2027 if (tuning_count) {
66c39dfc
AH		 2028 /*
2029 * In case tuning fails, host controllers which support
2030 * re-tuning can try tuning again at a later time, when the
2031 * re-tuning timer expires. So for these controllers, we
2032 * return 0. Since there might be other controllers who do not
2033 * have this capability, we return error for them.
2034 */
2035 err = 0;
cf2b5eea
AN		 2036 }
2037
66c39dfc 2038 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2039
b537f94c
RK		 2040 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2041 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2042out_unlock:
2b35bd83 2043 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2044 return err;
2045}
2046
cb849648
AH		 2047static int sdhci_select_drive_strength(struct mmc_card *card,
2048 unsigned int max_dtr, int host_drv,
2049 int card_drv, int *drv_type)
2050{
2051 struct sdhci_host *host = mmc_priv(card->host);
2052
2053 if (!host->ops->select_drive_strength)
2054 return 0;
2055
2056 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2057 card_drv, drv_type);
2058}
52983382
KL		 2059
2060static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2061{
4d55c5a1
AN		 2062 /* Host Controller v3.00 defines preset value registers */
2063 if (host->version < SDHCI_SPEC_300)
2064 return;
2065
4d55c5a1
AN		 2066 /*
2067 * We only enable or disable Preset Value if they are not already
2068 * enabled or disabled respectively. Otherwise, we bail out.
2069 */
da91a8f9
RK		 2070 if (host->preset_enabled != enable) {
2071 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2072
2073 if (enable)
2074 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2075 else
2076 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2077
4d55c5a1 2078 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2079
2080 if (enable)
2081 host->flags |= SDHCI_PV_ENABLED;
2082 else
2083 host->flags &= ~SDHCI_PV_ENABLED;
2084
2085 host->preset_enabled = enable;
4d55c5a1 2086 }
66fd8ad5
AH		 2087}
2088
348487cb
HC		 2089static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2090 int err)
2091{
2092 struct sdhci_host *host = mmc_priv(mmc);
2093 struct mmc_data *data = mrq->data;
2094
f48f039c 2095 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2096 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2097 data->flags & MMC_DATA_WRITE ?
2098 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2099
2100 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2101}
2102
348487cb
HC		 2103static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2104 bool is_first_req)
2105{
2106 struct sdhci_host *host = mmc_priv(mmc);
2107
d31911b9 2108 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2109
2110 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2111 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2112}
2113
71e69211 2114static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2115{
71e69211 2116 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2117 unsigned long flags;
2836766a 2118 int present;
d129bceb 2119
722e1280
CD		 2120 /* First check if client has provided their own card event */
2121 if (host->ops->card_event)
2122 host->ops->card_event(host);
2123
d3940f27 2124 present = mmc->ops->get_cd(mmc);
2836766a 2125
d129bceb
PO		 2126 spin_lock_irqsave(&host->lock, flags);
2127
66fd8ad5 2128 /* Check host->mrq first in case we are runtime suspended */
2836766a 2129 if (host->mrq && !present) {
a3c76eb9 2130 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2131 mmc_hostname(host->mmc));
a3c76eb9 2132 pr_err("%s: Resetting controller.\n",
66fd8ad5 2133 mmc_hostname(host->mmc));
d129bceb 2134
03231f9b
RK		 2135 sdhci_do_reset(host, SDHCI_RESET_CMD);
2136 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2137
66fd8ad5
AH		 2138 host->mrq->cmd->error = -ENOMEDIUM;
2139 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2140 }
2141
2142 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2143}
2144
2145static const struct mmc_host_ops sdhci_ops = {
2146 .request = sdhci_request,
348487cb
HC		 2147 .post_req = sdhci_post_req,
2148 .pre_req = sdhci_pre_req,
71e69211 2149 .set_ios = sdhci_set_ios,
94144a46 2150 .get_cd = sdhci_get_cd,
71e69211
GL		 2151 .get_ro = sdhci_get_ro,
2152 .hw_reset = sdhci_hw_reset,
2153 .enable_sdio_irq = sdhci_enable_sdio_irq,
2154 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2155 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2156 .execute_tuning = sdhci_execute_tuning,
cb849648 2157 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2158 .card_event = sdhci_card_event,
20b92a30 2159 .card_busy = sdhci_card_busy,
71e69211
GL		 2160};
2161
2162/*****************************************************************************\
2163 * *
2164 * Tasklets *
2165 * *
2166\*****************************************************************************/
2167
d129bceb
PO		 2168static void sdhci_tasklet_finish(unsigned long param)
2169{
2170 struct sdhci_host *host;
2171 unsigned long flags;
2172 struct mmc_request *mrq;
2173
2174 host = (struct sdhci_host*)param;
2175
66fd8ad5
AH		 2176 spin_lock_irqsave(&host->lock, flags);
2177
0c9c99a7
CB		 2178 /*
2179 * If this tasklet gets rescheduled while running, it will
2180 * be run again afterwards but without any active request.
2181 */
66fd8ad5
AH		 2182 if (!host->mrq) {
2183 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2184 return;
66fd8ad5 2185 }
d129bceb
PO		 2186
2187 del_timer(&host->timer);
2188
2189 mrq = host->mrq;
2190
054cedff
RK		 2191 /*
2192 * Always unmap the data buffers if they were mapped by
2193 * sdhci_prepare_data() whenever we finish with a request.
2194 * This avoids leaking DMA mappings on error.
2195 */
2196 if (host->flags & SDHCI_REQ_USE_DMA) {
2197 struct mmc_data *data = mrq->data;
2198
2199 if (data && data->host_cookie == COOKIE_MAPPED) {
2200 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2201 (data->flags & MMC_DATA_READ) ?
2202 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2203 data->host_cookie = COOKIE_UNMAPPED;
2204 }
2205 }
2206
d129bceb
PO		 2207 /*
2208 * The controller needs a reset of internal state machines
2209 * upon error conditions.
2210 */
1e72859e 2211 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2212 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2213 (mrq->sbc && mrq->sbc->error) ||
2214 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2215 (mrq->data->stop && mrq->data->stop->error))) ||
2216 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2217
2218 /* Some controllers need this kick or reset won't work here */
8213af3b 2219 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2220 /* This is to force an update */
1771059c 2221 host->ops->set_clock(host, host->clock);
645289dc
PO		 2222
2223 /* Spec says we should do both at the same time, but Ricoh
2224 controllers do not like that. */
03231f9b
RK		 2225 sdhci_do_reset(host, SDHCI_RESET_CMD);
2226 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2227 }
2228
2229 host->mrq = NULL;
2230 host->cmd = NULL;
2231 host->data = NULL;
7c89a3d9 2232 host->data_cmd = NULL;
d129bceb 2233
061d17a6 2234 sdhci_led_deactivate(host);
d129bceb 2235
5f25a66f 2236 mmiowb();
d129bceb
PO		 2237 spin_unlock_irqrestore(&host->lock, flags);
2238
2239 mmc_request_done(host->mmc, mrq);
2240}
2241
2242static void sdhci_timeout_timer(unsigned long data)
2243{
2244 struct sdhci_host *host;
2245 unsigned long flags;
2246
2247 host = (struct sdhci_host*)data;
2248
2249 spin_lock_irqsave(&host->lock, flags);
2250
2251 if (host->mrq) {
2e4456f0
MV		 2252 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2253 mmc_hostname(host->mmc));
d129bceb
PO		 2254 sdhci_dumpregs(host);
2255
2256 if (host->data) {
17b0429d 2257 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2258 sdhci_finish_data(host);
2259 } else {
2260 if (host->cmd)
17b0429d 2261 host->cmd->error = -ETIMEDOUT;
d129bceb 2262 else
17b0429d 2263 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2264
2265 tasklet_schedule(&host->finish_tasklet);
2266 }
2267 }
2268
5f25a66f 2269 mmiowb();
d129bceb
PO		 2270 spin_unlock_irqrestore(&host->lock, flags);
2271}
2272
2273/*****************************************************************************\
2274 * *
2275 * Interrupt handling *
2276 * *
2277\*****************************************************************************/
2278
61541397 2279static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb 2280{
d129bceb 2281 if (!host->cmd) {
2e4456f0
MV		 2282 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2283 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2284 sdhci_dumpregs(host);
2285 return;
2286 }
2287
ec014cba
RK		 2288 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2289 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2290 if (intmask & SDHCI_INT_TIMEOUT)
2291 host->cmd->error = -ETIMEDOUT;
2292 else
2293 host->cmd->error = -EILSEQ;
43b58b36 2294
71fcbda0
RK		 2295 /*
2296 * If this command initiates a data phase and a response
2297 * CRC error is signalled, the card can start transferring
2298 * data - the card may have received the command without
2299 * error. We must not terminate the mmc_request early.
2300 *
2301 * If the card did not receive the command or returned an
2302 * error which prevented it sending data, the data phase
2303 * will time out.
2304 */
2305 if (host->cmd->data &&
2306 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2307 SDHCI_INT_CRC) {
2308 host->cmd = NULL;
2309 return;
2310 }
2311
d129bceb 2312 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2313 return;
2314 }
2315
6bde8681
AH		 2316 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2317 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2318 host->cmd->opcode == MMC_STOP_TRANSMISSION)
61541397 2319 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2320
2321 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2322 sdhci_finish_command(host);
d129bceb
PO		 2323}
2324
0957c333 2325#ifdef CONFIG_MMC_DEBUG
08621b18 2326static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2327{
2328 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2329 void *desc = host->adma_table;
6882a8c0
BD		 2330
2331 sdhci_dumpregs(host);
2332
2333 while (true) {
e57a5f61
AH		 2334 struct sdhci_adma2_64_desc *dma_desc = desc;
2335
2336 if (host->flags & SDHCI_USE_64_BIT_DMA)
2337 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2338 name, desc, le32_to_cpu(dma_desc->addr_hi),
2339 le32_to_cpu(dma_desc->addr_lo),
2340 le16_to_cpu(dma_desc->len),
2341 le16_to_cpu(dma_desc->cmd));
2342 else
2343 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2344 name, desc, le32_to_cpu(dma_desc->addr_lo),
2345 le16_to_cpu(dma_desc->len),
2346 le16_to_cpu(dma_desc->cmd));
6882a8c0 2347
76fe379a 2348 desc += host->desc_sz;
6882a8c0 2349
0545230f 2350 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2351 break;
2352 }
2353}
2354#else
08621b18 2355static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2356#endif
2357
d129bceb
PO		 2358static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2359{
069c9f14 2360 u32 command;
d129bceb 2361
b513ea25
AN		 2362 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2363 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2364 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2365 if (command == MMC_SEND_TUNING_BLOCK ||
2366 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2367 host->tuning_done = 1;
2368 wake_up(&host->buf_ready_int);
2369 return;
2370 }
2371 }
2372
d129bceb 2373 if (!host->data) {
7c89a3d9
AH		 2374 struct mmc_command *data_cmd = host->data_cmd;
2375
2376 if (data_cmd)
2377 host->data_cmd = NULL;
2378
d129bceb 2379 /*
e809517f
PO		 2380 * The "data complete" interrupt is also used to
2381 * indicate that a busy state has ended. See comment
2382 * above in sdhci_cmd_irq().
d129bceb 2383 */
7c89a3d9 2384 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2385 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
7c89a3d9 2386 data_cmd->error = -ETIMEDOUT;
c5abd5e8
MC		 2387 tasklet_schedule(&host->finish_tasklet);
2388 return;
2389 }
e809517f 2390 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2391 /*
2392 * Some cards handle busy-end interrupt
2393 * before the command completed, so make
2394 * sure we do things in the proper order.
2395 */
2396 if (host->busy_handle)
6bde8681 2397 tasklet_schedule(&host->finish_tasklet);
e99783a4
CM		 2398 else
2399 host->busy_handle = 1;
e809517f
PO		 2400 return;
2401 }
2402 }
d129bceb 2403
2e4456f0
MV		 2404 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2405 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2406 sdhci_dumpregs(host);
2407
2408 return;
2409 }
2410
2411 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2412 host->data->error = -ETIMEDOUT;
22113efd
AL		 2413 else if (intmask & SDHCI_INT_DATA_END_BIT)
2414 host->data->error = -EILSEQ;
2415 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2416 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2417 != MMC_BUS_TEST_R)
17b0429d 2418 host->data->error = -EILSEQ;
6882a8c0 2419 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2420 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2421 sdhci_adma_show_error(host);
2134a922 2422 host->data->error = -EIO;
a4071fbb
HZ		 2423 if (host->ops->adma_workaround)
2424 host->ops->adma_workaround(host, intmask);
6882a8c0 2425 }
d129bceb 2426
17b0429d 2427 if (host->data->error)
d129bceb
PO		 2428 sdhci_finish_data(host);
2429 else {
a406f5a3 2430 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2431 sdhci_transfer_pio(host);
2432
6ba736a1
PO		 2433 /*
2434 * We currently don't do anything fancy with DMA
2435 * boundaries, but as we can't disable the feature
2436 * we need to at least restart the transfer.
f6a03cbf
MV		 2437 *
2438 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2439 * should return a valid address to continue from, but as
2440 * some controllers are faulty, don't trust them.
6ba736a1 2441 */
f6a03cbf
MV		 2442 if (intmask & SDHCI_INT_DMA_END) {
2443 u32 dmastart, dmanow;
2444 dmastart = sg_dma_address(host->data->sg);
2445 dmanow = dmastart + host->data->bytes_xfered;
2446 /*
2447 * Force update to the next DMA block boundary.
2448 */
2449 dmanow = (dmanow &
2450 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2451 SDHCI_DEFAULT_BOUNDARY_SIZE;
2452 host->data->bytes_xfered = dmanow - dmastart;
2453 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2454 " next 0x%08x\n",
2455 mmc_hostname(host->mmc), dmastart,
2456 host->data->bytes_xfered, dmanow);
2457 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2458 }
6ba736a1 2459
e538fbe8 2460 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2461 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2462 /*
2463 * Data managed to finish before the
2464 * command completed. Make sure we do
2465 * things in the proper order.
2466 */
2467 host->data_early = 1;
2468 } else {
2469 sdhci_finish_data(host);
2470 }
2471 }
d129bceb
PO		 2472 }
2473}
2474
7d12e780 2475static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2476{
781e989c 2477 irqreturn_t result = IRQ_NONE;
66fd8ad5 2478 struct sdhci_host *host = dev_id;
41005003 2479 u32 intmask, mask, unexpected = 0;
781e989c 2480 int max_loops = 16;
d129bceb
PO		 2481
2482 spin_lock(&host->lock);
2483
be138554 2484 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2485 spin_unlock(&host->lock);
655bca76 2486 return IRQ_NONE;
66fd8ad5
AH		 2487 }
2488
4e4141a5 2489 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2490 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2491 result = IRQ_NONE;
2492 goto out;
2493 }
2494
41005003
RK		 2495 do {
2496 /* Clear selected interrupts. */
2497 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2498 SDHCI_INT_BUS_POWER);
2499 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2500
41005003
RK		 2501 DBG("*** %s got interrupt: 0x%08x\n",
2502 mmc_hostname(host->mmc), intmask);
d129bceb 2503
41005003
RK		 2504 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2505 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2506 SDHCI_CARD_PRESENT;
d129bceb 2507
41005003
RK		 2508 /*
2509 * There is a observation on i.mx esdhc. INSERT
2510 * bit will be immediately set again when it gets
2511 * cleared, if a card is inserted. We have to mask
2512 * the irq to prevent interrupt storm which will
2513 * freeze the system. And the REMOVE gets the
2514 * same situation.
2515 *
2516 * More testing are needed here to ensure it works
2517 * for other platforms though.
2518 */
b537f94c
RK		 2519 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2520 SDHCI_INT_CARD_REMOVE);
2521 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2522 SDHCI_INT_CARD_INSERT;
2523 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2524 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2525
2526 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2527 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2528
2529 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2530 SDHCI_INT_CARD_REMOVE);
2531 result = IRQ_WAKE_THREAD;
41005003 2532 }
d129bceb 2533
41005003 2534 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2535 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2536 &intmask);
964f9ce2 2537
41005003
RK		 2538 if (intmask & SDHCI_INT_DATA_MASK)
2539 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2540
41005003
RK		 2541 if (intmask & SDHCI_INT_BUS_POWER)
2542 pr_err("%s: Card is consuming too much power!\n",
2543 mmc_hostname(host->mmc));
3192a28f 2544
781e989c
RK		 2545 if (intmask & SDHCI_INT_CARD_INT) {
2546 sdhci_enable_sdio_irq_nolock(host, false);
2547 host->thread_isr |= SDHCI_INT_CARD_INT;
2548 result = IRQ_WAKE_THREAD;
2549 }
f75979b7 2550
41005003
RK		 2551 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2552 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2553 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2554 SDHCI_INT_CARD_INT);
f75979b7 2555
41005003
RK		 2556 if (intmask) {
2557 unexpected |= intmask;
2558 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2559 }
d129bceb 2560
781e989c
RK		 2561 if (result == IRQ_NONE)
2562 result = IRQ_HANDLED;
d129bceb 2563
41005003 2564 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2565 } while (intmask && --max_loops);
d129bceb
PO		 2566out:
2567 spin_unlock(&host->lock);
2568
6379b237
AS		 2569 if (unexpected) {
2570 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2571 mmc_hostname(host->mmc), unexpected);
2572 sdhci_dumpregs(host);
2573 }
f75979b7 2574
d129bceb
PO		 2575 return result;
2576}
2577
781e989c
RK		 2578static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2579{
2580 struct sdhci_host *host = dev_id;
2581 unsigned long flags;
2582 u32 isr;
2583
2584 spin_lock_irqsave(&host->lock, flags);
2585 isr = host->thread_isr;
2586 host->thread_isr = 0;
2587 spin_unlock_irqrestore(&host->lock, flags);
2588
3560db8e 2589 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2590 struct mmc_host *mmc = host->mmc;
2591
2592 mmc->ops->card_event(mmc);
2593 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2594 }
2595
781e989c
RK		 2596 if (isr & SDHCI_INT_CARD_INT) {
2597 sdio_run_irqs(host->mmc);
2598
2599 spin_lock_irqsave(&host->lock, flags);
2600 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2601 sdhci_enable_sdio_irq_nolock(host, true);
2602 spin_unlock_irqrestore(&host->lock, flags);
2603 }
2604
2605 return isr ? IRQ_HANDLED : IRQ_NONE;
2606}
2607
d129bceb
PO		 2608/*****************************************************************************\
2609 * *
2610 * Suspend/resume *
2611 * *
2612\*****************************************************************************/
2613
2614#ifdef CONFIG_PM
84d62605
LD		 2615/*
2616 * To enable wakeup events, the corresponding events have to be enabled in
2617 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2618 * Table' in the SD Host Controller Standard Specification.
2619 * It is useless to restore SDHCI_INT_ENABLE state in
2620 * sdhci_disable_irq_wakeups() since it will be set by
2621 * sdhci_enable_card_detection() or sdhci_init().
2622 */
ad080d79
KL		 2623void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2624{
2625 u8 val;
2626 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2627 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2628 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2629 SDHCI_INT_CARD_INT;
ad080d79
KL		 2630
2631 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2632 val |= mask ;
2633 /* Avoid fake wake up */
84d62605 2634 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2635 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2636 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2637 }
ad080d79 2638 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2639 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2640}
2641EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2642
0b10f478 2643static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2644{
2645 u8 val;
2646 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2647 | SDHCI_WAKE_ON_INT;
2648
2649 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2650 val &= ~mask;
2651 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2652}
d129bceb 2653
29495aa0 2654int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2655{
7260cf5e
AV		 2656 sdhci_disable_card_detection(host);
2657
66c39dfc
AH		 2658 mmc_retune_timer_stop(host->mmc);
2659 mmc_retune_needed(host->mmc);
cf2b5eea 2660
ad080d79 2661 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2662 host->ier = 0;
2663 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2664 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2665 free_irq(host->irq, host);
2666 } else {
2667 sdhci_enable_irq_wakeups(host);
2668 enable_irq_wake(host->irq);
2669 }
4ee14ec6 2670 return 0;
d129bceb
PO		 2671}
2672
b8c86fc5 2673EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2674
b8c86fc5
PO		 2675int sdhci_resume_host(struct sdhci_host *host)
2676{
d3940f27 2677 struct mmc_host *mmc = host->mmc;
4ee14ec6 2678 int ret = 0;
d129bceb 2679
a13abc7b 2680 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2681 if (host->ops->enable_dma)
2682 host->ops->enable_dma(host);
2683 }
d129bceb 2684
6308d290
AH		 2685 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2686 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2687 /* Card keeps power but host controller does not */
2688 sdhci_init(host, 0);
2689 host->pwr = 0;
2690 host->clock = 0;
d3940f27 2691 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2692 } else {
2693 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2694 mmiowb();
2695 }
b8c86fc5 2696
14a7b416
HC		 2697 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2698 ret = request_threaded_irq(host->irq, sdhci_irq,
2699 sdhci_thread_irq, IRQF_SHARED,
2700 mmc_hostname(host->mmc), host);
2701 if (ret)
2702 return ret;
2703 } else {
2704 sdhci_disable_irq_wakeups(host);
2705 disable_irq_wake(host->irq);
2706 }
2707
7260cf5e
AV		 2708 sdhci_enable_card_detection(host);
2709
2f4cbb3d 2710 return ret;
d129bceb
PO		 2711}
2712
b8c86fc5 2713EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2714
66fd8ad5
AH		 2715int sdhci_runtime_suspend_host(struct sdhci_host *host)
2716{
2717 unsigned long flags;
66fd8ad5 2718
66c39dfc
AH		 2719 mmc_retune_timer_stop(host->mmc);
2720 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2721
2722 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2723 host->ier &= SDHCI_INT_CARD_INT;
2724 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2725 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2726 spin_unlock_irqrestore(&host->lock, flags);
2727
781e989c 2728 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2729
2730 spin_lock_irqsave(&host->lock, flags);
2731 host->runtime_suspended = true;
2732 spin_unlock_irqrestore(&host->lock, flags);
2733
8a125bad 2734 return 0;
66fd8ad5
AH		 2735}
2736EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2737
2738int sdhci_runtime_resume_host(struct sdhci_host *host)
2739{
d3940f27 2740 struct mmc_host *mmc = host->mmc;
66fd8ad5 2741 unsigned long flags;
8a125bad 2742 int host_flags = host->flags;
66fd8ad5
AH		 2743
2744 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2745 if (host->ops->enable_dma)
2746 host->ops->enable_dma(host);
2747 }
2748
2749 sdhci_init(host, 0);
2750
2751 /* Force clock and power re-program */
2752 host->pwr = 0;
2753 host->clock = 0;
d3940f27
AH		 2754 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2755 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2756
52983382
KL		 2757 if ((host_flags & SDHCI_PV_ENABLED) &&
2758 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2759 spin_lock_irqsave(&host->lock, flags);
2760 sdhci_enable_preset_value(host, true);
2761 spin_unlock_irqrestore(&host->lock, flags);
2762 }
66fd8ad5 2763
66fd8ad5
AH		 2764 spin_lock_irqsave(&host->lock, flags);
2765
2766 host->runtime_suspended = false;
2767
2768 /* Enable SDIO IRQ */
ef104333 2769 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2770 sdhci_enable_sdio_irq_nolock(host, true);
2771
2772 /* Enable Card Detection */
2773 sdhci_enable_card_detection(host);
2774
2775 spin_unlock_irqrestore(&host->lock, flags);
2776
8a125bad 2777 return 0;
66fd8ad5
AH		 2778}
2779EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2780
162d6f98 2781#endif /* CONFIG_PM */
66fd8ad5 2782
d129bceb
PO		 2783/*****************************************************************************\
2784 * *
b8c86fc5 2785 * Device allocation/registration *
d129bceb
PO		 2786 * *
2787\*****************************************************************************/
2788
b8c86fc5
PO		 2789struct sdhci_host *sdhci_alloc_host(struct device *dev,
2790 size_t priv_size)
d129bceb 2791{
d129bceb
PO		 2792 struct mmc_host *mmc;
2793 struct sdhci_host *host;
2794
b8c86fc5 2795 WARN_ON(dev == NULL);
d129bceb 2796
b8c86fc5 2797 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2798 if (!mmc)
b8c86fc5 2799 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2800
2801 host = mmc_priv(mmc);
2802 host->mmc = mmc;
bf60e592
AH		 2803 host->mmc_host_ops = sdhci_ops;
2804 mmc->ops = &host->mmc_host_ops;
d129bceb 2805
8cb851a4
AH		 2806 host->flags = SDHCI_SIGNALING_330;
2807
b8c86fc5
PO		 2808 return host;
2809}
8a4da143 2810
b8c86fc5 2811EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2812
7b91369b
AC		 2813static int sdhci_set_dma_mask(struct sdhci_host *host)
2814{
2815 struct mmc_host *mmc = host->mmc;
2816 struct device *dev = mmc_dev(mmc);
2817 int ret = -EINVAL;
2818
2819 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2820 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2821
2822 /* Try 64-bit mask if hardware is capable of it */
2823 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2824 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2825 if (ret) {
2826 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2827 mmc_hostname(mmc));
2828 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2829 }
2830 }
2831
2832 /* 32-bit mask as default & fallback */
2833 if (ret) {
2834 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2835 if (ret)
2836 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2837 mmc_hostname(mmc));
2838 }
2839
2840 return ret;
2841}
2842
6132a3bf
AH		 2843void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2844{
2845 u16 v;
2846
2847 if (host->read_caps)
2848 return;
2849
2850 host->read_caps = true;
2851
2852 if (debug_quirks)
2853 host->quirks = debug_quirks;
2854
2855 if (debug_quirks2)
2856 host->quirks2 = debug_quirks2;
2857
2858 sdhci_do_reset(host, SDHCI_RESET_ALL);
2859
2860 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
2861 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
2862
2863 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
2864 return;
2865
2866 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
2867
2868 if (host->version < SDHCI_SPEC_300)
2869 return;
2870
2871 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
2872}
2873EXPORT_SYMBOL_GPL(__sdhci_read_caps);
2874
52f5336d 2875int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 2876{
2877 struct mmc_host *mmc;
f2119df6
AN		 2878 u32 max_current_caps;
2879 unsigned int ocr_avail;
f5fa92e5 2880 unsigned int override_timeout_clk;
59241757 2881 u32 max_clk;
b8c86fc5 2882 int ret;
d129bceb 2883
b8c86fc5
PO		 2884 WARN_ON(host == NULL);
2885 if (host == NULL)
2886 return -EINVAL;
d129bceb 2887
b8c86fc5 2888 mmc = host->mmc;
d129bceb 2889
6132a3bf 2890 sdhci_read_caps(host);
d129bceb 2891
f5fa92e5
AH		 2892 override_timeout_clk = host->timeout_clk;
2893
85105c53 2894 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2895 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2896 mmc_hostname(mmc), host->version);
4a965505
PO		 2897 }
2898
b8c86fc5 2899 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2900 host->flags |= SDHCI_USE_SDMA;
28da3589 2901 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 2902 DBG("Controller doesn't have SDMA capability\n");
67435274 2903 else
a13abc7b 2904 host->flags |= SDHCI_USE_SDMA;
d129bceb 2905
b8c86fc5 2906 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2907 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2908 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2909 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2910 }
2911
f2119df6 2912 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 2913 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 2914 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2915
2916 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2917 (host->flags & SDHCI_USE_ADMA)) {
2918 DBG("Disabling ADMA as it is marked broken\n");
2919 host->flags &= ~SDHCI_USE_ADMA;
2920 }
2921
e57a5f61
AH		 2922 /*
2923 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2924 * and *must* do 64-bit DMA. A driver has the opportunity to change
2925 * that during the first call to ->enable_dma(). Similarly
2926 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2927 * implement.
2928 */
28da3589 2929 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 2930 host->flags |= SDHCI_USE_64_BIT_DMA;
2931
a13abc7b 2932 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 2933 ret = sdhci_set_dma_mask(host);
2934
2935 if (!ret && host->ops->enable_dma)
2936 ret = host->ops->enable_dma(host);
2937
2938 if (ret) {
2939 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2940 mmc_hostname(mmc));
2941 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2942
2943 ret = 0;
d129bceb
PO		 2944 }
2945 }
2946
e57a5f61
AH		 2947 /* SDMA does not support 64-bit DMA */
2948 if (host->flags & SDHCI_USE_64_BIT_DMA)
2949 host->flags &= ~SDHCI_USE_SDMA;
2950
2134a922 2951 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2952 dma_addr_t dma;
2953 void *buf;
2954
2134a922 2955 /*
76fe379a
AH		 2956 * The DMA descriptor table size is calculated as the maximum
2957 * number of segments times 2, to allow for an alignment
2958 * descriptor for each segment, plus 1 for a nop end descriptor,
2959 * all multipled by the descriptor size.
2134a922 2960 */
e57a5f61
AH		 2961 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2962 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2963 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2964 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2965 } else {
2966 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2967 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2968 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2969 }
e66e61cb 2970
04a5ae6f 2971 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2972 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2973 host->adma_table_sz, &dma, GFP_KERNEL);
2974 if (!buf) {
6606110d 2975 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2976 mmc_hostname(mmc));
2977 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2978 } else if ((dma + host->align_buffer_sz) &
2979 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2980 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2981 mmc_hostname(mmc));
d1e49f77 2982 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2983 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2984 host->adma_table_sz, buf, dma);
2985 } else {
2986 host->align_buffer = buf;
2987 host->align_addr = dma;
edd63fcc 2988
e66e61cb
RK		 2989 host->adma_table = buf + host->align_buffer_sz;
2990 host->adma_addr = dma + host->align_buffer_sz;
2991 }
2134a922
PO		 2992 }
2993
7659150c
PO		 2994 /*
2995 * If we use DMA, then it's up to the caller to set the DMA
2996 * mask, but PIO does not need the hw shim so we set a new
2997 * mask here in that case.
2998 */
a13abc7b 2999 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3000 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3001 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3002 }
d129bceb 3003
c4687d5f 3004 if (host->version >= SDHCI_SPEC_300)
28da3589 3005 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3006 >> SDHCI_CLOCK_BASE_SHIFT;
3007 else
28da3589 3008 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3009 >> SDHCI_CLOCK_BASE_SHIFT;
3010
4240ff0a 3011 host->max_clk *= 1000000;
f27f47ef
AV		 3012 if (host->max_clk == 0 || host->quirks &
3013 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3014 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3015 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3016 mmc_hostname(mmc));
eb5c20de
AH		 3017 ret = -ENODEV;
3018 goto undma;
4240ff0a
BD		 3019 }
3020 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3021 }
d129bceb 3022
c3ed3877
AN		 3023 /*
3024 * In case of Host Controller v3.00, find out whether clock
3025 * multiplier is supported.
3026 */
28da3589 3027 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3028 SDHCI_CLOCK_MUL_SHIFT;
3029
3030 /*
3031 * In case the value in Clock Multiplier is 0, then programmable
3032 * clock mode is not supported, otherwise the actual clock
3033 * multiplier is one more than the value of Clock Multiplier
3034 * in the Capabilities Register.
3035 */
3036 if (host->clk_mul)
3037 host->clk_mul += 1;
3038
d129bceb
PO		 3039 /*
3040 * Set host parameters.
3041 */
59241757
DA		 3042 max_clk = host->max_clk;
3043
ce5f036b 3044 if (host->ops->get_min_clock)
a9e58f25 3045 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3046 else if (host->version >= SDHCI_SPEC_300) {
3047 if (host->clk_mul) {
3048 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3049 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3050 } else
3051 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3052 } else
0397526d 3053 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3054
d310ae49 3055 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3056 mmc->f_max = max_clk;
3057
28aab053 3058 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3059 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3060 SDHCI_TIMEOUT_CLK_SHIFT;
3061 if (host->timeout_clk == 0) {
3062 if (host->ops->get_timeout_clock) {
3063 host->timeout_clk =
3064 host->ops->get_timeout_clock(host);
3065 } else {
3066 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3067 mmc_hostname(mmc));
eb5c20de
AH		 3068 ret = -ENODEV;
3069 goto undma;
28aab053 3070 }
272308ca 3071 }
272308ca 3072
28da3589 3073 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3074 host->timeout_clk *= 1000;
272308ca 3075
99513624
AH		 3076 if (override_timeout_clk)
3077 host->timeout_clk = override_timeout_clk;
3078
28aab053 3079 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3080 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3081 mmc->max_busy_timeout /= host->timeout_clk;
3082 }
58d1246d 3083
e89d456f 3084 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3085 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3086
3087 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3088 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3089
8edf6371 3090 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3091 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3092 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3093 !(host->flags & SDHCI_USE_SDMA)) &&
3094 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3095 host->flags |= SDHCI_AUTO_CMD23;
3096 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3097 } else {
3098 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3099 }
3100
15ec4461
PR		 3101 /*
3102 * A controller may support 8-bit width, but the board itself
3103 * might not have the pins brought out. Boards that support
3104 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3105 * their platform code before calling sdhci_add_host(), and we
3106 * won't assume 8-bit width for hosts without that CAP.
3107 */
5fe23c7f 3108 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3109 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3110
63ef5d8c
JH		 3111 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3112 mmc->caps &= ~MMC_CAP_CMD23;
3113
28da3589 3114 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3115 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3116
176d1ed4 3117 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3118 mmc_card_is_removable(mmc) &&
287980e4 3119 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3120 mmc->caps |= MMC_CAP_NEEDS_POLL;
3121
3a48edc4 3122 /* If there are external regulators, get them */
eb5c20de
AH		 3123 ret = mmc_regulator_get_supply(mmc);
3124 if (ret == -EPROBE_DEFER)
3125 goto undma;
3a48edc4 3126
6231f3de 3127 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3128 if (!IS_ERR(mmc->supply.vqmmc)) {
3129 ret = regulator_enable(mmc->supply.vqmmc);
3130 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3131 1950000))
28da3589
AH		 3132 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3133 SDHCI_SUPPORT_SDR50 |
3134 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3135 if (ret) {
3136 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3137 mmc_hostname(mmc), ret);
4bb74313 3138 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3139 }
8363c374 3140 }
6231f3de 3141
28da3589
AH		 3142 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3143 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3144 SDHCI_SUPPORT_DDR50);
3145 }
6a66180a 3146
4188bba0 3147 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3148 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3149 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3150 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3151
3152 /* SDR104 supports also implies SDR50 support */
28da3589 3153 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3154 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3155 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3156 * field can be promoted to support HS200.
3157 */
549c0b18 3158 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3159 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3160 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3161 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3162 }
f2119df6 3163
e9fb05d5 3164 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3165 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3166 mmc->caps2 |= MMC_CAP2_HS400;
3167
549c0b18
AH		 3168 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3169 (IS_ERR(mmc->supply.vqmmc) ||
3170 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3171 1300000)))
3172 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3173
28da3589
AH		 3174 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3175 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3176 mmc->caps |= MMC_CAP_UHS_DDR50;
3177
069c9f14 3178 /* Does the host need tuning for SDR50? */
28da3589 3179 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3180 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3181
d6d50a15 3182 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3183 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3184 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3185 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3186 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3187 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3188 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3189
cf2b5eea 3190 /* Initial value for re-tuning timer count */
28da3589
AH		 3191 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3192 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3193
3194 /*
3195 * In case Re-tuning Timer is not disabled, the actual value of
3196 * re-tuning timer will be 2 ^ (n - 1).
3197 */
3198 if (host->tuning_count)
3199 host->tuning_count = 1 << (host->tuning_count - 1);
3200
3201 /* Re-tuning mode supported by the Host Controller */
28da3589 3202 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3203 SDHCI_RETUNING_MODE_SHIFT;
3204
8f230f45 3205 ocr_avail = 0;
bad37e1a 3206
f2119df6
AN		 3207 /*
3208 * According to SD Host Controller spec v3.00, if the Host System
3209 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3210 * the value is meaningful only if Voltage Support in the Capabilities
3211 * register is set. The actual current value is 4 times the register
3212 * value.
3213 */
3214 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3215 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3216 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3217 if (curr > 0) {
3218
3219 /* convert to SDHCI_MAX_CURRENT format */
3220 curr = curr/1000; /* convert to mA */
3221 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3222
3223 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3224 max_current_caps =
3225 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3226 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3227 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3228 }
3229 }
f2119df6 3230
28da3589 3231 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3232 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3233
55c4665e 3234 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3235 SDHCI_MAX_CURRENT_330_MASK) >>
3236 SDHCI_MAX_CURRENT_330_SHIFT) *
3237 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3238 }
28da3589 3239 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3240 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3241
55c4665e 3242 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3243 SDHCI_MAX_CURRENT_300_MASK) >>
3244 SDHCI_MAX_CURRENT_300_SHIFT) *
3245 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3246 }
28da3589 3247 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3248 ocr_avail |= MMC_VDD_165_195;
3249
55c4665e 3250 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3251 SDHCI_MAX_CURRENT_180_MASK) >>
3252 SDHCI_MAX_CURRENT_180_SHIFT) *
3253 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3254 }
3255
5fd26c7e
UH		 3256 /* If OCR set by host, use it instead. */
3257 if (host->ocr_mask)
3258 ocr_avail = host->ocr_mask;
3259
3260 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3261 if (mmc->ocr_avail)
52221610 3262 ocr_avail = mmc->ocr_avail;
3a48edc4 3263
8f230f45
TI		 3264 mmc->ocr_avail = ocr_avail;
3265 mmc->ocr_avail_sdio = ocr_avail;
3266 if (host->ocr_avail_sdio)
3267 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3268 mmc->ocr_avail_sd = ocr_avail;
3269 if (host->ocr_avail_sd)
3270 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3271 else /* normal SD controllers don't support 1.8V */
3272 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3273 mmc->ocr_avail_mmc = ocr_avail;
3274 if (host->ocr_avail_mmc)
3275 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3276
3277 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3278 pr_err("%s: Hardware doesn't report any support voltages.\n",
3279 mmc_hostname(mmc));
eb5c20de
AH		 3280 ret = -ENODEV;
3281 goto unreg;
146ad66e
PO		 3282 }
3283
8cb851a4
AH		 3284 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3285 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3286 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3287 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3288 host->flags |= SDHCI_SIGNALING_180;
3289
3290 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3291 host->flags |= SDHCI_SIGNALING_120;
3292
d129bceb
PO		 3293 spin_lock_init(&host->lock);
3294
3295 /*
2134a922
PO		 3296 * Maximum number of segments. Depends on if the hardware
3297 * can do scatter/gather or not.
d129bceb 3298 */
2134a922 3299 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3300 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3301 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3302 mmc->max_segs = 1;
2134a922 3303 else /* PIO */
4fb213f8 3304 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3305
3306 /*
ac00531d
AH		 3307 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3308 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3309 * is less anyway.
d129bceb 3310 */
55db890a 3311 mmc->max_req_size = 524288;
d129bceb
PO		 3312
3313 /*
3314 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3315 * of bytes. When doing hardware scatter/gather, each entry cannot
3316 * be larger than 64 KiB though.
d129bceb 3317 */
30652aa3
OJ		 3318 if (host->flags & SDHCI_USE_ADMA) {
3319 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3320 mmc->max_seg_size = 65535;
3321 else
3322 mmc->max_seg_size = 65536;
3323 } else {
2134a922 3324 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3325 }
d129bceb 3326
fe4a3c7a
PO		 3327 /*
3328 * Maximum block size. This varies from controller to controller and
3329 * is specified in the capabilities register.
3330 */
0633f654
AV		 3331 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3332 mmc->max_blk_size = 2;
3333 } else {
28da3589 3334 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3335 SDHCI_MAX_BLOCK_SHIFT;
3336 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3337 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3338 mmc_hostname(mmc));
0633f654
AV		 3339 mmc->max_blk_size = 0;
3340 }
3341 }
3342
3343 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3344
55db890a
PO		 3345 /*
3346 * Maximum block count.
3347 */
1388eefd 3348 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3349
52f5336d
AH		 3350 return 0;
3351
3352unreg:
3353 if (!IS_ERR(mmc->supply.vqmmc))
3354 regulator_disable(mmc->supply.vqmmc);
3355undma:
3356 if (host->align_buffer)
3357 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3358 host->adma_table_sz, host->align_buffer,
3359 host->align_addr);
3360 host->adma_table = NULL;
3361 host->align_buffer = NULL;
3362
3363 return ret;
3364}
3365EXPORT_SYMBOL_GPL(sdhci_setup_host);
3366
3367int __sdhci_add_host(struct sdhci_host *host)
3368{
3369 struct mmc_host *mmc = host->mmc;
3370 int ret;
3371
d129bceb
PO		 3372 /*
3373 * Init tasklets.
3374 */
d129bceb
PO		 3375 tasklet_init(&host->finish_tasklet,
3376 sdhci_tasklet_finish, (unsigned long)host);
3377
e4cad1b5 3378 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3379
250fb7b4 3380 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3381
2af502ca
SG		 3382 sdhci_init(host, 0);
3383
781e989c
RK		 3384 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3385 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3386 if (ret) {
3387 pr_err("%s: Failed to request IRQ %d: %d\n",
3388 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3389 goto untasklet;
0fc81ee3 3390 }
d129bceb 3391
d129bceb
PO		 3392#ifdef CONFIG_MMC_DEBUG
3393 sdhci_dumpregs(host);
3394#endif
3395
061d17a6 3396 ret = sdhci_led_register(host);
0fc81ee3
MB		 3397 if (ret) {
3398 pr_err("%s: Failed to register LED device: %d\n",
3399 mmc_hostname(mmc), ret);
eb5c20de 3400 goto unirq;
0fc81ee3 3401 }
2f730fec 3402
5f25a66f
PO		 3403 mmiowb();
3404
eb5c20de
AH		 3405 ret = mmc_add_host(mmc);
3406 if (ret)
3407 goto unled;
d129bceb 3408
a3c76eb9 3409 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3410 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3411 (host->flags & SDHCI_USE_ADMA) ?
3412 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3413 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3414
7260cf5e
AV		 3415 sdhci_enable_card_detection(host);
3416
d129bceb
PO		 3417 return 0;
3418
eb5c20de 3419unled:
061d17a6 3420 sdhci_led_unregister(host);
eb5c20de 3421unirq:
03231f9b 3422 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3423 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3424 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3425 free_irq(host->irq, host);
8ef1a143 3426untasklet:
d129bceb 3427 tasklet_kill(&host->finish_tasklet);
52f5336d 3428
eb5c20de
AH		 3429 if (!IS_ERR(mmc->supply.vqmmc))
3430 regulator_disable(mmc->supply.vqmmc);
52f5336d 3431
eb5c20de
AH		 3432 if (host->align_buffer)
3433 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3434 host->adma_table_sz, host->align_buffer,
3435 host->align_addr);
3436 host->adma_table = NULL;
3437 host->align_buffer = NULL;
d129bceb
PO		 3438
3439 return ret;
3440}
52f5336d
AH		 3441EXPORT_SYMBOL_GPL(__sdhci_add_host);
3442
3443int sdhci_add_host(struct sdhci_host *host)
3444{
3445 int ret;
3446
3447 ret = sdhci_setup_host(host);
3448 if (ret)
3449 return ret;
d129bceb 3450
52f5336d
AH		 3451 return __sdhci_add_host(host);
3452}
b8c86fc5 3453EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3454
1e72859e 3455void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3456{
3a48edc4 3457 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3458 unsigned long flags;
3459
3460 if (dead) {
3461 spin_lock_irqsave(&host->lock, flags);
3462
3463 host->flags |= SDHCI_DEVICE_DEAD;
3464
3465 if (host->mrq) {
a3c76eb9 3466 pr_err("%s: Controller removed during "
4e743f1f 3467 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3468
3469 host->mrq->cmd->error = -ENOMEDIUM;
3470 tasklet_schedule(&host->finish_tasklet);
3471 }
3472
3473 spin_unlock_irqrestore(&host->lock, flags);
3474 }
3475
7260cf5e
AV		 3476 sdhci_disable_card_detection(host);
3477
4e743f1f 3478 mmc_remove_host(mmc);
d129bceb 3479
061d17a6 3480 sdhci_led_unregister(host);
2f730fec 3481
1e72859e 3482 if (!dead)
03231f9b 3483 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3484
b537f94c
RK		 3485 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3486 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3487 free_irq(host->irq, host);
3488
3489 del_timer_sync(&host->timer);
3490
d129bceb 3491 tasklet_kill(&host->finish_tasklet);
2134a922 3492
3a48edc4
TK		 3493 if (!IS_ERR(mmc->supply.vqmmc))
3494 regulator_disable(mmc->supply.vqmmc);
6231f3de 3495
edd63fcc 3496 if (host->align_buffer)
e66e61cb
RK		 3497 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3498 host->adma_table_sz, host->align_buffer,
3499 host->align_addr);
2134a922 3500
4efaa6fb 3501 host->adma_table = NULL;
2134a922 3502 host->align_buffer = NULL;
d129bceb
PO		 3503}
3504
b8c86fc5 3505EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3506
b8c86fc5 3507void sdhci_free_host(struct sdhci_host *host)
d129bceb 3508{
b8c86fc5 3509 mmc_free_host(host->mmc);
d129bceb
PO		 3510}
3511
b8c86fc5 3512EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3513
3514/*****************************************************************************\
3515 * *
3516 * Driver init/exit *
3517 * *
3518\*****************************************************************************/
3519
3520static int __init sdhci_drv_init(void)
3521{
a3c76eb9 3522 pr_info(DRIVER_NAME
52fbf9c9 3523 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3524 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3525
b8c86fc5 3526 return 0;
d129bceb
PO		 3527}
3528
3529static void __exit sdhci_drv_exit(void)
3530{
d129bceb
PO		 3531}
3532
3533module_init(sdhci_drv_init);
3534module_exit(sdhci_drv_exit);
3535
df673b22 3536module_param(debug_quirks, uint, 0444);
66fd8ad5 3537module_param(debug_quirks2, uint, 0444);
67435274 3538
32710e8f 3539MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3540MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3541MODULE_LICENSE("GPL");
67435274 3542
df673b22 3543MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3544MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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