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mmc: Revert "mmc: sdhci: Fix SDHCI_QUIRK_TIMEOUT_USES_SDCLK"
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
22113efd 26#include <linux/mmc/mmc.h>
d129bceb 27#include <linux/mmc/host.h>
d129bceb 28
d129bceb
PO		 29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
d129bceb 32
d129bceb 33#define DBG(f, x...) \
c6563178 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 35
f9134319
PO		 36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
67435274 44
d129bceb
PO		 45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 49static int sdhci_execute_tuning(struct mmc_host *mmc);
50static void sdhci_tuning_timer(unsigned long data);
d129bceb
PO		 51
52static void sdhci_dumpregs(struct sdhci_host *host)
53{
412ab659
PR		 54 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
55 mmc_hostname(host->mmc));
d129bceb
PO		 56
57 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 60 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 63 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 66 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 69 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 72 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 75 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 78 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 81 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 82 sdhci_readw(host, SDHCI_ACMD12_ERR),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 84 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 85 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 89 sdhci_readl(host, SDHCI_MAX_CURRENT));
f2119df6
AN		 90 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
91 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 92
be3f4ae0
BD		 93 if (host->flags & SDHCI_USE_ADMA)
94 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97
d129bceb
PO		 98 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
99}
100
101/*****************************************************************************\
102 * *
103 * Low level functions *
104 * *
105\*****************************************************************************/
106
7260cf5e
AV		 107static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
108{
109 u32 ier;
110
111 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
112 ier &= ~clear;
113 ier |= set;
114 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
115 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
116}
117
118static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
119{
120 sdhci_clear_set_irqs(host, 0, irqs);
121}
122
123static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
124{
125 sdhci_clear_set_irqs(host, irqs, 0);
126}
127
128static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
129{
d25928d1 130 u32 present, irqs;
7260cf5e 131
68d1fb7e
AV		 132 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
133 return;
134
d25928d1
SG		 135 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
136 SDHCI_CARD_PRESENT;
137 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
138
7260cf5e
AV		 139 if (enable)
140 sdhci_unmask_irqs(host, irqs);
141 else
142 sdhci_mask_irqs(host, irqs);
143}
144
145static void sdhci_enable_card_detection(struct sdhci_host *host)
146{
147 sdhci_set_card_detection(host, true);
148}
149
150static void sdhci_disable_card_detection(struct sdhci_host *host)
151{
152 sdhci_set_card_detection(host, false);
153}
154
d129bceb
PO		 155static void sdhci_reset(struct sdhci_host *host, u8 mask)
156{
e16514d8 157 unsigned long timeout;
063a9dbb 158 u32 uninitialized_var(ier);
e16514d8 159
b8c86fc5 160 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 161 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 162 SDHCI_CARD_PRESENT))
163 return;
164 }
165
063a9dbb
AV		 166 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
167 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
168
393c1a34
PR		 169 if (host->ops->platform_reset_enter)
170 host->ops->platform_reset_enter(host, mask);
171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
e16514d8 174 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 175 host->clock = 0;
176
e16514d8
PO		 177 /* Wait max 100 ms */
178 timeout = 100;
179
180 /* hw clears the bit when it's done */
4e4141a5 181 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 182 if (timeout == 0) {
acf1da45 183 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 184 mmc_hostname(host->mmc), (int)mask);
185 sdhci_dumpregs(host);
186 return;
187 }
188 timeout--;
189 mdelay(1);
d129bceb 190 }
063a9dbb 191
393c1a34
PR		 192 if (host->ops->platform_reset_exit)
193 host->ops->platform_reset_exit(host, mask);
194
063a9dbb
AV		 195 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
196 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 197}
198
2f4cbb3d
NP		 199static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
200
201static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 202{
2f4cbb3d
NP		 203 if (soft)
204 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
205 else
206 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 207
7260cf5e
AV		 208 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
209 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 210 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
211 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 212 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 213
214 if (soft) {
215 /* force clock reconfiguration */
216 host->clock = 0;
217 sdhci_set_ios(host->mmc, &host->mmc->ios);
218 }
7260cf5e 219}
d129bceb 220
7260cf5e
AV		 221static void sdhci_reinit(struct sdhci_host *host)
222{
2f4cbb3d 223 sdhci_init(host, 0);
7260cf5e 224 sdhci_enable_card_detection(host);
d129bceb
PO		 225}
226
227static void sdhci_activate_led(struct sdhci_host *host)
228{
229 u8 ctrl;
230
4e4141a5 231 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 232 ctrl |= SDHCI_CTRL_LED;
4e4141a5 233 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 234}
235
236static void sdhci_deactivate_led(struct sdhci_host *host)
237{
238 u8 ctrl;
239
4e4141a5 240 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 241 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 242 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 243}
244
f9134319 245#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 246static void sdhci_led_control(struct led_classdev *led,
247 enum led_brightness brightness)
248{
249 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
250 unsigned long flags;
251
252 spin_lock_irqsave(&host->lock, flags);
253
254 if (brightness == LED_OFF)
255 sdhci_deactivate_led(host);
256 else
257 sdhci_activate_led(host);
258
259 spin_unlock_irqrestore(&host->lock, flags);
260}
261#endif
262
d129bceb
PO		 263/*****************************************************************************\
264 * *
265 * Core functions *
266 * *
267\*****************************************************************************/
268
a406f5a3 269static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 270{
7659150c
PO		 271 unsigned long flags;
272 size_t blksize, len, chunk;
7244b85b 273 u32 uninitialized_var(scratch);
7659150c 274 u8 *buf;
d129bceb 275
a406f5a3 276 DBG("PIO reading\n");
d129bceb 277
a406f5a3 278 blksize = host->data->blksz;
7659150c 279 chunk = 0;
d129bceb 280
7659150c 281 local_irq_save(flags);
d129bceb 282
a406f5a3 283 while (blksize) {
7659150c
PO		 284 if (!sg_miter_next(&host->sg_miter))
285 BUG();
d129bceb 286
7659150c 287 len = min(host->sg_miter.length, blksize);
d129bceb 288
7659150c
PO		 289 blksize -= len;
290 host->sg_miter.consumed = len;
14d836e7 291
7659150c 292 buf = host->sg_miter.addr;
d129bceb 293
7659150c
PO		 294 while (len) {
295 if (chunk == 0) {
4e4141a5 296 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 297 chunk = 4;
a406f5a3 298 }
7659150c
PO		 299
300 *buf = scratch & 0xFF;
301
302 buf++;
303 scratch >>= 8;
304 chunk--;
305 len--;
d129bceb 306 }
a406f5a3 307 }
7659150c
PO		 308
309 sg_miter_stop(&host->sg_miter);
310
311 local_irq_restore(flags);
a406f5a3 312}
d129bceb 313
a406f5a3
PO		 314static void sdhci_write_block_pio(struct sdhci_host *host)
315{
7659150c
PO		 316 unsigned long flags;
317 size_t blksize, len, chunk;
318 u32 scratch;
319 u8 *buf;
d129bceb 320
a406f5a3
PO		 321 DBG("PIO writing\n");
322
323 blksize = host->data->blksz;
7659150c
PO		 324 chunk = 0;
325 scratch = 0;
d129bceb 326
7659150c 327 local_irq_save(flags);
d129bceb 328
a406f5a3 329 while (blksize) {
7659150c
PO		 330 if (!sg_miter_next(&host->sg_miter))
331 BUG();
a406f5a3 332
7659150c
PO		 333 len = min(host->sg_miter.length, blksize);
334
335 blksize -= len;
336 host->sg_miter.consumed = len;
337
338 buf = host->sg_miter.addr;
d129bceb 339
7659150c
PO		 340 while (len) {
341 scratch |= (u32)*buf << (chunk * 8);
342
343 buf++;
344 chunk++;
345 len--;
346
347 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 348 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 349 chunk = 0;
350 scratch = 0;
d129bceb 351 }
d129bceb
PO		 352 }
353 }
7659150c
PO		 354
355 sg_miter_stop(&host->sg_miter);
356
357 local_irq_restore(flags);
a406f5a3
PO		 358}
359
360static void sdhci_transfer_pio(struct sdhci_host *host)
361{
362 u32 mask;
363
364 BUG_ON(!host->data);
365
7659150c 366 if (host->blocks == 0)
a406f5a3
PO		 367 return;
368
369 if (host->data->flags & MMC_DATA_READ)
370 mask = SDHCI_DATA_AVAILABLE;
371 else
372 mask = SDHCI_SPACE_AVAILABLE;
373
4a3cba32
PO		 374 /*
375 * Some controllers (JMicron JMB38x) mess up the buffer bits
376 * for transfers < 4 bytes. As long as it is just one block,
377 * we can ignore the bits.
378 */
379 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
380 (host->data->blocks == 1))
381 mask = ~0;
382
4e4141a5 383 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 384 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
385 udelay(100);
386
a406f5a3
PO		 387 if (host->data->flags & MMC_DATA_READ)
388 sdhci_read_block_pio(host);
389 else
390 sdhci_write_block_pio(host);
d129bceb 391
7659150c
PO		 392 host->blocks--;
393 if (host->blocks == 0)
a406f5a3 394 break;
a406f5a3 395 }
d129bceb 396
a406f5a3 397 DBG("PIO transfer complete.\n");
d129bceb
PO		 398}
399
2134a922
PO		 400static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
401{
402 local_irq_save(*flags);
403 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
404}
405
406static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
407{
408 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
409 local_irq_restore(*flags);
410}
411
118cd17d
BD		 412static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
413{
9e506f35
BD		 414 __le32 *dataddr = (__le32 __force *)(desc + 4);
415 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 416
9e506f35
BD		 417 /* SDHCI specification says ADMA descriptors should be 4 byte
418 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 419
9e506f35
BD		 420 cmdlen[0] = cpu_to_le16(cmd);
421 cmdlen[1] = cpu_to_le16(len);
422
423 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 424}
425
8f1934ce 426static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 427 struct mmc_data *data)
428{
429 int direction;
430
431 u8 *desc;
432 u8 *align;
433 dma_addr_t addr;
434 dma_addr_t align_addr;
435 int len, offset;
436
437 struct scatterlist *sg;
438 int i;
439 char *buffer;
440 unsigned long flags;
441
442 /*
443 * The spec does not specify endianness of descriptor table.
444 * We currently guess that it is LE.
445 */
446
447 if (data->flags & MMC_DATA_READ)
448 direction = DMA_FROM_DEVICE;
449 else
450 direction = DMA_TO_DEVICE;
451
452 /*
453 * The ADMA descriptor table is mapped further down as we
454 * need to fill it with data first.
455 */
456
457 host->align_addr = dma_map_single(mmc_dev(host->mmc),
458 host->align_buffer, 128 * 4, direction);
8d8bb39b 459 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 460 goto fail;
2134a922
PO		 461 BUG_ON(host->align_addr & 0x3);
462
463 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
464 data->sg, data->sg_len, direction);
8f1934ce
PO		 465 if (host->sg_count == 0)
466 goto unmap_align;
2134a922
PO		 467
468 desc = host->adma_desc;
469 align = host->align_buffer;
470
471 align_addr = host->align_addr;
472
473 for_each_sg(data->sg, sg, host->sg_count, i) {
474 addr = sg_dma_address(sg);
475 len = sg_dma_len(sg);
476
477 /*
478 * The SDHCI specification states that ADMA
479 * addresses must be 32-bit aligned. If they
480 * aren't, then we use a bounce buffer for
481 * the (up to three) bytes that screw up the
482 * alignment.
483 */
484 offset = (4 - (addr & 0x3)) & 0x3;
485 if (offset) {
486 if (data->flags & MMC_DATA_WRITE) {
487 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 488 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 489 memcpy(align, buffer, offset);
490 sdhci_kunmap_atomic(buffer, &flags);
491 }
492
118cd17d
BD		 493 /* tran, valid */
494 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 495
496 BUG_ON(offset > 65536);
497
2134a922
PO		 498 align += 4;
499 align_addr += 4;
500
501 desc += 8;
502
503 addr += offset;
504 len -= offset;
505 }
506
2134a922
PO		 507 BUG_ON(len > 65536);
508
118cd17d
BD		 509 /* tran, valid */
510 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 511 desc += 8;
512
513 /*
514 * If this triggers then we have a calculation bug
515 * somewhere. :/
516 */
517 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
518 }
519
70764a90
TA		 520 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
521 /*
522 * Mark the last descriptor as the terminating descriptor
523 */
524 if (desc != host->adma_desc) {
525 desc -= 8;
526 desc[0] |= 0x2; /* end */
527 }
528 } else {
529 /*
530 * Add a terminating entry.
531 */
2134a922 532
70764a90
TA		 533 /* nop, end, valid */
534 sdhci_set_adma_desc(desc, 0, 0, 0x3);
535 }
2134a922
PO		 536
537 /*
538 * Resync align buffer as we might have changed it.
539 */
540 if (data->flags & MMC_DATA_WRITE) {
541 dma_sync_single_for_device(mmc_dev(host->mmc),
542 host->align_addr, 128 * 4, direction);
543 }
544
545 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
546 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 547 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 548 goto unmap_entries;
2134a922 549 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 550
551 return 0;
552
553unmap_entries:
554 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
555 data->sg_len, direction);
556unmap_align:
557 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
558 128 * 4, direction);
559fail:
560 return -EINVAL;
2134a922
PO		 561}
562
563static void sdhci_adma_table_post(struct sdhci_host *host,
564 struct mmc_data *data)
565{
566 int direction;
567
568 struct scatterlist *sg;
569 int i, size;
570 u8 *align;
571 char *buffer;
572 unsigned long flags;
573
574 if (data->flags & MMC_DATA_READ)
575 direction = DMA_FROM_DEVICE;
576 else
577 direction = DMA_TO_DEVICE;
578
579 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
580 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
581
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584
585 if (data->flags & MMC_DATA_READ) {
586 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
588
589 align = host->align_buffer;
590
591 for_each_sg(data->sg, sg, host->sg_count, i) {
592 if (sg_dma_address(sg) & 0x3) {
593 size = 4 - (sg_dma_address(sg) & 0x3);
594
595 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 596 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 597 memcpy(buffer, align, size);
598 sdhci_kunmap_atomic(buffer, &flags);
599
600 align += 4;
601 }
602 }
603 }
604
605 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
606 data->sg_len, direction);
607}
608
a3c7778f 609static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 610{
1c8cde92 611 u8 count;
a3c7778f 612 struct mmc_data *data = cmd->data;
1c8cde92 613 unsigned target_timeout, current_timeout;
d129bceb 614
ee53ab5d
PO		 615 /*
616 * If the host controller provides us with an incorrect timeout
617 * value, just skip the check and use 0xE. The hardware may take
618 * longer to time out, but that's much better than having a too-short
619 * timeout value.
620 */
11a2f1b7 621 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 622 return 0xE;
e538fbe8 623
a3c7778f
AW		 624 /* Unspecified timeout, assume max */
625 if (!data && !cmd->cmd_timeout_ms)
626 return 0xE;
d129bceb 627
a3c7778f
AW		 628 /* timeout in us */
629 if (!data)
630 target_timeout = cmd->cmd_timeout_ms * 1000;
631 else
632 target_timeout = data->timeout_ns / 1000 +
633 data->timeout_clks / host->clock;
81b39802 634
1c8cde92
PO		 635 /*
636 * Figure out needed cycles.
637 * We do this in steps in order to fit inside a 32 bit int.
638 * The first step is the minimum timeout, which will have a
639 * minimum resolution of 6 bits:
640 * (1) 2^13*1000 > 2^22,
641 * (2) host->timeout_clk < 2^16
642 * =>
643 * (1) / (2) > 2^6
644 */
645 count = 0;
646 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
647 while (current_timeout < target_timeout) {
648 count++;
649 current_timeout <<= 1;
650 if (count >= 0xF)
651 break;
652 }
653
654 if (count >= 0xF) {
a3c7778f
AW		 655 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
656 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 657 count = 0xE;
658 }
659
ee53ab5d
PO		 660 return count;
661}
662
6aa943ab
AV		 663static void sdhci_set_transfer_irqs(struct sdhci_host *host)
664{
665 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
666 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
667
668 if (host->flags & SDHCI_REQ_USE_DMA)
669 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
670 else
671 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
672}
673
a3c7778f 674static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 675{
676 u8 count;
2134a922 677 u8 ctrl;
a3c7778f 678 struct mmc_data *data = cmd->data;
8f1934ce 679 int ret;
ee53ab5d
PO		 680
681 WARN_ON(host->data);
682
a3c7778f
AW		 683 if (data || (cmd->flags & MMC_RSP_BUSY)) {
684 count = sdhci_calc_timeout(host, cmd);
685 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
686 }
687
688 if (!data)
ee53ab5d
PO		 689 return;
690
691 /* Sanity checks */
692 BUG_ON(data->blksz * data->blocks > 524288);
693 BUG_ON(data->blksz > host->mmc->max_blk_size);
694 BUG_ON(data->blocks > 65535);
695
696 host->data = data;
697 host->data_early = 0;
f6a03cbf 698 host->data->bytes_xfered = 0;
ee53ab5d 699
a13abc7b 700 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 701 host->flags |= SDHCI_REQ_USE_DMA;
702
2134a922
PO		 703 /*
704 * FIXME: This doesn't account for merging when mapping the
705 * scatterlist.
706 */
707 if (host->flags & SDHCI_REQ_USE_DMA) {
708 int broken, i;
709 struct scatterlist *sg;
710
711 broken = 0;
712 if (host->flags & SDHCI_USE_ADMA) {
713 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
714 broken = 1;
715 } else {
716 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
717 broken = 1;
718 }
719
720 if (unlikely(broken)) {
721 for_each_sg(data->sg, sg, data->sg_len, i) {
722 if (sg->length & 0x3) {
723 DBG("Reverting to PIO because of "
724 "transfer size (%d)\n",
725 sg->length);
726 host->flags &= ~SDHCI_REQ_USE_DMA;
727 break;
728 }
729 }
730 }
c9fddbc4
PO		 731 }
732
733 /*
734 * The assumption here being that alignment is the same after
735 * translation to device address space.
736 */
2134a922
PO		 737 if (host->flags & SDHCI_REQ_USE_DMA) {
738 int broken, i;
739 struct scatterlist *sg;
740
741 broken = 0;
742 if (host->flags & SDHCI_USE_ADMA) {
743 /*
744 * As we use 3 byte chunks to work around
745 * alignment problems, we need to check this
746 * quirk.
747 */
748 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
749 broken = 1;
750 } else {
751 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
752 broken = 1;
753 }
754
755 if (unlikely(broken)) {
756 for_each_sg(data->sg, sg, data->sg_len, i) {
757 if (sg->offset & 0x3) {
758 DBG("Reverting to PIO because of "
759 "bad alignment\n");
760 host->flags &= ~SDHCI_REQ_USE_DMA;
761 break;
762 }
763 }
764 }
765 }
766
8f1934ce
PO		 767 if (host->flags & SDHCI_REQ_USE_DMA) {
768 if (host->flags & SDHCI_USE_ADMA) {
769 ret = sdhci_adma_table_pre(host, data);
770 if (ret) {
771 /*
772 * This only happens when someone fed
773 * us an invalid request.
774 */
775 WARN_ON(1);
ebd6d357 776 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 777 } else {
4e4141a5
AV		 778 sdhci_writel(host, host->adma_addr,
779 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 780 }
781 } else {
c8b3e02e 782 int sg_cnt;
8f1934ce 783
c8b3e02e 784 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 785 data->sg, data->sg_len,
786 (data->flags & MMC_DATA_READ) ?
787 DMA_FROM_DEVICE :
788 DMA_TO_DEVICE);
c8b3e02e 789 if (sg_cnt == 0) {
8f1934ce
PO		 790 /*
791 * This only happens when someone fed
792 * us an invalid request.
793 */
794 WARN_ON(1);
ebd6d357 795 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 796 } else {
719a61b4 797 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 798 sdhci_writel(host, sg_dma_address(data->sg),
799 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 800 }
801 }
802 }
803
2134a922
PO		 804 /*
805 * Always adjust the DMA selection as some controllers
806 * (e.g. JMicron) can't do PIO properly when the selection
807 * is ADMA.
808 */
809 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 810 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 811 ctrl &= ~SDHCI_CTRL_DMA_MASK;
812 if ((host->flags & SDHCI_REQ_USE_DMA) &&
813 (host->flags & SDHCI_USE_ADMA))
814 ctrl |= SDHCI_CTRL_ADMA32;
815 else
816 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 817 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 818 }
819
8f1934ce 820 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 821 int flags;
822
823 flags = SG_MITER_ATOMIC;
824 if (host->data->flags & MMC_DATA_READ)
825 flags |= SG_MITER_TO_SG;
826 else
827 flags |= SG_MITER_FROM_SG;
828 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 829 host->blocks = data->blocks;
d129bceb 830 }
c7fa9963 831
6aa943ab
AV		 832 sdhci_set_transfer_irqs(host);
833
f6a03cbf
MV		 834 /* Set the DMA boundary value and block size */
835 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
836 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 837 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 838}
839
840static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 841 struct mmc_command *cmd)
c7fa9963
PO		 842{
843 u16 mode;
e89d456f 844 struct mmc_data *data = cmd->data;
c7fa9963 845
c7fa9963
PO		 846 if (data == NULL)
847 return;
848
e538fbe8
PO		 849 WARN_ON(!host->data);
850
c7fa9963 851 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 852 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
853 mode |= SDHCI_TRNS_MULTI;
854 /*
855 * If we are sending CMD23, CMD12 never gets sent
856 * on successful completion (so no Auto-CMD12).
857 */
858 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
859 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 860 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
861 mode |= SDHCI_TRNS_AUTO_CMD23;
862 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
863 }
c4512f79 864 }
8edf6371 865
c7fa9963
PO		 866 if (data->flags & MMC_DATA_READ)
867 mode |= SDHCI_TRNS_READ;
c9fddbc4 868 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 869 mode |= SDHCI_TRNS_DMA;
870
4e4141a5 871 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 872}
873
874static void sdhci_finish_data(struct sdhci_host *host)
875{
876 struct mmc_data *data;
d129bceb
PO		 877
878 BUG_ON(!host->data);
879
880 data = host->data;
881 host->data = NULL;
882
c9fddbc4 883 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 884 if (host->flags & SDHCI_USE_ADMA)
885 sdhci_adma_table_post(host, data);
886 else {
887 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
888 data->sg_len, (data->flags & MMC_DATA_READ) ?
889 DMA_FROM_DEVICE : DMA_TO_DEVICE);
890 }
d129bceb
PO		 891 }
892
893 /*
c9b74c5b
PO		 894 * The specification states that the block count register must
895 * be updated, but it does not specify at what point in the
896 * data flow. That makes the register entirely useless to read
897 * back so we have to assume that nothing made it to the card
898 * in the event of an error.
d129bceb 899 */
c9b74c5b
PO		 900 if (data->error)
901 data->bytes_xfered = 0;
d129bceb 902 else
c9b74c5b 903 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 904
e89d456f
AW		 905 /*
906 * Need to send CMD12 if -
907 * a) open-ended multiblock transfer (no CMD23)
908 * b) error in multiblock transfer
909 */
910 if (data->stop &&
911 (data->error ||
912 !host->mrq->sbc)) {
913
d129bceb
PO		 914 /*
915 * The controller needs a reset of internal state machines
916 * upon error conditions.
917 */
17b0429d 918 if (data->error) {
d129bceb
PO		 919 sdhci_reset(host, SDHCI_RESET_CMD);
920 sdhci_reset(host, SDHCI_RESET_DATA);
921 }
922
923 sdhci_send_command(host, data->stop);
924 } else
925 tasklet_schedule(&host->finish_tasklet);
926}
927
928static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
929{
930 int flags;
fd2208d7 931 u32 mask;
7cb2c76f 932 unsigned long timeout;
d129bceb
PO		 933
934 WARN_ON(host->cmd);
935
d129bceb 936 /* Wait max 10 ms */
7cb2c76f 937 timeout = 10;
fd2208d7
PO		 938
939 mask = SDHCI_CMD_INHIBIT;
940 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
941 mask |= SDHCI_DATA_INHIBIT;
942
943 /* We shouldn't wait for data inihibit for stop commands, even
944 though they might use busy signaling */
945 if (host->mrq->data && (cmd == host->mrq->data->stop))
946 mask &= ~SDHCI_DATA_INHIBIT;
947
4e4141a5 948 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 949 if (timeout == 0) {
d129bceb 950 printk(KERN_ERR "%s: Controller never released "
acf1da45 951 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 952 sdhci_dumpregs(host);
17b0429d 953 cmd->error = -EIO;
d129bceb
PO		 954 tasklet_schedule(&host->finish_tasklet);
955 return;
956 }
7cb2c76f
PO		 957 timeout--;
958 mdelay(1);
959 }
d129bceb
PO		 960
961 mod_timer(&host->timer, jiffies + 10 * HZ);
962
963 host->cmd = cmd;
964
a3c7778f 965 sdhci_prepare_data(host, cmd);
d129bceb 966
4e4141a5 967 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 968
e89d456f 969 sdhci_set_transfer_mode(host, cmd);
c7fa9963 970
d129bceb 971 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 972 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 973 mmc_hostname(host->mmc));
17b0429d 974 cmd->error = -EINVAL;
d129bceb
PO		 975 tasklet_schedule(&host->finish_tasklet);
976 return;
977 }
978
979 if (!(cmd->flags & MMC_RSP_PRESENT))
980 flags = SDHCI_CMD_RESP_NONE;
981 else if (cmd->flags & MMC_RSP_136)
982 flags = SDHCI_CMD_RESP_LONG;
983 else if (cmd->flags & MMC_RSP_BUSY)
984 flags = SDHCI_CMD_RESP_SHORT_BUSY;
985 else
986 flags = SDHCI_CMD_RESP_SHORT;
987
988 if (cmd->flags & MMC_RSP_CRC)
989 flags |= SDHCI_CMD_CRC;
990 if (cmd->flags & MMC_RSP_OPCODE)
991 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 992
993 /* CMD19 is special in that the Data Present Select should be set */
994 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 995 flags |= SDHCI_CMD_DATA;
996
4e4141a5 997 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 998}
999
1000static void sdhci_finish_command(struct sdhci_host *host)
1001{
1002 int i;
1003
1004 BUG_ON(host->cmd == NULL);
1005
1006 if (host->cmd->flags & MMC_RSP_PRESENT) {
1007 if (host->cmd->flags & MMC_RSP_136) {
1008 /* CRC is stripped so we need to do some shifting. */
1009 for (i = 0;i < 4;i++) {
4e4141a5 1010 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1011 SDHCI_RESPONSE + (3-i)*4) << 8;
1012 if (i != 3)
1013 host->cmd->resp[i] |=
4e4141a5 1014 sdhci_readb(host,
d129bceb
PO		 1015 SDHCI_RESPONSE + (3-i)*4-1);
1016 }
1017 } else {
4e4141a5 1018 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1019 }
1020 }
1021
17b0429d 1022 host->cmd->error = 0;
d129bceb 1023
e89d456f
AW		 1024 /* Finished CMD23, now send actual command. */
1025 if (host->cmd == host->mrq->sbc) {
1026 host->cmd = NULL;
1027 sdhci_send_command(host, host->mrq->cmd);
1028 } else {
e538fbe8 1029
e89d456f
AW		 1030 /* Processed actual command. */
1031 if (host->data && host->data_early)
1032 sdhci_finish_data(host);
d129bceb 1033
e89d456f
AW		 1034 if (!host->cmd->data)
1035 tasklet_schedule(&host->finish_tasklet);
1036
1037 host->cmd = NULL;
1038 }
d129bceb
PO		 1039}
1040
1041static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1042{
c3ed3877
AN		 1043 int div = 0; /* Initialized for compiler warning */
1044 u16 clk = 0;
7cb2c76f 1045 unsigned long timeout;
d129bceb
PO		 1046
1047 if (clock == host->clock)
1048 return;
1049
8114634c
AV		 1050 if (host->ops->set_clock) {
1051 host->ops->set_clock(host, clock);
1052 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1053 return;
1054 }
1055
4e4141a5 1056 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1057
1058 if (clock == 0)
1059 goto out;
1060
85105c53 1061 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1062 /*
1063 * Check if the Host Controller supports Programmable Clock
1064 * Mode.
1065 */
1066 if (host->clk_mul) {
1067 u16 ctrl;
1068
1069 /*
1070 * We need to figure out whether the Host Driver needs
1071 * to select Programmable Clock Mode, or the value can
1072 * be set automatically by the Host Controller based on
1073 * the Preset Value registers.
1074 */
1075 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1076 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1077 for (div = 1; div <= 1024; div++) {
1078 if (((host->max_clk * host->clk_mul) /
1079 div) <= clock)
1080 break;
1081 }
1082 /*
1083 * Set Programmable Clock Mode in the Clock
1084 * Control register.
1085 */
1086 clk = SDHCI_PROG_CLOCK_MODE;
1087 div--;
1088 }
1089 } else {
1090 /* Version 3.00 divisors must be a multiple of 2. */
1091 if (host->max_clk <= clock)
1092 div = 1;
1093 else {
1094 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1095 div += 2) {
1096 if ((host->max_clk / div) <= clock)
1097 break;
1098 }
85105c53 1099 }
c3ed3877 1100 div >>= 1;
85105c53
ZG		 1101 }
1102 } else {
1103 /* Version 2.00 divisors must be a power of 2. */
0397526d 1104 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1105 if ((host->max_clk / div) <= clock)
1106 break;
1107 }
c3ed3877 1108 div >>= 1;
d129bceb 1109 }
d129bceb 1110
c3ed3877 1111 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1112 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1113 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1114 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1115 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1116
27f6cb16
CB		 1117 /* Wait max 20 ms */
1118 timeout = 20;
4e4141a5 1119 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1120 & SDHCI_CLOCK_INT_STABLE)) {
1121 if (timeout == 0) {
acf1da45
PO		 1122 printk(KERN_ERR "%s: Internal clock never "
1123 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1124 sdhci_dumpregs(host);
1125 return;
1126 }
7cb2c76f
PO		 1127 timeout--;
1128 mdelay(1);
1129 }
d129bceb
PO		 1130
1131 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1132 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1133
1134out:
1135 host->clock = clock;
1136}
1137
146ad66e
PO		 1138static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1139{
8364248a 1140 u8 pwr = 0;
146ad66e 1141
8364248a 1142 if (power != (unsigned short)-1) {
ae628903
PO		 1143 switch (1 << power) {
1144 case MMC_VDD_165_195:
1145 pwr = SDHCI_POWER_180;
1146 break;
1147 case MMC_VDD_29_30:
1148 case MMC_VDD_30_31:
1149 pwr = SDHCI_POWER_300;
1150 break;
1151 case MMC_VDD_32_33:
1152 case MMC_VDD_33_34:
1153 pwr = SDHCI_POWER_330;
1154 break;
1155 default:
1156 BUG();
1157 }
1158 }
1159
1160 if (host->pwr == pwr)
146ad66e
PO		 1161 return;
1162
ae628903
PO		 1163 host->pwr = pwr;
1164
1165 if (pwr == 0) {
4e4141a5 1166 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1167 return;
9e9dc5f2
DS		 1168 }
1169
1170 /*
1171 * Spec says that we should clear the power reg before setting
1172 * a new value. Some controllers don't seem to like this though.
1173 */
b8c86fc5 1174 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1175 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1176
e08c1694 1177 /*
c71f6512 1178 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1179 * and set turn on power at the same time, so set the voltage first.
1180 */
11a2f1b7 1181 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1182 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1183
ae628903 1184 pwr |= SDHCI_POWER_ON;
146ad66e 1185
ae628903 1186 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1187
1188 /*
1189 * Some controllers need an extra 10ms delay of 10ms before they
1190 * can apply clock after applying power
1191 */
11a2f1b7 1192 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1193 mdelay(10);
146ad66e
PO		 1194}
1195
d129bceb
PO		 1196/*****************************************************************************\
1197 * *
1198 * MMC callbacks *
1199 * *
1200\*****************************************************************************/
1201
1202static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1203{
1204 struct sdhci_host *host;
68d1fb7e 1205 bool present;
d129bceb
PO		 1206 unsigned long flags;
1207
1208 host = mmc_priv(mmc);
1209
1210 spin_lock_irqsave(&host->lock, flags);
1211
1212 WARN_ON(host->mrq != NULL);
1213
f9134319 1214#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1215 sdhci_activate_led(host);
2f730fec 1216#endif
e89d456f
AW		 1217
1218 /*
1219 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1220 * requests if Auto-CMD12 is enabled.
1221 */
1222 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1223 if (mrq->stop) {
1224 mrq->data->stop = NULL;
1225 mrq->stop = NULL;
1226 }
1227 }
d129bceb
PO		 1228
1229 host->mrq = mrq;
1230
68d1fb7e
AV		 1231 /* If polling, assume that the card is always present. */
1232 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1233 present = true;
1234 else
1235 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1236 SDHCI_CARD_PRESENT;
1237
1238 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1239 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1240 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1241 } else {
1242 u32 present_state;
1243
1244 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1245 /*
1246 * Check if the re-tuning timer has already expired and there
1247 * is no on-going data transfer. If so, we need to execute
1248 * tuning procedure before sending command.
1249 */
1250 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1251 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1252 spin_unlock_irqrestore(&host->lock, flags);
1253 sdhci_execute_tuning(mmc);
1254 spin_lock_irqsave(&host->lock, flags);
1255
1256 /* Restore original mmc_request structure */
1257 host->mrq = mrq;
1258 }
1259
8edf6371 1260 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1261 sdhci_send_command(host, mrq->sbc);
1262 else
1263 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1264 }
d129bceb 1265
5f25a66f 1266 mmiowb();
d129bceb
PO		 1267 spin_unlock_irqrestore(&host->lock, flags);
1268}
1269
1270static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1271{
1272 struct sdhci_host *host;
1273 unsigned long flags;
1274 u8 ctrl;
1275
1276 host = mmc_priv(mmc);
1277
1278 spin_lock_irqsave(&host->lock, flags);
1279
1e72859e
PO		 1280 if (host->flags & SDHCI_DEVICE_DEAD)
1281 goto out;
1282
d129bceb
PO		 1283 /*
1284 * Reset the chip on each power off.
1285 * Should clear out any weird states.
1286 */
1287 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1288 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1289 sdhci_reinit(host);
d129bceb
PO		 1290 }
1291
1292 sdhci_set_clock(host, ios->clock);
1293
1294 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1295 sdhci_set_power(host, -1);
d129bceb 1296 else
146ad66e 1297 sdhci_set_power(host, ios->vdd);
d129bceb 1298
643a81ff
PR		 1299 if (host->ops->platform_send_init_74_clocks)
1300 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1301
15ec4461
PR		 1302 /*
1303 * If your platform has 8-bit width support but is not a v3 controller,
1304 * or if it requires special setup code, you should implement that in
1305 * platform_8bit_width().
1306 */
1307 if (host->ops->platform_8bit_width)
1308 host->ops->platform_8bit_width(host, ios->bus_width);
1309 else {
1310 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1311 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1312 ctrl &= ~SDHCI_CTRL_4BITBUS;
1313 if (host->version >= SDHCI_SPEC_300)
1314 ctrl |= SDHCI_CTRL_8BITBUS;
1315 } else {
1316 if (host->version >= SDHCI_SPEC_300)
1317 ctrl &= ~SDHCI_CTRL_8BITBUS;
1318 if (ios->bus_width == MMC_BUS_WIDTH_4)
1319 ctrl |= SDHCI_CTRL_4BITBUS;
1320 else
1321 ctrl &= ~SDHCI_CTRL_4BITBUS;
1322 }
1323 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1324 }
ae6d6c92 1325
15ec4461 1326 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1327
3ab9c8da
PR		 1328 if ((ios->timing == MMC_TIMING_SD_HS ||
1329 ios->timing == MMC_TIMING_MMC_HS)
1330 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1331 ctrl |= SDHCI_CTRL_HISPD;
1332 else
1333 ctrl &= ~SDHCI_CTRL_HISPD;
1334
d6d50a15 1335 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1336 u16 clk, ctrl_2;
1337 unsigned int clock;
1338
1339 /* In case of UHS-I modes, set High Speed Enable */
1340 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1341 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1342 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1343 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1344 (ios->timing == MMC_TIMING_UHS_SDR12))
1345 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1346
1347 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1348 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1349 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1350 /*
1351 * We only need to set Driver Strength if the
1352 * preset value enable is not set.
1353 */
1354 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1355 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1356 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1357 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1358 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1359
1360 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1361 } else {
1362 /*
1363 * According to SDHC Spec v3.00, if the Preset Value
1364 * Enable in the Host Control 2 register is set, we
1365 * need to reset SD Clock Enable before changing High
1366 * Speed Enable to avoid generating clock gliches.
1367 */
758535c4
AN		 1368
1369 /* Reset SD Clock Enable */
1370 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1371 clk &= ~SDHCI_CLOCK_CARD_EN;
1372 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1373
1374 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1375
1376 /* Re-enable SD Clock */
1377 clock = host->clock;
1378 host->clock = 0;
1379 sdhci_set_clock(host, clock);
d6d50a15 1380 }
49c468fc 1381
49c468fc
AN		 1382
1383 /* Reset SD Clock Enable */
1384 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1385 clk &= ~SDHCI_CLOCK_CARD_EN;
1386 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1387
6322cdd0
PR		 1388 if (host->ops->set_uhs_signaling)
1389 host->ops->set_uhs_signaling(host, ios->timing);
1390 else {
1391 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1392 /* Select Bus Speed Mode for host */
1393 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1394 if (ios->timing == MMC_TIMING_UHS_SDR12)
1395 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1396 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1397 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1398 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1399 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1400 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1401 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1402 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1403 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1404 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1405 }
49c468fc
AN		 1406
1407 /* Re-enable SD Clock */
1408 clock = host->clock;
1409 host->clock = 0;
1410 sdhci_set_clock(host, clock);
758535c4
AN		 1411 } else
1412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1413
b8352260
LD		 1414 /*
1415 * Some (ENE) controllers go apeshit on some ios operation,
1416 * signalling timeout and CRC errors even on CMD0. Resetting
1417 * it on each ios seems to solve the problem.
1418 */
b8c86fc5 1419 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1420 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1421
1e72859e 1422out:
5f25a66f 1423 mmiowb();
d129bceb
PO		 1424 spin_unlock_irqrestore(&host->lock, flags);
1425}
1426
82b0e23a 1427static int check_ro(struct sdhci_host *host)
d129bceb 1428{
d129bceb 1429 unsigned long flags;
2dfb579c 1430 int is_readonly;
d129bceb 1431
d129bceb
PO		 1432 spin_lock_irqsave(&host->lock, flags);
1433
1e72859e 1434 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1435 is_readonly = 0;
1436 else if (host->ops->get_ro)
1437 is_readonly = host->ops->get_ro(host);
1e72859e 1438 else
2dfb579c
WS		 1439 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1440 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1441
1442 spin_unlock_irqrestore(&host->lock, flags);
1443
2dfb579c
WS		 1444 /* This quirk needs to be replaced by a callback-function later */
1445 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1446 !is_readonly : is_readonly;
d129bceb
PO		 1447}
1448
82b0e23a
TI		 1449#define SAMPLE_COUNT 5
1450
1451static int sdhci_get_ro(struct mmc_host *mmc)
1452{
1453 struct sdhci_host *host;
1454 int i, ro_count;
1455
1456 host = mmc_priv(mmc);
1457
1458 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1459 return check_ro(host);
1460
1461 ro_count = 0;
1462 for (i = 0; i < SAMPLE_COUNT; i++) {
1463 if (check_ro(host)) {
1464 if (++ro_count > SAMPLE_COUNT / 2)
1465 return 1;
1466 }
1467 msleep(30);
1468 }
1469 return 0;
1470}
1471
f75979b7
PO		 1472static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1473{
1474 struct sdhci_host *host;
1475 unsigned long flags;
f75979b7
PO		 1476
1477 host = mmc_priv(mmc);
1478
1479 spin_lock_irqsave(&host->lock, flags);
1480
1e72859e
PO		 1481 if (host->flags & SDHCI_DEVICE_DEAD)
1482 goto out;
1483
f75979b7 1484 if (enable)
7260cf5e
AV		 1485 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1486 else
1487 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1488out:
f75979b7
PO		 1489 mmiowb();
1490
1491 spin_unlock_irqrestore(&host->lock, flags);
1492}
1493
f2119df6
AN		 1494static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1495 struct mmc_ios *ios)
1496{
1497 struct sdhci_host *host;
1498 u8 pwr;
1499 u16 clk, ctrl;
1500 u32 present_state;
1501
1502 host = mmc_priv(mmc);
1503
1504 /*
1505 * Signal Voltage Switching is only applicable for Host Controllers
1506 * v3.00 and above.
1507 */
1508 if (host->version < SDHCI_SPEC_300)
1509 return 0;
1510
1511 /*
1512 * We first check whether the request is to set signalling voltage
1513 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1514 */
1515 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1516 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1517 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1518 ctrl &= ~SDHCI_CTRL_VDD_180;
1519 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1520
1521 /* Wait for 5ms */
1522 usleep_range(5000, 5500);
1523
1524 /* 3.3V regulator output should be stable within 5 ms */
1525 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1526 if (!(ctrl & SDHCI_CTRL_VDD_180))
1527 return 0;
1528 else {
1529 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1530 "signalling voltage failed\n");
1531 return -EIO;
1532 }
1533 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1534 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1535 /* Stop SDCLK */
1536 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1537 clk &= ~SDHCI_CLOCK_CARD_EN;
1538 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539
1540 /* Check whether DAT[3:0] is 0000 */
1541 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1542 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1543 SDHCI_DATA_LVL_SHIFT)) {
1544 /*
1545 * Enable 1.8V Signal Enable in the Host Control2
1546 * register
1547 */
1548 ctrl |= SDHCI_CTRL_VDD_180;
1549 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1550
1551 /* Wait for 5ms */
1552 usleep_range(5000, 5500);
1553
1554 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1555 if (ctrl & SDHCI_CTRL_VDD_180) {
1556 /* Provide SDCLK again and wait for 1ms*/
1557 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1558 clk |= SDHCI_CLOCK_CARD_EN;
1559 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1560 usleep_range(1000, 1500);
1561
1562 /*
1563 * If DAT[3:0] level is 1111b, then the card
1564 * was successfully switched to 1.8V signaling.
1565 */
1566 present_state = sdhci_readl(host,
1567 SDHCI_PRESENT_STATE);
1568 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1569 SDHCI_DATA_LVL_MASK)
1570 return 0;
1571 }
1572 }
1573
1574 /*
1575 * If we are here, that means the switch to 1.8V signaling
1576 * failed. We power cycle the card, and retry initialization
1577 * sequence by setting S18R to 0.
1578 */
1579 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1580 pwr &= ~SDHCI_POWER_ON;
1581 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1582
1583 /* Wait for 1ms as per the spec */
1584 usleep_range(1000, 1500);
1585 pwr |= SDHCI_POWER_ON;
1586 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1587
1588 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1589 "voltage failed, retrying with S18R set to 0\n");
1590 return -EAGAIN;
1591 } else
1592 /* No signal voltage switch required */
1593 return 0;
1594}
1595
b513ea25
AN		 1596static int sdhci_execute_tuning(struct mmc_host *mmc)
1597{
1598 struct sdhci_host *host;
1599 u16 ctrl;
1600 u32 ier;
1601 int tuning_loop_counter = MAX_TUNING_LOOP;
1602 unsigned long timeout;
1603 int err = 0;
1604
1605 host = mmc_priv(mmc);
1606
1607 disable_irq(host->irq);
1608 spin_lock(&host->lock);
1609
1610 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1611
1612 /*
1613 * Host Controller needs tuning only in case of SDR104 mode
1614 * and for SDR50 mode when Use Tuning for SDR50 is set in
1615 * Capabilities register.
1616 */
1617 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1618 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1619 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1620 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1621 else {
1622 spin_unlock(&host->lock);
1623 enable_irq(host->irq);
1624 return 0;
1625 }
1626
1627 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1628
1629 /*
1630 * As per the Host Controller spec v3.00, tuning command
1631 * generates Buffer Read Ready interrupt, so enable that.
1632 *
1633 * Note: The spec clearly says that when tuning sequence
1634 * is being performed, the controller does not generate
1635 * interrupts other than Buffer Read Ready interrupt. But
1636 * to make sure we don't hit a controller bug, we _only_
1637 * enable Buffer Read Ready interrupt here.
1638 */
1639 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1640 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1641
1642 /*
1643 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1644 * of loops reaches 40 times or a timeout of 150ms occurs.
1645 */
1646 timeout = 150;
1647 do {
1648 struct mmc_command cmd = {0};
1649 struct mmc_request mrq = {0};
1650
1651 if (!tuning_loop_counter && !timeout)
1652 break;
1653
1654 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1655 cmd.arg = 0;
1656 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1657 cmd.retries = 0;
1658 cmd.data = NULL;
1659 cmd.error = 0;
1660
1661 mrq.cmd = &cmd;
1662 host->mrq = &mrq;
1663
1664 /*
1665 * In response to CMD19, the card sends 64 bytes of tuning
1666 * block to the Host Controller. So we set the block size
1667 * to 64 here.
1668 */
1669 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1670
1671 /*
1672 * The tuning block is sent by the card to the host controller.
1673 * So we set the TRNS_READ bit in the Transfer Mode register.
1674 * This also takes care of setting DMA Enable and Multi Block
1675 * Select in the same register to 0.
1676 */
1677 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1678
1679 sdhci_send_command(host, &cmd);
1680
1681 host->cmd = NULL;
1682 host->mrq = NULL;
1683
1684 spin_unlock(&host->lock);
1685 enable_irq(host->irq);
1686
1687 /* Wait for Buffer Read Ready interrupt */
1688 wait_event_interruptible_timeout(host->buf_ready_int,
1689 (host->tuning_done == 1),
1690 msecs_to_jiffies(50));
1691 disable_irq(host->irq);
1692 spin_lock(&host->lock);
1693
1694 if (!host->tuning_done) {
1695 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1696 "Buffer Read Ready interrupt during tuning "
1697 "procedure, falling back to fixed sampling "
1698 "clock\n");
1699 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1700 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1701 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1702 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1703
1704 err = -EIO;
1705 goto out;
1706 }
1707
1708 host->tuning_done = 0;
1709
1710 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1711 tuning_loop_counter--;
1712 timeout--;
1713 mdelay(1);
1714 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1715
1716 /*
1717 * The Host Driver has exhausted the maximum number of loops allowed,
1718 * so use fixed sampling frequency.
1719 */
1720 if (!tuning_loop_counter || !timeout) {
1721 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1722 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1723 } else {
1724 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1725 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1726 " failed, falling back to fixed sampling"
1727 " clock\n");
1728 err = -EIO;
1729 }
1730 }
1731
1732out:
cf2b5eea
AN		 1733 /*
1734 * If this is the very first time we are here, we start the retuning
1735 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1736 * flag won't be set, we check this condition before actually starting
1737 * the timer.
1738 */
1739 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1740 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1741 mod_timer(&host->tuning_timer, jiffies +
1742 host->tuning_count * HZ);
1743 /* Tuning mode 1 limits the maximum data length to 4MB */
1744 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1745 } else {
1746 host->flags &= ~SDHCI_NEEDS_RETUNING;
1747 /* Reload the new initial value for timer */
1748 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1749 mod_timer(&host->tuning_timer, jiffies +
1750 host->tuning_count * HZ);
1751 }
1752
1753 /*
1754 * In case tuning fails, host controllers which support re-tuning can
1755 * try tuning again at a later time, when the re-tuning timer expires.
1756 * So for these controllers, we return 0. Since there might be other
1757 * controllers who do not have this capability, we return error for
1758 * them.
1759 */
1760 if (err && host->tuning_count &&
1761 host->tuning_mode == SDHCI_TUNING_MODE_1)
1762 err = 0;
1763
b513ea25
AN		 1764 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1765 spin_unlock(&host->lock);
1766 enable_irq(host->irq);
1767
1768 return err;
1769}
1770
4d55c5a1
AN		 1771static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1772{
1773 struct sdhci_host *host;
1774 u16 ctrl;
1775 unsigned long flags;
1776
1777 host = mmc_priv(mmc);
1778
1779 /* Host Controller v3.00 defines preset value registers */
1780 if (host->version < SDHCI_SPEC_300)
1781 return;
1782
1783 spin_lock_irqsave(&host->lock, flags);
1784
1785 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1786
1787 /*
1788 * We only enable or disable Preset Value if they are not already
1789 * enabled or disabled respectively. Otherwise, we bail out.
1790 */
1791 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1792 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1793 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1794 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1795 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1796 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1797 }
1798
1799 spin_unlock_irqrestore(&host->lock, flags);
1800}
1801
ab7aefd0 1802static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1803 .request = sdhci_request,
1804 .set_ios = sdhci_set_ios,
1805 .get_ro = sdhci_get_ro,
f75979b7 1806 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1807 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1808 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1809 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1810};
1811
1812/*****************************************************************************\
1813 * *
1814 * Tasklets *
1815 * *
1816\*****************************************************************************/
1817
1818static void sdhci_tasklet_card(unsigned long param)
1819{
1820 struct sdhci_host *host;
1821 unsigned long flags;
1822
1823 host = (struct sdhci_host*)param;
1824
1825 spin_lock_irqsave(&host->lock, flags);
1826
4e4141a5 1827 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1828 if (host->mrq) {
1829 printk(KERN_ERR "%s: Card removed during transfer!\n",
1830 mmc_hostname(host->mmc));
1831 printk(KERN_ERR "%s: Resetting controller.\n",
1832 mmc_hostname(host->mmc));
1833
1834 sdhci_reset(host, SDHCI_RESET_CMD);
1835 sdhci_reset(host, SDHCI_RESET_DATA);
1836
17b0429d 1837 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1838 tasklet_schedule(&host->finish_tasklet);
1839 }
1840 }
1841
1842 spin_unlock_irqrestore(&host->lock, flags);
1843
04cf585d 1844 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1845}
1846
1847static void sdhci_tasklet_finish(unsigned long param)
1848{
1849 struct sdhci_host *host;
1850 unsigned long flags;
1851 struct mmc_request *mrq;
1852
1853 host = (struct sdhci_host*)param;
1854
0c9c99a7
CB		 1855 /*
1856 * If this tasklet gets rescheduled while running, it will
1857 * be run again afterwards but without any active request.
1858 */
1859 if (!host->mrq)
1860 return;
1861
d129bceb
PO		 1862 spin_lock_irqsave(&host->lock, flags);
1863
1864 del_timer(&host->timer);
1865
1866 mrq = host->mrq;
1867
d129bceb
PO		 1868 /*
1869 * The controller needs a reset of internal state machines
1870 * upon error conditions.
1871 */
1e72859e 1872 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1873 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1874 (mrq->data && (mrq->data->error ||
1875 (mrq->data->stop && mrq->data->stop->error))) ||
1876 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1877
1878 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1879 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1880 unsigned int clock;
1881
1882 /* This is to force an update */
1883 clock = host->clock;
1884 host->clock = 0;
1885 sdhci_set_clock(host, clock);
1886 }
1887
1888 /* Spec says we should do both at the same time, but Ricoh
1889 controllers do not like that. */
d129bceb
PO		 1890 sdhci_reset(host, SDHCI_RESET_CMD);
1891 sdhci_reset(host, SDHCI_RESET_DATA);
1892 }
1893
1894 host->mrq = NULL;
1895 host->cmd = NULL;
1896 host->data = NULL;
1897
f9134319 1898#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1899 sdhci_deactivate_led(host);
2f730fec 1900#endif
d129bceb 1901
5f25a66f 1902 mmiowb();
d129bceb
PO		 1903 spin_unlock_irqrestore(&host->lock, flags);
1904
1905 mmc_request_done(host->mmc, mrq);
1906}
1907
1908static void sdhci_timeout_timer(unsigned long data)
1909{
1910 struct sdhci_host *host;
1911 unsigned long flags;
1912
1913 host = (struct sdhci_host*)data;
1914
1915 spin_lock_irqsave(&host->lock, flags);
1916
1917 if (host->mrq) {
acf1da45
PO		 1918 printk(KERN_ERR "%s: Timeout waiting for hardware "
1919 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1920 sdhci_dumpregs(host);
1921
1922 if (host->data) {
17b0429d 1923 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1924 sdhci_finish_data(host);
1925 } else {
1926 if (host->cmd)
17b0429d 1927 host->cmd->error = -ETIMEDOUT;
d129bceb 1928 else
17b0429d 1929 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1930
1931 tasklet_schedule(&host->finish_tasklet);
1932 }
1933 }
1934
5f25a66f 1935 mmiowb();
d129bceb
PO		 1936 spin_unlock_irqrestore(&host->lock, flags);
1937}
1938
cf2b5eea
AN		 1939static void sdhci_tuning_timer(unsigned long data)
1940{
1941 struct sdhci_host *host;
1942 unsigned long flags;
1943
1944 host = (struct sdhci_host *)data;
1945
1946 spin_lock_irqsave(&host->lock, flags);
1947
1948 host->flags |= SDHCI_NEEDS_RETUNING;
1949
1950 spin_unlock_irqrestore(&host->lock, flags);
1951}
1952
d129bceb
PO		 1953/*****************************************************************************\
1954 * *
1955 * Interrupt handling *
1956 * *
1957\*****************************************************************************/
1958
1959static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1960{
1961 BUG_ON(intmask == 0);
1962
1963 if (!host->cmd) {
b67ac3f3
PO		 1964 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1965 "though no command operation was in progress.\n",
1966 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1967 sdhci_dumpregs(host);
1968 return;
1969 }
1970
43b58b36 1971 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1972 host->cmd->error = -ETIMEDOUT;
1973 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1974 SDHCI_INT_INDEX))
1975 host->cmd->error = -EILSEQ;
43b58b36 1976
e809517f 1977 if (host->cmd->error) {
d129bceb 1978 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1979 return;
1980 }
1981
1982 /*
1983 * The host can send and interrupt when the busy state has
1984 * ended, allowing us to wait without wasting CPU cycles.
1985 * Unfortunately this is overloaded on the "data complete"
1986 * interrupt, so we need to take some care when handling
1987 * it.
1988 *
1989 * Note: The 1.0 specification is a bit ambiguous about this
1990 * feature so there might be some problems with older
1991 * controllers.
1992 */
1993 if (host->cmd->flags & MMC_RSP_BUSY) {
1994 if (host->cmd->data)
1995 DBG("Cannot wait for busy signal when also "
1996 "doing a data transfer");
f945405c 1997 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1998 return;
f945405c
BD		 1999
2000 /* The controller does not support the end-of-busy IRQ,
2001 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2002 }
2003
2004 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2005 sdhci_finish_command(host);
d129bceb
PO		 2006}
2007
0957c333 2008#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2009static void sdhci_show_adma_error(struct sdhci_host *host)
2010{
2011 const char *name = mmc_hostname(host->mmc);
2012 u8 *desc = host->adma_desc;
2013 __le32 *dma;
2014 __le16 *len;
2015 u8 attr;
2016
2017 sdhci_dumpregs(host);
2018
2019 while (true) {
2020 dma = (__le32 *)(desc + 4);
2021 len = (__le16 *)(desc + 2);
2022 attr = *desc;
2023
2024 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2025 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2026
2027 desc += 8;
2028
2029 if (attr & 2)
2030 break;
2031 }
2032}
2033#else
2034static void sdhci_show_adma_error(struct sdhci_host *host) { }
2035#endif
2036
d129bceb
PO		 2037static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2038{
2039 BUG_ON(intmask == 0);
2040
b513ea25
AN		 2041 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2042 if (intmask & SDHCI_INT_DATA_AVAIL) {
2043 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2044 MMC_SEND_TUNING_BLOCK) {
2045 host->tuning_done = 1;
2046 wake_up(&host->buf_ready_int);
2047 return;
2048 }
2049 }
2050
d129bceb
PO		 2051 if (!host->data) {
2052 /*
e809517f
PO		 2053 * The "data complete" interrupt is also used to
2054 * indicate that a busy state has ended. See comment
2055 * above in sdhci_cmd_irq().
d129bceb 2056 */
e809517f
PO		 2057 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2058 if (intmask & SDHCI_INT_DATA_END) {
2059 sdhci_finish_command(host);
2060 return;
2061 }
2062 }
d129bceb 2063
b67ac3f3
PO		 2064 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2065 "though no data operation was in progress.\n",
2066 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2067 sdhci_dumpregs(host);
2068
2069 return;
2070 }
2071
2072 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2073 host->data->error = -ETIMEDOUT;
22113efd
AL		 2074 else if (intmask & SDHCI_INT_DATA_END_BIT)
2075 host->data->error = -EILSEQ;
2076 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2077 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2078 != MMC_BUS_TEST_R)
17b0429d 2079 host->data->error = -EILSEQ;
6882a8c0
BD		 2080 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2081 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2082 sdhci_show_adma_error(host);
2134a922 2083 host->data->error = -EIO;
6882a8c0 2084 }
d129bceb 2085
17b0429d 2086 if (host->data->error)
d129bceb
PO		 2087 sdhci_finish_data(host);
2088 else {
a406f5a3 2089 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2090 sdhci_transfer_pio(host);
2091
6ba736a1
PO		 2092 /*
2093 * We currently don't do anything fancy with DMA
2094 * boundaries, but as we can't disable the feature
2095 * we need to at least restart the transfer.
f6a03cbf
MV		 2096 *
2097 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2098 * should return a valid address to continue from, but as
2099 * some controllers are faulty, don't trust them.
6ba736a1 2100 */
f6a03cbf
MV		 2101 if (intmask & SDHCI_INT_DMA_END) {
2102 u32 dmastart, dmanow;
2103 dmastart = sg_dma_address(host->data->sg);
2104 dmanow = dmastart + host->data->bytes_xfered;
2105 /*
2106 * Force update to the next DMA block boundary.
2107 */
2108 dmanow = (dmanow &
2109 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2110 SDHCI_DEFAULT_BOUNDARY_SIZE;
2111 host->data->bytes_xfered = dmanow - dmastart;
2112 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2113 " next 0x%08x\n",
2114 mmc_hostname(host->mmc), dmastart,
2115 host->data->bytes_xfered, dmanow);
2116 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2117 }
6ba736a1 2118
e538fbe8
PO		 2119 if (intmask & SDHCI_INT_DATA_END) {
2120 if (host->cmd) {
2121 /*
2122 * Data managed to finish before the
2123 * command completed. Make sure we do
2124 * things in the proper order.
2125 */
2126 host->data_early = 1;
2127 } else {
2128 sdhci_finish_data(host);
2129 }
2130 }
d129bceb
PO		 2131 }
2132}
2133
7d12e780 2134static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2135{
2136 irqreturn_t result;
2137 struct sdhci_host* host = dev_id;
2138 u32 intmask;
f75979b7 2139 int cardint = 0;
d129bceb
PO		 2140
2141 spin_lock(&host->lock);
2142
4e4141a5 2143 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2144
62df67a5 2145 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2146 result = IRQ_NONE;
2147 goto out;
2148 }
2149
b69c9058
PO		 2150 DBG("*** %s got interrupt: 0x%08x\n",
2151 mmc_hostname(host->mmc), intmask);
d129bceb 2152
3192a28f 2153 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2154 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2155 SDHCI_CARD_PRESENT;
2156
2157 /*
2158 * There is a observation on i.mx esdhc. INSERT bit will be
2159 * immediately set again when it gets cleared, if a card is
2160 * inserted. We have to mask the irq to prevent interrupt
2161 * storm which will freeze the system. And the REMOVE gets
2162 * the same situation.
2163 *
2164 * More testing are needed here to ensure it works for other
2165 * platforms though.
2166 */
2167 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2168 SDHCI_INT_CARD_REMOVE);
2169 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2170 SDHCI_INT_CARD_INSERT);
2171
4e4141a5 2172 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2173 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2174 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2175 tasklet_schedule(&host->card_tasklet);
3192a28f 2176 }
d129bceb 2177
3192a28f 2178 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2179 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2180 SDHCI_INT_STATUS);
3192a28f 2181 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2182 }
2183
2184 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2185 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2186 SDHCI_INT_STATUS);
3192a28f 2187 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2188 }
2189
2190 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2191
964f9ce2
PO		 2192 intmask &= ~SDHCI_INT_ERROR;
2193
d129bceb 2194 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 2195 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 2196 mmc_hostname(host->mmc));
4e4141a5 2197 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2198 }
2199
9d26a5d3 2200 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2201
f75979b7
PO		 2202 if (intmask & SDHCI_INT_CARD_INT)
2203 cardint = 1;
2204
2205 intmask &= ~SDHCI_INT_CARD_INT;
2206
3192a28f 2207 if (intmask) {
acf1da45 2208 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2209 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2210 sdhci_dumpregs(host);
2211
4e4141a5 2212 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2213 }
d129bceb
PO		 2214
2215 result = IRQ_HANDLED;
2216
5f25a66f 2217 mmiowb();
d129bceb
PO		 2218out:
2219 spin_unlock(&host->lock);
2220
f75979b7
PO		 2221 /*
2222 * We have to delay this as it calls back into the driver.
2223 */
2224 if (cardint)
2225 mmc_signal_sdio_irq(host->mmc);
2226
d129bceb
PO		 2227 return result;
2228}
2229
2230/*****************************************************************************\
2231 * *
2232 * Suspend/resume *
2233 * *
2234\*****************************************************************************/
2235
2236#ifdef CONFIG_PM
2237
b8c86fc5 2238int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 2239{
b8c86fc5 2240 int ret;
a715dfc7 2241
7260cf5e
AV		 2242 sdhci_disable_card_detection(host);
2243
cf2b5eea
AN		 2244 /* Disable tuning since we are suspending */
2245 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2246 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2247 host->flags &= ~SDHCI_NEEDS_RETUNING;
2248 mod_timer(&host->tuning_timer, jiffies +
2249 host->tuning_count * HZ);
2250 }
2251
1a13f8fa 2252 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2253 if (ret)
2254 return ret;
a715dfc7 2255
b8c86fc5 2256 free_irq(host->irq, host);
d129bceb 2257
9bea3c85
MS		 2258 if (host->vmmc)
2259 ret = regulator_disable(host->vmmc);
2260
2261 return ret;
d129bceb
PO		 2262}
2263
b8c86fc5 2264EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2265
b8c86fc5
PO		 2266int sdhci_resume_host(struct sdhci_host *host)
2267{
2268 int ret;
d129bceb 2269
9bea3c85
MS		 2270 if (host->vmmc) {
2271 int ret = regulator_enable(host->vmmc);
2272 if (ret)
2273 return ret;
2274 }
2275
2276
a13abc7b 2277 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2278 if (host->ops->enable_dma)
2279 host->ops->enable_dma(host);
2280 }
d129bceb 2281
b8c86fc5
PO		 2282 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2283 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2284 if (ret)
2285 return ret;
d129bceb 2286
2f4cbb3d 2287 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2288 mmiowb();
2289
2290 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2291 sdhci_enable_card_detection(host);
2292
cf2b5eea
AN		 2293 /* Set the re-tuning expiration flag */
2294 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2295 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2296 host->flags |= SDHCI_NEEDS_RETUNING;
2297
2f4cbb3d 2298 return ret;
d129bceb
PO		 2299}
2300
b8c86fc5 2301EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2302
5f619704
DD		 2303void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2304{
2305 u8 val;
2306 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2307 val |= SDHCI_WAKE_ON_INT;
2308 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2309}
2310
2311EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2312
d129bceb
PO		 2313#endif /* CONFIG_PM */
2314
2315/*****************************************************************************\
2316 * *
b8c86fc5 2317 * Device allocation/registration *
d129bceb
PO		 2318 * *
2319\*****************************************************************************/
2320
b8c86fc5
PO		 2321struct sdhci_host *sdhci_alloc_host(struct device *dev,
2322 size_t priv_size)
d129bceb 2323{
d129bceb
PO		 2324 struct mmc_host *mmc;
2325 struct sdhci_host *host;
2326
b8c86fc5 2327 WARN_ON(dev == NULL);
d129bceb 2328
b8c86fc5 2329 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2330 if (!mmc)
b8c86fc5 2331 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2332
2333 host = mmc_priv(mmc);
2334 host->mmc = mmc;
2335
b8c86fc5
PO		 2336 return host;
2337}
8a4da143 2338
b8c86fc5 2339EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2340
b8c86fc5
PO		 2341int sdhci_add_host(struct sdhci_host *host)
2342{
2343 struct mmc_host *mmc;
f2119df6
AN		 2344 u32 caps[2];
2345 u32 max_current_caps;
2346 unsigned int ocr_avail;
b8c86fc5 2347 int ret;
d129bceb 2348
b8c86fc5
PO		 2349 WARN_ON(host == NULL);
2350 if (host == NULL)
2351 return -EINVAL;
d129bceb 2352
b8c86fc5 2353 mmc = host->mmc;
d129bceb 2354
b8c86fc5
PO		 2355 if (debug_quirks)
2356 host->quirks = debug_quirks;
d129bceb 2357
d96649ed
PO		 2358 sdhci_reset(host, SDHCI_RESET_ALL);
2359
4e4141a5 2360 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2361 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2362 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2363 if (host->version > SDHCI_SPEC_300) {
4a965505 2364 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 2365 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2366 host->version);
4a965505
PO		 2367 }
2368
f2119df6 2369 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2370 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2371
f2119df6
AN		 2372 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2373 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2374
b8c86fc5 2375 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2376 host->flags |= SDHCI_USE_SDMA;
f2119df6 2377 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2378 DBG("Controller doesn't have SDMA capability\n");
67435274 2379 else
a13abc7b 2380 host->flags |= SDHCI_USE_SDMA;
d129bceb 2381
b8c86fc5 2382 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2383 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2384 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2385 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2386 }
2387
f2119df6
AN		 2388 if ((host->version >= SDHCI_SPEC_200) &&
2389 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2390 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2391
2392 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2393 (host->flags & SDHCI_USE_ADMA)) {
2394 DBG("Disabling ADMA as it is marked broken\n");
2395 host->flags &= ~SDHCI_USE_ADMA;
2396 }
2397
a13abc7b 2398 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2399 if (host->ops->enable_dma) {
2400 if (host->ops->enable_dma(host)) {
2401 printk(KERN_WARNING "%s: No suitable DMA "
2402 "available. Falling back to PIO.\n",
2403 mmc_hostname(mmc));
a13abc7b
RR		 2404 host->flags &=
2405 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2406 }
d129bceb
PO		 2407 }
2408 }
2409
2134a922
PO		 2410 if (host->flags & SDHCI_USE_ADMA) {
2411 /*
2412 * We need to allocate descriptors for all sg entries
2413 * (128) and potentially one alignment transfer for
2414 * each of those entries.
2415 */
2416 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2417 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2418 if (!host->adma_desc || !host->align_buffer) {
2419 kfree(host->adma_desc);
2420 kfree(host->align_buffer);
2421 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2422 "buffers. Falling back to standard DMA.\n",
2423 mmc_hostname(mmc));
2424 host->flags &= ~SDHCI_USE_ADMA;
2425 }
2426 }
2427
7659150c
PO		 2428 /*
2429 * If we use DMA, then it's up to the caller to set the DMA
2430 * mask, but PIO does not need the hw shim so we set a new
2431 * mask here in that case.
2432 */
a13abc7b 2433 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2434 host->dma_mask = DMA_BIT_MASK(64);
2435 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2436 }
d129bceb 2437
c4687d5f 2438 if (host->version >= SDHCI_SPEC_300)
f2119df6 2439 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2440 >> SDHCI_CLOCK_BASE_SHIFT;
2441 else
f2119df6 2442 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2443 >> SDHCI_CLOCK_BASE_SHIFT;
2444
4240ff0a 2445 host->max_clk *= 1000000;
f27f47ef
AV		 2446 if (host->max_clk == 0 || host->quirks &
2447 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 2448 if (!host->ops->get_max_clock) {
2449 printk(KERN_ERR
2450 "%s: Hardware doesn't specify base clock "
2451 "frequency.\n", mmc_hostname(mmc));
2452 return -ENODEV;
2453 }
2454 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2455 }
d129bceb 2456
1c8cde92 2457 host->timeout_clk =
f2119df6 2458 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1c8cde92 2459 if (host->timeout_clk == 0) {
81b39802
AV		 2460 if (host->ops->get_timeout_clock) {
2461 host->timeout_clk = host->ops->get_timeout_clock(host);
2462 } else if (!(host->quirks &
2463 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 2464 printk(KERN_ERR
2465 "%s: Hardware doesn't specify timeout clock "
2466 "frequency.\n", mmc_hostname(mmc));
2467 return -ENODEV;
2468 }
1c8cde92 2469 }
f2119df6 2470 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
1c8cde92 2471 host->timeout_clk *= 1000;
d129bceb 2472
83cbcd93
AS		 2473 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2474 host->timeout_clk = host->clock / 1000;
2475
c3ed3877
AN		 2476 /*
2477 * In case of Host Controller v3.00, find out whether clock
2478 * multiplier is supported.
2479 */
2480 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2481 SDHCI_CLOCK_MUL_SHIFT;
2482
2483 /*
2484 * In case the value in Clock Multiplier is 0, then programmable
2485 * clock mode is not supported, otherwise the actual clock
2486 * multiplier is one more than the value of Clock Multiplier
2487 * in the Capabilities Register.
2488 */
2489 if (host->clk_mul)
2490 host->clk_mul += 1;
2491
d129bceb
PO		 2492 /*
2493 * Set host parameters.
2494 */
2495 mmc->ops = &sdhci_ops;
c3ed3877 2496 mmc->f_max = host->max_clk;
ce5f036b 2497 if (host->ops->get_min_clock)
a9e58f25 2498 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2499 else if (host->version >= SDHCI_SPEC_300) {
2500 if (host->clk_mul) {
2501 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2502 mmc->f_max = host->max_clk * host->clk_mul;
2503 } else
2504 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2505 } else
0397526d 2506 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2507
58d1246d
AH		 2508 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2509 mmc->max_discard_to = (1 << 27) / (mmc->f_max / 1000);
2510 else
2511 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2512
e89d456f
AW		 2513 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2514
2515 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2516 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2517
8edf6371 2518 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2519 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2520 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2521 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2522 host->flags |= SDHCI_AUTO_CMD23;
2523 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2524 } else {
2525 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2526 }
2527
15ec4461
PR		 2528 /*
2529 * A controller may support 8-bit width, but the board itself
2530 * might not have the pins brought out. Boards that support
2531 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2532 * their platform code before calling sdhci_add_host(), and we
2533 * won't assume 8-bit width for hosts without that CAP.
2534 */
5fe23c7f 2535 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2536 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2537
f2119df6 2538 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2539 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2540
176d1ed4
JC		 2541 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2542 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2543 mmc->caps |= MMC_CAP_NEEDS_POLL;
2544
f2119df6
AN		 2545 /* UHS-I mode(s) supported by the host controller. */
2546 if (host->version >= SDHCI_SPEC_300)
2547 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2548
2549 /* SDR104 supports also implies SDR50 support */
2550 if (caps[1] & SDHCI_SUPPORT_SDR104)
2551 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2552 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2553 mmc->caps |= MMC_CAP_UHS_SDR50;
2554
2555 if (caps[1] & SDHCI_SUPPORT_DDR50)
2556 mmc->caps |= MMC_CAP_UHS_DDR50;
2557
b513ea25
AN		 2558 /* Does the host needs tuning for SDR50? */
2559 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2560 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2561
d6d50a15
AN		 2562 /* Driver Type(s) (A, C, D) supported by the host */
2563 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2564 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2565 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2566 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2567 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2568 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2569
cf2b5eea
AN		 2570 /* Initial value for re-tuning timer count */
2571 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2572 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2573
2574 /*
2575 * In case Re-tuning Timer is not disabled, the actual value of
2576 * re-tuning timer will be 2 ^ (n - 1).
2577 */
2578 if (host->tuning_count)
2579 host->tuning_count = 1 << (host->tuning_count - 1);
2580
2581 /* Re-tuning mode supported by the Host Controller */
2582 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2583 SDHCI_RETUNING_MODE_SHIFT;
2584
8f230f45 2585 ocr_avail = 0;
f2119df6
AN		 2586 /*
2587 * According to SD Host Controller spec v3.00, if the Host System
2588 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2589 * the value is meaningful only if Voltage Support in the Capabilities
2590 * register is set. The actual current value is 4 times the register
2591 * value.
2592 */
2593 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2594
2595 if (caps[0] & SDHCI_CAN_VDD_330) {
2596 int max_current_330;
2597
8f230f45 2598 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2599
2600 max_current_330 = ((max_current_caps &
2601 SDHCI_MAX_CURRENT_330_MASK) >>
2602 SDHCI_MAX_CURRENT_330_SHIFT) *
2603 SDHCI_MAX_CURRENT_MULTIPLIER;
2604
2605 if (max_current_330 > 150)
2606 mmc->caps |= MMC_CAP_SET_XPC_330;
2607 }
2608 if (caps[0] & SDHCI_CAN_VDD_300) {
2609 int max_current_300;
2610
8f230f45 2611 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2612
2613 max_current_300 = ((max_current_caps &
2614 SDHCI_MAX_CURRENT_300_MASK) >>
2615 SDHCI_MAX_CURRENT_300_SHIFT) *
2616 SDHCI_MAX_CURRENT_MULTIPLIER;
2617
2618 if (max_current_300 > 150)
2619 mmc->caps |= MMC_CAP_SET_XPC_300;
2620 }
2621 if (caps[0] & SDHCI_CAN_VDD_180) {
2622 int max_current_180;
2623
8f230f45
TI		 2624 ocr_avail |= MMC_VDD_165_195;
2625
f2119df6
AN		 2626 max_current_180 = ((max_current_caps &
2627 SDHCI_MAX_CURRENT_180_MASK) >>
2628 SDHCI_MAX_CURRENT_180_SHIFT) *
2629 SDHCI_MAX_CURRENT_MULTIPLIER;
2630
2631 if (max_current_180 > 150)
2632 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2633
2634 /* Maximum current capabilities of the host at 1.8V */
2635 if (max_current_180 >= 800)
2636 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2637 else if (max_current_180 >= 600)
2638 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2639 else if (max_current_180 >= 400)
2640 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2641 else
2642 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2643 }
2644
8f230f45
TI		 2645 mmc->ocr_avail = ocr_avail;
2646 mmc->ocr_avail_sdio = ocr_avail;
2647 if (host->ocr_avail_sdio)
2648 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2649 mmc->ocr_avail_sd = ocr_avail;
2650 if (host->ocr_avail_sd)
2651 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2652 else /* normal SD controllers don't support 1.8V */
2653 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2654 mmc->ocr_avail_mmc = ocr_avail;
2655 if (host->ocr_avail_mmc)
2656 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2657
2658 if (mmc->ocr_avail == 0) {
2659 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 2660 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2661 return -ENODEV;
146ad66e
PO		 2662 }
2663
d129bceb
PO		 2664 spin_lock_init(&host->lock);
2665
2666 /*
2134a922
PO		 2667 * Maximum number of segments. Depends on if the hardware
2668 * can do scatter/gather or not.
d129bceb 2669 */
2134a922 2670 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2671 mmc->max_segs = 128;
a13abc7b 2672 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2673 mmc->max_segs = 1;
2134a922 2674 else /* PIO */
a36274e0 2675 mmc->max_segs = 128;
d129bceb
PO		 2676
2677 /*
bab76961 2678 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2679 * size (512KiB).
d129bceb 2680 */
55db890a 2681 mmc->max_req_size = 524288;
d129bceb
PO		 2682
2683 /*
2684 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2685 * of bytes. When doing hardware scatter/gather, each entry cannot
2686 * be larger than 64 KiB though.
d129bceb 2687 */
30652aa3
OJ		 2688 if (host->flags & SDHCI_USE_ADMA) {
2689 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2690 mmc->max_seg_size = 65535;
2691 else
2692 mmc->max_seg_size = 65536;
2693 } else {
2134a922 2694 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2695 }
d129bceb 2696
fe4a3c7a
PO		 2697 /*
2698 * Maximum block size. This varies from controller to controller and
2699 * is specified in the capabilities register.
2700 */
0633f654
AV		 2701 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2702 mmc->max_blk_size = 2;
2703 } else {
f2119df6 2704 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2705 SDHCI_MAX_BLOCK_SHIFT;
2706 if (mmc->max_blk_size >= 3) {
2707 printk(KERN_WARNING "%s: Invalid maximum block size, "
2708 "assuming 512 bytes\n", mmc_hostname(mmc));
2709 mmc->max_blk_size = 0;
2710 }
2711 }
2712
2713 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2714
55db890a
PO		 2715 /*
2716 * Maximum block count.
2717 */
1388eefd 2718 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2719
d129bceb
PO		 2720 /*
2721 * Init tasklets.
2722 */
2723 tasklet_init(&host->card_tasklet,
2724 sdhci_tasklet_card, (unsigned long)host);
2725 tasklet_init(&host->finish_tasklet,
2726 sdhci_tasklet_finish, (unsigned long)host);
2727
e4cad1b5 2728 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2729
cf2b5eea 2730 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2731 init_waitqueue_head(&host->buf_ready_int);
2732
cf2b5eea
AN		 2733 /* Initialize re-tuning timer */
2734 init_timer(&host->tuning_timer);
2735 host->tuning_timer.data = (unsigned long)host;
2736 host->tuning_timer.function = sdhci_tuning_timer;
2737 }
2738
dace1453 2739 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2740 mmc_hostname(mmc), host);
d129bceb 2741 if (ret)
8ef1a143 2742 goto untasklet;
d129bceb 2743
9bea3c85
MS		 2744 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2745 if (IS_ERR(host->vmmc)) {
2746 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2747 host->vmmc = NULL;
2748 } else {
2749 regulator_enable(host->vmmc);
2750 }
2751
2f4cbb3d 2752 sdhci_init(host, 0);
d129bceb
PO		 2753
2754#ifdef CONFIG_MMC_DEBUG
2755 sdhci_dumpregs(host);
2756#endif
2757
f9134319 2758#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2759 snprintf(host->led_name, sizeof(host->led_name),
2760 "%s::", mmc_hostname(mmc));
2761 host->led.name = host->led_name;
2f730fec
PO		 2762 host->led.brightness = LED_OFF;
2763 host->led.default_trigger = mmc_hostname(mmc);
2764 host->led.brightness_set = sdhci_led_control;
2765
b8c86fc5 2766 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2767 if (ret)
2768 goto reset;
2769#endif
2770
5f25a66f
PO		 2771 mmiowb();
2772
d129bceb
PO		 2773 mmc_add_host(mmc);
2774
a13abc7b 2775 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2776 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2777 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2778 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2779
7260cf5e
AV		 2780 sdhci_enable_card_detection(host);
2781
d129bceb
PO		 2782 return 0;
2783
f9134319 2784#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2785reset:
2786 sdhci_reset(host, SDHCI_RESET_ALL);
2787 free_irq(host->irq, host);
2788#endif
8ef1a143 2789untasklet:
d129bceb
PO		 2790 tasklet_kill(&host->card_tasklet);
2791 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2792
2793 return ret;
2794}
2795
b8c86fc5 2796EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2797
1e72859e 2798void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2799{
1e72859e
PO		 2800 unsigned long flags;
2801
2802 if (dead) {
2803 spin_lock_irqsave(&host->lock, flags);
2804
2805 host->flags |= SDHCI_DEVICE_DEAD;
2806
2807 if (host->mrq) {
2808 printk(KERN_ERR "%s: Controller removed during "
2809 " transfer!\n", mmc_hostname(host->mmc));
2810
2811 host->mrq->cmd->error = -ENOMEDIUM;
2812 tasklet_schedule(&host->finish_tasklet);
2813 }
2814
2815 spin_unlock_irqrestore(&host->lock, flags);
2816 }
2817
7260cf5e
AV		 2818 sdhci_disable_card_detection(host);
2819
b8c86fc5 2820 mmc_remove_host(host->mmc);
d129bceb 2821
f9134319 2822#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2823 led_classdev_unregister(&host->led);
2824#endif
2825
1e72859e
PO		 2826 if (!dead)
2827 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2828
2829 free_irq(host->irq, host);
2830
2831 del_timer_sync(&host->timer);
cf2b5eea
AN		 2832 if (host->version >= SDHCI_SPEC_300)
2833 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 2834
2835 tasklet_kill(&host->card_tasklet);
2836 tasklet_kill(&host->finish_tasklet);
2134a922 2837
9bea3c85
MS		 2838 if (host->vmmc) {
2839 regulator_disable(host->vmmc);
2840 regulator_put(host->vmmc);
2841 }
2842
2134a922
PO		 2843 kfree(host->adma_desc);
2844 kfree(host->align_buffer);
2845
2846 host->adma_desc = NULL;
2847 host->align_buffer = NULL;
d129bceb
PO		 2848}
2849
b8c86fc5 2850EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2851
b8c86fc5 2852void sdhci_free_host(struct sdhci_host *host)
d129bceb 2853{
b8c86fc5 2854 mmc_free_host(host->mmc);
d129bceb
PO		 2855}
2856
b8c86fc5 2857EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2858
2859/*****************************************************************************\
2860 * *
2861 * Driver init/exit *
2862 * *
2863\*****************************************************************************/
2864
2865static int __init sdhci_drv_init(void)
2866{
2867 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2868 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2869 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2870
b8c86fc5 2871 return 0;
d129bceb
PO		 2872}
2873
2874static void __exit sdhci_drv_exit(void)
2875{
d129bceb
PO		 2876}
2877
2878module_init(sdhci_drv_init);
2879module_exit(sdhci_drv_exit);
2880
df673b22 2881module_param(debug_quirks, uint, 0444);
67435274 2882
32710e8f 2883MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2884MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2885MODULE_LICENSE("GPL");
67435274 2886
df673b22 2887MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
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